i915_debugfs.c 58 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include "intel_drv.h"
  34. #include "intel_ringbuffer.h"
  35. #include <drm/i915_drm.h>
  36. #include "i915_drv.h"
  37. #define DRM_I915_RING_DEBUG 1
  38. #if defined(CONFIG_DEBUG_FS)
  39. enum {
  40. ACTIVE_LIST,
  41. INACTIVE_LIST,
  42. PINNED_LIST,
  43. };
  44. static const char *yesno(int v)
  45. {
  46. return v ? "yes" : "no";
  47. }
  48. static int i915_capabilities(struct seq_file *m, void *data)
  49. {
  50. struct drm_info_node *node = (struct drm_info_node *) m->private;
  51. struct drm_device *dev = node->minor->dev;
  52. const struct intel_device_info *info = INTEL_INFO(dev);
  53. seq_printf(m, "gen: %d\n", info->gen);
  54. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  55. #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  56. #define DEV_INFO_SEP ;
  57. DEV_INFO_FLAGS;
  58. #undef DEV_INFO_FLAG
  59. #undef DEV_INFO_SEP
  60. return 0;
  61. }
  62. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  63. {
  64. if (obj->user_pin_count > 0)
  65. return "P";
  66. else if (obj->pin_count > 0)
  67. return "p";
  68. else
  69. return " ";
  70. }
  71. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  72. {
  73. switch (obj->tiling_mode) {
  74. default:
  75. case I915_TILING_NONE: return " ";
  76. case I915_TILING_X: return "X";
  77. case I915_TILING_Y: return "Y";
  78. }
  79. }
  80. static const char *cache_level_str(int type)
  81. {
  82. switch (type) {
  83. case I915_CACHE_NONE: return " uncached";
  84. case I915_CACHE_LLC: return " snooped (LLC)";
  85. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  86. default: return "";
  87. }
  88. }
  89. static void
  90. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  91. {
  92. seq_printf(m, "%p: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
  93. &obj->base,
  94. get_pin_flag(obj),
  95. get_tiling_flag(obj),
  96. obj->base.size / 1024,
  97. obj->base.read_domains,
  98. obj->base.write_domain,
  99. obj->last_read_seqno,
  100. obj->last_write_seqno,
  101. obj->last_fenced_seqno,
  102. cache_level_str(obj->cache_level),
  103. obj->dirty ? " dirty" : "",
  104. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  105. if (obj->base.name)
  106. seq_printf(m, " (name: %d)", obj->base.name);
  107. if (obj->pin_count)
  108. seq_printf(m, " (pinned x %d)", obj->pin_count);
  109. if (obj->fence_reg != I915_FENCE_REG_NONE)
  110. seq_printf(m, " (fence: %d)", obj->fence_reg);
  111. if (obj->gtt_space != NULL)
  112. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  113. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  114. if (obj->stolen)
  115. seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
  116. if (obj->pin_mappable || obj->fault_mappable) {
  117. char s[3], *t = s;
  118. if (obj->pin_mappable)
  119. *t++ = 'p';
  120. if (obj->fault_mappable)
  121. *t++ = 'f';
  122. *t = '\0';
  123. seq_printf(m, " (%s mappable)", s);
  124. }
  125. if (obj->ring != NULL)
  126. seq_printf(m, " (%s)", obj->ring->name);
  127. }
  128. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  129. {
  130. struct drm_info_node *node = (struct drm_info_node *) m->private;
  131. uintptr_t list = (uintptr_t) node->info_ent->data;
  132. struct list_head *head;
  133. struct drm_device *dev = node->minor->dev;
  134. drm_i915_private_t *dev_priv = dev->dev_private;
  135. struct drm_i915_gem_object *obj;
  136. size_t total_obj_size, total_gtt_size;
  137. int count, ret;
  138. ret = mutex_lock_interruptible(&dev->struct_mutex);
  139. if (ret)
  140. return ret;
  141. switch (list) {
  142. case ACTIVE_LIST:
  143. seq_printf(m, "Active:\n");
  144. head = &dev_priv->mm.active_list;
  145. break;
  146. case INACTIVE_LIST:
  147. seq_printf(m, "Inactive:\n");
  148. head = &dev_priv->mm.inactive_list;
  149. break;
  150. default:
  151. mutex_unlock(&dev->struct_mutex);
  152. return -EINVAL;
  153. }
  154. total_obj_size = total_gtt_size = count = 0;
  155. list_for_each_entry(obj, head, mm_list) {
  156. seq_printf(m, " ");
  157. describe_obj(m, obj);
  158. seq_printf(m, "\n");
  159. total_obj_size += obj->base.size;
  160. total_gtt_size += obj->gtt_space->size;
  161. count++;
  162. }
  163. mutex_unlock(&dev->struct_mutex);
  164. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  165. count, total_obj_size, total_gtt_size);
  166. return 0;
  167. }
  168. #define count_objects(list, member) do { \
  169. list_for_each_entry(obj, list, member) { \
  170. size += obj->gtt_space->size; \
  171. ++count; \
  172. if (obj->map_and_fenceable) { \
  173. mappable_size += obj->gtt_space->size; \
  174. ++mappable_count; \
  175. } \
  176. } \
  177. } while (0)
  178. static int i915_gem_object_info(struct seq_file *m, void* data)
  179. {
  180. struct drm_info_node *node = (struct drm_info_node *) m->private;
  181. struct drm_device *dev = node->minor->dev;
  182. struct drm_i915_private *dev_priv = dev->dev_private;
  183. u32 count, mappable_count, purgeable_count;
  184. size_t size, mappable_size, purgeable_size;
  185. struct drm_i915_gem_object *obj;
  186. int ret;
  187. ret = mutex_lock_interruptible(&dev->struct_mutex);
  188. if (ret)
  189. return ret;
  190. seq_printf(m, "%u objects, %zu bytes\n",
  191. dev_priv->mm.object_count,
  192. dev_priv->mm.object_memory);
  193. size = count = mappable_size = mappable_count = 0;
  194. count_objects(&dev_priv->mm.bound_list, gtt_list);
  195. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  196. count, mappable_count, size, mappable_size);
  197. size = count = mappable_size = mappable_count = 0;
  198. count_objects(&dev_priv->mm.active_list, mm_list);
  199. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  200. count, mappable_count, size, mappable_size);
  201. size = count = mappable_size = mappable_count = 0;
  202. count_objects(&dev_priv->mm.inactive_list, mm_list);
  203. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  204. count, mappable_count, size, mappable_size);
  205. size = count = purgeable_size = purgeable_count = 0;
  206. list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
  207. size += obj->base.size, ++count;
  208. if (obj->madv == I915_MADV_DONTNEED)
  209. purgeable_size += obj->base.size, ++purgeable_count;
  210. }
  211. seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
  212. size = count = mappable_size = mappable_count = 0;
  213. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  214. if (obj->fault_mappable) {
  215. size += obj->gtt_space->size;
  216. ++count;
  217. }
  218. if (obj->pin_mappable) {
  219. mappable_size += obj->gtt_space->size;
  220. ++mappable_count;
  221. }
  222. if (obj->madv == I915_MADV_DONTNEED) {
  223. purgeable_size += obj->base.size;
  224. ++purgeable_count;
  225. }
  226. }
  227. seq_printf(m, "%u purgeable objects, %zu bytes\n",
  228. purgeable_count, purgeable_size);
  229. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  230. mappable_count, mappable_size);
  231. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  232. count, size);
  233. seq_printf(m, "%zu [%zu] gtt total\n",
  234. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  235. mutex_unlock(&dev->struct_mutex);
  236. return 0;
  237. }
  238. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  239. {
  240. struct drm_info_node *node = (struct drm_info_node *) m->private;
  241. struct drm_device *dev = node->minor->dev;
  242. uintptr_t list = (uintptr_t) node->info_ent->data;
  243. struct drm_i915_private *dev_priv = dev->dev_private;
  244. struct drm_i915_gem_object *obj;
  245. size_t total_obj_size, total_gtt_size;
  246. int count, ret;
  247. ret = mutex_lock_interruptible(&dev->struct_mutex);
  248. if (ret)
  249. return ret;
  250. total_obj_size = total_gtt_size = count = 0;
  251. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  252. if (list == PINNED_LIST && obj->pin_count == 0)
  253. continue;
  254. seq_printf(m, " ");
  255. describe_obj(m, obj);
  256. seq_printf(m, "\n");
  257. total_obj_size += obj->base.size;
  258. total_gtt_size += obj->gtt_space->size;
  259. count++;
  260. }
  261. mutex_unlock(&dev->struct_mutex);
  262. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  263. count, total_obj_size, total_gtt_size);
  264. return 0;
  265. }
  266. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  267. {
  268. struct drm_info_node *node = (struct drm_info_node *) m->private;
  269. struct drm_device *dev = node->minor->dev;
  270. unsigned long flags;
  271. struct intel_crtc *crtc;
  272. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  273. const char pipe = pipe_name(crtc->pipe);
  274. const char plane = plane_name(crtc->plane);
  275. struct intel_unpin_work *work;
  276. spin_lock_irqsave(&dev->event_lock, flags);
  277. work = crtc->unpin_work;
  278. if (work == NULL) {
  279. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  280. pipe, plane);
  281. } else {
  282. if (!work->pending) {
  283. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  284. pipe, plane);
  285. } else {
  286. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  287. pipe, plane);
  288. }
  289. if (work->enable_stall_check)
  290. seq_printf(m, "Stall check enabled, ");
  291. else
  292. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  293. seq_printf(m, "%d prepares\n", work->pending);
  294. if (work->old_fb_obj) {
  295. struct drm_i915_gem_object *obj = work->old_fb_obj;
  296. if (obj)
  297. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  298. }
  299. if (work->pending_flip_obj) {
  300. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  301. if (obj)
  302. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  303. }
  304. }
  305. spin_unlock_irqrestore(&dev->event_lock, flags);
  306. }
  307. return 0;
  308. }
  309. static int i915_gem_request_info(struct seq_file *m, void *data)
  310. {
  311. struct drm_info_node *node = (struct drm_info_node *) m->private;
  312. struct drm_device *dev = node->minor->dev;
  313. drm_i915_private_t *dev_priv = dev->dev_private;
  314. struct intel_ring_buffer *ring;
  315. struct drm_i915_gem_request *gem_request;
  316. int ret, count, i;
  317. ret = mutex_lock_interruptible(&dev->struct_mutex);
  318. if (ret)
  319. return ret;
  320. count = 0;
  321. for_each_ring(ring, dev_priv, i) {
  322. if (list_empty(&ring->request_list))
  323. continue;
  324. seq_printf(m, "%s requests:\n", ring->name);
  325. list_for_each_entry(gem_request,
  326. &ring->request_list,
  327. list) {
  328. seq_printf(m, " %d @ %d\n",
  329. gem_request->seqno,
  330. (int) (jiffies - gem_request->emitted_jiffies));
  331. }
  332. count++;
  333. }
  334. mutex_unlock(&dev->struct_mutex);
  335. if (count == 0)
  336. seq_printf(m, "No requests\n");
  337. return 0;
  338. }
  339. static void i915_ring_seqno_info(struct seq_file *m,
  340. struct intel_ring_buffer *ring)
  341. {
  342. if (ring->get_seqno) {
  343. seq_printf(m, "Current sequence (%s): %u\n",
  344. ring->name, ring->get_seqno(ring, false));
  345. }
  346. }
  347. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  348. {
  349. struct drm_info_node *node = (struct drm_info_node *) m->private;
  350. struct drm_device *dev = node->minor->dev;
  351. drm_i915_private_t *dev_priv = dev->dev_private;
  352. struct intel_ring_buffer *ring;
  353. int ret, i;
  354. ret = mutex_lock_interruptible(&dev->struct_mutex);
  355. if (ret)
  356. return ret;
  357. for_each_ring(ring, dev_priv, i)
  358. i915_ring_seqno_info(m, ring);
  359. mutex_unlock(&dev->struct_mutex);
  360. return 0;
  361. }
  362. static int i915_interrupt_info(struct seq_file *m, void *data)
  363. {
  364. struct drm_info_node *node = (struct drm_info_node *) m->private;
  365. struct drm_device *dev = node->minor->dev;
  366. drm_i915_private_t *dev_priv = dev->dev_private;
  367. struct intel_ring_buffer *ring;
  368. int ret, i, pipe;
  369. ret = mutex_lock_interruptible(&dev->struct_mutex);
  370. if (ret)
  371. return ret;
  372. if (IS_VALLEYVIEW(dev)) {
  373. seq_printf(m, "Display IER:\t%08x\n",
  374. I915_READ(VLV_IER));
  375. seq_printf(m, "Display IIR:\t%08x\n",
  376. I915_READ(VLV_IIR));
  377. seq_printf(m, "Display IIR_RW:\t%08x\n",
  378. I915_READ(VLV_IIR_RW));
  379. seq_printf(m, "Display IMR:\t%08x\n",
  380. I915_READ(VLV_IMR));
  381. for_each_pipe(pipe)
  382. seq_printf(m, "Pipe %c stat:\t%08x\n",
  383. pipe_name(pipe),
  384. I915_READ(PIPESTAT(pipe)));
  385. seq_printf(m, "Master IER:\t%08x\n",
  386. I915_READ(VLV_MASTER_IER));
  387. seq_printf(m, "Render IER:\t%08x\n",
  388. I915_READ(GTIER));
  389. seq_printf(m, "Render IIR:\t%08x\n",
  390. I915_READ(GTIIR));
  391. seq_printf(m, "Render IMR:\t%08x\n",
  392. I915_READ(GTIMR));
  393. seq_printf(m, "PM IER:\t\t%08x\n",
  394. I915_READ(GEN6_PMIER));
  395. seq_printf(m, "PM IIR:\t\t%08x\n",
  396. I915_READ(GEN6_PMIIR));
  397. seq_printf(m, "PM IMR:\t\t%08x\n",
  398. I915_READ(GEN6_PMIMR));
  399. seq_printf(m, "Port hotplug:\t%08x\n",
  400. I915_READ(PORT_HOTPLUG_EN));
  401. seq_printf(m, "DPFLIPSTAT:\t%08x\n",
  402. I915_READ(VLV_DPFLIPSTAT));
  403. seq_printf(m, "DPINVGTT:\t%08x\n",
  404. I915_READ(DPINVGTT));
  405. } else if (!HAS_PCH_SPLIT(dev)) {
  406. seq_printf(m, "Interrupt enable: %08x\n",
  407. I915_READ(IER));
  408. seq_printf(m, "Interrupt identity: %08x\n",
  409. I915_READ(IIR));
  410. seq_printf(m, "Interrupt mask: %08x\n",
  411. I915_READ(IMR));
  412. for_each_pipe(pipe)
  413. seq_printf(m, "Pipe %c stat: %08x\n",
  414. pipe_name(pipe),
  415. I915_READ(PIPESTAT(pipe)));
  416. } else {
  417. seq_printf(m, "North Display Interrupt enable: %08x\n",
  418. I915_READ(DEIER));
  419. seq_printf(m, "North Display Interrupt identity: %08x\n",
  420. I915_READ(DEIIR));
  421. seq_printf(m, "North Display Interrupt mask: %08x\n",
  422. I915_READ(DEIMR));
  423. seq_printf(m, "South Display Interrupt enable: %08x\n",
  424. I915_READ(SDEIER));
  425. seq_printf(m, "South Display Interrupt identity: %08x\n",
  426. I915_READ(SDEIIR));
  427. seq_printf(m, "South Display Interrupt mask: %08x\n",
  428. I915_READ(SDEIMR));
  429. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  430. I915_READ(GTIER));
  431. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  432. I915_READ(GTIIR));
  433. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  434. I915_READ(GTIMR));
  435. }
  436. seq_printf(m, "Interrupts received: %d\n",
  437. atomic_read(&dev_priv->irq_received));
  438. for_each_ring(ring, dev_priv, i) {
  439. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  440. seq_printf(m,
  441. "Graphics Interrupt mask (%s): %08x\n",
  442. ring->name, I915_READ_IMR(ring));
  443. }
  444. i915_ring_seqno_info(m, ring);
  445. }
  446. mutex_unlock(&dev->struct_mutex);
  447. return 0;
  448. }
  449. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  450. {
  451. struct drm_info_node *node = (struct drm_info_node *) m->private;
  452. struct drm_device *dev = node->minor->dev;
  453. drm_i915_private_t *dev_priv = dev->dev_private;
  454. int i, ret;
  455. ret = mutex_lock_interruptible(&dev->struct_mutex);
  456. if (ret)
  457. return ret;
  458. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  459. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  460. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  461. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  462. seq_printf(m, "Fence %d, pin count = %d, object = ",
  463. i, dev_priv->fence_regs[i].pin_count);
  464. if (obj == NULL)
  465. seq_printf(m, "unused");
  466. else
  467. describe_obj(m, obj);
  468. seq_printf(m, "\n");
  469. }
  470. mutex_unlock(&dev->struct_mutex);
  471. return 0;
  472. }
  473. static int i915_hws_info(struct seq_file *m, void *data)
  474. {
  475. struct drm_info_node *node = (struct drm_info_node *) m->private;
  476. struct drm_device *dev = node->minor->dev;
  477. drm_i915_private_t *dev_priv = dev->dev_private;
  478. struct intel_ring_buffer *ring;
  479. const u32 *hws;
  480. int i;
  481. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  482. hws = ring->status_page.page_addr;
  483. if (hws == NULL)
  484. return 0;
  485. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  486. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  487. i * 4,
  488. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  489. }
  490. return 0;
  491. }
  492. static const char *ring_str(int ring)
  493. {
  494. switch (ring) {
  495. case RCS: return "render";
  496. case VCS: return "bsd";
  497. case BCS: return "blt";
  498. default: return "";
  499. }
  500. }
  501. static const char *pin_flag(int pinned)
  502. {
  503. if (pinned > 0)
  504. return " P";
  505. else if (pinned < 0)
  506. return " p";
  507. else
  508. return "";
  509. }
  510. static const char *tiling_flag(int tiling)
  511. {
  512. switch (tiling) {
  513. default:
  514. case I915_TILING_NONE: return "";
  515. case I915_TILING_X: return " X";
  516. case I915_TILING_Y: return " Y";
  517. }
  518. }
  519. static const char *dirty_flag(int dirty)
  520. {
  521. return dirty ? " dirty" : "";
  522. }
  523. static const char *purgeable_flag(int purgeable)
  524. {
  525. return purgeable ? " purgeable" : "";
  526. }
  527. static void print_error_buffers(struct seq_file *m,
  528. const char *name,
  529. struct drm_i915_error_buffer *err,
  530. int count)
  531. {
  532. seq_printf(m, "%s [%d]:\n", name, count);
  533. while (count--) {
  534. seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
  535. err->gtt_offset,
  536. err->size,
  537. err->read_domains,
  538. err->write_domain,
  539. err->rseqno, err->wseqno,
  540. pin_flag(err->pinned),
  541. tiling_flag(err->tiling),
  542. dirty_flag(err->dirty),
  543. purgeable_flag(err->purgeable),
  544. err->ring != -1 ? " " : "",
  545. ring_str(err->ring),
  546. cache_level_str(err->cache_level));
  547. if (err->name)
  548. seq_printf(m, " (name: %d)", err->name);
  549. if (err->fence_reg != I915_FENCE_REG_NONE)
  550. seq_printf(m, " (fence: %d)", err->fence_reg);
  551. seq_printf(m, "\n");
  552. err++;
  553. }
  554. }
  555. static void i915_ring_error_state(struct seq_file *m,
  556. struct drm_device *dev,
  557. struct drm_i915_error_state *error,
  558. unsigned ring)
  559. {
  560. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  561. seq_printf(m, "%s command stream:\n", ring_str(ring));
  562. seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  563. seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  564. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  565. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  566. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  567. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  568. if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
  569. seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
  570. if (INTEL_INFO(dev)->gen >= 4)
  571. seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  572. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  573. seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  574. if (INTEL_INFO(dev)->gen >= 6) {
  575. seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  576. seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  577. seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
  578. error->semaphore_mboxes[ring][0],
  579. error->semaphore_seqno[ring][0]);
  580. seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
  581. error->semaphore_mboxes[ring][1],
  582. error->semaphore_seqno[ring][1]);
  583. }
  584. seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  585. seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  586. seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  587. seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  588. }
  589. struct i915_error_state_file_priv {
  590. struct drm_device *dev;
  591. struct drm_i915_error_state *error;
  592. };
  593. static int i915_error_state(struct seq_file *m, void *unused)
  594. {
  595. struct i915_error_state_file_priv *error_priv = m->private;
  596. struct drm_device *dev = error_priv->dev;
  597. drm_i915_private_t *dev_priv = dev->dev_private;
  598. struct drm_i915_error_state *error = error_priv->error;
  599. struct intel_ring_buffer *ring;
  600. int i, j, page, offset, elt;
  601. if (!error) {
  602. seq_printf(m, "no error state collected\n");
  603. return 0;
  604. }
  605. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  606. error->time.tv_usec);
  607. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  608. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  609. seq_printf(m, "IER: 0x%08x\n", error->ier);
  610. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  611. seq_printf(m, "CCID: 0x%08x\n", error->ccid);
  612. for (i = 0; i < dev_priv->num_fence_regs; i++)
  613. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  614. for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
  615. seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
  616. if (INTEL_INFO(dev)->gen >= 6) {
  617. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  618. seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  619. }
  620. if (INTEL_INFO(dev)->gen == 7)
  621. seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
  622. for_each_ring(ring, dev_priv, i)
  623. i915_ring_error_state(m, dev, error, i);
  624. if (error->active_bo)
  625. print_error_buffers(m, "Active",
  626. error->active_bo,
  627. error->active_bo_count);
  628. if (error->pinned_bo)
  629. print_error_buffers(m, "Pinned",
  630. error->pinned_bo,
  631. error->pinned_bo_count);
  632. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  633. struct drm_i915_error_object *obj;
  634. if ((obj = error->ring[i].batchbuffer)) {
  635. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  636. dev_priv->ring[i].name,
  637. obj->gtt_offset);
  638. offset = 0;
  639. for (page = 0; page < obj->page_count; page++) {
  640. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  641. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  642. offset += 4;
  643. }
  644. }
  645. }
  646. if (error->ring[i].num_requests) {
  647. seq_printf(m, "%s --- %d requests\n",
  648. dev_priv->ring[i].name,
  649. error->ring[i].num_requests);
  650. for (j = 0; j < error->ring[i].num_requests; j++) {
  651. seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  652. error->ring[i].requests[j].seqno,
  653. error->ring[i].requests[j].jiffies,
  654. error->ring[i].requests[j].tail);
  655. }
  656. }
  657. if ((obj = error->ring[i].ringbuffer)) {
  658. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  659. dev_priv->ring[i].name,
  660. obj->gtt_offset);
  661. offset = 0;
  662. for (page = 0; page < obj->page_count; page++) {
  663. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  664. seq_printf(m, "%08x : %08x\n",
  665. offset,
  666. obj->pages[page][elt]);
  667. offset += 4;
  668. }
  669. }
  670. }
  671. }
  672. if (error->overlay)
  673. intel_overlay_print_error_state(m, error->overlay);
  674. if (error->display)
  675. intel_display_print_error_state(m, dev, error->display);
  676. return 0;
  677. }
  678. static ssize_t
  679. i915_error_state_write(struct file *filp,
  680. const char __user *ubuf,
  681. size_t cnt,
  682. loff_t *ppos)
  683. {
  684. struct seq_file *m = filp->private_data;
  685. struct i915_error_state_file_priv *error_priv = m->private;
  686. struct drm_device *dev = error_priv->dev;
  687. int ret;
  688. DRM_DEBUG_DRIVER("Resetting error state\n");
  689. ret = mutex_lock_interruptible(&dev->struct_mutex);
  690. if (ret)
  691. return ret;
  692. i915_destroy_error_state(dev);
  693. mutex_unlock(&dev->struct_mutex);
  694. return cnt;
  695. }
  696. static int i915_error_state_open(struct inode *inode, struct file *file)
  697. {
  698. struct drm_device *dev = inode->i_private;
  699. drm_i915_private_t *dev_priv = dev->dev_private;
  700. struct i915_error_state_file_priv *error_priv;
  701. unsigned long flags;
  702. error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
  703. if (!error_priv)
  704. return -ENOMEM;
  705. error_priv->dev = dev;
  706. spin_lock_irqsave(&dev_priv->error_lock, flags);
  707. error_priv->error = dev_priv->first_error;
  708. if (error_priv->error)
  709. kref_get(&error_priv->error->ref);
  710. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  711. return single_open(file, i915_error_state, error_priv);
  712. }
  713. static int i915_error_state_release(struct inode *inode, struct file *file)
  714. {
  715. struct seq_file *m = file->private_data;
  716. struct i915_error_state_file_priv *error_priv = m->private;
  717. if (error_priv->error)
  718. kref_put(&error_priv->error->ref, i915_error_state_free);
  719. kfree(error_priv);
  720. return single_release(inode, file);
  721. }
  722. static const struct file_operations i915_error_state_fops = {
  723. .owner = THIS_MODULE,
  724. .open = i915_error_state_open,
  725. .read = seq_read,
  726. .write = i915_error_state_write,
  727. .llseek = default_llseek,
  728. .release = i915_error_state_release,
  729. };
  730. static ssize_t
  731. i915_next_seqno_read(struct file *filp,
  732. char __user *ubuf,
  733. size_t max,
  734. loff_t *ppos)
  735. {
  736. struct drm_device *dev = filp->private_data;
  737. drm_i915_private_t *dev_priv = dev->dev_private;
  738. char buf[80];
  739. int len;
  740. int ret;
  741. ret = mutex_lock_interruptible(&dev->struct_mutex);
  742. if (ret)
  743. return ret;
  744. len = snprintf(buf, sizeof(buf),
  745. "next_seqno : 0x%x\n",
  746. dev_priv->next_seqno);
  747. mutex_unlock(&dev->struct_mutex);
  748. if (len > sizeof(buf))
  749. len = sizeof(buf);
  750. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  751. }
  752. static ssize_t
  753. i915_next_seqno_write(struct file *filp,
  754. const char __user *ubuf,
  755. size_t cnt,
  756. loff_t *ppos)
  757. {
  758. struct drm_device *dev = filp->private_data;
  759. char buf[20];
  760. u32 val = 1;
  761. int ret;
  762. if (cnt > 0) {
  763. if (cnt > sizeof(buf) - 1)
  764. return -EINVAL;
  765. if (copy_from_user(buf, ubuf, cnt))
  766. return -EFAULT;
  767. buf[cnt] = 0;
  768. ret = kstrtouint(buf, 0, &val);
  769. if (ret < 0)
  770. return ret;
  771. }
  772. ret = mutex_lock_interruptible(&dev->struct_mutex);
  773. if (ret)
  774. return ret;
  775. ret = i915_gem_set_seqno(dev, val);
  776. mutex_unlock(&dev->struct_mutex);
  777. return ret ?: cnt;
  778. }
  779. static const struct file_operations i915_next_seqno_fops = {
  780. .owner = THIS_MODULE,
  781. .open = simple_open,
  782. .read = i915_next_seqno_read,
  783. .write = i915_next_seqno_write,
  784. .llseek = default_llseek,
  785. };
  786. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  787. {
  788. struct drm_info_node *node = (struct drm_info_node *) m->private;
  789. struct drm_device *dev = node->minor->dev;
  790. drm_i915_private_t *dev_priv = dev->dev_private;
  791. u16 crstanddelay;
  792. int ret;
  793. ret = mutex_lock_interruptible(&dev->struct_mutex);
  794. if (ret)
  795. return ret;
  796. crstanddelay = I915_READ16(CRSTANDVID);
  797. mutex_unlock(&dev->struct_mutex);
  798. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  799. return 0;
  800. }
  801. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  802. {
  803. struct drm_info_node *node = (struct drm_info_node *) m->private;
  804. struct drm_device *dev = node->minor->dev;
  805. drm_i915_private_t *dev_priv = dev->dev_private;
  806. int ret;
  807. if (IS_GEN5(dev)) {
  808. u16 rgvswctl = I915_READ16(MEMSWCTL);
  809. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  810. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  811. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  812. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  813. MEMSTAT_VID_SHIFT);
  814. seq_printf(m, "Current P-state: %d\n",
  815. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  816. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  817. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  818. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  819. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  820. u32 rpstat;
  821. u32 rpupei, rpcurup, rpprevup;
  822. u32 rpdownei, rpcurdown, rpprevdown;
  823. int max_freq;
  824. /* RPSTAT1 is in the GT power well */
  825. ret = mutex_lock_interruptible(&dev->struct_mutex);
  826. if (ret)
  827. return ret;
  828. gen6_gt_force_wake_get(dev_priv);
  829. rpstat = I915_READ(GEN6_RPSTAT1);
  830. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  831. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  832. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  833. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  834. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  835. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  836. gen6_gt_force_wake_put(dev_priv);
  837. mutex_unlock(&dev->struct_mutex);
  838. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  839. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  840. seq_printf(m, "Render p-state ratio: %d\n",
  841. (gt_perf_status & 0xff00) >> 8);
  842. seq_printf(m, "Render p-state VID: %d\n",
  843. gt_perf_status & 0xff);
  844. seq_printf(m, "Render p-state limit: %d\n",
  845. rp_state_limits & 0xff);
  846. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  847. GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
  848. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  849. GEN6_CURICONT_MASK);
  850. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  851. GEN6_CURBSYTAVG_MASK);
  852. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  853. GEN6_CURBSYTAVG_MASK);
  854. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  855. GEN6_CURIAVG_MASK);
  856. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  857. GEN6_CURBSYTAVG_MASK);
  858. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  859. GEN6_CURBSYTAVG_MASK);
  860. max_freq = (rp_state_cap & 0xff0000) >> 16;
  861. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  862. max_freq * GT_FREQUENCY_MULTIPLIER);
  863. max_freq = (rp_state_cap & 0xff00) >> 8;
  864. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  865. max_freq * GT_FREQUENCY_MULTIPLIER);
  866. max_freq = rp_state_cap & 0xff;
  867. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  868. max_freq * GT_FREQUENCY_MULTIPLIER);
  869. } else {
  870. seq_printf(m, "no P-state info available\n");
  871. }
  872. return 0;
  873. }
  874. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  875. {
  876. struct drm_info_node *node = (struct drm_info_node *) m->private;
  877. struct drm_device *dev = node->minor->dev;
  878. drm_i915_private_t *dev_priv = dev->dev_private;
  879. u32 delayfreq;
  880. int ret, i;
  881. ret = mutex_lock_interruptible(&dev->struct_mutex);
  882. if (ret)
  883. return ret;
  884. for (i = 0; i < 16; i++) {
  885. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  886. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  887. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  888. }
  889. mutex_unlock(&dev->struct_mutex);
  890. return 0;
  891. }
  892. static inline int MAP_TO_MV(int map)
  893. {
  894. return 1250 - (map * 25);
  895. }
  896. static int i915_inttoext_table(struct seq_file *m, void *unused)
  897. {
  898. struct drm_info_node *node = (struct drm_info_node *) m->private;
  899. struct drm_device *dev = node->minor->dev;
  900. drm_i915_private_t *dev_priv = dev->dev_private;
  901. u32 inttoext;
  902. int ret, i;
  903. ret = mutex_lock_interruptible(&dev->struct_mutex);
  904. if (ret)
  905. return ret;
  906. for (i = 1; i <= 32; i++) {
  907. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  908. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  909. }
  910. mutex_unlock(&dev->struct_mutex);
  911. return 0;
  912. }
  913. static int ironlake_drpc_info(struct seq_file *m)
  914. {
  915. struct drm_info_node *node = (struct drm_info_node *) m->private;
  916. struct drm_device *dev = node->minor->dev;
  917. drm_i915_private_t *dev_priv = dev->dev_private;
  918. u32 rgvmodectl, rstdbyctl;
  919. u16 crstandvid;
  920. int ret;
  921. ret = mutex_lock_interruptible(&dev->struct_mutex);
  922. if (ret)
  923. return ret;
  924. rgvmodectl = I915_READ(MEMMODECTL);
  925. rstdbyctl = I915_READ(RSTDBYCTL);
  926. crstandvid = I915_READ16(CRSTANDVID);
  927. mutex_unlock(&dev->struct_mutex);
  928. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  929. "yes" : "no");
  930. seq_printf(m, "Boost freq: %d\n",
  931. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  932. MEMMODE_BOOST_FREQ_SHIFT);
  933. seq_printf(m, "HW control enabled: %s\n",
  934. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  935. seq_printf(m, "SW control enabled: %s\n",
  936. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  937. seq_printf(m, "Gated voltage change: %s\n",
  938. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  939. seq_printf(m, "Starting frequency: P%d\n",
  940. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  941. seq_printf(m, "Max P-state: P%d\n",
  942. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  943. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  944. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  945. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  946. seq_printf(m, "Render standby enabled: %s\n",
  947. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  948. seq_printf(m, "Current RS state: ");
  949. switch (rstdbyctl & RSX_STATUS_MASK) {
  950. case RSX_STATUS_ON:
  951. seq_printf(m, "on\n");
  952. break;
  953. case RSX_STATUS_RC1:
  954. seq_printf(m, "RC1\n");
  955. break;
  956. case RSX_STATUS_RC1E:
  957. seq_printf(m, "RC1E\n");
  958. break;
  959. case RSX_STATUS_RS1:
  960. seq_printf(m, "RS1\n");
  961. break;
  962. case RSX_STATUS_RS2:
  963. seq_printf(m, "RS2 (RC6)\n");
  964. break;
  965. case RSX_STATUS_RS3:
  966. seq_printf(m, "RC3 (RC6+)\n");
  967. break;
  968. default:
  969. seq_printf(m, "unknown\n");
  970. break;
  971. }
  972. return 0;
  973. }
  974. static int gen6_drpc_info(struct seq_file *m)
  975. {
  976. struct drm_info_node *node = (struct drm_info_node *) m->private;
  977. struct drm_device *dev = node->minor->dev;
  978. struct drm_i915_private *dev_priv = dev->dev_private;
  979. u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
  980. unsigned forcewake_count;
  981. int count=0, ret;
  982. ret = mutex_lock_interruptible(&dev->struct_mutex);
  983. if (ret)
  984. return ret;
  985. spin_lock_irq(&dev_priv->gt_lock);
  986. forcewake_count = dev_priv->forcewake_count;
  987. spin_unlock_irq(&dev_priv->gt_lock);
  988. if (forcewake_count) {
  989. seq_printf(m, "RC information inaccurate because somebody "
  990. "holds a forcewake reference \n");
  991. } else {
  992. /* NB: we cannot use forcewake, else we read the wrong values */
  993. while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  994. udelay(10);
  995. seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
  996. }
  997. gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
  998. trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
  999. rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
  1000. rcctl1 = I915_READ(GEN6_RC_CONTROL);
  1001. mutex_unlock(&dev->struct_mutex);
  1002. mutex_lock(&dev_priv->rps.hw_lock);
  1003. sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
  1004. mutex_unlock(&dev_priv->rps.hw_lock);
  1005. seq_printf(m, "Video Turbo Mode: %s\n",
  1006. yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
  1007. seq_printf(m, "HW control enabled: %s\n",
  1008. yesno(rpmodectl1 & GEN6_RP_ENABLE));
  1009. seq_printf(m, "SW control enabled: %s\n",
  1010. yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
  1011. GEN6_RP_MEDIA_SW_MODE));
  1012. seq_printf(m, "RC1e Enabled: %s\n",
  1013. yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  1014. seq_printf(m, "RC6 Enabled: %s\n",
  1015. yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
  1016. seq_printf(m, "Deep RC6 Enabled: %s\n",
  1017. yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
  1018. seq_printf(m, "Deepest RC6 Enabled: %s\n",
  1019. yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
  1020. seq_printf(m, "Current RC state: ");
  1021. switch (gt_core_status & GEN6_RCn_MASK) {
  1022. case GEN6_RC0:
  1023. if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
  1024. seq_printf(m, "Core Power Down\n");
  1025. else
  1026. seq_printf(m, "on\n");
  1027. break;
  1028. case GEN6_RC3:
  1029. seq_printf(m, "RC3\n");
  1030. break;
  1031. case GEN6_RC6:
  1032. seq_printf(m, "RC6\n");
  1033. break;
  1034. case GEN6_RC7:
  1035. seq_printf(m, "RC7\n");
  1036. break;
  1037. default:
  1038. seq_printf(m, "Unknown\n");
  1039. break;
  1040. }
  1041. seq_printf(m, "Core Power Down: %s\n",
  1042. yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
  1043. /* Not exactly sure what this is */
  1044. seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
  1045. I915_READ(GEN6_GT_GFX_RC6_LOCKED));
  1046. seq_printf(m, "RC6 residency since boot: %u\n",
  1047. I915_READ(GEN6_GT_GFX_RC6));
  1048. seq_printf(m, "RC6+ residency since boot: %u\n",
  1049. I915_READ(GEN6_GT_GFX_RC6p));
  1050. seq_printf(m, "RC6++ residency since boot: %u\n",
  1051. I915_READ(GEN6_GT_GFX_RC6pp));
  1052. seq_printf(m, "RC6 voltage: %dmV\n",
  1053. GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
  1054. seq_printf(m, "RC6+ voltage: %dmV\n",
  1055. GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
  1056. seq_printf(m, "RC6++ voltage: %dmV\n",
  1057. GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
  1058. return 0;
  1059. }
  1060. static int i915_drpc_info(struct seq_file *m, void *unused)
  1061. {
  1062. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1063. struct drm_device *dev = node->minor->dev;
  1064. if (IS_GEN6(dev) || IS_GEN7(dev))
  1065. return gen6_drpc_info(m);
  1066. else
  1067. return ironlake_drpc_info(m);
  1068. }
  1069. static int i915_fbc_status(struct seq_file *m, void *unused)
  1070. {
  1071. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1072. struct drm_device *dev = node->minor->dev;
  1073. drm_i915_private_t *dev_priv = dev->dev_private;
  1074. if (!I915_HAS_FBC(dev)) {
  1075. seq_printf(m, "FBC unsupported on this chipset\n");
  1076. return 0;
  1077. }
  1078. if (intel_fbc_enabled(dev)) {
  1079. seq_printf(m, "FBC enabled\n");
  1080. } else {
  1081. seq_printf(m, "FBC disabled: ");
  1082. switch (dev_priv->no_fbc_reason) {
  1083. case FBC_NO_OUTPUT:
  1084. seq_printf(m, "no outputs");
  1085. break;
  1086. case FBC_STOLEN_TOO_SMALL:
  1087. seq_printf(m, "not enough stolen memory");
  1088. break;
  1089. case FBC_UNSUPPORTED_MODE:
  1090. seq_printf(m, "mode not supported");
  1091. break;
  1092. case FBC_MODE_TOO_LARGE:
  1093. seq_printf(m, "mode too large");
  1094. break;
  1095. case FBC_BAD_PLANE:
  1096. seq_printf(m, "FBC unsupported on plane");
  1097. break;
  1098. case FBC_NOT_TILED:
  1099. seq_printf(m, "scanout buffer not tiled");
  1100. break;
  1101. case FBC_MULTIPLE_PIPES:
  1102. seq_printf(m, "multiple pipes are enabled");
  1103. break;
  1104. case FBC_MODULE_PARAM:
  1105. seq_printf(m, "disabled per module param (default off)");
  1106. break;
  1107. default:
  1108. seq_printf(m, "unknown reason");
  1109. }
  1110. seq_printf(m, "\n");
  1111. }
  1112. return 0;
  1113. }
  1114. static int i915_sr_status(struct seq_file *m, void *unused)
  1115. {
  1116. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1117. struct drm_device *dev = node->minor->dev;
  1118. drm_i915_private_t *dev_priv = dev->dev_private;
  1119. bool sr_enabled = false;
  1120. if (HAS_PCH_SPLIT(dev))
  1121. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  1122. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  1123. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  1124. else if (IS_I915GM(dev))
  1125. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  1126. else if (IS_PINEVIEW(dev))
  1127. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  1128. seq_printf(m, "self-refresh: %s\n",
  1129. sr_enabled ? "enabled" : "disabled");
  1130. return 0;
  1131. }
  1132. static int i915_emon_status(struct seq_file *m, void *unused)
  1133. {
  1134. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1135. struct drm_device *dev = node->minor->dev;
  1136. drm_i915_private_t *dev_priv = dev->dev_private;
  1137. unsigned long temp, chipset, gfx;
  1138. int ret;
  1139. if (!IS_GEN5(dev))
  1140. return -ENODEV;
  1141. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1142. if (ret)
  1143. return ret;
  1144. temp = i915_mch_val(dev_priv);
  1145. chipset = i915_chipset_val(dev_priv);
  1146. gfx = i915_gfx_val(dev_priv);
  1147. mutex_unlock(&dev->struct_mutex);
  1148. seq_printf(m, "GMCH temp: %ld\n", temp);
  1149. seq_printf(m, "Chipset power: %ld\n", chipset);
  1150. seq_printf(m, "GFX power: %ld\n", gfx);
  1151. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1152. return 0;
  1153. }
  1154. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1155. {
  1156. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1157. struct drm_device *dev = node->minor->dev;
  1158. drm_i915_private_t *dev_priv = dev->dev_private;
  1159. int ret;
  1160. int gpu_freq, ia_freq;
  1161. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1162. seq_printf(m, "unsupported on this chipset\n");
  1163. return 0;
  1164. }
  1165. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1166. if (ret)
  1167. return ret;
  1168. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1169. for (gpu_freq = dev_priv->rps.min_delay;
  1170. gpu_freq <= dev_priv->rps.max_delay;
  1171. gpu_freq++) {
  1172. ia_freq = gpu_freq;
  1173. sandybridge_pcode_read(dev_priv,
  1174. GEN6_PCODE_READ_MIN_FREQ_TABLE,
  1175. &ia_freq);
  1176. seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
  1177. }
  1178. mutex_unlock(&dev_priv->rps.hw_lock);
  1179. return 0;
  1180. }
  1181. static int i915_gfxec(struct seq_file *m, void *unused)
  1182. {
  1183. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1184. struct drm_device *dev = node->minor->dev;
  1185. drm_i915_private_t *dev_priv = dev->dev_private;
  1186. int ret;
  1187. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1188. if (ret)
  1189. return ret;
  1190. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1191. mutex_unlock(&dev->struct_mutex);
  1192. return 0;
  1193. }
  1194. static int i915_opregion(struct seq_file *m, void *unused)
  1195. {
  1196. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1197. struct drm_device *dev = node->minor->dev;
  1198. drm_i915_private_t *dev_priv = dev->dev_private;
  1199. struct intel_opregion *opregion = &dev_priv->opregion;
  1200. void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
  1201. int ret;
  1202. if (data == NULL)
  1203. return -ENOMEM;
  1204. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1205. if (ret)
  1206. goto out;
  1207. if (opregion->header) {
  1208. memcpy_fromio(data, opregion->header, OPREGION_SIZE);
  1209. seq_write(m, data, OPREGION_SIZE);
  1210. }
  1211. mutex_unlock(&dev->struct_mutex);
  1212. out:
  1213. kfree(data);
  1214. return 0;
  1215. }
  1216. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1217. {
  1218. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1219. struct drm_device *dev = node->minor->dev;
  1220. drm_i915_private_t *dev_priv = dev->dev_private;
  1221. struct intel_fbdev *ifbdev;
  1222. struct intel_framebuffer *fb;
  1223. int ret;
  1224. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1225. if (ret)
  1226. return ret;
  1227. ifbdev = dev_priv->fbdev;
  1228. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1229. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1230. fb->base.width,
  1231. fb->base.height,
  1232. fb->base.depth,
  1233. fb->base.bits_per_pixel);
  1234. describe_obj(m, fb->obj);
  1235. seq_printf(m, "\n");
  1236. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1237. if (&fb->base == ifbdev->helper.fb)
  1238. continue;
  1239. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1240. fb->base.width,
  1241. fb->base.height,
  1242. fb->base.depth,
  1243. fb->base.bits_per_pixel);
  1244. describe_obj(m, fb->obj);
  1245. seq_printf(m, "\n");
  1246. }
  1247. mutex_unlock(&dev->mode_config.mutex);
  1248. return 0;
  1249. }
  1250. static int i915_context_status(struct seq_file *m, void *unused)
  1251. {
  1252. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1253. struct drm_device *dev = node->minor->dev;
  1254. drm_i915_private_t *dev_priv = dev->dev_private;
  1255. int ret;
  1256. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1257. if (ret)
  1258. return ret;
  1259. if (dev_priv->ips.pwrctx) {
  1260. seq_printf(m, "power context ");
  1261. describe_obj(m, dev_priv->ips.pwrctx);
  1262. seq_printf(m, "\n");
  1263. }
  1264. if (dev_priv->ips.renderctx) {
  1265. seq_printf(m, "render context ");
  1266. describe_obj(m, dev_priv->ips.renderctx);
  1267. seq_printf(m, "\n");
  1268. }
  1269. mutex_unlock(&dev->mode_config.mutex);
  1270. return 0;
  1271. }
  1272. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1273. {
  1274. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1275. struct drm_device *dev = node->minor->dev;
  1276. struct drm_i915_private *dev_priv = dev->dev_private;
  1277. unsigned forcewake_count;
  1278. spin_lock_irq(&dev_priv->gt_lock);
  1279. forcewake_count = dev_priv->forcewake_count;
  1280. spin_unlock_irq(&dev_priv->gt_lock);
  1281. seq_printf(m, "forcewake count = %u\n", forcewake_count);
  1282. return 0;
  1283. }
  1284. static const char *swizzle_string(unsigned swizzle)
  1285. {
  1286. switch(swizzle) {
  1287. case I915_BIT_6_SWIZZLE_NONE:
  1288. return "none";
  1289. case I915_BIT_6_SWIZZLE_9:
  1290. return "bit9";
  1291. case I915_BIT_6_SWIZZLE_9_10:
  1292. return "bit9/bit10";
  1293. case I915_BIT_6_SWIZZLE_9_11:
  1294. return "bit9/bit11";
  1295. case I915_BIT_6_SWIZZLE_9_10_11:
  1296. return "bit9/bit10/bit11";
  1297. case I915_BIT_6_SWIZZLE_9_17:
  1298. return "bit9/bit17";
  1299. case I915_BIT_6_SWIZZLE_9_10_17:
  1300. return "bit9/bit10/bit17";
  1301. case I915_BIT_6_SWIZZLE_UNKNOWN:
  1302. return "unkown";
  1303. }
  1304. return "bug";
  1305. }
  1306. static int i915_swizzle_info(struct seq_file *m, void *data)
  1307. {
  1308. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1309. struct drm_device *dev = node->minor->dev;
  1310. struct drm_i915_private *dev_priv = dev->dev_private;
  1311. int ret;
  1312. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1313. if (ret)
  1314. return ret;
  1315. seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
  1316. swizzle_string(dev_priv->mm.bit_6_swizzle_x));
  1317. seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
  1318. swizzle_string(dev_priv->mm.bit_6_swizzle_y));
  1319. if (IS_GEN3(dev) || IS_GEN4(dev)) {
  1320. seq_printf(m, "DDC = 0x%08x\n",
  1321. I915_READ(DCC));
  1322. seq_printf(m, "C0DRB3 = 0x%04x\n",
  1323. I915_READ16(C0DRB3));
  1324. seq_printf(m, "C1DRB3 = 0x%04x\n",
  1325. I915_READ16(C1DRB3));
  1326. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  1327. seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
  1328. I915_READ(MAD_DIMM_C0));
  1329. seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
  1330. I915_READ(MAD_DIMM_C1));
  1331. seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
  1332. I915_READ(MAD_DIMM_C2));
  1333. seq_printf(m, "TILECTL = 0x%08x\n",
  1334. I915_READ(TILECTL));
  1335. seq_printf(m, "ARB_MODE = 0x%08x\n",
  1336. I915_READ(ARB_MODE));
  1337. seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
  1338. I915_READ(DISP_ARB_CTL));
  1339. }
  1340. mutex_unlock(&dev->struct_mutex);
  1341. return 0;
  1342. }
  1343. static int i915_ppgtt_info(struct seq_file *m, void *data)
  1344. {
  1345. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1346. struct drm_device *dev = node->minor->dev;
  1347. struct drm_i915_private *dev_priv = dev->dev_private;
  1348. struct intel_ring_buffer *ring;
  1349. int i, ret;
  1350. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1351. if (ret)
  1352. return ret;
  1353. if (INTEL_INFO(dev)->gen == 6)
  1354. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  1355. for_each_ring(ring, dev_priv, i) {
  1356. seq_printf(m, "%s\n", ring->name);
  1357. if (INTEL_INFO(dev)->gen == 7)
  1358. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
  1359. seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
  1360. seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
  1361. seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
  1362. }
  1363. if (dev_priv->mm.aliasing_ppgtt) {
  1364. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1365. seq_printf(m, "aliasing PPGTT:\n");
  1366. seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
  1367. }
  1368. seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
  1369. mutex_unlock(&dev->struct_mutex);
  1370. return 0;
  1371. }
  1372. static int i915_dpio_info(struct seq_file *m, void *data)
  1373. {
  1374. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1375. struct drm_device *dev = node->minor->dev;
  1376. struct drm_i915_private *dev_priv = dev->dev_private;
  1377. int ret;
  1378. if (!IS_VALLEYVIEW(dev)) {
  1379. seq_printf(m, "unsupported\n");
  1380. return 0;
  1381. }
  1382. ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
  1383. if (ret)
  1384. return ret;
  1385. seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
  1386. seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
  1387. intel_dpio_read(dev_priv, _DPIO_DIV_A));
  1388. seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
  1389. intel_dpio_read(dev_priv, _DPIO_DIV_B));
  1390. seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
  1391. intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
  1392. seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
  1393. intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
  1394. seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
  1395. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
  1396. seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
  1397. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
  1398. seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
  1399. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
  1400. seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
  1401. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
  1402. seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
  1403. intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
  1404. mutex_unlock(&dev_priv->dpio_lock);
  1405. return 0;
  1406. }
  1407. static ssize_t
  1408. i915_wedged_read(struct file *filp,
  1409. char __user *ubuf,
  1410. size_t max,
  1411. loff_t *ppos)
  1412. {
  1413. struct drm_device *dev = filp->private_data;
  1414. drm_i915_private_t *dev_priv = dev->dev_private;
  1415. char buf[80];
  1416. int len;
  1417. len = snprintf(buf, sizeof(buf),
  1418. "wedged : %d\n",
  1419. atomic_read(&dev_priv->mm.wedged));
  1420. if (len > sizeof(buf))
  1421. len = sizeof(buf);
  1422. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1423. }
  1424. static ssize_t
  1425. i915_wedged_write(struct file *filp,
  1426. const char __user *ubuf,
  1427. size_t cnt,
  1428. loff_t *ppos)
  1429. {
  1430. struct drm_device *dev = filp->private_data;
  1431. char buf[20];
  1432. int val = 1;
  1433. if (cnt > 0) {
  1434. if (cnt > sizeof(buf) - 1)
  1435. return -EINVAL;
  1436. if (copy_from_user(buf, ubuf, cnt))
  1437. return -EFAULT;
  1438. buf[cnt] = 0;
  1439. val = simple_strtoul(buf, NULL, 0);
  1440. }
  1441. DRM_INFO("Manually setting wedged to %d\n", val);
  1442. i915_handle_error(dev, val);
  1443. return cnt;
  1444. }
  1445. static const struct file_operations i915_wedged_fops = {
  1446. .owner = THIS_MODULE,
  1447. .open = simple_open,
  1448. .read = i915_wedged_read,
  1449. .write = i915_wedged_write,
  1450. .llseek = default_llseek,
  1451. };
  1452. static ssize_t
  1453. i915_ring_stop_read(struct file *filp,
  1454. char __user *ubuf,
  1455. size_t max,
  1456. loff_t *ppos)
  1457. {
  1458. struct drm_device *dev = filp->private_data;
  1459. drm_i915_private_t *dev_priv = dev->dev_private;
  1460. char buf[20];
  1461. int len;
  1462. len = snprintf(buf, sizeof(buf),
  1463. "0x%08x\n", dev_priv->stop_rings);
  1464. if (len > sizeof(buf))
  1465. len = sizeof(buf);
  1466. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1467. }
  1468. static ssize_t
  1469. i915_ring_stop_write(struct file *filp,
  1470. const char __user *ubuf,
  1471. size_t cnt,
  1472. loff_t *ppos)
  1473. {
  1474. struct drm_device *dev = filp->private_data;
  1475. struct drm_i915_private *dev_priv = dev->dev_private;
  1476. char buf[20];
  1477. int val = 0, ret;
  1478. if (cnt > 0) {
  1479. if (cnt > sizeof(buf) - 1)
  1480. return -EINVAL;
  1481. if (copy_from_user(buf, ubuf, cnt))
  1482. return -EFAULT;
  1483. buf[cnt] = 0;
  1484. val = simple_strtoul(buf, NULL, 0);
  1485. }
  1486. DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
  1487. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1488. if (ret)
  1489. return ret;
  1490. dev_priv->stop_rings = val;
  1491. mutex_unlock(&dev->struct_mutex);
  1492. return cnt;
  1493. }
  1494. static const struct file_operations i915_ring_stop_fops = {
  1495. .owner = THIS_MODULE,
  1496. .open = simple_open,
  1497. .read = i915_ring_stop_read,
  1498. .write = i915_ring_stop_write,
  1499. .llseek = default_llseek,
  1500. };
  1501. static ssize_t
  1502. i915_max_freq_read(struct file *filp,
  1503. char __user *ubuf,
  1504. size_t max,
  1505. loff_t *ppos)
  1506. {
  1507. struct drm_device *dev = filp->private_data;
  1508. drm_i915_private_t *dev_priv = dev->dev_private;
  1509. char buf[80];
  1510. int len, ret;
  1511. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1512. return -ENODEV;
  1513. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1514. if (ret)
  1515. return ret;
  1516. len = snprintf(buf, sizeof(buf),
  1517. "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
  1518. mutex_unlock(&dev_priv->rps.hw_lock);
  1519. if (len > sizeof(buf))
  1520. len = sizeof(buf);
  1521. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1522. }
  1523. static ssize_t
  1524. i915_max_freq_write(struct file *filp,
  1525. const char __user *ubuf,
  1526. size_t cnt,
  1527. loff_t *ppos)
  1528. {
  1529. struct drm_device *dev = filp->private_data;
  1530. struct drm_i915_private *dev_priv = dev->dev_private;
  1531. char buf[20];
  1532. int val = 1, ret;
  1533. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1534. return -ENODEV;
  1535. if (cnt > 0) {
  1536. if (cnt > sizeof(buf) - 1)
  1537. return -EINVAL;
  1538. if (copy_from_user(buf, ubuf, cnt))
  1539. return -EFAULT;
  1540. buf[cnt] = 0;
  1541. val = simple_strtoul(buf, NULL, 0);
  1542. }
  1543. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1544. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1545. if (ret)
  1546. return ret;
  1547. /*
  1548. * Turbo will still be enabled, but won't go above the set value.
  1549. */
  1550. dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
  1551. gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
  1552. mutex_unlock(&dev_priv->rps.hw_lock);
  1553. return cnt;
  1554. }
  1555. static const struct file_operations i915_max_freq_fops = {
  1556. .owner = THIS_MODULE,
  1557. .open = simple_open,
  1558. .read = i915_max_freq_read,
  1559. .write = i915_max_freq_write,
  1560. .llseek = default_llseek,
  1561. };
  1562. static ssize_t
  1563. i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
  1564. loff_t *ppos)
  1565. {
  1566. struct drm_device *dev = filp->private_data;
  1567. drm_i915_private_t *dev_priv = dev->dev_private;
  1568. char buf[80];
  1569. int len, ret;
  1570. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1571. return -ENODEV;
  1572. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1573. if (ret)
  1574. return ret;
  1575. len = snprintf(buf, sizeof(buf),
  1576. "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
  1577. mutex_unlock(&dev_priv->rps.hw_lock);
  1578. if (len > sizeof(buf))
  1579. len = sizeof(buf);
  1580. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1581. }
  1582. static ssize_t
  1583. i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
  1584. loff_t *ppos)
  1585. {
  1586. struct drm_device *dev = filp->private_data;
  1587. struct drm_i915_private *dev_priv = dev->dev_private;
  1588. char buf[20];
  1589. int val = 1, ret;
  1590. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1591. return -ENODEV;
  1592. if (cnt > 0) {
  1593. if (cnt > sizeof(buf) - 1)
  1594. return -EINVAL;
  1595. if (copy_from_user(buf, ubuf, cnt))
  1596. return -EFAULT;
  1597. buf[cnt] = 0;
  1598. val = simple_strtoul(buf, NULL, 0);
  1599. }
  1600. DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
  1601. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1602. if (ret)
  1603. return ret;
  1604. /*
  1605. * Turbo will still be enabled, but won't go below the set value.
  1606. */
  1607. dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
  1608. gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
  1609. mutex_unlock(&dev_priv->rps.hw_lock);
  1610. return cnt;
  1611. }
  1612. static const struct file_operations i915_min_freq_fops = {
  1613. .owner = THIS_MODULE,
  1614. .open = simple_open,
  1615. .read = i915_min_freq_read,
  1616. .write = i915_min_freq_write,
  1617. .llseek = default_llseek,
  1618. };
  1619. static ssize_t
  1620. i915_cache_sharing_read(struct file *filp,
  1621. char __user *ubuf,
  1622. size_t max,
  1623. loff_t *ppos)
  1624. {
  1625. struct drm_device *dev = filp->private_data;
  1626. drm_i915_private_t *dev_priv = dev->dev_private;
  1627. char buf[80];
  1628. u32 snpcr;
  1629. int len, ret;
  1630. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1631. return -ENODEV;
  1632. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1633. if (ret)
  1634. return ret;
  1635. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1636. mutex_unlock(&dev_priv->dev->struct_mutex);
  1637. len = snprintf(buf, sizeof(buf),
  1638. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1639. GEN6_MBC_SNPCR_SHIFT);
  1640. if (len > sizeof(buf))
  1641. len = sizeof(buf);
  1642. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1643. }
  1644. static ssize_t
  1645. i915_cache_sharing_write(struct file *filp,
  1646. const char __user *ubuf,
  1647. size_t cnt,
  1648. loff_t *ppos)
  1649. {
  1650. struct drm_device *dev = filp->private_data;
  1651. struct drm_i915_private *dev_priv = dev->dev_private;
  1652. char buf[20];
  1653. u32 snpcr;
  1654. int val = 1;
  1655. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1656. return -ENODEV;
  1657. if (cnt > 0) {
  1658. if (cnt > sizeof(buf) - 1)
  1659. return -EINVAL;
  1660. if (copy_from_user(buf, ubuf, cnt))
  1661. return -EFAULT;
  1662. buf[cnt] = 0;
  1663. val = simple_strtoul(buf, NULL, 0);
  1664. }
  1665. if (val < 0 || val > 3)
  1666. return -EINVAL;
  1667. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1668. /* Update the cache sharing policy here as well */
  1669. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1670. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1671. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1672. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1673. return cnt;
  1674. }
  1675. static const struct file_operations i915_cache_sharing_fops = {
  1676. .owner = THIS_MODULE,
  1677. .open = simple_open,
  1678. .read = i915_cache_sharing_read,
  1679. .write = i915_cache_sharing_write,
  1680. .llseek = default_llseek,
  1681. };
  1682. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1683. * allocated we need to hook into the minor for release. */
  1684. static int
  1685. drm_add_fake_info_node(struct drm_minor *minor,
  1686. struct dentry *ent,
  1687. const void *key)
  1688. {
  1689. struct drm_info_node *node;
  1690. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1691. if (node == NULL) {
  1692. debugfs_remove(ent);
  1693. return -ENOMEM;
  1694. }
  1695. node->minor = minor;
  1696. node->dent = ent;
  1697. node->info_ent = (void *) key;
  1698. mutex_lock(&minor->debugfs_lock);
  1699. list_add(&node->list, &minor->debugfs_list);
  1700. mutex_unlock(&minor->debugfs_lock);
  1701. return 0;
  1702. }
  1703. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1704. {
  1705. struct drm_device *dev = inode->i_private;
  1706. struct drm_i915_private *dev_priv = dev->dev_private;
  1707. if (INTEL_INFO(dev)->gen < 6)
  1708. return 0;
  1709. gen6_gt_force_wake_get(dev_priv);
  1710. return 0;
  1711. }
  1712. static int i915_forcewake_release(struct inode *inode, struct file *file)
  1713. {
  1714. struct drm_device *dev = inode->i_private;
  1715. struct drm_i915_private *dev_priv = dev->dev_private;
  1716. if (INTEL_INFO(dev)->gen < 6)
  1717. return 0;
  1718. gen6_gt_force_wake_put(dev_priv);
  1719. return 0;
  1720. }
  1721. static const struct file_operations i915_forcewake_fops = {
  1722. .owner = THIS_MODULE,
  1723. .open = i915_forcewake_open,
  1724. .release = i915_forcewake_release,
  1725. };
  1726. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1727. {
  1728. struct drm_device *dev = minor->dev;
  1729. struct dentry *ent;
  1730. ent = debugfs_create_file("i915_forcewake_user",
  1731. S_IRUSR,
  1732. root, dev,
  1733. &i915_forcewake_fops);
  1734. if (IS_ERR(ent))
  1735. return PTR_ERR(ent);
  1736. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1737. }
  1738. static int i915_debugfs_create(struct dentry *root,
  1739. struct drm_minor *minor,
  1740. const char *name,
  1741. const struct file_operations *fops)
  1742. {
  1743. struct drm_device *dev = minor->dev;
  1744. struct dentry *ent;
  1745. ent = debugfs_create_file(name,
  1746. S_IRUGO | S_IWUSR,
  1747. root, dev,
  1748. fops);
  1749. if (IS_ERR(ent))
  1750. return PTR_ERR(ent);
  1751. return drm_add_fake_info_node(minor, ent, fops);
  1752. }
  1753. static struct drm_info_list i915_debugfs_list[] = {
  1754. {"i915_capabilities", i915_capabilities, 0},
  1755. {"i915_gem_objects", i915_gem_object_info, 0},
  1756. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1757. {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
  1758. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1759. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1760. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1761. {"i915_gem_request", i915_gem_request_info, 0},
  1762. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1763. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1764. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1765. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1766. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1767. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1768. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1769. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1770. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1771. {"i915_inttoext_table", i915_inttoext_table, 0},
  1772. {"i915_drpc_info", i915_drpc_info, 0},
  1773. {"i915_emon_status", i915_emon_status, 0},
  1774. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1775. {"i915_gfxec", i915_gfxec, 0},
  1776. {"i915_fbc_status", i915_fbc_status, 0},
  1777. {"i915_sr_status", i915_sr_status, 0},
  1778. {"i915_opregion", i915_opregion, 0},
  1779. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1780. {"i915_context_status", i915_context_status, 0},
  1781. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1782. {"i915_swizzle_info", i915_swizzle_info, 0},
  1783. {"i915_ppgtt_info", i915_ppgtt_info, 0},
  1784. {"i915_dpio", i915_dpio_info, 0},
  1785. };
  1786. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1787. int i915_debugfs_init(struct drm_minor *minor)
  1788. {
  1789. int ret;
  1790. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1791. "i915_wedged",
  1792. &i915_wedged_fops);
  1793. if (ret)
  1794. return ret;
  1795. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1796. if (ret)
  1797. return ret;
  1798. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1799. "i915_max_freq",
  1800. &i915_max_freq_fops);
  1801. if (ret)
  1802. return ret;
  1803. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1804. "i915_min_freq",
  1805. &i915_min_freq_fops);
  1806. if (ret)
  1807. return ret;
  1808. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1809. "i915_cache_sharing",
  1810. &i915_cache_sharing_fops);
  1811. if (ret)
  1812. return ret;
  1813. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1814. "i915_ring_stop",
  1815. &i915_ring_stop_fops);
  1816. if (ret)
  1817. return ret;
  1818. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1819. "i915_error_state",
  1820. &i915_error_state_fops);
  1821. if (ret)
  1822. return ret;
  1823. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1824. "i915_next_seqno",
  1825. &i915_next_seqno_fops);
  1826. if (ret)
  1827. return ret;
  1828. return drm_debugfs_create_files(i915_debugfs_list,
  1829. I915_DEBUGFS_ENTRIES,
  1830. minor->debugfs_root, minor);
  1831. }
  1832. void i915_debugfs_cleanup(struct drm_minor *minor)
  1833. {
  1834. drm_debugfs_remove_files(i915_debugfs_list,
  1835. I915_DEBUGFS_ENTRIES, minor);
  1836. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1837. 1, minor);
  1838. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1839. 1, minor);
  1840. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1841. 1, minor);
  1842. drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
  1843. 1, minor);
  1844. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1845. 1, minor);
  1846. drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
  1847. 1, minor);
  1848. drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
  1849. 1, minor);
  1850. drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
  1851. 1, minor);
  1852. }
  1853. #endif /* CONFIG_DEBUG_FS */