devices.c 7.4 KB

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  1. /*
  2. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor,
  17. * Boston, MA 02110-1301, USA.
  18. */
  19. #include <linux/dma-mapping.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/serial.h>
  23. #include <linux/gpio.h>
  24. #include <mach/hardware.h>
  25. #include <mach/irqs.h>
  26. #include <mach/common.h>
  27. #include <mach/mx3_camera.h>
  28. #include "devices.h"
  29. #ifdef CONFIG_ARCH_MX31
  30. static struct resource mxcsdhc0_resources[] = {
  31. {
  32. .start = MX31_MMC_SDHC1_BASE_ADDR,
  33. .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
  34. .flags = IORESOURCE_MEM,
  35. }, {
  36. .start = MX31_INT_MMC_SDHC1,
  37. .end = MX31_INT_MMC_SDHC1,
  38. .flags = IORESOURCE_IRQ,
  39. },
  40. };
  41. static struct resource mxcsdhc1_resources[] = {
  42. {
  43. .start = MX31_MMC_SDHC2_BASE_ADDR,
  44. .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
  45. .flags = IORESOURCE_MEM,
  46. }, {
  47. .start = MX31_INT_MMC_SDHC2,
  48. .end = MX31_INT_MMC_SDHC2,
  49. .flags = IORESOURCE_IRQ,
  50. },
  51. };
  52. struct platform_device mxcsdhc_device0 = {
  53. .name = "mxc-mmc",
  54. .id = 0,
  55. .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
  56. .resource = mxcsdhc0_resources,
  57. };
  58. struct platform_device mxcsdhc_device1 = {
  59. .name = "mxc-mmc",
  60. .id = 1,
  61. .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
  62. .resource = mxcsdhc1_resources,
  63. };
  64. static struct resource rnga_resources[] = {
  65. {
  66. .start = MX3x_RNGA_BASE_ADDR,
  67. .end = MX3x_RNGA_BASE_ADDR + 0x28,
  68. .flags = IORESOURCE_MEM,
  69. },
  70. };
  71. struct platform_device mxc_rnga_device = {
  72. .name = "mxc_rnga",
  73. .id = -1,
  74. .num_resources = 1,
  75. .resource = rnga_resources,
  76. };
  77. #endif /* CONFIG_ARCH_MX31 */
  78. /* i.MX31 Image Processing Unit */
  79. /* The resource order is important! */
  80. static struct resource mx3_ipu_rsrc[] = {
  81. {
  82. .start = MX3x_IPU_CTRL_BASE_ADDR,
  83. .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
  84. .flags = IORESOURCE_MEM,
  85. }, {
  86. .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
  87. .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
  88. .flags = IORESOURCE_MEM,
  89. }, {
  90. .start = MX3x_INT_IPU_SYN,
  91. .end = MX3x_INT_IPU_SYN,
  92. .flags = IORESOURCE_IRQ,
  93. }, {
  94. .start = MX3x_INT_IPU_ERR,
  95. .end = MX3x_INT_IPU_ERR,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. struct platform_device mx3_ipu = {
  100. .name = "ipu-core",
  101. .id = -1,
  102. .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
  103. .resource = mx3_ipu_rsrc,
  104. };
  105. static struct resource fb_resources[] = {
  106. {
  107. .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
  108. .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
  109. .flags = IORESOURCE_MEM,
  110. },
  111. };
  112. struct platform_device mx3_fb = {
  113. .name = "mx3_sdc_fb",
  114. .id = -1,
  115. .num_resources = ARRAY_SIZE(fb_resources),
  116. .resource = fb_resources,
  117. .dev = {
  118. .coherent_dma_mask = DMA_BIT_MASK(32),
  119. },
  120. };
  121. static struct resource camera_resources[] = {
  122. {
  123. .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
  124. .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
  125. .flags = IORESOURCE_MEM,
  126. },
  127. };
  128. struct platform_device mx3_camera = {
  129. .name = "mx3-camera",
  130. .id = 0,
  131. .num_resources = ARRAY_SIZE(camera_resources),
  132. .resource = camera_resources,
  133. .dev = {
  134. .coherent_dma_mask = DMA_BIT_MASK(32),
  135. },
  136. };
  137. static struct resource otg_resources[] = {
  138. {
  139. .start = MX31_OTG_BASE_ADDR,
  140. .end = MX31_OTG_BASE_ADDR + 0x1ff,
  141. .flags = IORESOURCE_MEM,
  142. }, {
  143. .start = MX31_INT_USB3,
  144. .end = MX31_INT_USB3,
  145. .flags = IORESOURCE_IRQ,
  146. },
  147. };
  148. static u64 otg_dmamask = DMA_BIT_MASK(32);
  149. /* OTG gadget device */
  150. struct platform_device mxc_otg_udc_device = {
  151. .name = "fsl-usb2-udc",
  152. .id = -1,
  153. .dev = {
  154. .dma_mask = &otg_dmamask,
  155. .coherent_dma_mask = DMA_BIT_MASK(32),
  156. },
  157. .resource = otg_resources,
  158. .num_resources = ARRAY_SIZE(otg_resources),
  159. };
  160. /* OTG host */
  161. struct platform_device mxc_otg_host = {
  162. .name = "mxc-ehci",
  163. .id = 0,
  164. .dev = {
  165. .coherent_dma_mask = 0xffffffff,
  166. .dma_mask = &otg_dmamask,
  167. },
  168. .resource = otg_resources,
  169. .num_resources = ARRAY_SIZE(otg_resources),
  170. };
  171. /* USB host 1 */
  172. static u64 usbh1_dmamask = ~(u32)0;
  173. static struct resource mxc_usbh1_resources[] = {
  174. {
  175. .start = MX31_OTG_BASE_ADDR + 0x200,
  176. .end = MX31_OTG_BASE_ADDR + 0x3ff,
  177. .flags = IORESOURCE_MEM,
  178. }, {
  179. .start = MX31_INT_USB1,
  180. .end = MX31_INT_USB1,
  181. .flags = IORESOURCE_IRQ,
  182. },
  183. };
  184. struct platform_device mxc_usbh1 = {
  185. .name = "mxc-ehci",
  186. .id = 1,
  187. .dev = {
  188. .coherent_dma_mask = 0xffffffff,
  189. .dma_mask = &usbh1_dmamask,
  190. },
  191. .resource = mxc_usbh1_resources,
  192. .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
  193. };
  194. #ifdef CONFIG_ARCH_MX31
  195. /* USB host 2 */
  196. static u64 usbh2_dmamask = ~(u32)0;
  197. static struct resource mxc_usbh2_resources[] = {
  198. {
  199. .start = MX31_OTG_BASE_ADDR + 0x400,
  200. .end = MX31_OTG_BASE_ADDR + 0x5ff,
  201. .flags = IORESOURCE_MEM,
  202. }, {
  203. .start = MX31_INT_USB2,
  204. .end = MX31_INT_USB2,
  205. .flags = IORESOURCE_IRQ,
  206. },
  207. };
  208. struct platform_device mxc_usbh2 = {
  209. .name = "mxc-ehci",
  210. .id = 2,
  211. .dev = {
  212. .coherent_dma_mask = 0xffffffff,
  213. .dma_mask = &usbh2_dmamask,
  214. },
  215. .resource = mxc_usbh2_resources,
  216. .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
  217. };
  218. #endif
  219. static struct resource imx_wdt_resources[] = {
  220. {
  221. .flags = IORESOURCE_MEM,
  222. },
  223. };
  224. struct platform_device imx_wdt_device0 = {
  225. .name = "imx2-wdt",
  226. .id = 0,
  227. .num_resources = ARRAY_SIZE(imx_wdt_resources),
  228. .resource = imx_wdt_resources,
  229. };
  230. static struct resource imx_rtc_resources[] = {
  231. {
  232. .start = MX31_RTC_BASE_ADDR,
  233. .end = MX31_RTC_BASE_ADDR + 0x3fff,
  234. .flags = IORESOURCE_MEM,
  235. },
  236. {
  237. .start = MX31_INT_RTC,
  238. .flags = IORESOURCE_IRQ,
  239. },
  240. };
  241. struct platform_device imx_rtc_device0 = {
  242. .name = "mxc_rtc",
  243. .id = -1,
  244. .num_resources = ARRAY_SIZE(imx_rtc_resources),
  245. .resource = imx_rtc_resources,
  246. };
  247. static struct resource imx_kpp_resources[] = {
  248. {
  249. .start = MX3x_KPP_BASE_ADDR,
  250. .end = MX3x_KPP_BASE_ADDR + 0xf,
  251. .flags = IORESOURCE_MEM
  252. }, {
  253. .start = MX3x_INT_KPP,
  254. .end = MX3x_INT_KPP,
  255. .flags = IORESOURCE_IRQ,
  256. },
  257. };
  258. struct platform_device imx_kpp_device = {
  259. .name = "imx-keypad",
  260. .id = -1,
  261. .num_resources = ARRAY_SIZE(imx_kpp_resources),
  262. .resource = imx_kpp_resources,
  263. };
  264. static int __init mx3_devices_init(void)
  265. {
  266. #if defined(CONFIG_ARCH_MX31)
  267. if (cpu_is_mx31()) {
  268. imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
  269. imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
  270. mxc_register_device(&mxc_rnga_device, NULL);
  271. }
  272. #endif
  273. #if defined(CONFIG_ARCH_MX35)
  274. if (cpu_is_mx35()) {
  275. otg_resources[0].start = MX35_OTG_BASE_ADDR;
  276. otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
  277. otg_resources[1].start = MX35_INT_USBOTG;
  278. otg_resources[1].end = MX35_INT_USBOTG;
  279. mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
  280. mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
  281. mxc_usbh1_resources[1].start = MX35_INT_USBHS;
  282. mxc_usbh1_resources[1].end = MX35_INT_USBHS;
  283. imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
  284. imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
  285. }
  286. #endif
  287. return 0;
  288. }
  289. subsys_initcall(mx3_devices_init);