iwl-agn.c 124 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/mac80211.h>
  46. #include <asm/div64.h>
  47. #define DRV_NAME "iwlagn"
  48. #include "iwl-eeprom.h"
  49. #include "iwl-dev.h"
  50. #include "iwl-core.h"
  51. #include "iwl-io.h"
  52. #include "iwl-helpers.h"
  53. #include "iwl-sta.h"
  54. #include "iwl-agn-calib.h"
  55. #include "iwl-agn.h"
  56. #include "iwl-agn-led.h"
  57. /******************************************************************************
  58. *
  59. * module boiler plate
  60. *
  61. ******************************************************************************/
  62. /*
  63. * module name, copyright, version, etc.
  64. */
  65. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  66. #ifdef CONFIG_IWLWIFI_DEBUG
  67. #define VD "d"
  68. #else
  69. #define VD
  70. #endif
  71. #define DRV_VERSION IWLWIFI_VERSION VD
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. static int iwlagn_ant_coupling;
  77. static bool iwlagn_bt_ch_announce = 1;
  78. void iwl_update_chain_flags(struct iwl_priv *priv)
  79. {
  80. struct iwl_rxon_context *ctx;
  81. if (priv->cfg->ops->hcmd->set_rxon_chain) {
  82. for_each_context(priv, ctx) {
  83. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  84. if (ctx->active.rx_chain != ctx->staging.rx_chain)
  85. iwlcore_commit_rxon(priv, ctx);
  86. }
  87. }
  88. }
  89. static void iwl_clear_free_frames(struct iwl_priv *priv)
  90. {
  91. struct list_head *element;
  92. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  93. priv->frames_count);
  94. while (!list_empty(&priv->free_frames)) {
  95. element = priv->free_frames.next;
  96. list_del(element);
  97. kfree(list_entry(element, struct iwl_frame, list));
  98. priv->frames_count--;
  99. }
  100. if (priv->frames_count) {
  101. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  102. priv->frames_count);
  103. priv->frames_count = 0;
  104. }
  105. }
  106. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  107. {
  108. struct iwl_frame *frame;
  109. struct list_head *element;
  110. if (list_empty(&priv->free_frames)) {
  111. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  112. if (!frame) {
  113. IWL_ERR(priv, "Could not allocate frame!\n");
  114. return NULL;
  115. }
  116. priv->frames_count++;
  117. return frame;
  118. }
  119. element = priv->free_frames.next;
  120. list_del(element);
  121. return list_entry(element, struct iwl_frame, list);
  122. }
  123. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  124. {
  125. memset(frame, 0, sizeof(*frame));
  126. list_add(&frame->list, &priv->free_frames);
  127. }
  128. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  129. struct ieee80211_hdr *hdr,
  130. int left)
  131. {
  132. lockdep_assert_held(&priv->mutex);
  133. if (!priv->beacon_skb)
  134. return 0;
  135. if (priv->beacon_skb->len > left)
  136. return 0;
  137. memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
  138. return priv->beacon_skb->len;
  139. }
  140. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  141. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  142. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  143. u8 *beacon, u32 frame_size)
  144. {
  145. u16 tim_idx;
  146. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  147. /*
  148. * The index is relative to frame start but we start looking at the
  149. * variable-length part of the beacon.
  150. */
  151. tim_idx = mgmt->u.beacon.variable - beacon;
  152. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  153. while ((tim_idx < (frame_size - 2)) &&
  154. (beacon[tim_idx] != WLAN_EID_TIM))
  155. tim_idx += beacon[tim_idx+1] + 2;
  156. /* If TIM field was found, set variables */
  157. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  158. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  159. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  160. } else
  161. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  162. }
  163. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  164. struct iwl_frame *frame)
  165. {
  166. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  167. u32 frame_size;
  168. u32 rate_flags;
  169. u32 rate;
  170. /*
  171. * We have to set up the TX command, the TX Beacon command, and the
  172. * beacon contents.
  173. */
  174. lockdep_assert_held(&priv->mutex);
  175. if (!priv->beacon_ctx) {
  176. IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
  177. return 0;
  178. }
  179. /* Initialize memory */
  180. tx_beacon_cmd = &frame->u.beacon;
  181. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  182. /* Set up TX beacon contents */
  183. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  184. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  185. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  186. return 0;
  187. if (!frame_size)
  188. return 0;
  189. /* Set up TX command fields */
  190. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  191. tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
  192. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  193. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  194. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  195. /* Set up TX beacon command fields */
  196. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  197. frame_size);
  198. /* Set up packet rate and flags */
  199. rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
  200. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  201. priv->hw_params.valid_tx_ant);
  202. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  203. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  204. rate_flags |= RATE_MCS_CCK_MSK;
  205. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  206. rate_flags);
  207. return sizeof(*tx_beacon_cmd) + frame_size;
  208. }
  209. int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
  210. {
  211. struct iwl_frame *frame;
  212. unsigned int frame_size;
  213. int rc;
  214. frame = iwl_get_free_frame(priv);
  215. if (!frame) {
  216. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  217. "command.\n");
  218. return -ENOMEM;
  219. }
  220. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  221. if (!frame_size) {
  222. IWL_ERR(priv, "Error configuring the beacon command\n");
  223. iwl_free_frame(priv, frame);
  224. return -EINVAL;
  225. }
  226. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  227. &frame->u.cmd[0]);
  228. iwl_free_frame(priv, frame);
  229. return rc;
  230. }
  231. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  232. {
  233. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  234. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  235. if (sizeof(dma_addr_t) > sizeof(u32))
  236. addr |=
  237. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  238. return addr;
  239. }
  240. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  241. {
  242. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  243. return le16_to_cpu(tb->hi_n_len) >> 4;
  244. }
  245. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  246. dma_addr_t addr, u16 len)
  247. {
  248. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  249. u16 hi_n_len = len << 4;
  250. put_unaligned_le32(addr, &tb->lo);
  251. if (sizeof(dma_addr_t) > sizeof(u32))
  252. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  253. tb->hi_n_len = cpu_to_le16(hi_n_len);
  254. tfd->num_tbs = idx + 1;
  255. }
  256. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  257. {
  258. return tfd->num_tbs & 0x1f;
  259. }
  260. /**
  261. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  262. * @priv - driver private data
  263. * @txq - tx queue
  264. *
  265. * Does NOT advance any TFD circular buffer read/write indexes
  266. * Does NOT free the TFD itself (which is within circular buffer)
  267. */
  268. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  269. {
  270. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  271. struct iwl_tfd *tfd;
  272. struct pci_dev *dev = priv->pci_dev;
  273. int index = txq->q.read_ptr;
  274. int i;
  275. int num_tbs;
  276. tfd = &tfd_tmp[index];
  277. /* Sanity check on number of chunks */
  278. num_tbs = iwl_tfd_get_num_tbs(tfd);
  279. if (num_tbs >= IWL_NUM_OF_TBS) {
  280. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  281. /* @todo issue fatal error, it is quite serious situation */
  282. return;
  283. }
  284. /* Unmap tx_cmd */
  285. if (num_tbs)
  286. pci_unmap_single(dev,
  287. dma_unmap_addr(&txq->meta[index], mapping),
  288. dma_unmap_len(&txq->meta[index], len),
  289. PCI_DMA_BIDIRECTIONAL);
  290. /* Unmap chunks, if any. */
  291. for (i = 1; i < num_tbs; i++)
  292. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  293. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  294. /* free SKB */
  295. if (txq->txb) {
  296. struct sk_buff *skb;
  297. skb = txq->txb[txq->q.read_ptr].skb;
  298. /* can be called from irqs-disabled context */
  299. if (skb) {
  300. dev_kfree_skb_any(skb);
  301. txq->txb[txq->q.read_ptr].skb = NULL;
  302. }
  303. }
  304. }
  305. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  306. struct iwl_tx_queue *txq,
  307. dma_addr_t addr, u16 len,
  308. u8 reset, u8 pad)
  309. {
  310. struct iwl_queue *q;
  311. struct iwl_tfd *tfd, *tfd_tmp;
  312. u32 num_tbs;
  313. q = &txq->q;
  314. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  315. tfd = &tfd_tmp[q->write_ptr];
  316. if (reset)
  317. memset(tfd, 0, sizeof(*tfd));
  318. num_tbs = iwl_tfd_get_num_tbs(tfd);
  319. /* Each TFD can point to a maximum 20 Tx buffers */
  320. if (num_tbs >= IWL_NUM_OF_TBS) {
  321. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  322. IWL_NUM_OF_TBS);
  323. return -EINVAL;
  324. }
  325. BUG_ON(addr & ~DMA_BIT_MASK(36));
  326. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  327. IWL_ERR(priv, "Unaligned address = %llx\n",
  328. (unsigned long long)addr);
  329. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  330. return 0;
  331. }
  332. /*
  333. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  334. * given Tx queue, and enable the DMA channel used for that queue.
  335. *
  336. * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  337. * channels supported in hardware.
  338. */
  339. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  340. struct iwl_tx_queue *txq)
  341. {
  342. int txq_id = txq->q.id;
  343. /* Circular buffer (TFD queue in DRAM) physical base address */
  344. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  345. txq->q.dma_addr >> 8);
  346. return 0;
  347. }
  348. static void iwl_bg_beacon_update(struct work_struct *work)
  349. {
  350. struct iwl_priv *priv =
  351. container_of(work, struct iwl_priv, beacon_update);
  352. struct sk_buff *beacon;
  353. mutex_lock(&priv->mutex);
  354. if (!priv->beacon_ctx) {
  355. IWL_ERR(priv, "updating beacon w/o beacon context!\n");
  356. goto out;
  357. }
  358. if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
  359. /*
  360. * The ucode will send beacon notifications even in
  361. * IBSS mode, but we don't want to process them. But
  362. * we need to defer the type check to here due to
  363. * requiring locking around the beacon_ctx access.
  364. */
  365. goto out;
  366. }
  367. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  368. beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
  369. if (!beacon) {
  370. IWL_ERR(priv, "update beacon failed -- keeping old\n");
  371. goto out;
  372. }
  373. /* new beacon skb is allocated every time; dispose previous.*/
  374. dev_kfree_skb(priv->beacon_skb);
  375. priv->beacon_skb = beacon;
  376. iwlagn_send_beacon_cmd(priv);
  377. out:
  378. mutex_unlock(&priv->mutex);
  379. }
  380. static void iwl_bg_bt_runtime_config(struct work_struct *work)
  381. {
  382. struct iwl_priv *priv =
  383. container_of(work, struct iwl_priv, bt_runtime_config);
  384. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  385. return;
  386. /* dont send host command if rf-kill is on */
  387. if (!iwl_is_ready_rf(priv))
  388. return;
  389. priv->cfg->ops->hcmd->send_bt_config(priv);
  390. }
  391. static void iwl_bg_bt_full_concurrency(struct work_struct *work)
  392. {
  393. struct iwl_priv *priv =
  394. container_of(work, struct iwl_priv, bt_full_concurrency);
  395. struct iwl_rxon_context *ctx;
  396. mutex_lock(&priv->mutex);
  397. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  398. goto out;
  399. /* dont send host command if rf-kill is on */
  400. if (!iwl_is_ready_rf(priv))
  401. goto out;
  402. IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
  403. priv->bt_full_concurrent ?
  404. "full concurrency" : "3-wire");
  405. /*
  406. * LQ & RXON updated cmds must be sent before BT Config cmd
  407. * to avoid 3-wire collisions
  408. */
  409. for_each_context(priv, ctx) {
  410. if (priv->cfg->ops->hcmd->set_rxon_chain)
  411. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  412. iwlcore_commit_rxon(priv, ctx);
  413. }
  414. priv->cfg->ops->hcmd->send_bt_config(priv);
  415. out:
  416. mutex_unlock(&priv->mutex);
  417. }
  418. /**
  419. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  420. *
  421. * This callback is provided in order to send a statistics request.
  422. *
  423. * This timer function is continually reset to execute within
  424. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  425. * was received. We need to ensure we receive the statistics in order
  426. * to update the temperature used for calibrating the TXPOWER.
  427. */
  428. static void iwl_bg_statistics_periodic(unsigned long data)
  429. {
  430. struct iwl_priv *priv = (struct iwl_priv *)data;
  431. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  432. return;
  433. /* dont send host command if rf-kill is on */
  434. if (!iwl_is_ready_rf(priv))
  435. return;
  436. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  437. }
  438. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  439. u32 start_idx, u32 num_events,
  440. u32 mode)
  441. {
  442. u32 i;
  443. u32 ptr; /* SRAM byte address of log data */
  444. u32 ev, time, data; /* event log data */
  445. unsigned long reg_flags;
  446. if (mode == 0)
  447. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  448. else
  449. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  450. /* Make sure device is powered up for SRAM reads */
  451. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  452. if (iwl_grab_nic_access(priv)) {
  453. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  454. return;
  455. }
  456. /* Set starting address; reads will auto-increment */
  457. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  458. rmb();
  459. /*
  460. * "time" is actually "data" for mode 0 (no timestamp).
  461. * place event id # at far right for easier visual parsing.
  462. */
  463. for (i = 0; i < num_events; i++) {
  464. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  465. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  466. if (mode == 0) {
  467. trace_iwlwifi_dev_ucode_cont_event(priv,
  468. 0, time, ev);
  469. } else {
  470. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  471. trace_iwlwifi_dev_ucode_cont_event(priv,
  472. time, data, ev);
  473. }
  474. }
  475. /* Allow device to power down */
  476. iwl_release_nic_access(priv);
  477. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  478. }
  479. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  480. {
  481. u32 capacity; /* event log capacity in # entries */
  482. u32 base; /* SRAM byte address of event log header */
  483. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  484. u32 num_wraps; /* # times uCode wrapped to top of log */
  485. u32 next_entry; /* index of next entry to be written by uCode */
  486. base = priv->device_pointers.error_event_table;
  487. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  488. capacity = iwl_read_targ_mem(priv, base);
  489. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  490. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  491. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  492. } else
  493. return;
  494. if (num_wraps == priv->event_log.num_wraps) {
  495. iwl_print_cont_event_trace(priv,
  496. base, priv->event_log.next_entry,
  497. next_entry - priv->event_log.next_entry,
  498. mode);
  499. priv->event_log.non_wraps_count++;
  500. } else {
  501. if ((num_wraps - priv->event_log.num_wraps) > 1)
  502. priv->event_log.wraps_more_count++;
  503. else
  504. priv->event_log.wraps_once_count++;
  505. trace_iwlwifi_dev_ucode_wrap_event(priv,
  506. num_wraps - priv->event_log.num_wraps,
  507. next_entry, priv->event_log.next_entry);
  508. if (next_entry < priv->event_log.next_entry) {
  509. iwl_print_cont_event_trace(priv, base,
  510. priv->event_log.next_entry,
  511. capacity - priv->event_log.next_entry,
  512. mode);
  513. iwl_print_cont_event_trace(priv, base, 0,
  514. next_entry, mode);
  515. } else {
  516. iwl_print_cont_event_trace(priv, base,
  517. next_entry, capacity - next_entry,
  518. mode);
  519. iwl_print_cont_event_trace(priv, base, 0,
  520. next_entry, mode);
  521. }
  522. }
  523. priv->event_log.num_wraps = num_wraps;
  524. priv->event_log.next_entry = next_entry;
  525. }
  526. /**
  527. * iwl_bg_ucode_trace - Timer callback to log ucode event
  528. *
  529. * The timer is continually set to execute every
  530. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  531. * this function is to perform continuous uCode event logging operation
  532. * if enabled
  533. */
  534. static void iwl_bg_ucode_trace(unsigned long data)
  535. {
  536. struct iwl_priv *priv = (struct iwl_priv *)data;
  537. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  538. return;
  539. if (priv->event_log.ucode_trace) {
  540. iwl_continuous_event_trace(priv);
  541. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  542. mod_timer(&priv->ucode_trace,
  543. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  544. }
  545. }
  546. static void iwl_bg_tx_flush(struct work_struct *work)
  547. {
  548. struct iwl_priv *priv =
  549. container_of(work, struct iwl_priv, tx_flush);
  550. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  551. return;
  552. /* do nothing if rf-kill is on */
  553. if (!iwl_is_ready_rf(priv))
  554. return;
  555. if (priv->cfg->ops->lib->txfifo_flush) {
  556. IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
  557. iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
  558. }
  559. }
  560. /**
  561. * iwl_rx_handle - Main entry function for receiving responses from uCode
  562. *
  563. * Uses the priv->rx_handlers callback function array to invoke
  564. * the appropriate handlers, including command responses,
  565. * frame-received notifications, and other notifications.
  566. */
  567. static void iwl_rx_handle(struct iwl_priv *priv)
  568. {
  569. struct iwl_rx_mem_buffer *rxb;
  570. struct iwl_rx_packet *pkt;
  571. struct iwl_rx_queue *rxq = &priv->rxq;
  572. u32 r, i;
  573. int reclaim;
  574. unsigned long flags;
  575. u8 fill_rx = 0;
  576. u32 count = 8;
  577. int total_empty;
  578. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  579. * buffer that the driver may process (last buffer filled by ucode). */
  580. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  581. i = rxq->read;
  582. /* Rx interrupt, but nothing sent from uCode */
  583. if (i == r)
  584. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  585. /* calculate total frames need to be restock after handling RX */
  586. total_empty = r - rxq->write_actual;
  587. if (total_empty < 0)
  588. total_empty += RX_QUEUE_SIZE;
  589. if (total_empty > (RX_QUEUE_SIZE / 2))
  590. fill_rx = 1;
  591. while (i != r) {
  592. int len;
  593. rxb = rxq->queue[i];
  594. /* If an RXB doesn't have a Rx queue slot associated with it,
  595. * then a bug has been introduced in the queue refilling
  596. * routines -- catch it here */
  597. BUG_ON(rxb == NULL);
  598. rxq->queue[i] = NULL;
  599. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  600. PAGE_SIZE << priv->hw_params.rx_page_order,
  601. PCI_DMA_FROMDEVICE);
  602. pkt = rxb_addr(rxb);
  603. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  604. len += sizeof(u32); /* account for status word */
  605. trace_iwlwifi_dev_rx(priv, pkt, len);
  606. /* Reclaim a command buffer only if this packet is a response
  607. * to a (driver-originated) command.
  608. * If the packet (e.g. Rx frame) originated from uCode,
  609. * there is no command buffer to reclaim.
  610. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  611. * but apparently a few don't get set; catch them here. */
  612. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  613. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  614. (pkt->hdr.cmd != REPLY_RX) &&
  615. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  616. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  617. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  618. (pkt->hdr.cmd != REPLY_TX);
  619. /*
  620. * Do the notification wait before RX handlers so
  621. * even if the RX handler consumes the RXB we have
  622. * access to it in the notification wait entry.
  623. */
  624. if (!list_empty(&priv->_agn.notif_waits)) {
  625. struct iwl_notification_wait *w;
  626. spin_lock(&priv->_agn.notif_wait_lock);
  627. list_for_each_entry(w, &priv->_agn.notif_waits, list) {
  628. if (w->cmd == pkt->hdr.cmd) {
  629. w->triggered = true;
  630. if (w->fn)
  631. w->fn(priv, pkt);
  632. }
  633. }
  634. spin_unlock(&priv->_agn.notif_wait_lock);
  635. wake_up_all(&priv->_agn.notif_waitq);
  636. }
  637. /* Based on type of command response or notification,
  638. * handle those that need handling via function in
  639. * rx_handlers table. See iwl_setup_rx_handlers() */
  640. if (priv->rx_handlers[pkt->hdr.cmd]) {
  641. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  642. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  643. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  644. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  645. } else {
  646. /* No handling needed */
  647. IWL_DEBUG_RX(priv,
  648. "r %d i %d No handler needed for %s, 0x%02x\n",
  649. r, i, get_cmd_string(pkt->hdr.cmd),
  650. pkt->hdr.cmd);
  651. }
  652. /*
  653. * XXX: After here, we should always check rxb->page
  654. * against NULL before touching it or its virtual
  655. * memory (pkt). Because some rx_handler might have
  656. * already taken or freed the pages.
  657. */
  658. if (reclaim) {
  659. /* Invoke any callbacks, transfer the buffer to caller,
  660. * and fire off the (possibly) blocking iwl_send_cmd()
  661. * as we reclaim the driver command queue */
  662. if (rxb->page)
  663. iwl_tx_cmd_complete(priv, rxb);
  664. else
  665. IWL_WARN(priv, "Claim null rxb?\n");
  666. }
  667. /* Reuse the page if possible. For notification packets and
  668. * SKBs that fail to Rx correctly, add them back into the
  669. * rx_free list for reuse later. */
  670. spin_lock_irqsave(&rxq->lock, flags);
  671. if (rxb->page != NULL) {
  672. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  673. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  674. PCI_DMA_FROMDEVICE);
  675. list_add_tail(&rxb->list, &rxq->rx_free);
  676. rxq->free_count++;
  677. } else
  678. list_add_tail(&rxb->list, &rxq->rx_used);
  679. spin_unlock_irqrestore(&rxq->lock, flags);
  680. i = (i + 1) & RX_QUEUE_MASK;
  681. /* If there are a lot of unused frames,
  682. * restock the Rx queue so ucode wont assert. */
  683. if (fill_rx) {
  684. count++;
  685. if (count >= 8) {
  686. rxq->read = i;
  687. iwlagn_rx_replenish_now(priv);
  688. count = 0;
  689. }
  690. }
  691. }
  692. /* Backtrack one entry */
  693. rxq->read = i;
  694. if (fill_rx)
  695. iwlagn_rx_replenish_now(priv);
  696. else
  697. iwlagn_rx_queue_restock(priv);
  698. }
  699. /* call this function to flush any scheduled tasklet */
  700. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  701. {
  702. /* wait to make sure we flush pending tasklet*/
  703. synchronize_irq(priv->pci_dev->irq);
  704. tasklet_kill(&priv->irq_tasklet);
  705. }
  706. /* tasklet for iwlagn interrupt */
  707. static void iwl_irq_tasklet(struct iwl_priv *priv)
  708. {
  709. u32 inta = 0;
  710. u32 handled = 0;
  711. unsigned long flags;
  712. u32 i;
  713. #ifdef CONFIG_IWLWIFI_DEBUG
  714. u32 inta_mask;
  715. #endif
  716. spin_lock_irqsave(&priv->lock, flags);
  717. /* Ack/clear/reset pending uCode interrupts.
  718. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  719. */
  720. /* There is a hardware bug in the interrupt mask function that some
  721. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  722. * they are disabled in the CSR_INT_MASK register. Furthermore the
  723. * ICT interrupt handling mechanism has another bug that might cause
  724. * these unmasked interrupts fail to be detected. We workaround the
  725. * hardware bugs here by ACKing all the possible interrupts so that
  726. * interrupt coalescing can still be achieved.
  727. */
  728. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  729. inta = priv->_agn.inta;
  730. #ifdef CONFIG_IWLWIFI_DEBUG
  731. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  732. /* just for debug */
  733. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  734. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  735. inta, inta_mask);
  736. }
  737. #endif
  738. spin_unlock_irqrestore(&priv->lock, flags);
  739. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  740. priv->_agn.inta = 0;
  741. /* Now service all interrupt bits discovered above. */
  742. if (inta & CSR_INT_BIT_HW_ERR) {
  743. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  744. /* Tell the device to stop sending interrupts */
  745. iwl_disable_interrupts(priv);
  746. priv->isr_stats.hw++;
  747. iwl_irq_handle_error(priv);
  748. handled |= CSR_INT_BIT_HW_ERR;
  749. return;
  750. }
  751. #ifdef CONFIG_IWLWIFI_DEBUG
  752. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  753. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  754. if (inta & CSR_INT_BIT_SCD) {
  755. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  756. "the frame/frames.\n");
  757. priv->isr_stats.sch++;
  758. }
  759. /* Alive notification via Rx interrupt will do the real work */
  760. if (inta & CSR_INT_BIT_ALIVE) {
  761. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  762. priv->isr_stats.alive++;
  763. }
  764. }
  765. #endif
  766. /* Safely ignore these bits for debug checks below */
  767. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  768. /* HW RF KILL switch toggled */
  769. if (inta & CSR_INT_BIT_RF_KILL) {
  770. int hw_rf_kill = 0;
  771. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  772. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  773. hw_rf_kill = 1;
  774. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  775. hw_rf_kill ? "disable radio" : "enable radio");
  776. priv->isr_stats.rfkill++;
  777. /* driver only loads ucode once setting the interface up.
  778. * the driver allows loading the ucode even if the radio
  779. * is killed. Hence update the killswitch state here. The
  780. * rfkill handler will care about restarting if needed.
  781. */
  782. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  783. if (hw_rf_kill)
  784. set_bit(STATUS_RF_KILL_HW, &priv->status);
  785. else
  786. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  787. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  788. }
  789. handled |= CSR_INT_BIT_RF_KILL;
  790. }
  791. /* Chip got too hot and stopped itself */
  792. if (inta & CSR_INT_BIT_CT_KILL) {
  793. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  794. priv->isr_stats.ctkill++;
  795. handled |= CSR_INT_BIT_CT_KILL;
  796. }
  797. /* Error detected by uCode */
  798. if (inta & CSR_INT_BIT_SW_ERR) {
  799. IWL_ERR(priv, "Microcode SW error detected. "
  800. " Restarting 0x%X.\n", inta);
  801. priv->isr_stats.sw++;
  802. iwl_irq_handle_error(priv);
  803. handled |= CSR_INT_BIT_SW_ERR;
  804. }
  805. /* uCode wakes up after power-down sleep */
  806. if (inta & CSR_INT_BIT_WAKEUP) {
  807. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  808. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  809. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  810. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  811. priv->isr_stats.wakeup++;
  812. handled |= CSR_INT_BIT_WAKEUP;
  813. }
  814. /* All uCode command responses, including Tx command responses,
  815. * Rx "responses" (frame-received notification), and other
  816. * notifications from uCode come through here*/
  817. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  818. CSR_INT_BIT_RX_PERIODIC)) {
  819. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  820. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  821. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  822. iwl_write32(priv, CSR_FH_INT_STATUS,
  823. CSR_FH_INT_RX_MASK);
  824. }
  825. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  826. handled |= CSR_INT_BIT_RX_PERIODIC;
  827. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  828. }
  829. /* Sending RX interrupt require many steps to be done in the
  830. * the device:
  831. * 1- write interrupt to current index in ICT table.
  832. * 2- dma RX frame.
  833. * 3- update RX shared data to indicate last write index.
  834. * 4- send interrupt.
  835. * This could lead to RX race, driver could receive RX interrupt
  836. * but the shared data changes does not reflect this;
  837. * periodic interrupt will detect any dangling Rx activity.
  838. */
  839. /* Disable periodic interrupt; we use it as just a one-shot. */
  840. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  841. CSR_INT_PERIODIC_DIS);
  842. iwl_rx_handle(priv);
  843. /*
  844. * Enable periodic interrupt in 8 msec only if we received
  845. * real RX interrupt (instead of just periodic int), to catch
  846. * any dangling Rx interrupt. If it was just the periodic
  847. * interrupt, there was no dangling Rx activity, and no need
  848. * to extend the periodic interrupt; one-shot is enough.
  849. */
  850. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  851. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  852. CSR_INT_PERIODIC_ENA);
  853. priv->isr_stats.rx++;
  854. }
  855. /* This "Tx" DMA channel is used only for loading uCode */
  856. if (inta & CSR_INT_BIT_FH_TX) {
  857. iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
  858. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  859. priv->isr_stats.tx++;
  860. handled |= CSR_INT_BIT_FH_TX;
  861. /* Wake up uCode load routine, now that load is complete */
  862. priv->ucode_write_complete = 1;
  863. wake_up_interruptible(&priv->wait_command_queue);
  864. }
  865. if (inta & ~handled) {
  866. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  867. priv->isr_stats.unhandled++;
  868. }
  869. if (inta & ~(priv->inta_mask)) {
  870. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  871. inta & ~priv->inta_mask);
  872. }
  873. /* Re-enable all interrupts */
  874. /* only Re-enable if disabled by irq */
  875. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  876. iwl_enable_interrupts(priv);
  877. /* Re-enable RF_KILL if it occurred */
  878. else if (handled & CSR_INT_BIT_RF_KILL)
  879. iwl_enable_rfkill_int(priv);
  880. }
  881. /*****************************************************************************
  882. *
  883. * sysfs attributes
  884. *
  885. *****************************************************************************/
  886. #ifdef CONFIG_IWLWIFI_DEBUG
  887. /*
  888. * The following adds a new attribute to the sysfs representation
  889. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  890. * used for controlling the debug level.
  891. *
  892. * See the level definitions in iwl for details.
  893. *
  894. * The debug_level being managed using sysfs below is a per device debug
  895. * level that is used instead of the global debug level if it (the per
  896. * device debug level) is set.
  897. */
  898. static ssize_t show_debug_level(struct device *d,
  899. struct device_attribute *attr, char *buf)
  900. {
  901. struct iwl_priv *priv = dev_get_drvdata(d);
  902. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  903. }
  904. static ssize_t store_debug_level(struct device *d,
  905. struct device_attribute *attr,
  906. const char *buf, size_t count)
  907. {
  908. struct iwl_priv *priv = dev_get_drvdata(d);
  909. unsigned long val;
  910. int ret;
  911. ret = strict_strtoul(buf, 0, &val);
  912. if (ret)
  913. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  914. else {
  915. priv->debug_level = val;
  916. if (iwl_alloc_traffic_mem(priv))
  917. IWL_ERR(priv,
  918. "Not enough memory to generate traffic log\n");
  919. }
  920. return strnlen(buf, count);
  921. }
  922. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  923. show_debug_level, store_debug_level);
  924. #endif /* CONFIG_IWLWIFI_DEBUG */
  925. static ssize_t show_temperature(struct device *d,
  926. struct device_attribute *attr, char *buf)
  927. {
  928. struct iwl_priv *priv = dev_get_drvdata(d);
  929. if (!iwl_is_alive(priv))
  930. return -EAGAIN;
  931. return sprintf(buf, "%d\n", priv->temperature);
  932. }
  933. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  934. static ssize_t show_tx_power(struct device *d,
  935. struct device_attribute *attr, char *buf)
  936. {
  937. struct iwl_priv *priv = dev_get_drvdata(d);
  938. if (!iwl_is_ready_rf(priv))
  939. return sprintf(buf, "off\n");
  940. else
  941. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  942. }
  943. static ssize_t store_tx_power(struct device *d,
  944. struct device_attribute *attr,
  945. const char *buf, size_t count)
  946. {
  947. struct iwl_priv *priv = dev_get_drvdata(d);
  948. unsigned long val;
  949. int ret;
  950. ret = strict_strtoul(buf, 10, &val);
  951. if (ret)
  952. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  953. else {
  954. ret = iwl_set_tx_power(priv, val, false);
  955. if (ret)
  956. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  957. ret);
  958. else
  959. ret = count;
  960. }
  961. return ret;
  962. }
  963. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  964. static struct attribute *iwl_sysfs_entries[] = {
  965. &dev_attr_temperature.attr,
  966. &dev_attr_tx_power.attr,
  967. #ifdef CONFIG_IWLWIFI_DEBUG
  968. &dev_attr_debug_level.attr,
  969. #endif
  970. NULL
  971. };
  972. static struct attribute_group iwl_attribute_group = {
  973. .name = NULL, /* put in device directory */
  974. .attrs = iwl_sysfs_entries,
  975. };
  976. /******************************************************************************
  977. *
  978. * uCode download functions
  979. *
  980. ******************************************************************************/
  981. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  982. {
  983. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  984. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  985. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  986. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  987. }
  988. static void iwl_nic_start(struct iwl_priv *priv)
  989. {
  990. /* Remove all resets to allow NIC to operate */
  991. iwl_write32(priv, CSR_RESET, 0);
  992. }
  993. struct iwlagn_ucode_capabilities {
  994. u32 max_probe_length;
  995. u32 standard_phy_calibration_size;
  996. u32 flags;
  997. };
  998. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  999. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1000. struct iwlagn_ucode_capabilities *capa);
  1001. #define UCODE_EXPERIMENTAL_INDEX 100
  1002. #define UCODE_EXPERIMENTAL_TAG "exp"
  1003. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1004. {
  1005. const char *name_pre = priv->cfg->fw_name_pre;
  1006. char tag[8];
  1007. if (first) {
  1008. #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
  1009. priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
  1010. strcpy(tag, UCODE_EXPERIMENTAL_TAG);
  1011. } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
  1012. #endif
  1013. priv->fw_index = priv->cfg->ucode_api_max;
  1014. sprintf(tag, "%d", priv->fw_index);
  1015. } else {
  1016. priv->fw_index--;
  1017. sprintf(tag, "%d", priv->fw_index);
  1018. }
  1019. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1020. IWL_ERR(priv, "no suitable firmware found!\n");
  1021. return -ENOENT;
  1022. }
  1023. sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
  1024. IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
  1025. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  1026. ? "EXPERIMENTAL " : "",
  1027. priv->firmware_name);
  1028. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1029. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1030. iwl_ucode_callback);
  1031. }
  1032. struct iwlagn_firmware_pieces {
  1033. const void *inst, *data, *init, *init_data;
  1034. size_t inst_size, data_size, init_size, init_data_size;
  1035. u32 build;
  1036. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  1037. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  1038. };
  1039. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1040. const struct firmware *ucode_raw,
  1041. struct iwlagn_firmware_pieces *pieces)
  1042. {
  1043. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1044. u32 api_ver, hdr_size;
  1045. const u8 *src;
  1046. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1047. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1048. switch (api_ver) {
  1049. default:
  1050. hdr_size = 28;
  1051. if (ucode_raw->size < hdr_size) {
  1052. IWL_ERR(priv, "File size too small!\n");
  1053. return -EINVAL;
  1054. }
  1055. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1056. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1057. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1058. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1059. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1060. src = ucode->u.v2.data;
  1061. break;
  1062. case 0:
  1063. case 1:
  1064. case 2:
  1065. hdr_size = 24;
  1066. if (ucode_raw->size < hdr_size) {
  1067. IWL_ERR(priv, "File size too small!\n");
  1068. return -EINVAL;
  1069. }
  1070. pieces->build = 0;
  1071. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1072. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1073. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1074. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1075. src = ucode->u.v1.data;
  1076. break;
  1077. }
  1078. /* Verify size of file vs. image size info in file's header */
  1079. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1080. pieces->data_size + pieces->init_size +
  1081. pieces->init_data_size) {
  1082. IWL_ERR(priv,
  1083. "uCode file size %d does not match expected size\n",
  1084. (int)ucode_raw->size);
  1085. return -EINVAL;
  1086. }
  1087. pieces->inst = src;
  1088. src += pieces->inst_size;
  1089. pieces->data = src;
  1090. src += pieces->data_size;
  1091. pieces->init = src;
  1092. src += pieces->init_size;
  1093. pieces->init_data = src;
  1094. src += pieces->init_data_size;
  1095. return 0;
  1096. }
  1097. static int iwlagn_wanted_ucode_alternative = 1;
  1098. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1099. const struct firmware *ucode_raw,
  1100. struct iwlagn_firmware_pieces *pieces,
  1101. struct iwlagn_ucode_capabilities *capa)
  1102. {
  1103. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1104. struct iwl_ucode_tlv *tlv;
  1105. size_t len = ucode_raw->size;
  1106. const u8 *data;
  1107. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1108. u64 alternatives;
  1109. u32 tlv_len;
  1110. enum iwl_ucode_tlv_type tlv_type;
  1111. const u8 *tlv_data;
  1112. if (len < sizeof(*ucode)) {
  1113. IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
  1114. return -EINVAL;
  1115. }
  1116. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
  1117. IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
  1118. le32_to_cpu(ucode->magic));
  1119. return -EINVAL;
  1120. }
  1121. /*
  1122. * Check which alternatives are present, and "downgrade"
  1123. * when the chosen alternative is not present, warning
  1124. * the user when that happens. Some files may not have
  1125. * any alternatives, so don't warn in that case.
  1126. */
  1127. alternatives = le64_to_cpu(ucode->alternatives);
  1128. tmp = wanted_alternative;
  1129. if (wanted_alternative > 63)
  1130. wanted_alternative = 63;
  1131. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1132. wanted_alternative--;
  1133. if (wanted_alternative && wanted_alternative != tmp)
  1134. IWL_WARN(priv,
  1135. "uCode alternative %d not available, choosing %d\n",
  1136. tmp, wanted_alternative);
  1137. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1138. pieces->build = le32_to_cpu(ucode->build);
  1139. data = ucode->data;
  1140. len -= sizeof(*ucode);
  1141. while (len >= sizeof(*tlv)) {
  1142. u16 tlv_alt;
  1143. len -= sizeof(*tlv);
  1144. tlv = (void *)data;
  1145. tlv_len = le32_to_cpu(tlv->length);
  1146. tlv_type = le16_to_cpu(tlv->type);
  1147. tlv_alt = le16_to_cpu(tlv->alternative);
  1148. tlv_data = tlv->data;
  1149. if (len < tlv_len) {
  1150. IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
  1151. len, tlv_len);
  1152. return -EINVAL;
  1153. }
  1154. len -= ALIGN(tlv_len, 4);
  1155. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1156. /*
  1157. * Alternative 0 is always valid.
  1158. *
  1159. * Skip alternative TLVs that are not selected.
  1160. */
  1161. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1162. continue;
  1163. switch (tlv_type) {
  1164. case IWL_UCODE_TLV_INST:
  1165. pieces->inst = tlv_data;
  1166. pieces->inst_size = tlv_len;
  1167. break;
  1168. case IWL_UCODE_TLV_DATA:
  1169. pieces->data = tlv_data;
  1170. pieces->data_size = tlv_len;
  1171. break;
  1172. case IWL_UCODE_TLV_INIT:
  1173. pieces->init = tlv_data;
  1174. pieces->init_size = tlv_len;
  1175. break;
  1176. case IWL_UCODE_TLV_INIT_DATA:
  1177. pieces->init_data = tlv_data;
  1178. pieces->init_data_size = tlv_len;
  1179. break;
  1180. case IWL_UCODE_TLV_BOOT:
  1181. IWL_ERR(priv, "Found unexpected BOOT ucode\n");
  1182. break;
  1183. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1184. if (tlv_len != sizeof(u32))
  1185. goto invalid_tlv_len;
  1186. capa->max_probe_length =
  1187. le32_to_cpup((__le32 *)tlv_data);
  1188. break;
  1189. case IWL_UCODE_TLV_PAN:
  1190. if (tlv_len)
  1191. goto invalid_tlv_len;
  1192. capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
  1193. break;
  1194. case IWL_UCODE_TLV_FLAGS:
  1195. /* must be at least one u32 */
  1196. if (tlv_len < sizeof(u32))
  1197. goto invalid_tlv_len;
  1198. /* and a proper number of u32s */
  1199. if (tlv_len % sizeof(u32))
  1200. goto invalid_tlv_len;
  1201. /*
  1202. * This driver only reads the first u32 as
  1203. * right now no more features are defined,
  1204. * if that changes then either the driver
  1205. * will not work with the new firmware, or
  1206. * it'll not take advantage of new features.
  1207. */
  1208. capa->flags = le32_to_cpup((__le32 *)tlv_data);
  1209. break;
  1210. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1211. if (tlv_len != sizeof(u32))
  1212. goto invalid_tlv_len;
  1213. pieces->init_evtlog_ptr =
  1214. le32_to_cpup((__le32 *)tlv_data);
  1215. break;
  1216. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1217. if (tlv_len != sizeof(u32))
  1218. goto invalid_tlv_len;
  1219. pieces->init_evtlog_size =
  1220. le32_to_cpup((__le32 *)tlv_data);
  1221. break;
  1222. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1223. if (tlv_len != sizeof(u32))
  1224. goto invalid_tlv_len;
  1225. pieces->init_errlog_ptr =
  1226. le32_to_cpup((__le32 *)tlv_data);
  1227. break;
  1228. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1229. if (tlv_len != sizeof(u32))
  1230. goto invalid_tlv_len;
  1231. pieces->inst_evtlog_ptr =
  1232. le32_to_cpup((__le32 *)tlv_data);
  1233. break;
  1234. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1235. if (tlv_len != sizeof(u32))
  1236. goto invalid_tlv_len;
  1237. pieces->inst_evtlog_size =
  1238. le32_to_cpup((__le32 *)tlv_data);
  1239. break;
  1240. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1241. if (tlv_len != sizeof(u32))
  1242. goto invalid_tlv_len;
  1243. pieces->inst_errlog_ptr =
  1244. le32_to_cpup((__le32 *)tlv_data);
  1245. break;
  1246. case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
  1247. if (tlv_len)
  1248. goto invalid_tlv_len;
  1249. priv->enhance_sensitivity_table = true;
  1250. break;
  1251. case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
  1252. if (tlv_len != sizeof(u32))
  1253. goto invalid_tlv_len;
  1254. capa->standard_phy_calibration_size =
  1255. le32_to_cpup((__le32 *)tlv_data);
  1256. break;
  1257. default:
  1258. IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
  1259. break;
  1260. }
  1261. }
  1262. if (len) {
  1263. IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
  1264. iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
  1265. return -EINVAL;
  1266. }
  1267. return 0;
  1268. invalid_tlv_len:
  1269. IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
  1270. iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
  1271. return -EINVAL;
  1272. }
  1273. /**
  1274. * iwl_ucode_callback - callback when firmware was loaded
  1275. *
  1276. * If loaded successfully, copies the firmware into buffers
  1277. * for the card to fetch (via DMA).
  1278. */
  1279. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1280. {
  1281. struct iwl_priv *priv = context;
  1282. struct iwl_ucode_header *ucode;
  1283. int err;
  1284. struct iwlagn_firmware_pieces pieces;
  1285. const unsigned int api_max = priv->cfg->ucode_api_max;
  1286. const unsigned int api_min = priv->cfg->ucode_api_min;
  1287. u32 api_ver;
  1288. char buildstr[25];
  1289. u32 build;
  1290. struct iwlagn_ucode_capabilities ucode_capa = {
  1291. .max_probe_length = 200,
  1292. .standard_phy_calibration_size =
  1293. IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
  1294. };
  1295. memset(&pieces, 0, sizeof(pieces));
  1296. if (!ucode_raw) {
  1297. if (priv->fw_index <= priv->cfg->ucode_api_max)
  1298. IWL_ERR(priv,
  1299. "request for firmware file '%s' failed.\n",
  1300. priv->firmware_name);
  1301. goto try_again;
  1302. }
  1303. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1304. priv->firmware_name, ucode_raw->size);
  1305. /* Make sure that we got at least the API version number */
  1306. if (ucode_raw->size < 4) {
  1307. IWL_ERR(priv, "File size way too small!\n");
  1308. goto try_again;
  1309. }
  1310. /* Data from ucode file: header followed by uCode images */
  1311. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1312. if (ucode->ver)
  1313. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1314. else
  1315. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1316. &ucode_capa);
  1317. if (err)
  1318. goto try_again;
  1319. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1320. build = pieces.build;
  1321. /*
  1322. * api_ver should match the api version forming part of the
  1323. * firmware filename ... but we don't check for that and only rely
  1324. * on the API version read from firmware header from here on forward
  1325. */
  1326. /* no api version check required for experimental uCode */
  1327. if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
  1328. if (api_ver < api_min || api_ver > api_max) {
  1329. IWL_ERR(priv,
  1330. "Driver unable to support your firmware API. "
  1331. "Driver supports v%u, firmware is v%u.\n",
  1332. api_max, api_ver);
  1333. goto try_again;
  1334. }
  1335. if (api_ver != api_max)
  1336. IWL_ERR(priv,
  1337. "Firmware has old API version. Expected v%u, "
  1338. "got v%u. New firmware can be obtained "
  1339. "from http://www.intellinuxwireless.org.\n",
  1340. api_max, api_ver);
  1341. }
  1342. if (build)
  1343. sprintf(buildstr, " build %u%s", build,
  1344. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  1345. ? " (EXP)" : "");
  1346. else
  1347. buildstr[0] = '\0';
  1348. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1349. IWL_UCODE_MAJOR(priv->ucode_ver),
  1350. IWL_UCODE_MINOR(priv->ucode_ver),
  1351. IWL_UCODE_API(priv->ucode_ver),
  1352. IWL_UCODE_SERIAL(priv->ucode_ver),
  1353. buildstr);
  1354. snprintf(priv->hw->wiphy->fw_version,
  1355. sizeof(priv->hw->wiphy->fw_version),
  1356. "%u.%u.%u.%u%s",
  1357. IWL_UCODE_MAJOR(priv->ucode_ver),
  1358. IWL_UCODE_MINOR(priv->ucode_ver),
  1359. IWL_UCODE_API(priv->ucode_ver),
  1360. IWL_UCODE_SERIAL(priv->ucode_ver),
  1361. buildstr);
  1362. /*
  1363. * For any of the failures below (before allocating pci memory)
  1364. * we will try to load a version with a smaller API -- maybe the
  1365. * user just got a corrupted version of the latest API.
  1366. */
  1367. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1368. priv->ucode_ver);
  1369. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1370. pieces.inst_size);
  1371. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1372. pieces.data_size);
  1373. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1374. pieces.init_size);
  1375. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1376. pieces.init_data_size);
  1377. /* Verify that uCode images will fit in card's SRAM */
  1378. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1379. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1380. pieces.inst_size);
  1381. goto try_again;
  1382. }
  1383. if (pieces.data_size > priv->hw_params.max_data_size) {
  1384. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1385. pieces.data_size);
  1386. goto try_again;
  1387. }
  1388. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1389. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1390. pieces.init_size);
  1391. goto try_again;
  1392. }
  1393. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1394. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1395. pieces.init_data_size);
  1396. goto try_again;
  1397. }
  1398. /* Allocate ucode buffers for card's bus-master loading ... */
  1399. /* Runtime instructions and 2 copies of data:
  1400. * 1) unmodified from disk
  1401. * 2) backup cache for save/restore during power-downs */
  1402. priv->ucode_code.len = pieces.inst_size;
  1403. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1404. priv->ucode_data.len = pieces.data_size;
  1405. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1406. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
  1407. goto err_pci_alloc;
  1408. /* Initialization instructions and data */
  1409. if (pieces.init_size && pieces.init_data_size) {
  1410. priv->ucode_init.len = pieces.init_size;
  1411. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1412. priv->ucode_init_data.len = pieces.init_data_size;
  1413. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1414. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1415. goto err_pci_alloc;
  1416. }
  1417. /* Now that we can no longer fail, copy information */
  1418. /*
  1419. * The (size - 16) / 12 formula is based on the information recorded
  1420. * for each event, which is of mode 1 (including timestamp) for all
  1421. * new microcodes that include this information.
  1422. */
  1423. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1424. if (pieces.init_evtlog_size)
  1425. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1426. else
  1427. priv->_agn.init_evtlog_size =
  1428. priv->cfg->base_params->max_event_log_size;
  1429. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1430. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1431. if (pieces.inst_evtlog_size)
  1432. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1433. else
  1434. priv->_agn.inst_evtlog_size =
  1435. priv->cfg->base_params->max_event_log_size;
  1436. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1437. if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
  1438. priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
  1439. priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
  1440. } else
  1441. priv->sta_key_max_num = STA_KEY_MAX_NUM;
  1442. if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_BTSTATS ||
  1443. (priv->cfg->bt_params && priv->cfg->bt_params->bt_statistics))
  1444. priv->bt_statistics = true;
  1445. /* Copy images into buffers for card's bus-master reads ... */
  1446. /* Runtime instructions (first block of data in file) */
  1447. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1448. pieces.inst_size);
  1449. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1450. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1451. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1452. /*
  1453. * Runtime data
  1454. * NOTE: Copy into backup buffer will be done in iwl_up()
  1455. */
  1456. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1457. pieces.data_size);
  1458. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1459. /* Initialization instructions */
  1460. if (pieces.init_size) {
  1461. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1462. pieces.init_size);
  1463. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1464. }
  1465. /* Initialization data */
  1466. if (pieces.init_data_size) {
  1467. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1468. pieces.init_data_size);
  1469. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1470. pieces.init_data_size);
  1471. }
  1472. /*
  1473. * figure out the offset of chain noise reset and gain commands
  1474. * base on the size of standard phy calibration commands table size
  1475. */
  1476. if (ucode_capa.standard_phy_calibration_size >
  1477. IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
  1478. ucode_capa.standard_phy_calibration_size =
  1479. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1480. priv->_agn.phy_calib_chain_noise_reset_cmd =
  1481. ucode_capa.standard_phy_calibration_size;
  1482. priv->_agn.phy_calib_chain_noise_gain_cmd =
  1483. ucode_capa.standard_phy_calibration_size + 1;
  1484. /**************************************************
  1485. * This is still part of probe() in a sense...
  1486. *
  1487. * 9. Setup and register with mac80211 and debugfs
  1488. **************************************************/
  1489. err = iwl_mac_setup_register(priv, &ucode_capa);
  1490. if (err)
  1491. goto out_unbind;
  1492. err = iwl_dbgfs_register(priv, DRV_NAME);
  1493. if (err)
  1494. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1495. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1496. &iwl_attribute_group);
  1497. if (err) {
  1498. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1499. goto out_unbind;
  1500. }
  1501. /* We have our copies now, allow OS release its copies */
  1502. release_firmware(ucode_raw);
  1503. complete(&priv->_agn.firmware_loading_complete);
  1504. return;
  1505. try_again:
  1506. /* try next, if any */
  1507. if (iwl_request_firmware(priv, false))
  1508. goto out_unbind;
  1509. release_firmware(ucode_raw);
  1510. return;
  1511. err_pci_alloc:
  1512. IWL_ERR(priv, "failed to allocate pci memory\n");
  1513. iwl_dealloc_ucode_pci(priv);
  1514. out_unbind:
  1515. complete(&priv->_agn.firmware_loading_complete);
  1516. device_release_driver(&priv->pci_dev->dev);
  1517. release_firmware(ucode_raw);
  1518. }
  1519. static const char *desc_lookup_text[] = {
  1520. "OK",
  1521. "FAIL",
  1522. "BAD_PARAM",
  1523. "BAD_CHECKSUM",
  1524. "NMI_INTERRUPT_WDG",
  1525. "SYSASSERT",
  1526. "FATAL_ERROR",
  1527. "BAD_COMMAND",
  1528. "HW_ERROR_TUNE_LOCK",
  1529. "HW_ERROR_TEMPERATURE",
  1530. "ILLEGAL_CHAN_FREQ",
  1531. "VCC_NOT_STABLE",
  1532. "FH_ERROR",
  1533. "NMI_INTERRUPT_HOST",
  1534. "NMI_INTERRUPT_ACTION_PT",
  1535. "NMI_INTERRUPT_UNKNOWN",
  1536. "UCODE_VERSION_MISMATCH",
  1537. "HW_ERROR_ABS_LOCK",
  1538. "HW_ERROR_CAL_LOCK_FAIL",
  1539. "NMI_INTERRUPT_INST_ACTION_PT",
  1540. "NMI_INTERRUPT_DATA_ACTION_PT",
  1541. "NMI_TRM_HW_ER",
  1542. "NMI_INTERRUPT_TRM",
  1543. "NMI_INTERRUPT_BREAK_POINT"
  1544. "DEBUG_0",
  1545. "DEBUG_1",
  1546. "DEBUG_2",
  1547. "DEBUG_3",
  1548. };
  1549. static struct { char *name; u8 num; } advanced_lookup[] = {
  1550. { "NMI_INTERRUPT_WDG", 0x34 },
  1551. { "SYSASSERT", 0x35 },
  1552. { "UCODE_VERSION_MISMATCH", 0x37 },
  1553. { "BAD_COMMAND", 0x38 },
  1554. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1555. { "FATAL_ERROR", 0x3D },
  1556. { "NMI_TRM_HW_ERR", 0x46 },
  1557. { "NMI_INTERRUPT_TRM", 0x4C },
  1558. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1559. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1560. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1561. { "NMI_INTERRUPT_HOST", 0x66 },
  1562. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1563. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1564. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1565. { "ADVANCED_SYSASSERT", 0 },
  1566. };
  1567. static const char *desc_lookup(u32 num)
  1568. {
  1569. int i;
  1570. int max = ARRAY_SIZE(desc_lookup_text);
  1571. if (num < max)
  1572. return desc_lookup_text[num];
  1573. max = ARRAY_SIZE(advanced_lookup) - 1;
  1574. for (i = 0; i < max; i++) {
  1575. if (advanced_lookup[i].num == num)
  1576. break;;
  1577. }
  1578. return advanced_lookup[i].name;
  1579. }
  1580. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1581. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1582. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1583. {
  1584. u32 data2, line;
  1585. u32 desc, time, count, base, data1;
  1586. u32 blink1, blink2, ilink1, ilink2;
  1587. u32 pc, hcmd;
  1588. base = priv->device_pointers.error_event_table;
  1589. if (priv->ucode_type == UCODE_INIT) {
  1590. if (!base)
  1591. base = priv->_agn.init_errlog_ptr;
  1592. } else {
  1593. if (!base)
  1594. base = priv->_agn.inst_errlog_ptr;
  1595. }
  1596. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1597. IWL_ERR(priv,
  1598. "Not valid error log pointer 0x%08X for %s uCode\n",
  1599. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1600. return;
  1601. }
  1602. count = iwl_read_targ_mem(priv, base);
  1603. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1604. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1605. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1606. priv->status, count);
  1607. }
  1608. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1609. priv->isr_stats.err_code = desc;
  1610. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  1611. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1612. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1613. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1614. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1615. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1616. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1617. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1618. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1619. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  1620. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1621. blink1, blink2, ilink1, ilink2);
  1622. IWL_ERR(priv, "Desc Time "
  1623. "data1 data2 line\n");
  1624. IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  1625. desc_lookup(desc), desc, time, data1, data2, line);
  1626. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  1627. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  1628. pc, blink1, blink2, ilink1, ilink2, hcmd);
  1629. }
  1630. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1631. /**
  1632. * iwl_print_event_log - Dump error event log to syslog
  1633. *
  1634. */
  1635. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1636. u32 num_events, u32 mode,
  1637. int pos, char **buf, size_t bufsz)
  1638. {
  1639. u32 i;
  1640. u32 base; /* SRAM byte address of event log header */
  1641. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1642. u32 ptr; /* SRAM byte address of log data */
  1643. u32 ev, time, data; /* event log data */
  1644. unsigned long reg_flags;
  1645. if (num_events == 0)
  1646. return pos;
  1647. base = priv->device_pointers.log_event_table;
  1648. if (priv->ucode_type == UCODE_INIT) {
  1649. if (!base)
  1650. base = priv->_agn.init_evtlog_ptr;
  1651. } else {
  1652. if (!base)
  1653. base = priv->_agn.inst_evtlog_ptr;
  1654. }
  1655. if (mode == 0)
  1656. event_size = 2 * sizeof(u32);
  1657. else
  1658. event_size = 3 * sizeof(u32);
  1659. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1660. /* Make sure device is powered up for SRAM reads */
  1661. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1662. iwl_grab_nic_access(priv);
  1663. /* Set starting address; reads will auto-increment */
  1664. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1665. rmb();
  1666. /* "time" is actually "data" for mode 0 (no timestamp).
  1667. * place event id # at far right for easier visual parsing. */
  1668. for (i = 0; i < num_events; i++) {
  1669. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1670. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1671. if (mode == 0) {
  1672. /* data, ev */
  1673. if (bufsz) {
  1674. pos += scnprintf(*buf + pos, bufsz - pos,
  1675. "EVT_LOG:0x%08x:%04u\n",
  1676. time, ev);
  1677. } else {
  1678. trace_iwlwifi_dev_ucode_event(priv, 0,
  1679. time, ev);
  1680. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1681. time, ev);
  1682. }
  1683. } else {
  1684. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1685. if (bufsz) {
  1686. pos += scnprintf(*buf + pos, bufsz - pos,
  1687. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1688. time, data, ev);
  1689. } else {
  1690. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1691. time, data, ev);
  1692. trace_iwlwifi_dev_ucode_event(priv, time,
  1693. data, ev);
  1694. }
  1695. }
  1696. }
  1697. /* Allow device to power down */
  1698. iwl_release_nic_access(priv);
  1699. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1700. return pos;
  1701. }
  1702. /**
  1703. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1704. */
  1705. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1706. u32 num_wraps, u32 next_entry,
  1707. u32 size, u32 mode,
  1708. int pos, char **buf, size_t bufsz)
  1709. {
  1710. /*
  1711. * display the newest DEFAULT_LOG_ENTRIES entries
  1712. * i.e the entries just before the next ont that uCode would fill.
  1713. */
  1714. if (num_wraps) {
  1715. if (next_entry < size) {
  1716. pos = iwl_print_event_log(priv,
  1717. capacity - (size - next_entry),
  1718. size - next_entry, mode,
  1719. pos, buf, bufsz);
  1720. pos = iwl_print_event_log(priv, 0,
  1721. next_entry, mode,
  1722. pos, buf, bufsz);
  1723. } else
  1724. pos = iwl_print_event_log(priv, next_entry - size,
  1725. size, mode, pos, buf, bufsz);
  1726. } else {
  1727. if (next_entry < size) {
  1728. pos = iwl_print_event_log(priv, 0, next_entry,
  1729. mode, pos, buf, bufsz);
  1730. } else {
  1731. pos = iwl_print_event_log(priv, next_entry - size,
  1732. size, mode, pos, buf, bufsz);
  1733. }
  1734. }
  1735. return pos;
  1736. }
  1737. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1738. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1739. char **buf, bool display)
  1740. {
  1741. u32 base; /* SRAM byte address of event log header */
  1742. u32 capacity; /* event log capacity in # entries */
  1743. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1744. u32 num_wraps; /* # times uCode wrapped to top of log */
  1745. u32 next_entry; /* index of next entry to be written by uCode */
  1746. u32 size; /* # entries that we'll print */
  1747. u32 logsize;
  1748. int pos = 0;
  1749. size_t bufsz = 0;
  1750. base = priv->device_pointers.log_event_table;
  1751. if (priv->ucode_type == UCODE_INIT) {
  1752. logsize = priv->_agn.init_evtlog_size;
  1753. if (!base)
  1754. base = priv->_agn.init_evtlog_ptr;
  1755. } else {
  1756. logsize = priv->_agn.inst_evtlog_size;
  1757. if (!base)
  1758. base = priv->_agn.inst_evtlog_ptr;
  1759. }
  1760. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1761. IWL_ERR(priv,
  1762. "Invalid event log pointer 0x%08X for %s uCode\n",
  1763. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1764. return -EINVAL;
  1765. }
  1766. /* event log header */
  1767. capacity = iwl_read_targ_mem(priv, base);
  1768. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1769. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1770. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1771. if (capacity > logsize) {
  1772. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1773. capacity, logsize);
  1774. capacity = logsize;
  1775. }
  1776. if (next_entry > logsize) {
  1777. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1778. next_entry, logsize);
  1779. next_entry = logsize;
  1780. }
  1781. size = num_wraps ? capacity : next_entry;
  1782. /* bail out if nothing in log */
  1783. if (size == 0) {
  1784. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1785. return pos;
  1786. }
  1787. /* enable/disable bt channel inhibition */
  1788. priv->bt_ch_announce = iwlagn_bt_ch_announce;
  1789. #ifdef CONFIG_IWLWIFI_DEBUG
  1790. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1791. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1792. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1793. #else
  1794. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1795. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1796. #endif
  1797. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1798. size);
  1799. #ifdef CONFIG_IWLWIFI_DEBUG
  1800. if (display) {
  1801. if (full_log)
  1802. bufsz = capacity * 48;
  1803. else
  1804. bufsz = size * 48;
  1805. *buf = kmalloc(bufsz, GFP_KERNEL);
  1806. if (!*buf)
  1807. return -ENOMEM;
  1808. }
  1809. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1810. /*
  1811. * if uCode has wrapped back to top of log,
  1812. * start at the oldest entry,
  1813. * i.e the next one that uCode would fill.
  1814. */
  1815. if (num_wraps)
  1816. pos = iwl_print_event_log(priv, next_entry,
  1817. capacity - next_entry, mode,
  1818. pos, buf, bufsz);
  1819. /* (then/else) start at top of log */
  1820. pos = iwl_print_event_log(priv, 0,
  1821. next_entry, mode, pos, buf, bufsz);
  1822. } else
  1823. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1824. next_entry, size, mode,
  1825. pos, buf, bufsz);
  1826. #else
  1827. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1828. next_entry, size, mode,
  1829. pos, buf, bufsz);
  1830. #endif
  1831. return pos;
  1832. }
  1833. static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1834. {
  1835. struct iwl_ct_kill_config cmd;
  1836. struct iwl_ct_kill_throttling_config adv_cmd;
  1837. unsigned long flags;
  1838. int ret = 0;
  1839. spin_lock_irqsave(&priv->lock, flags);
  1840. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1841. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1842. spin_unlock_irqrestore(&priv->lock, flags);
  1843. priv->thermal_throttle.ct_kill_toggle = false;
  1844. if (priv->cfg->base_params->support_ct_kill_exit) {
  1845. adv_cmd.critical_temperature_enter =
  1846. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1847. adv_cmd.critical_temperature_exit =
  1848. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1849. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1850. sizeof(adv_cmd), &adv_cmd);
  1851. if (ret)
  1852. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1853. else
  1854. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1855. "succeeded, "
  1856. "critical temperature enter is %d,"
  1857. "exit is %d\n",
  1858. priv->hw_params.ct_kill_threshold,
  1859. priv->hw_params.ct_kill_exit_threshold);
  1860. } else {
  1861. cmd.critical_temperature_R =
  1862. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1863. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1864. sizeof(cmd), &cmd);
  1865. if (ret)
  1866. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1867. else
  1868. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1869. "succeeded, "
  1870. "critical temperature is %d\n",
  1871. priv->hw_params.ct_kill_threshold);
  1872. }
  1873. }
  1874. static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
  1875. {
  1876. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  1877. struct iwl_host_cmd cmd = {
  1878. .id = CALIBRATION_CFG_CMD,
  1879. .len = sizeof(struct iwl_calib_cfg_cmd),
  1880. .data = &calib_cfg_cmd,
  1881. };
  1882. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  1883. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  1884. calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
  1885. return iwl_send_cmd(priv, &cmd);
  1886. }
  1887. /**
  1888. * iwl_alive_start - called after REPLY_ALIVE notification received
  1889. * from protocol/runtime uCode (initialization uCode's
  1890. * Alive gets handled by iwl_init_alive_start()).
  1891. */
  1892. static void iwl_alive_start(struct iwl_priv *priv)
  1893. {
  1894. int ret = 0;
  1895. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  1896. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1897. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1898. * This is a paranoid check, because we would not have gotten the
  1899. * "runtime" alive if code weren't properly loaded. */
  1900. if (iwl_verify_ucode(priv, &priv->ucode_code)) {
  1901. /* Runtime instruction load was bad;
  1902. * take it all the way back down so we can try again */
  1903. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1904. goto restart;
  1905. }
  1906. ret = iwlagn_alive_notify(priv);
  1907. if (ret) {
  1908. IWL_WARN(priv,
  1909. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1910. goto restart;
  1911. }
  1912. /* After the ALIVE response, we can send host commands to the uCode */
  1913. set_bit(STATUS_ALIVE, &priv->status);
  1914. /* Enable watchdog to monitor the driver tx queues */
  1915. iwl_setup_watchdog(priv);
  1916. if (iwl_is_rfkill(priv))
  1917. return;
  1918. /* download priority table before any calibration request */
  1919. if (priv->cfg->bt_params &&
  1920. priv->cfg->bt_params->advanced_bt_coexist) {
  1921. /* Configure Bluetooth device coexistence support */
  1922. priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
  1923. priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
  1924. priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
  1925. priv->cfg->ops->hcmd->send_bt_config(priv);
  1926. priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
  1927. iwlagn_send_prio_tbl(priv);
  1928. /* FIXME: w/a to force change uCode BT state machine */
  1929. iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  1930. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  1931. iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
  1932. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  1933. }
  1934. if (priv->hw_params.calib_rt_cfg)
  1935. iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
  1936. ieee80211_wake_queues(priv->hw);
  1937. priv->active_rate = IWL_RATES_MASK;
  1938. /* Configure Tx antenna selection based on H/W config */
  1939. if (priv->cfg->ops->hcmd->set_tx_ant)
  1940. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1941. if (iwl_is_associated_ctx(ctx)) {
  1942. struct iwl_rxon_cmd *active_rxon =
  1943. (struct iwl_rxon_cmd *)&ctx->active;
  1944. /* apply any changes in staging */
  1945. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1946. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1947. } else {
  1948. struct iwl_rxon_context *tmp;
  1949. /* Initialize our rx_config data */
  1950. for_each_context(priv, tmp)
  1951. iwl_connection_init_rx_config(priv, tmp);
  1952. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1953. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  1954. }
  1955. if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
  1956. !priv->cfg->bt_params->advanced_bt_coexist)) {
  1957. /*
  1958. * default is 2-wire BT coexexistence support
  1959. */
  1960. priv->cfg->ops->hcmd->send_bt_config(priv);
  1961. }
  1962. iwl_reset_run_time_calib(priv);
  1963. set_bit(STATUS_READY, &priv->status);
  1964. /* Configure the adapter for unassociated operation */
  1965. iwlcore_commit_rxon(priv, ctx);
  1966. /* At this point, the NIC is initialized and operational */
  1967. iwl_rf_kill_ct_config(priv);
  1968. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1969. wake_up_interruptible(&priv->wait_command_queue);
  1970. iwl_power_update_mode(priv, true);
  1971. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  1972. return;
  1973. restart:
  1974. queue_work(priv->workqueue, &priv->restart);
  1975. }
  1976. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1977. static void __iwl_down(struct iwl_priv *priv)
  1978. {
  1979. unsigned long flags;
  1980. int exit_pending;
  1981. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1982. iwl_scan_cancel_timeout(priv, 200);
  1983. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  1984. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  1985. * to prevent rearm timer */
  1986. del_timer_sync(&priv->watchdog);
  1987. iwl_clear_ucode_stations(priv, NULL);
  1988. iwl_dealloc_bcast_stations(priv);
  1989. iwl_clear_driver_stations(priv);
  1990. /* reset BT coex data */
  1991. priv->bt_status = 0;
  1992. if (priv->cfg->bt_params)
  1993. priv->bt_traffic_load =
  1994. priv->cfg->bt_params->bt_init_traffic_load;
  1995. else
  1996. priv->bt_traffic_load = 0;
  1997. priv->bt_full_concurrent = false;
  1998. priv->bt_ci_compliance = 0;
  1999. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2000. * exiting the module */
  2001. if (!exit_pending)
  2002. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2003. /* stop and reset the on-board processor */
  2004. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2005. /* tell the device to stop sending interrupts */
  2006. spin_lock_irqsave(&priv->lock, flags);
  2007. iwl_disable_interrupts(priv);
  2008. spin_unlock_irqrestore(&priv->lock, flags);
  2009. iwl_synchronize_irq(priv);
  2010. if (priv->mac80211_registered)
  2011. ieee80211_stop_queues(priv->hw);
  2012. /* If we have not previously called iwl_init() then
  2013. * clear all bits but the RF Kill bit and return */
  2014. if (!iwl_is_init(priv)) {
  2015. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2016. STATUS_RF_KILL_HW |
  2017. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2018. STATUS_GEO_CONFIGURED |
  2019. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2020. STATUS_EXIT_PENDING;
  2021. goto exit;
  2022. }
  2023. /* ...otherwise clear out all the status bits but the RF Kill
  2024. * bit and continue taking the NIC down. */
  2025. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2026. STATUS_RF_KILL_HW |
  2027. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2028. STATUS_GEO_CONFIGURED |
  2029. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2030. STATUS_FW_ERROR |
  2031. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2032. STATUS_EXIT_PENDING;
  2033. /* device going down, Stop using ICT table */
  2034. if (priv->cfg->ops->lib->isr_ops.disable)
  2035. priv->cfg->ops->lib->isr_ops.disable(priv);
  2036. iwlagn_txq_ctx_stop(priv);
  2037. iwlagn_rxq_stop(priv);
  2038. /* Power-down device's busmaster DMA clocks */
  2039. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2040. udelay(5);
  2041. /* Make sure (redundant) we've released our request to stay awake */
  2042. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2043. /* Stop the device, and put it in low power state */
  2044. iwl_apm_stop(priv);
  2045. exit:
  2046. dev_kfree_skb(priv->beacon_skb);
  2047. priv->beacon_skb = NULL;
  2048. /* clear out any free frames */
  2049. iwl_clear_free_frames(priv);
  2050. }
  2051. static void iwl_down(struct iwl_priv *priv)
  2052. {
  2053. mutex_lock(&priv->mutex);
  2054. __iwl_down(priv);
  2055. mutex_unlock(&priv->mutex);
  2056. iwl_cancel_deferred_work(priv);
  2057. }
  2058. #define HW_READY_TIMEOUT (50)
  2059. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2060. {
  2061. int ret = 0;
  2062. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2063. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2064. /* See if we got it */
  2065. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2066. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2067. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2068. HW_READY_TIMEOUT);
  2069. if (ret != -ETIMEDOUT)
  2070. priv->hw_ready = true;
  2071. else
  2072. priv->hw_ready = false;
  2073. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2074. (priv->hw_ready == 1) ? "ready" : "not ready");
  2075. return ret;
  2076. }
  2077. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2078. {
  2079. int ret = 0;
  2080. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2081. ret = iwl_set_hw_ready(priv);
  2082. if (priv->hw_ready)
  2083. return ret;
  2084. /* If HW is not ready, prepare the conditions to check again */
  2085. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2086. CSR_HW_IF_CONFIG_REG_PREPARE);
  2087. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2088. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2089. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2090. /* HW should be ready by now, check again. */
  2091. if (ret != -ETIMEDOUT)
  2092. iwl_set_hw_ready(priv);
  2093. return ret;
  2094. }
  2095. #define MAX_HW_RESTARTS 5
  2096. static int __iwl_up(struct iwl_priv *priv)
  2097. {
  2098. struct iwl_rxon_context *ctx;
  2099. int i;
  2100. int ret;
  2101. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2102. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2103. return -EIO;
  2104. }
  2105. for_each_context(priv, ctx) {
  2106. ret = iwlagn_alloc_bcast_station(priv, ctx);
  2107. if (ret) {
  2108. iwl_dealloc_bcast_stations(priv);
  2109. return ret;
  2110. }
  2111. }
  2112. iwl_prepare_card_hw(priv);
  2113. if (!priv->hw_ready) {
  2114. IWL_WARN(priv, "Exit HW not ready\n");
  2115. return -EIO;
  2116. }
  2117. /* If platform's RF_KILL switch is NOT set to KILL */
  2118. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2119. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2120. else
  2121. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2122. if (iwl_is_rfkill(priv)) {
  2123. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2124. iwl_enable_interrupts(priv);
  2125. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2126. return 0;
  2127. }
  2128. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2129. /* must be initialised before iwl_hw_nic_init */
  2130. if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
  2131. priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
  2132. else
  2133. priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
  2134. ret = iwlagn_hw_nic_init(priv);
  2135. if (ret) {
  2136. IWL_ERR(priv, "Unable to init nic\n");
  2137. return ret;
  2138. }
  2139. /* make sure rfkill handshake bits are cleared */
  2140. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2141. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2142. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2143. /* clear (again), then enable host interrupts */
  2144. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2145. iwl_enable_interrupts(priv);
  2146. /* really make sure rfkill handshake bits are cleared */
  2147. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2148. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2149. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2150. /* load bootstrap state machine,
  2151. * load bootstrap program into processor's memory,
  2152. * prepare to load the "initialize" uCode */
  2153. ret = iwlagn_load_ucode(priv);
  2154. if (ret) {
  2155. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2156. ret);
  2157. continue;
  2158. }
  2159. /* start card; "initialize" will load runtime ucode */
  2160. iwl_nic_start(priv);
  2161. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2162. return 0;
  2163. }
  2164. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2165. __iwl_down(priv);
  2166. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2167. /* tried to restart and config the device for as long as our
  2168. * patience could withstand */
  2169. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2170. return -EIO;
  2171. }
  2172. /*****************************************************************************
  2173. *
  2174. * Workqueue callbacks
  2175. *
  2176. *****************************************************************************/
  2177. static void iwl_bg_init_alive_start(struct work_struct *data)
  2178. {
  2179. struct iwl_priv *priv =
  2180. container_of(data, struct iwl_priv, init_alive_start.work);
  2181. mutex_lock(&priv->mutex);
  2182. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2183. mutex_unlock(&priv->mutex);
  2184. return;
  2185. }
  2186. iwlagn_init_alive_start(priv);
  2187. mutex_unlock(&priv->mutex);
  2188. }
  2189. static void iwl_bg_alive_start(struct work_struct *data)
  2190. {
  2191. struct iwl_priv *priv =
  2192. container_of(data, struct iwl_priv, alive_start.work);
  2193. mutex_lock(&priv->mutex);
  2194. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2195. goto unlock;
  2196. /* enable dram interrupt */
  2197. if (priv->cfg->ops->lib->isr_ops.reset)
  2198. priv->cfg->ops->lib->isr_ops.reset(priv);
  2199. iwl_alive_start(priv);
  2200. unlock:
  2201. mutex_unlock(&priv->mutex);
  2202. }
  2203. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2204. {
  2205. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2206. run_time_calib_work);
  2207. mutex_lock(&priv->mutex);
  2208. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2209. test_bit(STATUS_SCANNING, &priv->status)) {
  2210. mutex_unlock(&priv->mutex);
  2211. return;
  2212. }
  2213. if (priv->start_calib) {
  2214. if (iwl_bt_statistics(priv)) {
  2215. iwl_chain_noise_calibration(priv,
  2216. (void *)&priv->_agn.statistics_bt);
  2217. iwl_sensitivity_calibration(priv,
  2218. (void *)&priv->_agn.statistics_bt);
  2219. } else {
  2220. iwl_chain_noise_calibration(priv,
  2221. (void *)&priv->_agn.statistics);
  2222. iwl_sensitivity_calibration(priv,
  2223. (void *)&priv->_agn.statistics);
  2224. }
  2225. }
  2226. mutex_unlock(&priv->mutex);
  2227. }
  2228. static void iwl_bg_restart(struct work_struct *data)
  2229. {
  2230. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2231. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2232. return;
  2233. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2234. struct iwl_rxon_context *ctx;
  2235. bool bt_full_concurrent;
  2236. u8 bt_ci_compliance;
  2237. u8 bt_load;
  2238. u8 bt_status;
  2239. mutex_lock(&priv->mutex);
  2240. for_each_context(priv, ctx)
  2241. ctx->vif = NULL;
  2242. priv->is_open = 0;
  2243. /*
  2244. * __iwl_down() will clear the BT status variables,
  2245. * which is correct, but when we restart we really
  2246. * want to keep them so restore them afterwards.
  2247. *
  2248. * The restart process will later pick them up and
  2249. * re-configure the hw when we reconfigure the BT
  2250. * command.
  2251. */
  2252. bt_full_concurrent = priv->bt_full_concurrent;
  2253. bt_ci_compliance = priv->bt_ci_compliance;
  2254. bt_load = priv->bt_traffic_load;
  2255. bt_status = priv->bt_status;
  2256. __iwl_down(priv);
  2257. priv->bt_full_concurrent = bt_full_concurrent;
  2258. priv->bt_ci_compliance = bt_ci_compliance;
  2259. priv->bt_traffic_load = bt_load;
  2260. priv->bt_status = bt_status;
  2261. mutex_unlock(&priv->mutex);
  2262. iwl_cancel_deferred_work(priv);
  2263. ieee80211_restart_hw(priv->hw);
  2264. } else {
  2265. iwl_down(priv);
  2266. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2267. return;
  2268. mutex_lock(&priv->mutex);
  2269. __iwl_up(priv);
  2270. mutex_unlock(&priv->mutex);
  2271. }
  2272. }
  2273. static void iwl_bg_rx_replenish(struct work_struct *data)
  2274. {
  2275. struct iwl_priv *priv =
  2276. container_of(data, struct iwl_priv, rx_replenish);
  2277. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2278. return;
  2279. mutex_lock(&priv->mutex);
  2280. iwlagn_rx_replenish(priv);
  2281. mutex_unlock(&priv->mutex);
  2282. }
  2283. static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  2284. struct ieee80211_channel *chan,
  2285. enum nl80211_channel_type channel_type,
  2286. unsigned int wait)
  2287. {
  2288. struct iwl_priv *priv = hw->priv;
  2289. int ret;
  2290. /* Not supported if we don't have PAN */
  2291. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
  2292. ret = -EOPNOTSUPP;
  2293. goto free;
  2294. }
  2295. /* Not supported on pre-P2P firmware */
  2296. if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
  2297. BIT(NL80211_IFTYPE_P2P_CLIENT))) {
  2298. ret = -EOPNOTSUPP;
  2299. goto free;
  2300. }
  2301. mutex_lock(&priv->mutex);
  2302. if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
  2303. /*
  2304. * If the PAN context is free, use the normal
  2305. * way of doing remain-on-channel offload + TX.
  2306. */
  2307. ret = 1;
  2308. goto out;
  2309. }
  2310. /* TODO: queue up if scanning? */
  2311. if (test_bit(STATUS_SCANNING, &priv->status) ||
  2312. priv->_agn.offchan_tx_skb) {
  2313. ret = -EBUSY;
  2314. goto out;
  2315. }
  2316. /*
  2317. * max_scan_ie_len doesn't include the blank SSID or the header,
  2318. * so need to add that again here.
  2319. */
  2320. if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
  2321. ret = -ENOBUFS;
  2322. goto out;
  2323. }
  2324. priv->_agn.offchan_tx_skb = skb;
  2325. priv->_agn.offchan_tx_timeout = wait;
  2326. priv->_agn.offchan_tx_chan = chan;
  2327. ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
  2328. IWL_SCAN_OFFCH_TX, chan->band);
  2329. if (ret)
  2330. priv->_agn.offchan_tx_skb = NULL;
  2331. out:
  2332. mutex_unlock(&priv->mutex);
  2333. free:
  2334. if (ret < 0)
  2335. kfree_skb(skb);
  2336. return ret;
  2337. }
  2338. static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
  2339. {
  2340. struct iwl_priv *priv = hw->priv;
  2341. int ret;
  2342. mutex_lock(&priv->mutex);
  2343. if (!priv->_agn.offchan_tx_skb) {
  2344. ret = -EINVAL;
  2345. goto unlock;
  2346. }
  2347. priv->_agn.offchan_tx_skb = NULL;
  2348. ret = iwl_scan_cancel_timeout(priv, 200);
  2349. if (ret)
  2350. ret = -EIO;
  2351. unlock:
  2352. mutex_unlock(&priv->mutex);
  2353. return ret;
  2354. }
  2355. /*****************************************************************************
  2356. *
  2357. * mac80211 entry point functions
  2358. *
  2359. *****************************************************************************/
  2360. #define UCODE_READY_TIMEOUT (4 * HZ)
  2361. /*
  2362. * Not a mac80211 entry point function, but it fits in with all the
  2363. * other mac80211 functions grouped here.
  2364. */
  2365. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2366. struct iwlagn_ucode_capabilities *capa)
  2367. {
  2368. int ret;
  2369. struct ieee80211_hw *hw = priv->hw;
  2370. struct iwl_rxon_context *ctx;
  2371. hw->rate_control_algorithm = "iwl-agn-rs";
  2372. /* Tell mac80211 our characteristics */
  2373. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2374. IEEE80211_HW_AMPDU_AGGREGATION |
  2375. IEEE80211_HW_NEED_DTIM_PERIOD |
  2376. IEEE80211_HW_SPECTRUM_MGMT |
  2377. IEEE80211_HW_REPORTS_TX_ACK_STATUS;
  2378. hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
  2379. if (!priv->cfg->base_params->broken_powersave)
  2380. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2381. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2382. if (priv->cfg->sku & IWL_SKU_N)
  2383. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2384. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2385. if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
  2386. hw->flags |= IEEE80211_HW_MFP_CAPABLE;
  2387. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2388. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2389. for_each_context(priv, ctx) {
  2390. hw->wiphy->interface_modes |= ctx->interface_modes;
  2391. hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
  2392. }
  2393. hw->wiphy->max_remain_on_channel_duration = 1000;
  2394. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2395. WIPHY_FLAG_DISABLE_BEACON_HINTS |
  2396. WIPHY_FLAG_IBSS_RSN;
  2397. /*
  2398. * For now, disable PS by default because it affects
  2399. * RX performance significantly.
  2400. */
  2401. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2402. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2403. /* we create the 802.11 header and a zero-length SSID element */
  2404. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2405. /* Default value; 4 EDCA QOS priorities */
  2406. hw->queues = 4;
  2407. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2408. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2409. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2410. &priv->bands[IEEE80211_BAND_2GHZ];
  2411. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2412. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2413. &priv->bands[IEEE80211_BAND_5GHZ];
  2414. iwl_leds_init(priv);
  2415. ret = ieee80211_register_hw(priv->hw);
  2416. if (ret) {
  2417. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2418. return ret;
  2419. }
  2420. priv->mac80211_registered = 1;
  2421. return 0;
  2422. }
  2423. static int iwlagn_mac_start(struct ieee80211_hw *hw)
  2424. {
  2425. struct iwl_priv *priv = hw->priv;
  2426. int ret;
  2427. IWL_DEBUG_MAC80211(priv, "enter\n");
  2428. /* we should be verifying the device is ready to be opened */
  2429. mutex_lock(&priv->mutex);
  2430. ret = __iwl_up(priv);
  2431. mutex_unlock(&priv->mutex);
  2432. if (ret)
  2433. return ret;
  2434. if (iwl_is_rfkill(priv))
  2435. goto out;
  2436. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2437. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2438. * mac80211 will not be run successfully. */
  2439. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2440. test_bit(STATUS_READY, &priv->status),
  2441. UCODE_READY_TIMEOUT);
  2442. if (!ret) {
  2443. if (!test_bit(STATUS_READY, &priv->status)) {
  2444. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2445. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2446. return -ETIMEDOUT;
  2447. }
  2448. }
  2449. iwlagn_led_enable(priv);
  2450. out:
  2451. priv->is_open = 1;
  2452. IWL_DEBUG_MAC80211(priv, "leave\n");
  2453. return 0;
  2454. }
  2455. static void iwlagn_mac_stop(struct ieee80211_hw *hw)
  2456. {
  2457. struct iwl_priv *priv = hw->priv;
  2458. IWL_DEBUG_MAC80211(priv, "enter\n");
  2459. if (!priv->is_open)
  2460. return;
  2461. priv->is_open = 0;
  2462. iwl_down(priv);
  2463. flush_workqueue(priv->workqueue);
  2464. /* User space software may expect getting rfkill changes
  2465. * even if interface is down */
  2466. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2467. iwl_enable_rfkill_int(priv);
  2468. IWL_DEBUG_MAC80211(priv, "leave\n");
  2469. }
  2470. static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2471. {
  2472. struct iwl_priv *priv = hw->priv;
  2473. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2474. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2475. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2476. if (iwlagn_tx_skb(priv, skb))
  2477. dev_kfree_skb_any(skb);
  2478. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2479. }
  2480. static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
  2481. struct ieee80211_vif *vif,
  2482. struct ieee80211_key_conf *keyconf,
  2483. struct ieee80211_sta *sta,
  2484. u32 iv32, u16 *phase1key)
  2485. {
  2486. struct iwl_priv *priv = hw->priv;
  2487. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2488. IWL_DEBUG_MAC80211(priv, "enter\n");
  2489. iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
  2490. iv32, phase1key);
  2491. IWL_DEBUG_MAC80211(priv, "leave\n");
  2492. }
  2493. static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2494. struct ieee80211_vif *vif,
  2495. struct ieee80211_sta *sta,
  2496. struct ieee80211_key_conf *key)
  2497. {
  2498. struct iwl_priv *priv = hw->priv;
  2499. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2500. struct iwl_rxon_context *ctx = vif_priv->ctx;
  2501. int ret;
  2502. u8 sta_id;
  2503. bool is_default_wep_key = false;
  2504. IWL_DEBUG_MAC80211(priv, "enter\n");
  2505. if (priv->cfg->mod_params->sw_crypto) {
  2506. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2507. return -EOPNOTSUPP;
  2508. }
  2509. /*
  2510. * To support IBSS RSN, don't program group keys in IBSS, the
  2511. * hardware will then not attempt to decrypt the frames.
  2512. */
  2513. if (vif->type == NL80211_IFTYPE_ADHOC &&
  2514. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  2515. return -EOPNOTSUPP;
  2516. sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
  2517. if (sta_id == IWL_INVALID_STATION)
  2518. return -EINVAL;
  2519. mutex_lock(&priv->mutex);
  2520. iwl_scan_cancel_timeout(priv, 100);
  2521. /*
  2522. * If we are getting WEP group key and we didn't receive any key mapping
  2523. * so far, we are in legacy wep mode (group key only), otherwise we are
  2524. * in 1X mode.
  2525. * In legacy wep mode, we use another host command to the uCode.
  2526. */
  2527. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  2528. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  2529. !sta) {
  2530. if (cmd == SET_KEY)
  2531. is_default_wep_key = !ctx->key_mapping_keys;
  2532. else
  2533. is_default_wep_key =
  2534. (key->hw_key_idx == HW_KEY_DEFAULT);
  2535. }
  2536. switch (cmd) {
  2537. case SET_KEY:
  2538. if (is_default_wep_key)
  2539. ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
  2540. else
  2541. ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
  2542. key, sta_id);
  2543. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2544. break;
  2545. case DISABLE_KEY:
  2546. if (is_default_wep_key)
  2547. ret = iwl_remove_default_wep_key(priv, ctx, key);
  2548. else
  2549. ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
  2550. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2551. break;
  2552. default:
  2553. ret = -EINVAL;
  2554. }
  2555. mutex_unlock(&priv->mutex);
  2556. IWL_DEBUG_MAC80211(priv, "leave\n");
  2557. return ret;
  2558. }
  2559. static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
  2560. struct ieee80211_vif *vif,
  2561. enum ieee80211_ampdu_mlme_action action,
  2562. struct ieee80211_sta *sta, u16 tid, u16 *ssn,
  2563. u8 buf_size)
  2564. {
  2565. struct iwl_priv *priv = hw->priv;
  2566. int ret = -EINVAL;
  2567. struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
  2568. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2569. sta->addr, tid);
  2570. if (!(priv->cfg->sku & IWL_SKU_N))
  2571. return -EACCES;
  2572. mutex_lock(&priv->mutex);
  2573. switch (action) {
  2574. case IEEE80211_AMPDU_RX_START:
  2575. IWL_DEBUG_HT(priv, "start Rx\n");
  2576. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2577. break;
  2578. case IEEE80211_AMPDU_RX_STOP:
  2579. IWL_DEBUG_HT(priv, "stop Rx\n");
  2580. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2581. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2582. ret = 0;
  2583. break;
  2584. case IEEE80211_AMPDU_TX_START:
  2585. IWL_DEBUG_HT(priv, "start Tx\n");
  2586. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2587. if (ret == 0) {
  2588. priv->_agn.agg_tids_count++;
  2589. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2590. priv->_agn.agg_tids_count);
  2591. }
  2592. break;
  2593. case IEEE80211_AMPDU_TX_STOP:
  2594. IWL_DEBUG_HT(priv, "stop Tx\n");
  2595. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2596. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2597. priv->_agn.agg_tids_count--;
  2598. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2599. priv->_agn.agg_tids_count);
  2600. }
  2601. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2602. ret = 0;
  2603. if (priv->cfg->ht_params &&
  2604. priv->cfg->ht_params->use_rts_for_aggregation) {
  2605. struct iwl_station_priv *sta_priv =
  2606. (void *) sta->drv_priv;
  2607. /*
  2608. * switch off RTS/CTS if it was previously enabled
  2609. */
  2610. sta_priv->lq_sta.lq.general_params.flags &=
  2611. ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2612. iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
  2613. &sta_priv->lq_sta.lq, CMD_ASYNC, false);
  2614. }
  2615. break;
  2616. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2617. buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
  2618. iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
  2619. /*
  2620. * If the limit is 0, then it wasn't initialised yet,
  2621. * use the default. We can do that since we take the
  2622. * minimum below, and we don't want to go above our
  2623. * default due to hardware restrictions.
  2624. */
  2625. if (sta_priv->max_agg_bufsize == 0)
  2626. sta_priv->max_agg_bufsize =
  2627. LINK_QUAL_AGG_FRAME_LIMIT_DEF;
  2628. /*
  2629. * Even though in theory the peer could have different
  2630. * aggregation reorder buffer sizes for different sessions,
  2631. * our ucode doesn't allow for that and has a global limit
  2632. * for each station. Therefore, use the minimum of all the
  2633. * aggregation sessions and our default value.
  2634. */
  2635. sta_priv->max_agg_bufsize =
  2636. min(sta_priv->max_agg_bufsize, buf_size);
  2637. if (priv->cfg->ht_params &&
  2638. priv->cfg->ht_params->use_rts_for_aggregation) {
  2639. /*
  2640. * switch to RTS/CTS if it is the prefer protection
  2641. * method for HT traffic
  2642. */
  2643. sta_priv->lq_sta.lq.general_params.flags |=
  2644. LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2645. }
  2646. sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
  2647. sta_priv->max_agg_bufsize;
  2648. iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
  2649. &sta_priv->lq_sta.lq, CMD_ASYNC, false);
  2650. ret = 0;
  2651. break;
  2652. }
  2653. mutex_unlock(&priv->mutex);
  2654. return ret;
  2655. }
  2656. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2657. struct ieee80211_vif *vif,
  2658. struct ieee80211_sta *sta)
  2659. {
  2660. struct iwl_priv *priv = hw->priv;
  2661. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2662. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2663. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2664. int ret;
  2665. u8 sta_id;
  2666. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2667. sta->addr);
  2668. mutex_lock(&priv->mutex);
  2669. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2670. sta->addr);
  2671. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2672. atomic_set(&sta_priv->pending_frames, 0);
  2673. if (vif->type == NL80211_IFTYPE_AP)
  2674. sta_priv->client = true;
  2675. ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
  2676. is_ap, sta, &sta_id);
  2677. if (ret) {
  2678. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2679. sta->addr, ret);
  2680. /* Should we return success if return code is EEXIST ? */
  2681. mutex_unlock(&priv->mutex);
  2682. return ret;
  2683. }
  2684. sta_priv->common.sta_id = sta_id;
  2685. /* Initialize rate scaling */
  2686. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2687. sta->addr);
  2688. iwl_rs_rate_init(priv, sta, sta_id);
  2689. mutex_unlock(&priv->mutex);
  2690. return 0;
  2691. }
  2692. static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
  2693. struct ieee80211_channel_switch *ch_switch)
  2694. {
  2695. struct iwl_priv *priv = hw->priv;
  2696. const struct iwl_channel_info *ch_info;
  2697. struct ieee80211_conf *conf = &hw->conf;
  2698. struct ieee80211_channel *channel = ch_switch->channel;
  2699. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2700. /*
  2701. * MULTI-FIXME
  2702. * When we add support for multiple interfaces, we need to
  2703. * revisit this. The channel switch command in the device
  2704. * only affects the BSS context, but what does that really
  2705. * mean? And what if we get a CSA on the second interface?
  2706. * This needs a lot of work.
  2707. */
  2708. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2709. u16 ch;
  2710. unsigned long flags = 0;
  2711. IWL_DEBUG_MAC80211(priv, "enter\n");
  2712. mutex_lock(&priv->mutex);
  2713. if (iwl_is_rfkill(priv))
  2714. goto out;
  2715. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2716. test_bit(STATUS_SCANNING, &priv->status))
  2717. goto out;
  2718. if (!iwl_is_associated_ctx(ctx))
  2719. goto out;
  2720. /* channel switch in progress */
  2721. if (priv->switch_rxon.switch_in_progress == true)
  2722. goto out;
  2723. if (priv->cfg->ops->lib->set_channel_switch) {
  2724. ch = channel->hw_value;
  2725. if (le16_to_cpu(ctx->active.channel) != ch) {
  2726. ch_info = iwl_get_channel_info(priv,
  2727. channel->band,
  2728. ch);
  2729. if (!is_channel_valid(ch_info)) {
  2730. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  2731. goto out;
  2732. }
  2733. spin_lock_irqsave(&priv->lock, flags);
  2734. priv->current_ht_config.smps = conf->smps_mode;
  2735. /* Configure HT40 channels */
  2736. ctx->ht.enabled = conf_is_ht(conf);
  2737. if (ctx->ht.enabled) {
  2738. if (conf_is_ht40_minus(conf)) {
  2739. ctx->ht.extension_chan_offset =
  2740. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2741. ctx->ht.is_40mhz = true;
  2742. } else if (conf_is_ht40_plus(conf)) {
  2743. ctx->ht.extension_chan_offset =
  2744. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2745. ctx->ht.is_40mhz = true;
  2746. } else {
  2747. ctx->ht.extension_chan_offset =
  2748. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2749. ctx->ht.is_40mhz = false;
  2750. }
  2751. } else
  2752. ctx->ht.is_40mhz = false;
  2753. if ((le16_to_cpu(ctx->staging.channel) != ch))
  2754. ctx->staging.flags = 0;
  2755. iwl_set_rxon_channel(priv, channel, ctx);
  2756. iwl_set_rxon_ht(priv, ht_conf);
  2757. iwl_set_flags_for_band(priv, ctx, channel->band,
  2758. ctx->vif);
  2759. spin_unlock_irqrestore(&priv->lock, flags);
  2760. iwl_set_rate(priv);
  2761. /*
  2762. * at this point, staging_rxon has the
  2763. * configuration for channel switch
  2764. */
  2765. if (priv->cfg->ops->lib->set_channel_switch(priv,
  2766. ch_switch))
  2767. priv->switch_rxon.switch_in_progress = false;
  2768. }
  2769. }
  2770. out:
  2771. mutex_unlock(&priv->mutex);
  2772. if (!priv->switch_rxon.switch_in_progress)
  2773. ieee80211_chswitch_done(ctx->vif, false);
  2774. IWL_DEBUG_MAC80211(priv, "leave\n");
  2775. }
  2776. static void iwlagn_configure_filter(struct ieee80211_hw *hw,
  2777. unsigned int changed_flags,
  2778. unsigned int *total_flags,
  2779. u64 multicast)
  2780. {
  2781. struct iwl_priv *priv = hw->priv;
  2782. __le32 filter_or = 0, filter_nand = 0;
  2783. struct iwl_rxon_context *ctx;
  2784. #define CHK(test, flag) do { \
  2785. if (*total_flags & (test)) \
  2786. filter_or |= (flag); \
  2787. else \
  2788. filter_nand |= (flag); \
  2789. } while (0)
  2790. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2791. changed_flags, *total_flags);
  2792. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2793. /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
  2794. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
  2795. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2796. #undef CHK
  2797. mutex_lock(&priv->mutex);
  2798. for_each_context(priv, ctx) {
  2799. ctx->staging.filter_flags &= ~filter_nand;
  2800. ctx->staging.filter_flags |= filter_or;
  2801. /*
  2802. * Not committing directly because hardware can perform a scan,
  2803. * but we'll eventually commit the filter flags change anyway.
  2804. */
  2805. }
  2806. mutex_unlock(&priv->mutex);
  2807. /*
  2808. * Receiving all multicast frames is always enabled by the
  2809. * default flags setup in iwl_connection_init_rx_config()
  2810. * since we currently do not support programming multicast
  2811. * filters into the device.
  2812. */
  2813. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2814. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2815. }
  2816. static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
  2817. {
  2818. struct iwl_priv *priv = hw->priv;
  2819. mutex_lock(&priv->mutex);
  2820. IWL_DEBUG_MAC80211(priv, "enter\n");
  2821. /* do not support "flush" */
  2822. if (!priv->cfg->ops->lib->txfifo_flush)
  2823. goto done;
  2824. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2825. IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
  2826. goto done;
  2827. }
  2828. if (iwl_is_rfkill(priv)) {
  2829. IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
  2830. goto done;
  2831. }
  2832. /*
  2833. * mac80211 will not push any more frames for transmit
  2834. * until the flush is completed
  2835. */
  2836. if (drop) {
  2837. IWL_DEBUG_MAC80211(priv, "send flush command\n");
  2838. if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
  2839. IWL_ERR(priv, "flush request fail\n");
  2840. goto done;
  2841. }
  2842. }
  2843. IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
  2844. iwlagn_wait_tx_queue_empty(priv);
  2845. done:
  2846. mutex_unlock(&priv->mutex);
  2847. IWL_DEBUG_MAC80211(priv, "leave\n");
  2848. }
  2849. static void iwlagn_disable_roc(struct iwl_priv *priv)
  2850. {
  2851. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
  2852. struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
  2853. lockdep_assert_held(&priv->mutex);
  2854. if (!ctx->is_active)
  2855. return;
  2856. ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
  2857. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2858. iwl_set_rxon_channel(priv, chan, ctx);
  2859. iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
  2860. priv->_agn.hw_roc_channel = NULL;
  2861. iwlcore_commit_rxon(priv, ctx);
  2862. ctx->is_active = false;
  2863. }
  2864. static void iwlagn_bg_roc_done(struct work_struct *work)
  2865. {
  2866. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2867. _agn.hw_roc_work.work);
  2868. mutex_lock(&priv->mutex);
  2869. ieee80211_remain_on_channel_expired(priv->hw);
  2870. iwlagn_disable_roc(priv);
  2871. mutex_unlock(&priv->mutex);
  2872. }
  2873. static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
  2874. struct ieee80211_channel *channel,
  2875. enum nl80211_channel_type channel_type,
  2876. int duration)
  2877. {
  2878. struct iwl_priv *priv = hw->priv;
  2879. int err = 0;
  2880. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
  2881. return -EOPNOTSUPP;
  2882. if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
  2883. BIT(NL80211_IFTYPE_P2P_CLIENT)))
  2884. return -EOPNOTSUPP;
  2885. mutex_lock(&priv->mutex);
  2886. if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
  2887. test_bit(STATUS_SCAN_HW, &priv->status)) {
  2888. err = -EBUSY;
  2889. goto out;
  2890. }
  2891. priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
  2892. priv->_agn.hw_roc_channel = channel;
  2893. priv->_agn.hw_roc_chantype = channel_type;
  2894. priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
  2895. iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
  2896. queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
  2897. msecs_to_jiffies(duration + 20));
  2898. msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
  2899. ieee80211_ready_on_channel(priv->hw);
  2900. out:
  2901. mutex_unlock(&priv->mutex);
  2902. return err;
  2903. }
  2904. static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
  2905. {
  2906. struct iwl_priv *priv = hw->priv;
  2907. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
  2908. return -EOPNOTSUPP;
  2909. cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
  2910. mutex_lock(&priv->mutex);
  2911. iwlagn_disable_roc(priv);
  2912. mutex_unlock(&priv->mutex);
  2913. return 0;
  2914. }
  2915. /*****************************************************************************
  2916. *
  2917. * driver setup and teardown
  2918. *
  2919. *****************************************************************************/
  2920. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2921. {
  2922. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2923. init_waitqueue_head(&priv->wait_command_queue);
  2924. INIT_WORK(&priv->restart, iwl_bg_restart);
  2925. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2926. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2927. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2928. INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
  2929. INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
  2930. INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
  2931. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2932. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2933. INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
  2934. iwl_setup_scan_deferred_work(priv);
  2935. if (priv->cfg->ops->lib->setup_deferred_work)
  2936. priv->cfg->ops->lib->setup_deferred_work(priv);
  2937. init_timer(&priv->statistics_periodic);
  2938. priv->statistics_periodic.data = (unsigned long)priv;
  2939. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2940. init_timer(&priv->ucode_trace);
  2941. priv->ucode_trace.data = (unsigned long)priv;
  2942. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2943. init_timer(&priv->watchdog);
  2944. priv->watchdog.data = (unsigned long)priv;
  2945. priv->watchdog.function = iwl_bg_watchdog;
  2946. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2947. iwl_irq_tasklet, (unsigned long)priv);
  2948. }
  2949. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2950. {
  2951. if (priv->cfg->ops->lib->cancel_deferred_work)
  2952. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2953. cancel_delayed_work_sync(&priv->init_alive_start);
  2954. cancel_delayed_work(&priv->alive_start);
  2955. cancel_work_sync(&priv->run_time_calib_work);
  2956. cancel_work_sync(&priv->beacon_update);
  2957. iwl_cancel_scan_deferred_work(priv);
  2958. cancel_work_sync(&priv->bt_full_concurrency);
  2959. cancel_work_sync(&priv->bt_runtime_config);
  2960. del_timer_sync(&priv->statistics_periodic);
  2961. del_timer_sync(&priv->ucode_trace);
  2962. }
  2963. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2964. struct ieee80211_rate *rates)
  2965. {
  2966. int i;
  2967. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2968. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2969. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2970. rates[i].hw_value_short = i;
  2971. rates[i].flags = 0;
  2972. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2973. /*
  2974. * If CCK != 1M then set short preamble rate flag.
  2975. */
  2976. rates[i].flags |=
  2977. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2978. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2979. }
  2980. }
  2981. }
  2982. static int iwl_init_drv(struct iwl_priv *priv)
  2983. {
  2984. int ret;
  2985. spin_lock_init(&priv->sta_lock);
  2986. spin_lock_init(&priv->hcmd_lock);
  2987. INIT_LIST_HEAD(&priv->free_frames);
  2988. mutex_init(&priv->mutex);
  2989. priv->ieee_channels = NULL;
  2990. priv->ieee_rates = NULL;
  2991. priv->band = IEEE80211_BAND_2GHZ;
  2992. priv->iw_mode = NL80211_IFTYPE_STATION;
  2993. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2994. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2995. priv->_agn.agg_tids_count = 0;
  2996. /* initialize force reset */
  2997. priv->force_reset[IWL_RF_RESET].reset_duration =
  2998. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2999. priv->force_reset[IWL_FW_RESET].reset_duration =
  3000. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3001. priv->rx_statistics_jiffies = jiffies;
  3002. /* Choose which receivers/antennas to use */
  3003. if (priv->cfg->ops->hcmd->set_rxon_chain)
  3004. priv->cfg->ops->hcmd->set_rxon_chain(priv,
  3005. &priv->contexts[IWL_RXON_CTX_BSS]);
  3006. iwl_init_scan_params(priv);
  3007. /* init bt coex */
  3008. if (priv->cfg->bt_params &&
  3009. priv->cfg->bt_params->advanced_bt_coexist) {
  3010. priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
  3011. priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
  3012. priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
  3013. priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
  3014. priv->bt_duration = BT_DURATION_LIMIT_DEF;
  3015. priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
  3016. }
  3017. /* Set the tx_power_user_lmt to the lowest power level
  3018. * this value will get overwritten by channel max power avg
  3019. * from eeprom */
  3020. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  3021. priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  3022. ret = iwl_init_channel_map(priv);
  3023. if (ret) {
  3024. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3025. goto err;
  3026. }
  3027. ret = iwlcore_init_geos(priv);
  3028. if (ret) {
  3029. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3030. goto err_free_channel_map;
  3031. }
  3032. iwl_init_hw_rates(priv, priv->ieee_rates);
  3033. return 0;
  3034. err_free_channel_map:
  3035. iwl_free_channel_map(priv);
  3036. err:
  3037. return ret;
  3038. }
  3039. static void iwl_uninit_drv(struct iwl_priv *priv)
  3040. {
  3041. iwl_calib_free_results(priv);
  3042. iwlcore_free_geos(priv);
  3043. iwl_free_channel_map(priv);
  3044. kfree(priv->scan_cmd);
  3045. }
  3046. struct ieee80211_ops iwlagn_hw_ops = {
  3047. .tx = iwlagn_mac_tx,
  3048. .start = iwlagn_mac_start,
  3049. .stop = iwlagn_mac_stop,
  3050. .add_interface = iwl_mac_add_interface,
  3051. .remove_interface = iwl_mac_remove_interface,
  3052. .change_interface = iwl_mac_change_interface,
  3053. .config = iwlagn_mac_config,
  3054. .configure_filter = iwlagn_configure_filter,
  3055. .set_key = iwlagn_mac_set_key,
  3056. .update_tkip_key = iwlagn_mac_update_tkip_key,
  3057. .conf_tx = iwl_mac_conf_tx,
  3058. .bss_info_changed = iwlagn_bss_info_changed,
  3059. .ampdu_action = iwlagn_mac_ampdu_action,
  3060. .hw_scan = iwl_mac_hw_scan,
  3061. .sta_notify = iwlagn_mac_sta_notify,
  3062. .sta_add = iwlagn_mac_sta_add,
  3063. .sta_remove = iwl_mac_sta_remove,
  3064. .channel_switch = iwlagn_mac_channel_switch,
  3065. .flush = iwlagn_mac_flush,
  3066. .tx_last_beacon = iwl_mac_tx_last_beacon,
  3067. .remain_on_channel = iwl_mac_remain_on_channel,
  3068. .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
  3069. .offchannel_tx = iwl_mac_offchannel_tx,
  3070. .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
  3071. };
  3072. static void iwl_hw_detect(struct iwl_priv *priv)
  3073. {
  3074. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  3075. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  3076. priv->rev_id = priv->pci_dev->revision;
  3077. IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
  3078. }
  3079. static int iwl_set_hw_params(struct iwl_priv *priv)
  3080. {
  3081. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  3082. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  3083. if (priv->cfg->mod_params->amsdu_size_8K)
  3084. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  3085. else
  3086. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  3087. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  3088. if (priv->cfg->mod_params->disable_11n)
  3089. priv->cfg->sku &= ~IWL_SKU_N;
  3090. /* Device-specific setup */
  3091. return priv->cfg->ops->lib->set_hw_params(priv);
  3092. }
  3093. static const u8 iwlagn_bss_ac_to_fifo[] = {
  3094. IWL_TX_FIFO_VO,
  3095. IWL_TX_FIFO_VI,
  3096. IWL_TX_FIFO_BE,
  3097. IWL_TX_FIFO_BK,
  3098. };
  3099. static const u8 iwlagn_bss_ac_to_queue[] = {
  3100. 0, 1, 2, 3,
  3101. };
  3102. static const u8 iwlagn_pan_ac_to_fifo[] = {
  3103. IWL_TX_FIFO_VO_IPAN,
  3104. IWL_TX_FIFO_VI_IPAN,
  3105. IWL_TX_FIFO_BE_IPAN,
  3106. IWL_TX_FIFO_BK_IPAN,
  3107. };
  3108. static const u8 iwlagn_pan_ac_to_queue[] = {
  3109. 7, 6, 5, 4,
  3110. };
  3111. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3112. {
  3113. int err = 0, i;
  3114. struct iwl_priv *priv;
  3115. struct ieee80211_hw *hw;
  3116. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3117. unsigned long flags;
  3118. u16 pci_cmd, num_mac;
  3119. /************************
  3120. * 1. Allocating HW data
  3121. ************************/
  3122. hw = iwl_alloc_all(cfg);
  3123. if (!hw) {
  3124. err = -ENOMEM;
  3125. goto out;
  3126. }
  3127. priv = hw->priv;
  3128. /* At this point both hw and priv are allocated. */
  3129. /*
  3130. * The default context is always valid,
  3131. * more may be discovered when firmware
  3132. * is loaded.
  3133. */
  3134. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  3135. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  3136. priv->contexts[i].ctxid = i;
  3137. priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
  3138. priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
  3139. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  3140. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  3141. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  3142. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  3143. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  3144. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  3145. priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
  3146. priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
  3147. priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
  3148. BIT(NL80211_IFTYPE_ADHOC);
  3149. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  3150. BIT(NL80211_IFTYPE_STATION);
  3151. priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
  3152. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  3153. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  3154. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  3155. priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
  3156. priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
  3157. priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
  3158. priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
  3159. priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
  3160. priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
  3161. priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
  3162. priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
  3163. priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
  3164. priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
  3165. priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
  3166. priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
  3167. BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
  3168. #ifdef CONFIG_IWL_P2P
  3169. priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
  3170. BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
  3171. #endif
  3172. priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
  3173. priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
  3174. priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
  3175. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
  3176. SET_IEEE80211_DEV(hw, &pdev->dev);
  3177. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3178. priv->cfg = cfg;
  3179. priv->pci_dev = pdev;
  3180. priv->inta_mask = CSR_INI_SET_MASK;
  3181. /* is antenna coupling more than 35dB ? */
  3182. priv->bt_ant_couple_ok =
  3183. (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
  3184. true : false;
  3185. /* enable/disable bt channel inhibition */
  3186. priv->bt_ch_announce = iwlagn_bt_ch_announce;
  3187. IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
  3188. (priv->bt_ch_announce) ? "On" : "Off");
  3189. if (iwl_alloc_traffic_mem(priv))
  3190. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3191. /**************************
  3192. * 2. Initializing PCI bus
  3193. **************************/
  3194. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3195. PCIE_LINK_STATE_CLKPM);
  3196. if (pci_enable_device(pdev)) {
  3197. err = -ENODEV;
  3198. goto out_ieee80211_free_hw;
  3199. }
  3200. pci_set_master(pdev);
  3201. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3202. if (!err)
  3203. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3204. if (err) {
  3205. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3206. if (!err)
  3207. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3208. /* both attempts failed: */
  3209. if (err) {
  3210. IWL_WARN(priv, "No suitable DMA available.\n");
  3211. goto out_pci_disable_device;
  3212. }
  3213. }
  3214. err = pci_request_regions(pdev, DRV_NAME);
  3215. if (err)
  3216. goto out_pci_disable_device;
  3217. pci_set_drvdata(pdev, priv);
  3218. /***********************
  3219. * 3. Read REV register
  3220. ***********************/
  3221. priv->hw_base = pci_iomap(pdev, 0, 0);
  3222. if (!priv->hw_base) {
  3223. err = -ENODEV;
  3224. goto out_pci_release_regions;
  3225. }
  3226. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3227. (unsigned long long) pci_resource_len(pdev, 0));
  3228. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3229. /* these spin locks will be used in apm_ops.init and EEPROM access
  3230. * we should init now
  3231. */
  3232. spin_lock_init(&priv->reg_lock);
  3233. spin_lock_init(&priv->lock);
  3234. /*
  3235. * stop and reset the on-board processor just in case it is in a
  3236. * strange state ... like being left stranded by a primary kernel
  3237. * and this is now the kdump kernel trying to start up
  3238. */
  3239. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3240. iwl_hw_detect(priv);
  3241. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3242. priv->cfg->name, priv->hw_rev);
  3243. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3244. * PCI Tx retries from interfering with C3 CPU state */
  3245. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3246. iwl_prepare_card_hw(priv);
  3247. if (!priv->hw_ready) {
  3248. IWL_WARN(priv, "Failed, HW not ready\n");
  3249. goto out_iounmap;
  3250. }
  3251. /*****************
  3252. * 4. Read EEPROM
  3253. *****************/
  3254. /* Read the EEPROM */
  3255. err = iwl_eeprom_init(priv);
  3256. if (err) {
  3257. IWL_ERR(priv, "Unable to init EEPROM\n");
  3258. goto out_iounmap;
  3259. }
  3260. err = iwl_eeprom_check_version(priv);
  3261. if (err)
  3262. goto out_free_eeprom;
  3263. err = iwl_eeprom_check_sku(priv);
  3264. if (err)
  3265. goto out_free_eeprom;
  3266. /* extract MAC Address */
  3267. iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
  3268. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  3269. priv->hw->wiphy->addresses = priv->addresses;
  3270. priv->hw->wiphy->n_addresses = 1;
  3271. num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
  3272. if (num_mac > 1) {
  3273. memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
  3274. ETH_ALEN);
  3275. priv->addresses[1].addr[5]++;
  3276. priv->hw->wiphy->n_addresses++;
  3277. }
  3278. /************************
  3279. * 5. Setup HW constants
  3280. ************************/
  3281. if (iwl_set_hw_params(priv)) {
  3282. IWL_ERR(priv, "failed to set hw parameters\n");
  3283. goto out_free_eeprom;
  3284. }
  3285. /*******************
  3286. * 6. Setup priv
  3287. *******************/
  3288. err = iwl_init_drv(priv);
  3289. if (err)
  3290. goto out_free_eeprom;
  3291. /* At this point both hw and priv are initialized. */
  3292. /********************
  3293. * 7. Setup services
  3294. ********************/
  3295. spin_lock_irqsave(&priv->lock, flags);
  3296. iwl_disable_interrupts(priv);
  3297. spin_unlock_irqrestore(&priv->lock, flags);
  3298. pci_enable_msi(priv->pci_dev);
  3299. if (priv->cfg->ops->lib->isr_ops.alloc)
  3300. priv->cfg->ops->lib->isr_ops.alloc(priv);
  3301. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
  3302. IRQF_SHARED, DRV_NAME, priv);
  3303. if (err) {
  3304. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3305. goto out_disable_msi;
  3306. }
  3307. iwl_setup_deferred_work(priv);
  3308. iwl_setup_rx_handlers(priv);
  3309. /*********************************************
  3310. * 8. Enable interrupts and read RFKILL state
  3311. *********************************************/
  3312. /* enable rfkill interrupt: hw bug w/a */
  3313. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3314. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3315. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3316. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3317. }
  3318. iwl_enable_rfkill_int(priv);
  3319. /* If platform's RF_KILL switch is NOT set to KILL */
  3320. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3321. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3322. else
  3323. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3324. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3325. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3326. iwl_power_initialize(priv);
  3327. iwl_tt_initialize(priv);
  3328. init_completion(&priv->_agn.firmware_loading_complete);
  3329. err = iwl_request_firmware(priv, true);
  3330. if (err)
  3331. goto out_destroy_workqueue;
  3332. return 0;
  3333. out_destroy_workqueue:
  3334. destroy_workqueue(priv->workqueue);
  3335. priv->workqueue = NULL;
  3336. free_irq(priv->pci_dev->irq, priv);
  3337. if (priv->cfg->ops->lib->isr_ops.free)
  3338. priv->cfg->ops->lib->isr_ops.free(priv);
  3339. out_disable_msi:
  3340. pci_disable_msi(priv->pci_dev);
  3341. iwl_uninit_drv(priv);
  3342. out_free_eeprom:
  3343. iwl_eeprom_free(priv);
  3344. out_iounmap:
  3345. pci_iounmap(pdev, priv->hw_base);
  3346. out_pci_release_regions:
  3347. pci_set_drvdata(pdev, NULL);
  3348. pci_release_regions(pdev);
  3349. out_pci_disable_device:
  3350. pci_disable_device(pdev);
  3351. out_ieee80211_free_hw:
  3352. iwl_free_traffic_mem(priv);
  3353. ieee80211_free_hw(priv->hw);
  3354. out:
  3355. return err;
  3356. }
  3357. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3358. {
  3359. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3360. unsigned long flags;
  3361. if (!priv)
  3362. return;
  3363. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3364. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3365. iwl_dbgfs_unregister(priv);
  3366. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3367. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3368. * to be called and iwl_down since we are removing the device
  3369. * we need to set STATUS_EXIT_PENDING bit.
  3370. */
  3371. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3372. iwl_leds_exit(priv);
  3373. if (priv->mac80211_registered) {
  3374. ieee80211_unregister_hw(priv->hw);
  3375. priv->mac80211_registered = 0;
  3376. } else {
  3377. iwl_down(priv);
  3378. }
  3379. /*
  3380. * Make sure device is reset to low power before unloading driver.
  3381. * This may be redundant with iwl_down(), but there are paths to
  3382. * run iwl_down() without calling apm_ops.stop(), and there are
  3383. * paths to avoid running iwl_down() at all before leaving driver.
  3384. * This (inexpensive) call *makes sure* device is reset.
  3385. */
  3386. iwl_apm_stop(priv);
  3387. iwl_tt_exit(priv);
  3388. /* make sure we flush any pending irq or
  3389. * tasklet for the driver
  3390. */
  3391. spin_lock_irqsave(&priv->lock, flags);
  3392. iwl_disable_interrupts(priv);
  3393. spin_unlock_irqrestore(&priv->lock, flags);
  3394. iwl_synchronize_irq(priv);
  3395. iwl_dealloc_ucode_pci(priv);
  3396. if (priv->rxq.bd)
  3397. iwlagn_rx_queue_free(priv, &priv->rxq);
  3398. iwlagn_hw_txq_ctx_free(priv);
  3399. iwl_eeprom_free(priv);
  3400. /*netif_stop_queue(dev); */
  3401. flush_workqueue(priv->workqueue);
  3402. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3403. * priv->workqueue... so we can't take down the workqueue
  3404. * until now... */
  3405. destroy_workqueue(priv->workqueue);
  3406. priv->workqueue = NULL;
  3407. iwl_free_traffic_mem(priv);
  3408. free_irq(priv->pci_dev->irq, priv);
  3409. pci_disable_msi(priv->pci_dev);
  3410. pci_iounmap(pdev, priv->hw_base);
  3411. pci_release_regions(pdev);
  3412. pci_disable_device(pdev);
  3413. pci_set_drvdata(pdev, NULL);
  3414. iwl_uninit_drv(priv);
  3415. if (priv->cfg->ops->lib->isr_ops.free)
  3416. priv->cfg->ops->lib->isr_ops.free(priv);
  3417. dev_kfree_skb(priv->beacon_skb);
  3418. ieee80211_free_hw(priv->hw);
  3419. }
  3420. /*****************************************************************************
  3421. *
  3422. * driver and module entry point
  3423. *
  3424. *****************************************************************************/
  3425. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3426. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3427. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3428. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3429. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3430. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3431. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3432. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3433. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3434. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3435. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3436. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3437. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3438. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3439. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3440. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3441. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3442. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3443. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3444. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3445. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3446. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3447. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3448. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3449. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3450. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3451. /* 5300 Series WiFi */
  3452. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3453. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3454. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3455. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3456. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3457. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3458. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3459. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3460. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3461. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3462. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3463. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3464. /* 5350 Series WiFi/WiMax */
  3465. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3466. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3467. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3468. /* 5150 Series Wifi/WiMax */
  3469. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3470. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3471. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3472. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3473. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3474. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3475. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3476. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3477. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3478. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3479. /* 6x00 Series */
  3480. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3481. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3482. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3483. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3484. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3485. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3486. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3487. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3488. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3489. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3490. /* 6x05 Series */
  3491. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
  3492. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
  3493. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
  3494. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
  3495. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
  3496. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
  3497. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
  3498. /* 6x30 Series */
  3499. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
  3500. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
  3501. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
  3502. {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
  3503. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
  3504. {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
  3505. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
  3506. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
  3507. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
  3508. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
  3509. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
  3510. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
  3511. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
  3512. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
  3513. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
  3514. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
  3515. /* 6x50 WiFi/WiMax Series */
  3516. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3517. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3518. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3519. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3520. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3521. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3522. /* 6150 WiFi/WiMax Series */
  3523. {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
  3524. {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
  3525. {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
  3526. {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
  3527. {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
  3528. {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
  3529. /* 1000 Series WiFi */
  3530. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3531. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3532. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3533. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3534. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3535. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3536. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3537. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3538. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3539. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3540. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3541. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3542. /* 100 Series WiFi */
  3543. {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
  3544. {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
  3545. {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
  3546. {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
  3547. {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
  3548. {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
  3549. /* 130 Series WiFi */
  3550. {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
  3551. {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
  3552. {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
  3553. {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
  3554. {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
  3555. {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
  3556. /* 2x00 Series */
  3557. {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
  3558. {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
  3559. {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
  3560. {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
  3561. {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
  3562. {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
  3563. /* 2x30 Series */
  3564. {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
  3565. {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
  3566. {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
  3567. {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
  3568. {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
  3569. {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
  3570. /* 6x35 Series */
  3571. {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
  3572. {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
  3573. {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
  3574. {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
  3575. {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
  3576. {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
  3577. {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
  3578. {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
  3579. {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
  3580. /* 200 Series */
  3581. {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
  3582. {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
  3583. {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
  3584. {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
  3585. {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
  3586. {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
  3587. /* 230 Series */
  3588. {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
  3589. {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
  3590. {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
  3591. {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
  3592. {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
  3593. {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
  3594. {0}
  3595. };
  3596. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3597. static struct pci_driver iwl_driver = {
  3598. .name = DRV_NAME,
  3599. .id_table = iwl_hw_card_ids,
  3600. .probe = iwl_pci_probe,
  3601. .remove = __devexit_p(iwl_pci_remove),
  3602. .driver.pm = IWL_PM_OPS,
  3603. };
  3604. static int __init iwl_init(void)
  3605. {
  3606. int ret;
  3607. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3608. pr_info(DRV_COPYRIGHT "\n");
  3609. ret = iwlagn_rate_control_register();
  3610. if (ret) {
  3611. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3612. return ret;
  3613. }
  3614. ret = pci_register_driver(&iwl_driver);
  3615. if (ret) {
  3616. pr_err("Unable to initialize PCI module\n");
  3617. goto error_register;
  3618. }
  3619. return ret;
  3620. error_register:
  3621. iwlagn_rate_control_unregister();
  3622. return ret;
  3623. }
  3624. static void __exit iwl_exit(void)
  3625. {
  3626. pci_unregister_driver(&iwl_driver);
  3627. iwlagn_rate_control_unregister();
  3628. }
  3629. module_exit(iwl_exit);
  3630. module_init(iwl_init);
  3631. #ifdef CONFIG_IWLWIFI_DEBUG
  3632. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3633. MODULE_PARM_DESC(debug, "debug output mask");
  3634. #endif
  3635. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3636. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3637. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3638. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3639. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3640. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3641. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3642. int, S_IRUGO);
  3643. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3644. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3645. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3646. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3647. S_IRUGO);
  3648. MODULE_PARM_DESC(ucode_alternative,
  3649. "specify ucode alternative to use from ucode file");
  3650. module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
  3651. MODULE_PARM_DESC(antenna_coupling,
  3652. "specify antenna coupling in dB (defualt: 0 dB)");
  3653. module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
  3654. MODULE_PARM_DESC(bt_ch_inhibition,
  3655. "Disable BT channel inhibition (default: enable)");
  3656. module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
  3657. MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
  3658. module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
  3659. MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");