arizona-core.c 23 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/slab.h>
  25. #include <linux/mfd/arizona/core.h>
  26. #include <linux/mfd/arizona/registers.h>
  27. #include "arizona.h"
  28. static const char *wm5102_core_supplies[] = {
  29. "AVDD",
  30. "DBVDD1",
  31. };
  32. int arizona_clk32k_enable(struct arizona *arizona)
  33. {
  34. int ret = 0;
  35. mutex_lock(&arizona->clk_lock);
  36. arizona->clk32k_ref++;
  37. if (arizona->clk32k_ref == 1) {
  38. switch (arizona->pdata.clk32k_src) {
  39. case ARIZONA_32KZ_MCLK1:
  40. ret = pm_runtime_get_sync(arizona->dev);
  41. if (ret != 0)
  42. goto out;
  43. break;
  44. }
  45. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  46. ARIZONA_CLK_32K_ENA,
  47. ARIZONA_CLK_32K_ENA);
  48. }
  49. out:
  50. if (ret != 0)
  51. arizona->clk32k_ref--;
  52. mutex_unlock(&arizona->clk_lock);
  53. return ret;
  54. }
  55. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  56. int arizona_clk32k_disable(struct arizona *arizona)
  57. {
  58. int ret = 0;
  59. mutex_lock(&arizona->clk_lock);
  60. BUG_ON(arizona->clk32k_ref <= 0);
  61. arizona->clk32k_ref--;
  62. if (arizona->clk32k_ref == 0) {
  63. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  64. ARIZONA_CLK_32K_ENA, 0);
  65. switch (arizona->pdata.clk32k_src) {
  66. case ARIZONA_32KZ_MCLK1:
  67. pm_runtime_put_sync(arizona->dev);
  68. break;
  69. }
  70. }
  71. mutex_unlock(&arizona->clk_lock);
  72. return ret;
  73. }
  74. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  75. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  76. {
  77. struct arizona *arizona = data;
  78. dev_err(arizona->dev, "CLKGEN error\n");
  79. return IRQ_HANDLED;
  80. }
  81. static irqreturn_t arizona_underclocked(int irq, void *data)
  82. {
  83. struct arizona *arizona = data;
  84. unsigned int val;
  85. int ret;
  86. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  87. &val);
  88. if (ret != 0) {
  89. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  90. ret);
  91. return IRQ_NONE;
  92. }
  93. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  94. dev_err(arizona->dev, "AIF3 underclocked\n");
  95. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  96. dev_err(arizona->dev, "AIF2 underclocked\n");
  97. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  98. dev_err(arizona->dev, "AIF1 underclocked\n");
  99. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  100. dev_err(arizona->dev, "ISRC2 underclocked\n");
  101. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  102. dev_err(arizona->dev, "ISRC1 underclocked\n");
  103. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  104. dev_err(arizona->dev, "FX underclocked\n");
  105. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  106. dev_err(arizona->dev, "ASRC underclocked\n");
  107. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  108. dev_err(arizona->dev, "DAC underclocked\n");
  109. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  110. dev_err(arizona->dev, "ADC underclocked\n");
  111. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  112. dev_err(arizona->dev, "Mixer dropped sample\n");
  113. return IRQ_HANDLED;
  114. }
  115. static irqreturn_t arizona_overclocked(int irq, void *data)
  116. {
  117. struct arizona *arizona = data;
  118. unsigned int val[2];
  119. int ret;
  120. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  121. &val[0], 2);
  122. if (ret != 0) {
  123. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  124. ret);
  125. return IRQ_NONE;
  126. }
  127. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  128. dev_err(arizona->dev, "PWM overclocked\n");
  129. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  130. dev_err(arizona->dev, "FX core overclocked\n");
  131. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  132. dev_err(arizona->dev, "DAC SYS overclocked\n");
  133. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  134. dev_err(arizona->dev, "DAC WARP overclocked\n");
  135. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  136. dev_err(arizona->dev, "ADC overclocked\n");
  137. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  138. dev_err(arizona->dev, "Mixer overclocked\n");
  139. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  140. dev_err(arizona->dev, "AIF3 overclocked\n");
  141. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  142. dev_err(arizona->dev, "AIF2 overclocked\n");
  143. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  144. dev_err(arizona->dev, "AIF1 overclocked\n");
  145. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  146. dev_err(arizona->dev, "Pad control overclocked\n");
  147. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  148. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  149. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  150. dev_err(arizona->dev, "Slimbus async overclocked\n");
  151. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  152. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  153. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  154. dev_err(arizona->dev, "ASRC async system overclocked\n");
  155. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  156. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  157. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  158. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  159. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  160. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  161. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  162. dev_err(arizona->dev, "DSP1 overclocked\n");
  163. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  164. dev_err(arizona->dev, "ISRC2 overclocked\n");
  165. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  166. dev_err(arizona->dev, "ISRC1 overclocked\n");
  167. return IRQ_HANDLED;
  168. }
  169. static int arizona_poll_reg(struct arizona *arizona,
  170. int timeout, unsigned int reg,
  171. unsigned int mask, unsigned int target)
  172. {
  173. unsigned int val = 0;
  174. int ret, i;
  175. for (i = 0; i < timeout; i++) {
  176. ret = regmap_read(arizona->regmap, reg, &val);
  177. if (ret != 0) {
  178. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  179. reg, ret);
  180. continue;
  181. }
  182. if ((val & mask) == target)
  183. return 0;
  184. msleep(1);
  185. }
  186. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  187. return -ETIMEDOUT;
  188. }
  189. static int arizona_wait_for_boot(struct arizona *arizona)
  190. {
  191. int ret;
  192. /*
  193. * We can't use an interrupt as we need to runtime resume to do so,
  194. * we won't race with the interrupt handler as it'll be blocked on
  195. * runtime resume.
  196. */
  197. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  198. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  199. if (!ret)
  200. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  201. ARIZONA_BOOT_DONE_STS);
  202. pm_runtime_mark_last_busy(arizona->dev);
  203. return ret;
  204. }
  205. static int arizona_apply_hardware_patch(struct arizona* arizona)
  206. {
  207. unsigned int fll, sysclk;
  208. int ret, err;
  209. regcache_cache_bypass(arizona->regmap, true);
  210. /* Cache existing FLL and SYSCLK settings */
  211. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll);
  212. if (ret != 0) {
  213. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  214. ret);
  215. return ret;
  216. }
  217. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk);
  218. if (ret != 0) {
  219. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  220. ret);
  221. return ret;
  222. }
  223. /* Start up SYSCLK using the FLL in free running mode */
  224. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  225. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  226. if (ret != 0) {
  227. dev_err(arizona->dev,
  228. "Failed to start FLL in freerunning mode: %d\n",
  229. ret);
  230. return ret;
  231. }
  232. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  233. ARIZONA_FLL1_CLOCK_OK_STS,
  234. ARIZONA_FLL1_CLOCK_OK_STS);
  235. if (ret != 0) {
  236. ret = -ETIMEDOUT;
  237. goto err_fll;
  238. }
  239. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  240. if (ret != 0) {
  241. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  242. goto err_fll;
  243. }
  244. /* Start the write sequencer and wait for it to finish */
  245. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  246. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  247. if (ret != 0) {
  248. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  249. ret);
  250. goto err_sysclk;
  251. }
  252. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  253. ARIZONA_WSEQ_BUSY, 0);
  254. if (ret != 0) {
  255. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  256. ARIZONA_WSEQ_ABORT);
  257. ret = -ETIMEDOUT;
  258. }
  259. err_sysclk:
  260. err = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk);
  261. if (err != 0) {
  262. dev_err(arizona->dev,
  263. "Failed to re-apply old SYSCLK settings: %d\n",
  264. err);
  265. }
  266. err_fll:
  267. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll);
  268. if (err != 0) {
  269. dev_err(arizona->dev,
  270. "Failed to re-apply old FLL settings: %d\n",
  271. err);
  272. }
  273. regcache_cache_bypass(arizona->regmap, false);
  274. if (ret != 0)
  275. return ret;
  276. else
  277. return err;
  278. }
  279. #ifdef CONFIG_PM_RUNTIME
  280. static int arizona_runtime_resume(struct device *dev)
  281. {
  282. struct arizona *arizona = dev_get_drvdata(dev);
  283. int ret;
  284. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  285. ret = regulator_enable(arizona->dcvdd);
  286. if (ret != 0) {
  287. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  288. return ret;
  289. }
  290. regcache_cache_only(arizona->regmap, false);
  291. switch (arizona->type) {
  292. case WM5102:
  293. ret = wm5102_patch(arizona);
  294. if (ret != 0) {
  295. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  296. ret);
  297. goto err;
  298. }
  299. ret = arizona_apply_hardware_patch(arizona);
  300. if (ret != 0) {
  301. dev_err(arizona->dev,
  302. "Failed to apply hardware patch: %d\n",
  303. ret);
  304. goto err;
  305. }
  306. break;
  307. default:
  308. ret = arizona_wait_for_boot(arizona);
  309. if (ret != 0) {
  310. goto err;
  311. }
  312. break;
  313. }
  314. switch (arizona->type) {
  315. case WM5102:
  316. ret = wm5102_patch(arizona);
  317. if (ret != 0) {
  318. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  319. ret);
  320. goto err;
  321. }
  322. default:
  323. break;
  324. }
  325. ret = regcache_sync(arizona->regmap);
  326. if (ret != 0) {
  327. dev_err(arizona->dev, "Failed to restore register cache\n");
  328. goto err;
  329. }
  330. return 0;
  331. err:
  332. regcache_cache_only(arizona->regmap, true);
  333. regulator_disable(arizona->dcvdd);
  334. return ret;
  335. }
  336. static int arizona_runtime_suspend(struct device *dev)
  337. {
  338. struct arizona *arizona = dev_get_drvdata(dev);
  339. dev_dbg(arizona->dev, "Entering AoD mode\n");
  340. regulator_disable(arizona->dcvdd);
  341. regcache_cache_only(arizona->regmap, true);
  342. regcache_mark_dirty(arizona->regmap);
  343. return 0;
  344. }
  345. #endif
  346. #ifdef CONFIG_PM_SLEEP
  347. static int arizona_suspend(struct device *dev)
  348. {
  349. struct arizona *arizona = dev_get_drvdata(dev);
  350. dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
  351. disable_irq(arizona->irq);
  352. return 0;
  353. }
  354. static int arizona_suspend_late(struct device *dev)
  355. {
  356. struct arizona *arizona = dev_get_drvdata(dev);
  357. dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
  358. enable_irq(arizona->irq);
  359. return 0;
  360. }
  361. static int arizona_resume_noirq(struct device *dev)
  362. {
  363. struct arizona *arizona = dev_get_drvdata(dev);
  364. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  365. disable_irq(arizona->irq);
  366. return 0;
  367. }
  368. static int arizona_resume(struct device *dev)
  369. {
  370. struct arizona *arizona = dev_get_drvdata(dev);
  371. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  372. enable_irq(arizona->irq);
  373. return 0;
  374. }
  375. #endif
  376. const struct dev_pm_ops arizona_pm_ops = {
  377. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  378. arizona_runtime_resume,
  379. NULL)
  380. SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
  381. #ifdef CONFIG_PM_SLEEP
  382. .suspend_late = arizona_suspend_late,
  383. .resume_noirq = arizona_resume_noirq,
  384. #endif
  385. };
  386. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  387. #ifdef CONFIG_OF
  388. int arizona_of_get_type(struct device *dev)
  389. {
  390. const struct of_device_id *id = of_match_device(arizona_of_match, dev);
  391. if (id)
  392. return (int)id->data;
  393. else
  394. return 0;
  395. }
  396. EXPORT_SYMBOL_GPL(arizona_of_get_type);
  397. static int arizona_of_get_core_pdata(struct arizona *arizona)
  398. {
  399. int ret, i;
  400. arizona->pdata.reset = of_get_named_gpio(arizona->dev->of_node,
  401. "wlf,reset", 0);
  402. if (arizona->pdata.reset < 0)
  403. arizona->pdata.reset = 0;
  404. arizona->pdata.ldoena = of_get_named_gpio(arizona->dev->of_node,
  405. "wlf,ldoena", 0);
  406. if (arizona->pdata.ldoena < 0)
  407. arizona->pdata.ldoena = 0;
  408. ret = of_property_read_u32_array(arizona->dev->of_node,
  409. "wlf,gpio-defaults",
  410. arizona->pdata.gpio_defaults,
  411. ARRAY_SIZE(arizona->pdata.gpio_defaults));
  412. if (ret >= 0) {
  413. /*
  414. * All values are literal except out of range values
  415. * which are chip default, translate into platform
  416. * data which uses 0 as chip default and out of range
  417. * as zero.
  418. */
  419. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  420. if (arizona->pdata.gpio_defaults[i] > 0xffff)
  421. arizona->pdata.gpio_defaults[i] = 0;
  422. if (arizona->pdata.gpio_defaults[i] == 0)
  423. arizona->pdata.gpio_defaults[i] = 0x10000;
  424. }
  425. } else {
  426. dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
  427. ret);
  428. }
  429. return 0;
  430. }
  431. const struct of_device_id arizona_of_match[] = {
  432. { .compatible = "wlf,wm5102", .data = (void *)WM5102 },
  433. { .compatible = "wlf,wm5110", .data = (void *)WM5110 },
  434. {},
  435. };
  436. EXPORT_SYMBOL_GPL(arizona_of_match);
  437. #else
  438. static inline int arizona_of_get_core_pdata(struct arizona *arizona)
  439. {
  440. return 0;
  441. }
  442. #endif
  443. static struct mfd_cell early_devs[] = {
  444. { .name = "arizona-ldo1" },
  445. };
  446. static struct mfd_cell wm5102_devs[] = {
  447. { .name = "arizona-micsupp" },
  448. { .name = "arizona-extcon" },
  449. { .name = "arizona-gpio" },
  450. { .name = "arizona-haptics" },
  451. { .name = "arizona-pwm" },
  452. { .name = "wm5102-codec" },
  453. };
  454. static struct mfd_cell wm5110_devs[] = {
  455. { .name = "arizona-micsupp" },
  456. { .name = "arizona-extcon" },
  457. { .name = "arizona-gpio" },
  458. { .name = "arizona-haptics" },
  459. { .name = "arizona-pwm" },
  460. { .name = "wm5110-codec" },
  461. };
  462. int arizona_dev_init(struct arizona *arizona)
  463. {
  464. struct device *dev = arizona->dev;
  465. const char *type_name;
  466. unsigned int reg, val;
  467. int (*apply_patch)(struct arizona *) = NULL;
  468. int ret, i;
  469. dev_set_drvdata(arizona->dev, arizona);
  470. mutex_init(&arizona->clk_lock);
  471. arizona_of_get_core_pdata(arizona);
  472. if (dev_get_platdata(arizona->dev))
  473. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  474. sizeof(arizona->pdata));
  475. regcache_cache_only(arizona->regmap, true);
  476. switch (arizona->type) {
  477. case WM5102:
  478. case WM5110:
  479. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  480. arizona->core_supplies[i].supply
  481. = wm5102_core_supplies[i];
  482. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  483. break;
  484. default:
  485. dev_err(arizona->dev, "Unknown device type %d\n",
  486. arizona->type);
  487. return -EINVAL;
  488. }
  489. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  490. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  491. if (ret != 0) {
  492. dev_err(dev, "Failed to add early children: %d\n", ret);
  493. return ret;
  494. }
  495. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  496. arizona->core_supplies);
  497. if (ret != 0) {
  498. dev_err(dev, "Failed to request core supplies: %d\n",
  499. ret);
  500. goto err_early;
  501. }
  502. arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
  503. if (IS_ERR(arizona->dcvdd)) {
  504. ret = PTR_ERR(arizona->dcvdd);
  505. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  506. goto err_early;
  507. }
  508. if (arizona->pdata.reset) {
  509. /* Start out with /RESET low to put the chip into reset */
  510. ret = gpio_request_one(arizona->pdata.reset,
  511. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  512. "arizona /RESET");
  513. if (ret != 0) {
  514. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  515. goto err_early;
  516. }
  517. }
  518. ret = regulator_bulk_enable(arizona->num_core_supplies,
  519. arizona->core_supplies);
  520. if (ret != 0) {
  521. dev_err(dev, "Failed to enable core supplies: %d\n",
  522. ret);
  523. goto err_early;
  524. }
  525. ret = regulator_enable(arizona->dcvdd);
  526. if (ret != 0) {
  527. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  528. goto err_enable;
  529. }
  530. if (arizona->pdata.reset) {
  531. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  532. msleep(1);
  533. }
  534. regcache_cache_only(arizona->regmap, false);
  535. /* Verify that this is a chip we know about */
  536. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  537. if (ret != 0) {
  538. dev_err(dev, "Failed to read ID register: %d\n", ret);
  539. goto err_reset;
  540. }
  541. switch (reg) {
  542. case 0x5102:
  543. case 0x5110:
  544. break;
  545. default:
  546. dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
  547. goto err_reset;
  548. }
  549. /* If we have a /RESET GPIO we'll already be reset */
  550. if (!arizona->pdata.reset) {
  551. regcache_mark_dirty(arizona->regmap);
  552. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  553. if (ret != 0) {
  554. dev_err(dev, "Failed to reset device: %d\n", ret);
  555. goto err_reset;
  556. }
  557. msleep(1);
  558. ret = regcache_sync(arizona->regmap);
  559. if (ret != 0) {
  560. dev_err(dev, "Failed to sync device: %d\n", ret);
  561. goto err_reset;
  562. }
  563. }
  564. /* Ensure device startup is complete */
  565. switch (arizona->type) {
  566. case WM5102:
  567. ret = regmap_read(arizona->regmap, 0x19, &val);
  568. if (ret != 0)
  569. dev_err(dev,
  570. "Failed to check write sequencer state: %d\n",
  571. ret);
  572. else if (val & 0x01)
  573. break;
  574. /* Fall through */
  575. default:
  576. ret = arizona_wait_for_boot(arizona);
  577. if (ret != 0) {
  578. dev_err(arizona->dev,
  579. "Device failed initial boot: %d\n", ret);
  580. goto err_reset;
  581. }
  582. break;
  583. }
  584. /* Read the device ID information & do device specific stuff */
  585. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  586. if (ret != 0) {
  587. dev_err(dev, "Failed to read ID register: %d\n", ret);
  588. goto err_reset;
  589. }
  590. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  591. &arizona->rev);
  592. if (ret != 0) {
  593. dev_err(dev, "Failed to read revision register: %d\n", ret);
  594. goto err_reset;
  595. }
  596. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  597. switch (reg) {
  598. #ifdef CONFIG_MFD_WM5102
  599. case 0x5102:
  600. type_name = "WM5102";
  601. if (arizona->type != WM5102) {
  602. dev_err(arizona->dev, "WM5102 registered as %d\n",
  603. arizona->type);
  604. arizona->type = WM5102;
  605. }
  606. apply_patch = wm5102_patch;
  607. arizona->rev &= 0x7;
  608. break;
  609. #endif
  610. #ifdef CONFIG_MFD_WM5110
  611. case 0x5110:
  612. type_name = "WM5110";
  613. if (arizona->type != WM5110) {
  614. dev_err(arizona->dev, "WM5110 registered as %d\n",
  615. arizona->type);
  616. arizona->type = WM5110;
  617. }
  618. apply_patch = wm5110_patch;
  619. break;
  620. #endif
  621. default:
  622. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  623. goto err_reset;
  624. }
  625. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  626. if (apply_patch) {
  627. ret = apply_patch(arizona);
  628. if (ret != 0) {
  629. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  630. ret);
  631. goto err_reset;
  632. }
  633. switch (arizona->type) {
  634. case WM5102:
  635. ret = arizona_apply_hardware_patch(arizona);
  636. if (ret != 0) {
  637. dev_err(arizona->dev,
  638. "Failed to apply hardware patch: %d\n",
  639. ret);
  640. goto err_reset;
  641. }
  642. break;
  643. default:
  644. break;
  645. }
  646. }
  647. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  648. if (!arizona->pdata.gpio_defaults[i])
  649. continue;
  650. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  651. arizona->pdata.gpio_defaults[i]);
  652. }
  653. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  654. pm_runtime_use_autosuspend(arizona->dev);
  655. pm_runtime_enable(arizona->dev);
  656. /* Chip default */
  657. if (!arizona->pdata.clk32k_src)
  658. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  659. switch (arizona->pdata.clk32k_src) {
  660. case ARIZONA_32KZ_MCLK1:
  661. case ARIZONA_32KZ_MCLK2:
  662. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  663. ARIZONA_CLK_32K_SRC_MASK,
  664. arizona->pdata.clk32k_src - 1);
  665. arizona_clk32k_enable(arizona);
  666. break;
  667. case ARIZONA_32KZ_NONE:
  668. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  669. ARIZONA_CLK_32K_SRC_MASK, 2);
  670. break;
  671. default:
  672. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  673. arizona->pdata.clk32k_src);
  674. ret = -EINVAL;
  675. goto err_reset;
  676. }
  677. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  678. if (!arizona->pdata.micbias[i].mV &&
  679. !arizona->pdata.micbias[i].bypass)
  680. continue;
  681. /* Apply default for bypass mode */
  682. if (!arizona->pdata.micbias[i].mV)
  683. arizona->pdata.micbias[i].mV = 2800;
  684. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  685. val <<= ARIZONA_MICB1_LVL_SHIFT;
  686. if (arizona->pdata.micbias[i].ext_cap)
  687. val |= ARIZONA_MICB1_EXT_CAP;
  688. if (arizona->pdata.micbias[i].discharge)
  689. val |= ARIZONA_MICB1_DISCH;
  690. if (arizona->pdata.micbias[i].fast_start)
  691. val |= ARIZONA_MICB1_RATE;
  692. if (arizona->pdata.micbias[i].bypass)
  693. val |= ARIZONA_MICB1_BYPASS;
  694. regmap_update_bits(arizona->regmap,
  695. ARIZONA_MIC_BIAS_CTRL_1 + i,
  696. ARIZONA_MICB1_LVL_MASK |
  697. ARIZONA_MICB1_DISCH |
  698. ARIZONA_MICB1_BYPASS |
  699. ARIZONA_MICB1_RATE, val);
  700. }
  701. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  702. /* Default for both is 0 so noop with defaults */
  703. val = arizona->pdata.dmic_ref[i]
  704. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  705. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  706. regmap_update_bits(arizona->regmap,
  707. ARIZONA_IN1L_CONTROL + (i * 8),
  708. ARIZONA_IN1_DMIC_SUP_MASK |
  709. ARIZONA_IN1_MODE_MASK, val);
  710. }
  711. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  712. /* Default is 0 so noop with defaults */
  713. if (arizona->pdata.out_mono[i])
  714. val = ARIZONA_OUT1_MONO;
  715. else
  716. val = 0;
  717. regmap_update_bits(arizona->regmap,
  718. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  719. ARIZONA_OUT1_MONO, val);
  720. }
  721. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  722. if (arizona->pdata.spk_mute[i])
  723. regmap_update_bits(arizona->regmap,
  724. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  725. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  726. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  727. arizona->pdata.spk_mute[i]);
  728. if (arizona->pdata.spk_fmt[i])
  729. regmap_update_bits(arizona->regmap,
  730. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  731. ARIZONA_SPK1_FMT_MASK,
  732. arizona->pdata.spk_fmt[i]);
  733. }
  734. /* Set up for interrupts */
  735. ret = arizona_irq_init(arizona);
  736. if (ret != 0)
  737. goto err_reset;
  738. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  739. arizona_clkgen_err, arizona);
  740. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  741. arizona_overclocked, arizona);
  742. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  743. arizona_underclocked, arizona);
  744. switch (arizona->type) {
  745. case WM5102:
  746. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  747. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  748. break;
  749. case WM5110:
  750. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  751. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  752. break;
  753. }
  754. if (ret != 0) {
  755. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  756. goto err_irq;
  757. }
  758. #ifdef CONFIG_PM_RUNTIME
  759. regulator_disable(arizona->dcvdd);
  760. #endif
  761. return 0;
  762. err_irq:
  763. arizona_irq_exit(arizona);
  764. err_reset:
  765. if (arizona->pdata.reset) {
  766. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  767. gpio_free(arizona->pdata.reset);
  768. }
  769. regulator_disable(arizona->dcvdd);
  770. err_enable:
  771. regulator_bulk_disable(arizona->num_core_supplies,
  772. arizona->core_supplies);
  773. err_early:
  774. mfd_remove_devices(dev);
  775. return ret;
  776. }
  777. EXPORT_SYMBOL_GPL(arizona_dev_init);
  778. int arizona_dev_exit(struct arizona *arizona)
  779. {
  780. mfd_remove_devices(arizona->dev);
  781. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  782. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  783. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  784. pm_runtime_disable(arizona->dev);
  785. arizona_irq_exit(arizona);
  786. if (arizona->pdata.reset)
  787. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  788. regulator_disable(arizona->dcvdd);
  789. regulator_bulk_disable(ARRAY_SIZE(arizona->core_supplies),
  790. arizona->core_supplies);
  791. return 0;
  792. }
  793. EXPORT_SYMBOL_GPL(arizona_dev_exit);