r8a7791.dtsi 1.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859
  1. /*
  2. * Device Tree Source for the r8a7791 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Electronics Corporation
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. / {
  12. compatible = "renesas,r8a7791";
  13. interrupt-parent = <&gic>;
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu0: cpu@0 {
  20. device_type = "cpu";
  21. compatible = "arm,cortex-a15";
  22. reg = <0>;
  23. clock-frequency = <1300000000>;
  24. };
  25. };
  26. gic: interrupt-controller@f1001000 {
  27. compatible = "arm,cortex-a15-gic";
  28. #interrupt-cells = <3>;
  29. #address-cells = <0>;
  30. interrupt-controller;
  31. reg = <0 0xf1001000 0 0x1000>,
  32. <0 0xf1002000 0 0x1000>,
  33. <0 0xf1004000 0 0x2000>,
  34. <0 0xf1006000 0 0x2000>;
  35. interrupts = <1 9 0xf04>;
  36. };
  37. irqc0: interrupt-controller@e61c0000 {
  38. compatible = "renesas,irqc";
  39. #interrupt-cells = <2>;
  40. interrupt-controller;
  41. reg = <0 0xe61c0000 0 0x200>;
  42. interrupt-parent = <&gic>;
  43. interrupts = <0 0 4>,
  44. <0 1 4>,
  45. <0 2 4>,
  46. <0 3 4>,
  47. <0 12 4>,
  48. <0 13 4>,
  49. <0 14 4>,
  50. <0 15 4>,
  51. <0 16 4>,
  52. <0 17 4>;
  53. };
  54. };