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plat-mxc
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irqs.h

irqs.h 2.0 KB
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  1. /*
    2. 

  2.  *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
    3. 

  3.  */
    4. 

  4. 

  5. /*
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __ASM_ARCH_MXC_IRQS_H__
    12. 

  12. #define __ASM_ARCH_MXC_IRQS_H__
    13. 

  13. 

  14. /*
    15. 

  15.  * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
    16. 

  16.  */
    17. 

  17. #ifdef CONFIG_MXC_TZIC
    18. 

  18. #define MXC_INTERNAL_IRQS	128
    19. 

  19. #else
    20. 

  20. #define MXC_INTERNAL_IRQS	64
    21. 

  21. #endif
    22. 

  22. 

  23. #define MXC_GPIO_IRQ_START	MXC_INTERNAL_IRQS
    24. 

  24. 

  25. /* these are ordered by size to support multi-SoC kernels */
    26. 

  26. #if defined CONFIG_SOC_IMX53
    27. 

  27. #define MXC_GPIO_IRQS		(32 * 7)
    28. 

  28. #elif defined CONFIG_ARCH_MX2
    29. 

  29. #define MXC_GPIO_IRQS		(32 * 6)
    30. 

  30. #elif defined CONFIG_SOC_IMX50
    31. 

  31. #define MXC_GPIO_IRQS		(32 * 6)
    32. 

  32. #elif defined CONFIG_ARCH_MX1
    33. 

  33. #define MXC_GPIO_IRQS		(32 * 4)
    34. 

  34. #elif defined CONFIG_ARCH_MX25
    35. 

  35. #define MXC_GPIO_IRQS		(32 * 4)
    36. 

  36. #elif defined CONFIG_SOC_IMX51
    37. 

  37. #define MXC_GPIO_IRQS		(32 * 4)
    38. 

  38. #elif defined CONFIG_ARCH_MX3
    39. 

  39. #define MXC_GPIO_IRQS		(32 * 3)
    40. 

  40. #endif
    41. 

  41. 

  42. /*
    43. 

  43.  * The next 16 interrupts are for board specific purposes.  Since
    44. 

  44.  * the kernel can only run on one machine at a time, we can re-use
    45. 

  45.  * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
    46. 

  46.  * within sensible limits.
    47. 

  47.  */
    48. 

  48. #define MXC_BOARD_IRQ_START	(MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
    49. 

  49. 

  50. #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
    51. 

  51. #define MXC_BOARD_IRQS  80
    52. 

  52. #else
    53. 

  53. #define MXC_BOARD_IRQS	16
    54. 

  54. #endif
    55. 

  55. 

  56. #define MXC_IPU_IRQ_START	(MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
    57. 

  57. 

  58. #ifdef CONFIG_MX3_IPU_IRQS
    59. 

  59. #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
    60. 

  60. #else
    61. 

  61. #define MX3_IPU_IRQS 0
    62. 

  62. #endif
    63. 

  63. /* REVISIT: Add IPU irqs on IMX51 */
    64. 

  64. 

  65. #define NR_IRQS			(MXC_IPU_IRQ_START + MX3_IPU_IRQS)
    66. 

  66. 

  67. extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
    68. 

  68. 

  69. /* all normal IRQs can be FIQs */
    70. 

  70. #define FIQ_START	0
    71. 

  71. /* switch between IRQ and FIQ */
    72. 

  72. extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
    73. 

  73. 

  74. #endif /* __ASM_ARCH_MXC_IRQS_H__ */
    75.