events.c 37 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636
  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. static LIST_HEAD(xen_irq_list_head);
  55. /* IRQ <-> VIRQ mapping. */
  56. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  57. /* IRQ <-> IPI mapping */
  58. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  59. /* Interrupt types. */
  60. enum xen_irq_type {
  61. IRQT_UNBOUND = 0,
  62. IRQT_PIRQ,
  63. IRQT_VIRQ,
  64. IRQT_IPI,
  65. IRQT_EVTCHN
  66. };
  67. /*
  68. * Packed IRQ information:
  69. * type - enum xen_irq_type
  70. * event channel - irq->event channel mapping
  71. * cpu - cpu this event channel is bound to
  72. * index - type-specific information:
  73. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  74. * guest, or GSI (real passthrough IRQ) of the device.
  75. * VIRQ - virq number
  76. * IPI - IPI vector
  77. * EVTCHN -
  78. */
  79. struct irq_info
  80. {
  81. struct list_head list;
  82. enum xen_irq_type type; /* type */
  83. unsigned irq;
  84. unsigned short evtchn; /* event channel */
  85. unsigned short cpu; /* cpu bound */
  86. union {
  87. unsigned short virq;
  88. enum ipi_vector ipi;
  89. struct {
  90. unsigned short pirq;
  91. unsigned short gsi;
  92. unsigned char vector;
  93. unsigned char flags;
  94. } pirq;
  95. } u;
  96. };
  97. #define PIRQ_NEEDS_EOI (1 << 0)
  98. #define PIRQ_SHAREABLE (1 << 1)
  99. static int *evtchn_to_irq;
  100. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  101. cpu_evtchn_mask);
  102. /* Xen will never allocate port zero for any purpose. */
  103. #define VALID_EVTCHN(chn) ((chn) != 0)
  104. static struct irq_chip xen_dynamic_chip;
  105. static struct irq_chip xen_percpu_chip;
  106. static struct irq_chip xen_pirq_chip;
  107. /* Get info for IRQ */
  108. static struct irq_info *info_for_irq(unsigned irq)
  109. {
  110. return irq_get_handler_data(irq);
  111. }
  112. /* Constructors for packed IRQ information. */
  113. static void xen_irq_info_common_init(struct irq_info *info,
  114. unsigned irq,
  115. enum xen_irq_type type,
  116. unsigned short evtchn,
  117. unsigned short cpu)
  118. {
  119. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  120. info->type = type;
  121. info->irq = irq;
  122. info->evtchn = evtchn;
  123. info->cpu = cpu;
  124. evtchn_to_irq[evtchn] = irq;
  125. }
  126. static void xen_irq_info_evtchn_init(unsigned irq,
  127. unsigned short evtchn)
  128. {
  129. struct irq_info *info = info_for_irq(irq);
  130. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  131. }
  132. static void xen_irq_info_ipi_init(unsigned cpu,
  133. unsigned irq,
  134. unsigned short evtchn,
  135. enum ipi_vector ipi)
  136. {
  137. struct irq_info *info = info_for_irq(irq);
  138. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  139. info->u.ipi = ipi;
  140. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  141. }
  142. static void xen_irq_info_virq_init(unsigned cpu,
  143. unsigned irq,
  144. unsigned short evtchn,
  145. unsigned short virq)
  146. {
  147. struct irq_info *info = info_for_irq(irq);
  148. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  149. info->u.virq = virq;
  150. per_cpu(virq_to_irq, cpu)[virq] = irq;
  151. }
  152. static void xen_irq_info_pirq_init(unsigned irq,
  153. unsigned short evtchn,
  154. unsigned short pirq,
  155. unsigned short gsi,
  156. unsigned short vector,
  157. unsigned char flags)
  158. {
  159. struct irq_info *info = info_for_irq(irq);
  160. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  161. info->u.pirq.pirq = pirq;
  162. info->u.pirq.gsi = gsi;
  163. info->u.pirq.vector = vector;
  164. info->u.pirq.flags = flags;
  165. }
  166. /*
  167. * Accessors for packed IRQ information.
  168. */
  169. static unsigned int evtchn_from_irq(unsigned irq)
  170. {
  171. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  172. return 0;
  173. return info_for_irq(irq)->evtchn;
  174. }
  175. unsigned irq_from_evtchn(unsigned int evtchn)
  176. {
  177. return evtchn_to_irq[evtchn];
  178. }
  179. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  180. static enum ipi_vector ipi_from_irq(unsigned irq)
  181. {
  182. struct irq_info *info = info_for_irq(irq);
  183. BUG_ON(info == NULL);
  184. BUG_ON(info->type != IRQT_IPI);
  185. return info->u.ipi;
  186. }
  187. static unsigned virq_from_irq(unsigned irq)
  188. {
  189. struct irq_info *info = info_for_irq(irq);
  190. BUG_ON(info == NULL);
  191. BUG_ON(info->type != IRQT_VIRQ);
  192. return info->u.virq;
  193. }
  194. static unsigned pirq_from_irq(unsigned irq)
  195. {
  196. struct irq_info *info = info_for_irq(irq);
  197. BUG_ON(info == NULL);
  198. BUG_ON(info->type != IRQT_PIRQ);
  199. return info->u.pirq.pirq;
  200. }
  201. static enum xen_irq_type type_from_irq(unsigned irq)
  202. {
  203. return info_for_irq(irq)->type;
  204. }
  205. static unsigned cpu_from_irq(unsigned irq)
  206. {
  207. return info_for_irq(irq)->cpu;
  208. }
  209. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  210. {
  211. int irq = evtchn_to_irq[evtchn];
  212. unsigned ret = 0;
  213. if (irq != -1)
  214. ret = cpu_from_irq(irq);
  215. return ret;
  216. }
  217. static bool pirq_needs_eoi(unsigned irq)
  218. {
  219. struct irq_info *info = info_for_irq(irq);
  220. BUG_ON(info->type != IRQT_PIRQ);
  221. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  222. }
  223. static inline unsigned long active_evtchns(unsigned int cpu,
  224. struct shared_info *sh,
  225. unsigned int idx)
  226. {
  227. return (sh->evtchn_pending[idx] &
  228. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  229. ~sh->evtchn_mask[idx]);
  230. }
  231. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  232. {
  233. int irq = evtchn_to_irq[chn];
  234. BUG_ON(irq == -1);
  235. #ifdef CONFIG_SMP
  236. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  237. #endif
  238. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  239. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  240. info_for_irq(irq)->cpu = cpu;
  241. }
  242. static void init_evtchn_cpu_bindings(void)
  243. {
  244. int i;
  245. #ifdef CONFIG_SMP
  246. struct irq_info *info;
  247. /* By default all event channels notify CPU#0. */
  248. list_for_each_entry(info, &xen_irq_list_head, list) {
  249. struct irq_desc *desc = irq_to_desc(info->irq);
  250. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  251. }
  252. #endif
  253. for_each_possible_cpu(i)
  254. memset(per_cpu(cpu_evtchn_mask, i),
  255. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  256. }
  257. static inline void clear_evtchn(int port)
  258. {
  259. struct shared_info *s = HYPERVISOR_shared_info;
  260. sync_clear_bit(port, &s->evtchn_pending[0]);
  261. }
  262. static inline void set_evtchn(int port)
  263. {
  264. struct shared_info *s = HYPERVISOR_shared_info;
  265. sync_set_bit(port, &s->evtchn_pending[0]);
  266. }
  267. static inline int test_evtchn(int port)
  268. {
  269. struct shared_info *s = HYPERVISOR_shared_info;
  270. return sync_test_bit(port, &s->evtchn_pending[0]);
  271. }
  272. /**
  273. * notify_remote_via_irq - send event to remote end of event channel via irq
  274. * @irq: irq of event channel to send event to
  275. *
  276. * Unlike notify_remote_via_evtchn(), this is safe to use across
  277. * save/restore. Notifications on a broken connection are silently
  278. * dropped.
  279. */
  280. void notify_remote_via_irq(int irq)
  281. {
  282. int evtchn = evtchn_from_irq(irq);
  283. if (VALID_EVTCHN(evtchn))
  284. notify_remote_via_evtchn(evtchn);
  285. }
  286. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  287. static void mask_evtchn(int port)
  288. {
  289. struct shared_info *s = HYPERVISOR_shared_info;
  290. sync_set_bit(port, &s->evtchn_mask[0]);
  291. }
  292. static void unmask_evtchn(int port)
  293. {
  294. struct shared_info *s = HYPERVISOR_shared_info;
  295. unsigned int cpu = get_cpu();
  296. BUG_ON(!irqs_disabled());
  297. /* Slow path (hypercall) if this is a non-local port. */
  298. if (unlikely(cpu != cpu_from_evtchn(port))) {
  299. struct evtchn_unmask unmask = { .port = port };
  300. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  301. } else {
  302. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  303. sync_clear_bit(port, &s->evtchn_mask[0]);
  304. /*
  305. * The following is basically the equivalent of
  306. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  307. * the interrupt edge' if the channel is masked.
  308. */
  309. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  310. !sync_test_and_set_bit(port / BITS_PER_LONG,
  311. &vcpu_info->evtchn_pending_sel))
  312. vcpu_info->evtchn_upcall_pending = 1;
  313. }
  314. put_cpu();
  315. }
  316. static void xen_irq_init(unsigned irq)
  317. {
  318. struct irq_info *info;
  319. struct irq_desc *desc = irq_to_desc(irq);
  320. #ifdef CONFIG_SMP
  321. /* By default all event channels notify CPU#0. */
  322. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  323. #endif
  324. info = kzalloc(sizeof(*info), GFP_KERNEL);
  325. if (info == NULL)
  326. panic("Unable to allocate metadata for IRQ%d\n", irq);
  327. info->type = IRQT_UNBOUND;
  328. irq_set_handler_data(irq, info);
  329. list_add_tail(&info->list, &xen_irq_list_head);
  330. }
  331. static int __must_check xen_allocate_irq_dynamic(void)
  332. {
  333. int first = 0;
  334. int irq;
  335. #ifdef CONFIG_X86_IO_APIC
  336. /*
  337. * For an HVM guest or domain 0 which see "real" (emulated or
  338. * actual respectively) GSIs we allocate dynamic IRQs
  339. * e.g. those corresponding to event channels or MSIs
  340. * etc. from the range above those "real" GSIs to avoid
  341. * collisions.
  342. */
  343. if (xen_initial_domain() || xen_hvm_domain())
  344. first = get_nr_irqs_gsi();
  345. #endif
  346. irq = irq_alloc_desc_from(first, -1);
  347. xen_irq_init(irq);
  348. return irq;
  349. }
  350. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  351. {
  352. int irq;
  353. /*
  354. * A PV guest has no concept of a GSI (since it has no ACPI
  355. * nor access to/knowledge of the physical APICs). Therefore
  356. * all IRQs are dynamically allocated from the entire IRQ
  357. * space.
  358. */
  359. if (xen_pv_domain() && !xen_initial_domain())
  360. return xen_allocate_irq_dynamic();
  361. /* Legacy IRQ descriptors are already allocated by the arch. */
  362. if (gsi < NR_IRQS_LEGACY)
  363. irq = gsi;
  364. else
  365. irq = irq_alloc_desc_at(gsi, -1);
  366. xen_irq_init(irq);
  367. return irq;
  368. }
  369. static void xen_free_irq(unsigned irq)
  370. {
  371. struct irq_info *info = irq_get_handler_data(irq);
  372. list_del(&info->list);
  373. irq_set_handler_data(irq, NULL);
  374. kfree(info);
  375. /* Legacy IRQ descriptors are managed by the arch. */
  376. if (irq < NR_IRQS_LEGACY)
  377. return;
  378. irq_free_desc(irq);
  379. }
  380. static void pirq_unmask_notify(int irq)
  381. {
  382. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  383. if (unlikely(pirq_needs_eoi(irq))) {
  384. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  385. WARN_ON(rc);
  386. }
  387. }
  388. static void pirq_query_unmask(int irq)
  389. {
  390. struct physdev_irq_status_query irq_status;
  391. struct irq_info *info = info_for_irq(irq);
  392. BUG_ON(info->type != IRQT_PIRQ);
  393. irq_status.irq = pirq_from_irq(irq);
  394. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  395. irq_status.flags = 0;
  396. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  397. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  398. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  399. }
  400. static bool probing_irq(int irq)
  401. {
  402. struct irq_desc *desc = irq_to_desc(irq);
  403. return desc && desc->action == NULL;
  404. }
  405. static unsigned int __startup_pirq(unsigned int irq)
  406. {
  407. struct evtchn_bind_pirq bind_pirq;
  408. struct irq_info *info = info_for_irq(irq);
  409. int evtchn = evtchn_from_irq(irq);
  410. int rc;
  411. BUG_ON(info->type != IRQT_PIRQ);
  412. if (VALID_EVTCHN(evtchn))
  413. goto out;
  414. bind_pirq.pirq = pirq_from_irq(irq);
  415. /* NB. We are happy to share unless we are probing. */
  416. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  417. BIND_PIRQ__WILL_SHARE : 0;
  418. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  419. if (rc != 0) {
  420. if (!probing_irq(irq))
  421. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  422. irq);
  423. return 0;
  424. }
  425. evtchn = bind_pirq.port;
  426. pirq_query_unmask(irq);
  427. evtchn_to_irq[evtchn] = irq;
  428. bind_evtchn_to_cpu(evtchn, 0);
  429. info->evtchn = evtchn;
  430. out:
  431. unmask_evtchn(evtchn);
  432. pirq_unmask_notify(irq);
  433. return 0;
  434. }
  435. static unsigned int startup_pirq(struct irq_data *data)
  436. {
  437. return __startup_pirq(data->irq);
  438. }
  439. static void shutdown_pirq(struct irq_data *data)
  440. {
  441. struct evtchn_close close;
  442. unsigned int irq = data->irq;
  443. struct irq_info *info = info_for_irq(irq);
  444. int evtchn = evtchn_from_irq(irq);
  445. BUG_ON(info->type != IRQT_PIRQ);
  446. if (!VALID_EVTCHN(evtchn))
  447. return;
  448. mask_evtchn(evtchn);
  449. close.port = evtchn;
  450. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  451. BUG();
  452. bind_evtchn_to_cpu(evtchn, 0);
  453. evtchn_to_irq[evtchn] = -1;
  454. info->evtchn = 0;
  455. }
  456. static void enable_pirq(struct irq_data *data)
  457. {
  458. startup_pirq(data);
  459. }
  460. static void disable_pirq(struct irq_data *data)
  461. {
  462. }
  463. static void ack_pirq(struct irq_data *data)
  464. {
  465. int evtchn = evtchn_from_irq(data->irq);
  466. irq_move_irq(data);
  467. if (VALID_EVTCHN(evtchn)) {
  468. mask_evtchn(evtchn);
  469. clear_evtchn(evtchn);
  470. }
  471. }
  472. static int find_irq_by_gsi(unsigned gsi)
  473. {
  474. struct irq_info *info;
  475. list_for_each_entry(info, &xen_irq_list_head, list) {
  476. if (info->type != IRQT_PIRQ)
  477. continue;
  478. if (info->u.pirq.gsi == gsi)
  479. return info->irq;
  480. }
  481. return -1;
  482. }
  483. int xen_allocate_pirq_gsi(unsigned gsi)
  484. {
  485. return gsi;
  486. }
  487. /*
  488. * Do not make any assumptions regarding the relationship between the
  489. * IRQ number returned here and the Xen pirq argument.
  490. *
  491. * Note: We don't assign an event channel until the irq actually started
  492. * up. Return an existing irq if we've already got one for the gsi.
  493. */
  494. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  495. unsigned pirq, int shareable, char *name)
  496. {
  497. int irq = -1;
  498. struct physdev_irq irq_op;
  499. spin_lock(&irq_mapping_update_lock);
  500. irq = find_irq_by_gsi(gsi);
  501. if (irq != -1) {
  502. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  503. irq, gsi);
  504. goto out; /* XXX need refcount? */
  505. }
  506. irq = xen_allocate_irq_gsi(gsi);
  507. if (irq < 0)
  508. goto out;
  509. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
  510. name);
  511. irq_op.irq = irq;
  512. irq_op.vector = 0;
  513. /* Only the privileged domain can do this. For non-priv, the pcifront
  514. * driver provides a PCI bus that does the call to do exactly
  515. * this in the priv domain. */
  516. if (xen_initial_domain() &&
  517. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  518. xen_free_irq(irq);
  519. irq = -ENOSPC;
  520. goto out;
  521. }
  522. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector,
  523. shareable ? PIRQ_SHAREABLE : 0);
  524. out:
  525. spin_unlock(&irq_mapping_update_lock);
  526. return irq;
  527. }
  528. #ifdef CONFIG_PCI_MSI
  529. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  530. {
  531. int rc;
  532. struct physdev_get_free_pirq op_get_free_pirq;
  533. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  534. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  535. WARN_ONCE(rc == -ENOSYS,
  536. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  537. return rc ? -1 : op_get_free_pirq.pirq;
  538. }
  539. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  540. int pirq, int vector, const char *name)
  541. {
  542. int irq, ret;
  543. spin_lock(&irq_mapping_update_lock);
  544. irq = xen_allocate_irq_dynamic();
  545. if (irq == -1)
  546. goto out;
  547. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
  548. name);
  549. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0);
  550. ret = irq_set_msi_desc(irq, msidesc);
  551. if (ret < 0)
  552. goto error_irq;
  553. out:
  554. spin_unlock(&irq_mapping_update_lock);
  555. return irq;
  556. error_irq:
  557. spin_unlock(&irq_mapping_update_lock);
  558. xen_free_irq(irq);
  559. return -1;
  560. }
  561. #endif
  562. int xen_destroy_irq(int irq)
  563. {
  564. struct irq_desc *desc;
  565. struct physdev_unmap_pirq unmap_irq;
  566. struct irq_info *info = info_for_irq(irq);
  567. int rc = -ENOENT;
  568. spin_lock(&irq_mapping_update_lock);
  569. desc = irq_to_desc(irq);
  570. if (!desc)
  571. goto out;
  572. if (xen_initial_domain()) {
  573. unmap_irq.pirq = info->u.pirq.pirq;
  574. unmap_irq.domid = DOMID_SELF;
  575. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  576. if (rc) {
  577. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  578. goto out;
  579. }
  580. }
  581. xen_free_irq(irq);
  582. out:
  583. spin_unlock(&irq_mapping_update_lock);
  584. return rc;
  585. }
  586. int xen_irq_from_pirq(unsigned pirq)
  587. {
  588. int irq;
  589. struct irq_info *info;
  590. spin_lock(&irq_mapping_update_lock);
  591. list_for_each_entry(info, &xen_irq_list_head, list) {
  592. if (info == NULL || info->type != IRQT_PIRQ)
  593. continue;
  594. irq = info->irq;
  595. if (info->u.pirq.pirq == pirq)
  596. goto out;
  597. }
  598. irq = -1;
  599. out:
  600. spin_unlock(&irq_mapping_update_lock);
  601. return irq;
  602. }
  603. int bind_evtchn_to_irq(unsigned int evtchn)
  604. {
  605. int irq;
  606. spin_lock(&irq_mapping_update_lock);
  607. irq = evtchn_to_irq[evtchn];
  608. if (irq == -1) {
  609. irq = xen_allocate_irq_dynamic();
  610. if (irq == -1)
  611. goto out;
  612. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  613. handle_fasteoi_irq, "event");
  614. xen_irq_info_evtchn_init(irq, evtchn);
  615. }
  616. out:
  617. spin_unlock(&irq_mapping_update_lock);
  618. return irq;
  619. }
  620. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  621. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  622. {
  623. struct evtchn_bind_ipi bind_ipi;
  624. int evtchn, irq;
  625. spin_lock(&irq_mapping_update_lock);
  626. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  627. if (irq == -1) {
  628. irq = xen_allocate_irq_dynamic();
  629. if (irq < 0)
  630. goto out;
  631. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  632. handle_percpu_irq, "ipi");
  633. bind_ipi.vcpu = cpu;
  634. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  635. &bind_ipi) != 0)
  636. BUG();
  637. evtchn = bind_ipi.port;
  638. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  639. bind_evtchn_to_cpu(evtchn, cpu);
  640. }
  641. out:
  642. spin_unlock(&irq_mapping_update_lock);
  643. return irq;
  644. }
  645. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  646. unsigned int remote_port)
  647. {
  648. struct evtchn_bind_interdomain bind_interdomain;
  649. int err;
  650. bind_interdomain.remote_dom = remote_domain;
  651. bind_interdomain.remote_port = remote_port;
  652. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  653. &bind_interdomain);
  654. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  655. }
  656. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  657. {
  658. struct evtchn_bind_virq bind_virq;
  659. int evtchn, irq;
  660. spin_lock(&irq_mapping_update_lock);
  661. irq = per_cpu(virq_to_irq, cpu)[virq];
  662. if (irq == -1) {
  663. irq = xen_allocate_irq_dynamic();
  664. if (irq == -1)
  665. goto out;
  666. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  667. handle_percpu_irq, "virq");
  668. bind_virq.virq = virq;
  669. bind_virq.vcpu = cpu;
  670. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  671. &bind_virq) != 0)
  672. BUG();
  673. evtchn = bind_virq.port;
  674. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  675. bind_evtchn_to_cpu(evtchn, cpu);
  676. }
  677. out:
  678. spin_unlock(&irq_mapping_update_lock);
  679. return irq;
  680. }
  681. static void unbind_from_irq(unsigned int irq)
  682. {
  683. struct evtchn_close close;
  684. int evtchn = evtchn_from_irq(irq);
  685. spin_lock(&irq_mapping_update_lock);
  686. if (VALID_EVTCHN(evtchn)) {
  687. close.port = evtchn;
  688. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  689. BUG();
  690. switch (type_from_irq(irq)) {
  691. case IRQT_VIRQ:
  692. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  693. [virq_from_irq(irq)] = -1;
  694. break;
  695. case IRQT_IPI:
  696. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  697. [ipi_from_irq(irq)] = -1;
  698. break;
  699. default:
  700. break;
  701. }
  702. /* Closed ports are implicitly re-bound to VCPU0. */
  703. bind_evtchn_to_cpu(evtchn, 0);
  704. evtchn_to_irq[evtchn] = -1;
  705. }
  706. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  707. xen_free_irq(irq);
  708. spin_unlock(&irq_mapping_update_lock);
  709. }
  710. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  711. irq_handler_t handler,
  712. unsigned long irqflags,
  713. const char *devname, void *dev_id)
  714. {
  715. int irq, retval;
  716. irq = bind_evtchn_to_irq(evtchn);
  717. if (irq < 0)
  718. return irq;
  719. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  720. if (retval != 0) {
  721. unbind_from_irq(irq);
  722. return retval;
  723. }
  724. return irq;
  725. }
  726. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  727. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  728. unsigned int remote_port,
  729. irq_handler_t handler,
  730. unsigned long irqflags,
  731. const char *devname,
  732. void *dev_id)
  733. {
  734. int irq, retval;
  735. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  736. if (irq < 0)
  737. return irq;
  738. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  739. if (retval != 0) {
  740. unbind_from_irq(irq);
  741. return retval;
  742. }
  743. return irq;
  744. }
  745. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  746. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  747. irq_handler_t handler,
  748. unsigned long irqflags, const char *devname, void *dev_id)
  749. {
  750. int irq, retval;
  751. irq = bind_virq_to_irq(virq, cpu);
  752. if (irq < 0)
  753. return irq;
  754. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  755. if (retval != 0) {
  756. unbind_from_irq(irq);
  757. return retval;
  758. }
  759. return irq;
  760. }
  761. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  762. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  763. unsigned int cpu,
  764. irq_handler_t handler,
  765. unsigned long irqflags,
  766. const char *devname,
  767. void *dev_id)
  768. {
  769. int irq, retval;
  770. irq = bind_ipi_to_irq(ipi, cpu);
  771. if (irq < 0)
  772. return irq;
  773. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
  774. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  775. if (retval != 0) {
  776. unbind_from_irq(irq);
  777. return retval;
  778. }
  779. return irq;
  780. }
  781. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  782. {
  783. free_irq(irq, dev_id);
  784. unbind_from_irq(irq);
  785. }
  786. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  787. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  788. {
  789. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  790. BUG_ON(irq < 0);
  791. notify_remote_via_irq(irq);
  792. }
  793. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  794. {
  795. struct shared_info *sh = HYPERVISOR_shared_info;
  796. int cpu = smp_processor_id();
  797. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  798. int i;
  799. unsigned long flags;
  800. static DEFINE_SPINLOCK(debug_lock);
  801. struct vcpu_info *v;
  802. spin_lock_irqsave(&debug_lock, flags);
  803. printk("\nvcpu %d\n ", cpu);
  804. for_each_online_cpu(i) {
  805. int pending;
  806. v = per_cpu(xen_vcpu, i);
  807. pending = (get_irq_regs() && i == cpu)
  808. ? xen_irqs_disabled(get_irq_regs())
  809. : v->evtchn_upcall_mask;
  810. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  811. pending, v->evtchn_upcall_pending,
  812. (int)(sizeof(v->evtchn_pending_sel)*2),
  813. v->evtchn_pending_sel);
  814. }
  815. v = per_cpu(xen_vcpu, cpu);
  816. printk("\npending:\n ");
  817. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  818. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  819. sh->evtchn_pending[i],
  820. i % 8 == 0 ? "\n " : " ");
  821. printk("\nglobal mask:\n ");
  822. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  823. printk("%0*lx%s",
  824. (int)(sizeof(sh->evtchn_mask[0])*2),
  825. sh->evtchn_mask[i],
  826. i % 8 == 0 ? "\n " : " ");
  827. printk("\nglobally unmasked:\n ");
  828. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  829. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  830. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  831. i % 8 == 0 ? "\n " : " ");
  832. printk("\nlocal cpu%d mask:\n ", cpu);
  833. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  834. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  835. cpu_evtchn[i],
  836. i % 8 == 0 ? "\n " : " ");
  837. printk("\nlocally unmasked:\n ");
  838. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  839. unsigned long pending = sh->evtchn_pending[i]
  840. & ~sh->evtchn_mask[i]
  841. & cpu_evtchn[i];
  842. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  843. pending, i % 8 == 0 ? "\n " : " ");
  844. }
  845. printk("\npending list:\n");
  846. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  847. if (sync_test_bit(i, sh->evtchn_pending)) {
  848. int word_idx = i / BITS_PER_LONG;
  849. printk(" %d: event %d -> irq %d%s%s%s\n",
  850. cpu_from_evtchn(i), i,
  851. evtchn_to_irq[i],
  852. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  853. ? "" : " l2-clear",
  854. !sync_test_bit(i, sh->evtchn_mask)
  855. ? "" : " globally-masked",
  856. sync_test_bit(i, cpu_evtchn)
  857. ? "" : " locally-masked");
  858. }
  859. }
  860. spin_unlock_irqrestore(&debug_lock, flags);
  861. return IRQ_HANDLED;
  862. }
  863. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  864. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  865. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  866. /*
  867. * Mask out the i least significant bits of w
  868. */
  869. #define MASK_LSBS(w, i) (w & ((~0UL) << i))
  870. /*
  871. * Search the CPUs pending events bitmasks. For each one found, map
  872. * the event number to an irq, and feed it into do_IRQ() for
  873. * handling.
  874. *
  875. * Xen uses a two-level bitmap to speed searching. The first level is
  876. * a bitset of words which contain pending event bits. The second
  877. * level is a bitset of pending events themselves.
  878. */
  879. static void __xen_evtchn_do_upcall(void)
  880. {
  881. int start_word_idx, start_bit_idx;
  882. int word_idx, bit_idx;
  883. int i;
  884. int cpu = get_cpu();
  885. struct shared_info *s = HYPERVISOR_shared_info;
  886. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  887. unsigned count;
  888. do {
  889. unsigned long pending_words;
  890. vcpu_info->evtchn_upcall_pending = 0;
  891. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  892. goto out;
  893. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  894. /* Clear master flag /before/ clearing selector flag. */
  895. wmb();
  896. #endif
  897. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  898. start_word_idx = __this_cpu_read(current_word_idx);
  899. start_bit_idx = __this_cpu_read(current_bit_idx);
  900. word_idx = start_word_idx;
  901. for (i = 0; pending_words != 0; i++) {
  902. unsigned long pending_bits;
  903. unsigned long words;
  904. words = MASK_LSBS(pending_words, word_idx);
  905. /*
  906. * If we masked out all events, wrap to beginning.
  907. */
  908. if (words == 0) {
  909. word_idx = 0;
  910. bit_idx = 0;
  911. continue;
  912. }
  913. word_idx = __ffs(words);
  914. pending_bits = active_evtchns(cpu, s, word_idx);
  915. bit_idx = 0; /* usually scan entire word from start */
  916. if (word_idx == start_word_idx) {
  917. /* We scan the starting word in two parts */
  918. if (i == 0)
  919. /* 1st time: start in the middle */
  920. bit_idx = start_bit_idx;
  921. else
  922. /* 2nd time: mask bits done already */
  923. bit_idx &= (1UL << start_bit_idx) - 1;
  924. }
  925. do {
  926. unsigned long bits;
  927. int port, irq;
  928. struct irq_desc *desc;
  929. bits = MASK_LSBS(pending_bits, bit_idx);
  930. /* If we masked out all events, move on. */
  931. if (bits == 0)
  932. break;
  933. bit_idx = __ffs(bits);
  934. /* Process port. */
  935. port = (word_idx * BITS_PER_LONG) + bit_idx;
  936. irq = evtchn_to_irq[port];
  937. mask_evtchn(port);
  938. clear_evtchn(port);
  939. if (irq != -1) {
  940. desc = irq_to_desc(irq);
  941. if (desc)
  942. generic_handle_irq_desc(irq, desc);
  943. }
  944. bit_idx = (bit_idx + 1) % BITS_PER_LONG;
  945. /* Next caller starts at last processed + 1 */
  946. __this_cpu_write(current_word_idx,
  947. bit_idx ? word_idx :
  948. (word_idx+1) % BITS_PER_LONG);
  949. __this_cpu_write(current_bit_idx, bit_idx);
  950. } while (bit_idx != 0);
  951. /* Scan start_l1i twice; all others once. */
  952. if ((word_idx != start_word_idx) || (i != 0))
  953. pending_words &= ~(1UL << word_idx);
  954. word_idx = (word_idx + 1) % BITS_PER_LONG;
  955. }
  956. BUG_ON(!irqs_disabled());
  957. count = __this_cpu_read(xed_nesting_count);
  958. __this_cpu_write(xed_nesting_count, 0);
  959. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  960. out:
  961. put_cpu();
  962. }
  963. void xen_evtchn_do_upcall(struct pt_regs *regs)
  964. {
  965. struct pt_regs *old_regs = set_irq_regs(regs);
  966. exit_idle();
  967. irq_enter();
  968. __xen_evtchn_do_upcall();
  969. irq_exit();
  970. set_irq_regs(old_regs);
  971. }
  972. void xen_hvm_evtchn_do_upcall(void)
  973. {
  974. __xen_evtchn_do_upcall();
  975. }
  976. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  977. /* Rebind a new event channel to an existing irq. */
  978. void rebind_evtchn_irq(int evtchn, int irq)
  979. {
  980. struct irq_info *info = info_for_irq(irq);
  981. /* Make sure the irq is masked, since the new event channel
  982. will also be masked. */
  983. disable_irq(irq);
  984. spin_lock(&irq_mapping_update_lock);
  985. /* After resume the irq<->evtchn mappings are all cleared out */
  986. BUG_ON(evtchn_to_irq[evtchn] != -1);
  987. /* Expect irq to have been bound before,
  988. so there should be a proper type */
  989. BUG_ON(info->type == IRQT_UNBOUND);
  990. xen_irq_info_evtchn_init(irq, evtchn);
  991. spin_unlock(&irq_mapping_update_lock);
  992. /* new event channels are always bound to cpu 0 */
  993. irq_set_affinity(irq, cpumask_of(0));
  994. /* Unmask the event channel. */
  995. enable_irq(irq);
  996. }
  997. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  998. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  999. {
  1000. struct evtchn_bind_vcpu bind_vcpu;
  1001. int evtchn = evtchn_from_irq(irq);
  1002. if (!VALID_EVTCHN(evtchn))
  1003. return -1;
  1004. /*
  1005. * Events delivered via platform PCI interrupts are always
  1006. * routed to vcpu 0 and hence cannot be rebound.
  1007. */
  1008. if (xen_hvm_domain() && !xen_have_vector_callback)
  1009. return -1;
  1010. /* Send future instances of this interrupt to other vcpu. */
  1011. bind_vcpu.port = evtchn;
  1012. bind_vcpu.vcpu = tcpu;
  1013. /*
  1014. * If this fails, it usually just indicates that we're dealing with a
  1015. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1016. * it, but don't do the xenlinux-level rebind in that case.
  1017. */
  1018. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1019. bind_evtchn_to_cpu(evtchn, tcpu);
  1020. return 0;
  1021. }
  1022. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1023. bool force)
  1024. {
  1025. unsigned tcpu = cpumask_first(dest);
  1026. return rebind_irq_to_cpu(data->irq, tcpu);
  1027. }
  1028. int resend_irq_on_evtchn(unsigned int irq)
  1029. {
  1030. int masked, evtchn = evtchn_from_irq(irq);
  1031. struct shared_info *s = HYPERVISOR_shared_info;
  1032. if (!VALID_EVTCHN(evtchn))
  1033. return 1;
  1034. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1035. sync_set_bit(evtchn, s->evtchn_pending);
  1036. if (!masked)
  1037. unmask_evtchn(evtchn);
  1038. return 1;
  1039. }
  1040. static void enable_dynirq(struct irq_data *data)
  1041. {
  1042. int evtchn = evtchn_from_irq(data->irq);
  1043. if (VALID_EVTCHN(evtchn))
  1044. unmask_evtchn(evtchn);
  1045. }
  1046. static void disable_dynirq(struct irq_data *data)
  1047. {
  1048. int evtchn = evtchn_from_irq(data->irq);
  1049. if (VALID_EVTCHN(evtchn))
  1050. mask_evtchn(evtchn);
  1051. }
  1052. static void ack_dynirq(struct irq_data *data)
  1053. {
  1054. int evtchn = evtchn_from_irq(data->irq);
  1055. irq_move_masked_irq(data);
  1056. if (VALID_EVTCHN(evtchn))
  1057. unmask_evtchn(evtchn);
  1058. }
  1059. static int retrigger_dynirq(struct irq_data *data)
  1060. {
  1061. int evtchn = evtchn_from_irq(data->irq);
  1062. struct shared_info *sh = HYPERVISOR_shared_info;
  1063. int ret = 0;
  1064. if (VALID_EVTCHN(evtchn)) {
  1065. int masked;
  1066. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1067. sync_set_bit(evtchn, sh->evtchn_pending);
  1068. if (!masked)
  1069. unmask_evtchn(evtchn);
  1070. ret = 1;
  1071. }
  1072. return ret;
  1073. }
  1074. static void restore_pirqs(void)
  1075. {
  1076. int pirq, rc, irq, gsi;
  1077. struct physdev_map_pirq map_irq;
  1078. struct irq_info *info;
  1079. list_for_each_entry(info, &xen_irq_list_head, list) {
  1080. if (info->type != IRQT_PIRQ)
  1081. continue;
  1082. pirq = info->u.pirq.pirq;
  1083. gsi = info->u.pirq.gsi;
  1084. irq = info->irq;
  1085. /* save/restore of PT devices doesn't work, so at this point the
  1086. * only devices present are GSI based emulated devices */
  1087. if (!gsi)
  1088. continue;
  1089. map_irq.domid = DOMID_SELF;
  1090. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1091. map_irq.index = gsi;
  1092. map_irq.pirq = pirq;
  1093. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1094. if (rc) {
  1095. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1096. gsi, irq, pirq, rc);
  1097. xen_free_irq(irq);
  1098. continue;
  1099. }
  1100. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1101. __startup_pirq(irq);
  1102. }
  1103. }
  1104. static void restore_cpu_virqs(unsigned int cpu)
  1105. {
  1106. struct evtchn_bind_virq bind_virq;
  1107. int virq, irq, evtchn;
  1108. for (virq = 0; virq < NR_VIRQS; virq++) {
  1109. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1110. continue;
  1111. BUG_ON(virq_from_irq(irq) != virq);
  1112. /* Get a new binding from Xen. */
  1113. bind_virq.virq = virq;
  1114. bind_virq.vcpu = cpu;
  1115. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1116. &bind_virq) != 0)
  1117. BUG();
  1118. evtchn = bind_virq.port;
  1119. /* Record the new mapping. */
  1120. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1121. bind_evtchn_to_cpu(evtchn, cpu);
  1122. }
  1123. }
  1124. static void restore_cpu_ipis(unsigned int cpu)
  1125. {
  1126. struct evtchn_bind_ipi bind_ipi;
  1127. int ipi, irq, evtchn;
  1128. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1129. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1130. continue;
  1131. BUG_ON(ipi_from_irq(irq) != ipi);
  1132. /* Get a new binding from Xen. */
  1133. bind_ipi.vcpu = cpu;
  1134. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1135. &bind_ipi) != 0)
  1136. BUG();
  1137. evtchn = bind_ipi.port;
  1138. /* Record the new mapping. */
  1139. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1140. bind_evtchn_to_cpu(evtchn, cpu);
  1141. }
  1142. }
  1143. /* Clear an irq's pending state, in preparation for polling on it */
  1144. void xen_clear_irq_pending(int irq)
  1145. {
  1146. int evtchn = evtchn_from_irq(irq);
  1147. if (VALID_EVTCHN(evtchn))
  1148. clear_evtchn(evtchn);
  1149. }
  1150. EXPORT_SYMBOL(xen_clear_irq_pending);
  1151. void xen_set_irq_pending(int irq)
  1152. {
  1153. int evtchn = evtchn_from_irq(irq);
  1154. if (VALID_EVTCHN(evtchn))
  1155. set_evtchn(evtchn);
  1156. }
  1157. bool xen_test_irq_pending(int irq)
  1158. {
  1159. int evtchn = evtchn_from_irq(irq);
  1160. bool ret = false;
  1161. if (VALID_EVTCHN(evtchn))
  1162. ret = test_evtchn(evtchn);
  1163. return ret;
  1164. }
  1165. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1166. * the irq will be disabled so it won't deliver an interrupt. */
  1167. void xen_poll_irq_timeout(int irq, u64 timeout)
  1168. {
  1169. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1170. if (VALID_EVTCHN(evtchn)) {
  1171. struct sched_poll poll;
  1172. poll.nr_ports = 1;
  1173. poll.timeout = timeout;
  1174. set_xen_guest_handle(poll.ports, &evtchn);
  1175. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1176. BUG();
  1177. }
  1178. }
  1179. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1180. /* Poll waiting for an irq to become pending. In the usual case, the
  1181. * irq will be disabled so it won't deliver an interrupt. */
  1182. void xen_poll_irq(int irq)
  1183. {
  1184. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1185. }
  1186. void xen_irq_resume(void)
  1187. {
  1188. unsigned int cpu, evtchn;
  1189. struct irq_info *info;
  1190. init_evtchn_cpu_bindings();
  1191. /* New event-channel space is not 'live' yet. */
  1192. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1193. mask_evtchn(evtchn);
  1194. /* No IRQ <-> event-channel mappings. */
  1195. list_for_each_entry(info, &xen_irq_list_head, list)
  1196. info->evtchn = 0; /* zap event-channel binding */
  1197. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1198. evtchn_to_irq[evtchn] = -1;
  1199. for_each_possible_cpu(cpu) {
  1200. restore_cpu_virqs(cpu);
  1201. restore_cpu_ipis(cpu);
  1202. }
  1203. restore_pirqs();
  1204. }
  1205. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1206. .name = "xen-dyn",
  1207. .irq_disable = disable_dynirq,
  1208. .irq_mask = disable_dynirq,
  1209. .irq_unmask = enable_dynirq,
  1210. .irq_eoi = ack_dynirq,
  1211. .irq_set_affinity = set_affinity_irq,
  1212. .irq_retrigger = retrigger_dynirq,
  1213. };
  1214. static struct irq_chip xen_pirq_chip __read_mostly = {
  1215. .name = "xen-pirq",
  1216. .irq_startup = startup_pirq,
  1217. .irq_shutdown = shutdown_pirq,
  1218. .irq_enable = enable_pirq,
  1219. .irq_unmask = enable_pirq,
  1220. .irq_disable = disable_pirq,
  1221. .irq_mask = disable_pirq,
  1222. .irq_ack = ack_pirq,
  1223. .irq_set_affinity = set_affinity_irq,
  1224. .irq_retrigger = retrigger_dynirq,
  1225. };
  1226. static struct irq_chip xen_percpu_chip __read_mostly = {
  1227. .name = "xen-percpu",
  1228. .irq_disable = disable_dynirq,
  1229. .irq_mask = disable_dynirq,
  1230. .irq_unmask = enable_dynirq,
  1231. .irq_ack = ack_dynirq,
  1232. };
  1233. int xen_set_callback_via(uint64_t via)
  1234. {
  1235. struct xen_hvm_param a;
  1236. a.domid = DOMID_SELF;
  1237. a.index = HVM_PARAM_CALLBACK_IRQ;
  1238. a.value = via;
  1239. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1240. }
  1241. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1242. #ifdef CONFIG_XEN_PVHVM
  1243. /* Vector callbacks are better than PCI interrupts to receive event
  1244. * channel notifications because we can receive vector callbacks on any
  1245. * vcpu and we don't need PCI support or APIC interactions. */
  1246. void xen_callback_vector(void)
  1247. {
  1248. int rc;
  1249. uint64_t callback_via;
  1250. if (xen_have_vector_callback) {
  1251. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1252. rc = xen_set_callback_via(callback_via);
  1253. if (rc) {
  1254. printk(KERN_ERR "Request for Xen HVM callback vector"
  1255. " failed.\n");
  1256. xen_have_vector_callback = 0;
  1257. return;
  1258. }
  1259. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1260. "enabled\n");
  1261. /* in the restore case the vector has already been allocated */
  1262. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1263. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1264. }
  1265. }
  1266. #else
  1267. void xen_callback_vector(void) {}
  1268. #endif
  1269. void __init xen_init_IRQ(void)
  1270. {
  1271. int i;
  1272. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1273. GFP_KERNEL);
  1274. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1275. evtchn_to_irq[i] = -1;
  1276. init_evtchn_cpu_bindings();
  1277. /* No event channels are 'live' right now. */
  1278. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1279. mask_evtchn(i);
  1280. if (xen_hvm_domain()) {
  1281. xen_callback_vector();
  1282. native_init_IRQ();
  1283. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1284. * __acpi_register_gsi can point at the right function */
  1285. pci_xen_hvm_init();
  1286. } else {
  1287. irq_ctx_init(smp_processor_id());
  1288. if (xen_initial_domain())
  1289. xen_setup_pirqs();
  1290. }
  1291. }