ml_ioh_gpio.c 8.2 KB

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  1. /*
  2. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/gpio.h>
  20. #define PCI_VENDOR_ID_ROHM 0x10DB
  21. struct ioh_reg_comn {
  22. u32 ien;
  23. u32 istatus;
  24. u32 idisp;
  25. u32 iclr;
  26. u32 imask;
  27. u32 imaskclr;
  28. u32 po;
  29. u32 pi;
  30. u32 pm;
  31. u32 im_0;
  32. u32 im_1;
  33. u32 reserved;
  34. };
  35. struct ioh_regs {
  36. struct ioh_reg_comn regs[8];
  37. u32 reserve1[16];
  38. u32 ioh_sel_reg[4];
  39. u32 reserve2[11];
  40. u32 srst;
  41. };
  42. /**
  43. * struct ioh_gpio_reg_data - The register store data.
  44. * @po_reg: To store contents of PO register.
  45. * @pm_reg: To store contents of PM register.
  46. */
  47. struct ioh_gpio_reg_data {
  48. u32 po_reg;
  49. u32 pm_reg;
  50. };
  51. /**
  52. * struct ioh_gpio - GPIO private data structure.
  53. * @base: PCI base address of Memory mapped I/O register.
  54. * @reg: Memory mapped IOH GPIO register list.
  55. * @dev: Pointer to device structure.
  56. * @gpio: Data for GPIO infrastructure.
  57. * @ioh_gpio_reg: Memory mapped Register data is saved here
  58. * when suspend.
  59. * @ch: Indicate GPIO channel
  60. */
  61. struct ioh_gpio {
  62. void __iomem *base;
  63. struct ioh_regs __iomem *reg;
  64. struct device *dev;
  65. struct gpio_chip gpio;
  66. struct ioh_gpio_reg_data ioh_gpio_reg;
  67. struct mutex lock;
  68. int ch;
  69. };
  70. static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
  71. static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  72. {
  73. u32 reg_val;
  74. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  75. mutex_lock(&chip->lock);
  76. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  77. if (val)
  78. reg_val |= (1 << nr);
  79. else
  80. reg_val &= ~(1 << nr);
  81. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  82. mutex_unlock(&chip->lock);
  83. }
  84. static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
  85. {
  86. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  87. return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
  88. }
  89. static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
  90. int val)
  91. {
  92. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  93. u32 pm;
  94. u32 reg_val;
  95. mutex_lock(&chip->lock);
  96. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  97. ((1 << num_ports[chip->ch]) - 1);
  98. pm |= (1 << nr);
  99. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  100. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  101. if (val)
  102. reg_val |= (1 << nr);
  103. else
  104. reg_val &= ~(1 << nr);
  105. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  106. mutex_unlock(&chip->lock);
  107. return 0;
  108. }
  109. static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  110. {
  111. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  112. u32 pm;
  113. mutex_lock(&chip->lock);
  114. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  115. ((1 << num_ports[chip->ch]) - 1);
  116. pm &= ~(1 << nr);
  117. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  118. mutex_unlock(&chip->lock);
  119. return 0;
  120. }
  121. /*
  122. * Save register configuration and disable interrupts.
  123. */
  124. static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
  125. {
  126. chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
  127. chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
  128. }
  129. /*
  130. * This function restores the register configuration of the GPIO device.
  131. */
  132. static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
  133. {
  134. /* to store contents of PO register */
  135. iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
  136. /* to store contents of PM register */
  137. iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
  138. }
  139. static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
  140. {
  141. struct gpio_chip *gpio = &chip->gpio;
  142. gpio->label = dev_name(chip->dev);
  143. gpio->owner = THIS_MODULE;
  144. gpio->direction_input = ioh_gpio_direction_input;
  145. gpio->get = ioh_gpio_get;
  146. gpio->direction_output = ioh_gpio_direction_output;
  147. gpio->set = ioh_gpio_set;
  148. gpio->dbg_show = NULL;
  149. gpio->base = -1;
  150. gpio->ngpio = num_port;
  151. gpio->can_sleep = 0;
  152. }
  153. static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
  154. const struct pci_device_id *id)
  155. {
  156. int ret;
  157. int i;
  158. struct ioh_gpio *chip;
  159. void __iomem *base;
  160. void __iomem *chip_save;
  161. ret = pci_enable_device(pdev);
  162. if (ret) {
  163. dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
  164. goto err_pci_enable;
  165. }
  166. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  167. if (ret) {
  168. dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
  169. goto err_request_regions;
  170. }
  171. base = pci_iomap(pdev, 1, 0);
  172. if (base == 0) {
  173. dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
  174. ret = -ENOMEM;
  175. goto err_iomap;
  176. }
  177. chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
  178. if (chip_save == NULL) {
  179. dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
  180. ret = -ENOMEM;
  181. goto err_kzalloc;
  182. }
  183. chip = chip_save;
  184. for (i = 0; i < 8; i++, chip++) {
  185. chip->dev = &pdev->dev;
  186. chip->base = base;
  187. chip->reg = chip->base;
  188. chip->ch = i;
  189. mutex_init(&chip->lock);
  190. ioh_gpio_setup(chip, num_ports[i]);
  191. ret = gpiochip_add(&chip->gpio);
  192. if (ret) {
  193. dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
  194. goto err_gpiochip_add;
  195. }
  196. }
  197. chip = chip_save;
  198. pci_set_drvdata(pdev, chip);
  199. return 0;
  200. err_gpiochip_add:
  201. for (; i != 0; i--) {
  202. chip--;
  203. ret = gpiochip_remove(&chip->gpio);
  204. if (ret)
  205. dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
  206. }
  207. kfree(chip_save);
  208. err_kzalloc:
  209. pci_iounmap(pdev, base);
  210. err_iomap:
  211. pci_release_regions(pdev);
  212. err_request_regions:
  213. pci_disable_device(pdev);
  214. err_pci_enable:
  215. dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
  216. return ret;
  217. }
  218. static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
  219. {
  220. int err;
  221. int i;
  222. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  223. void __iomem *chip_save;
  224. chip_save = chip;
  225. for (i = 0; i < 8; i++, chip++) {
  226. err = gpiochip_remove(&chip->gpio);
  227. if (err)
  228. dev_err(&pdev->dev, "Failed gpiochip_remove\n");
  229. }
  230. chip = chip_save;
  231. pci_iounmap(pdev, chip->base);
  232. pci_release_regions(pdev);
  233. pci_disable_device(pdev);
  234. kfree(chip);
  235. }
  236. #ifdef CONFIG_PM
  237. static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
  238. {
  239. s32 ret;
  240. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  241. ioh_gpio_save_reg_conf(chip);
  242. ioh_gpio_restore_reg_conf(chip);
  243. ret = pci_save_state(pdev);
  244. if (ret) {
  245. dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
  246. return ret;
  247. }
  248. pci_disable_device(pdev);
  249. pci_set_power_state(pdev, PCI_D0);
  250. ret = pci_enable_wake(pdev, PCI_D0, 1);
  251. if (ret)
  252. dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
  253. return 0;
  254. }
  255. static int ioh_gpio_resume(struct pci_dev *pdev)
  256. {
  257. s32 ret;
  258. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  259. ret = pci_enable_wake(pdev, PCI_D0, 0);
  260. pci_set_power_state(pdev, PCI_D0);
  261. ret = pci_enable_device(pdev);
  262. if (ret) {
  263. dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
  264. return ret;
  265. }
  266. pci_restore_state(pdev);
  267. iowrite32(0x01, &chip->reg->srst);
  268. iowrite32(0x00, &chip->reg->srst);
  269. ioh_gpio_restore_reg_conf(chip);
  270. return 0;
  271. }
  272. #else
  273. #define ioh_gpio_suspend NULL
  274. #define ioh_gpio_resume NULL
  275. #endif
  276. static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
  277. { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
  278. { 0, }
  279. };
  280. MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
  281. static struct pci_driver ioh_gpio_driver = {
  282. .name = "ml_ioh_gpio",
  283. .id_table = ioh_gpio_pcidev_id,
  284. .probe = ioh_gpio_probe,
  285. .remove = __devexit_p(ioh_gpio_remove),
  286. .suspend = ioh_gpio_suspend,
  287. .resume = ioh_gpio_resume
  288. };
  289. static int __init ioh_gpio_pci_init(void)
  290. {
  291. return pci_register_driver(&ioh_gpio_driver);
  292. }
  293. module_init(ioh_gpio_pci_init);
  294. static void __exit ioh_gpio_pci_exit(void)
  295. {
  296. pci_unregister_driver(&ioh_gpio_driver);
  297. }
  298. module_exit(ioh_gpio_pci_exit);
  299. MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
  300. MODULE_LICENSE("GPL");