p54pci.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683
  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <net/mac80211.h>
  21. #include "p54.h"
  22. #include "lmac.h"
  23. #include "p54pci.h"
  24. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  25. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  26. MODULE_LICENSE("GPL");
  27. MODULE_ALIAS("prism54pci");
  28. MODULE_FIRMWARE("isl3886pci");
  29. static struct pci_device_id p54p_table[] __devinitdata = {
  30. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  31. { PCI_DEVICE(0x1260, 0x3890) },
  32. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  33. { PCI_DEVICE(0x10b7, 0x6001) },
  34. /* Intersil PRISM Indigo Wireless LAN adapter */
  35. { PCI_DEVICE(0x1260, 0x3877) },
  36. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  37. { PCI_DEVICE(0x1260, 0x3886) },
  38. { },
  39. };
  40. MODULE_DEVICE_TABLE(pci, p54p_table);
  41. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  42. {
  43. struct p54p_priv *priv = dev->priv;
  44. __le32 reg;
  45. int err;
  46. __le32 *data;
  47. u32 remains, left, device_addr;
  48. P54P_WRITE(int_enable, cpu_to_le32(0));
  49. P54P_READ(int_enable);
  50. udelay(10);
  51. reg = P54P_READ(ctrl_stat);
  52. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  53. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  54. P54P_WRITE(ctrl_stat, reg);
  55. P54P_READ(ctrl_stat);
  56. udelay(10);
  57. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  58. P54P_WRITE(ctrl_stat, reg);
  59. wmb();
  60. udelay(10);
  61. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  62. P54P_WRITE(ctrl_stat, reg);
  63. wmb();
  64. /* wait for the firmware to reset properly */
  65. mdelay(10);
  66. err = p54_parse_firmware(dev, priv->firmware);
  67. if (err)
  68. return err;
  69. if (priv->common.fw_interface != FW_LM86) {
  70. dev_err(&priv->pdev->dev, "wrong firmware, "
  71. "please get a LM86(PCI) firmware a try again.\n");
  72. return -EINVAL;
  73. }
  74. data = (__le32 *) priv->firmware->data;
  75. remains = priv->firmware->size;
  76. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  77. while (remains) {
  78. u32 i = 0;
  79. left = min((u32)0x1000, remains);
  80. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  81. P54P_READ(int_enable);
  82. device_addr += 0x1000;
  83. while (i < left) {
  84. P54P_WRITE(direct_mem_win[i], *data++);
  85. i += sizeof(u32);
  86. }
  87. remains -= left;
  88. P54P_READ(int_enable);
  89. }
  90. reg = P54P_READ(ctrl_stat);
  91. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  92. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  93. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  94. P54P_WRITE(ctrl_stat, reg);
  95. P54P_READ(ctrl_stat);
  96. udelay(10);
  97. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  98. P54P_WRITE(ctrl_stat, reg);
  99. wmb();
  100. udelay(10);
  101. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  102. P54P_WRITE(ctrl_stat, reg);
  103. wmb();
  104. udelay(10);
  105. /* wait for the firmware to boot properly */
  106. mdelay(100);
  107. return 0;
  108. }
  109. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  110. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  111. struct sk_buff **rx_buf)
  112. {
  113. struct p54p_priv *priv = dev->priv;
  114. struct p54p_ring_control *ring_control = priv->ring_control;
  115. u32 limit, idx, i;
  116. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  117. limit = idx;
  118. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  119. limit = ring_limit - limit;
  120. i = idx % ring_limit;
  121. while (limit-- > 1) {
  122. struct p54p_desc *desc = &ring[i];
  123. if (!desc->host_addr) {
  124. struct sk_buff *skb;
  125. dma_addr_t mapping;
  126. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  127. if (!skb)
  128. break;
  129. mapping = pci_map_single(priv->pdev,
  130. skb_tail_pointer(skb),
  131. priv->common.rx_mtu + 32,
  132. PCI_DMA_FROMDEVICE);
  133. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  134. dev_kfree_skb_any(skb);
  135. dev_err(&priv->pdev->dev,
  136. "RX DMA Mapping error\n");
  137. break;
  138. }
  139. desc->host_addr = cpu_to_le32(mapping);
  140. desc->device_addr = 0; // FIXME: necessary?
  141. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  142. desc->flags = 0;
  143. rx_buf[i] = skb;
  144. }
  145. i++;
  146. idx++;
  147. i %= ring_limit;
  148. }
  149. wmb();
  150. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  151. }
  152. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  153. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  154. struct sk_buff **rx_buf)
  155. {
  156. struct p54p_priv *priv = dev->priv;
  157. struct p54p_ring_control *ring_control = priv->ring_control;
  158. struct p54p_desc *desc;
  159. u32 idx, i;
  160. i = (*index) % ring_limit;
  161. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  162. idx %= ring_limit;
  163. while (i != idx) {
  164. u16 len;
  165. struct sk_buff *skb;
  166. desc = &ring[i];
  167. len = le16_to_cpu(desc->len);
  168. skb = rx_buf[i];
  169. if (!skb) {
  170. i++;
  171. i %= ring_limit;
  172. continue;
  173. }
  174. if (unlikely(len > priv->common.rx_mtu)) {
  175. if (net_ratelimit())
  176. dev_err(&priv->pdev->dev, "rx'd frame size "
  177. "exceeds length threshold.\n");
  178. len = priv->common.rx_mtu;
  179. }
  180. skb_put(skb, len);
  181. if (p54_rx(dev, skb)) {
  182. pci_unmap_single(priv->pdev,
  183. le32_to_cpu(desc->host_addr),
  184. priv->common.rx_mtu + 32,
  185. PCI_DMA_FROMDEVICE);
  186. rx_buf[i] = NULL;
  187. desc->host_addr = 0;
  188. } else {
  189. skb_trim(skb, 0);
  190. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  191. }
  192. i++;
  193. i %= ring_limit;
  194. }
  195. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  196. }
  197. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  198. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  199. struct sk_buff **tx_buf)
  200. {
  201. unsigned long flags;
  202. struct p54p_priv *priv = dev->priv;
  203. struct p54p_ring_control *ring_control = priv->ring_control;
  204. struct p54p_desc *desc;
  205. struct sk_buff *skb;
  206. u32 idx, i;
  207. i = (*index) % ring_limit;
  208. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  209. idx %= ring_limit;
  210. spin_lock_irqsave(&priv->lock, flags);
  211. while (i != idx) {
  212. desc = &ring[i];
  213. skb = tx_buf[i];
  214. tx_buf[i] = NULL;
  215. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  216. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  217. desc->host_addr = 0;
  218. desc->device_addr = 0;
  219. desc->len = 0;
  220. desc->flags = 0;
  221. if (skb && FREE_AFTER_TX(skb)) {
  222. spin_unlock_irqrestore(&priv->lock, flags);
  223. p54_free_skb(dev, skb);
  224. spin_lock_irqsave(&priv->lock, flags);
  225. }
  226. i++;
  227. i %= ring_limit;
  228. }
  229. spin_unlock_irqrestore(&priv->lock, flags);
  230. }
  231. static void p54p_tasklet(unsigned long dev_id)
  232. {
  233. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  234. struct p54p_priv *priv = dev->priv;
  235. struct p54p_ring_control *ring_control = priv->ring_control;
  236. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  237. ARRAY_SIZE(ring_control->tx_mgmt),
  238. priv->tx_buf_mgmt);
  239. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  240. ARRAY_SIZE(ring_control->tx_data),
  241. priv->tx_buf_data);
  242. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  243. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  244. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  245. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  246. wmb();
  247. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  248. }
  249. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  250. {
  251. struct ieee80211_hw *dev = dev_id;
  252. struct p54p_priv *priv = dev->priv;
  253. __le32 reg;
  254. spin_lock(&priv->lock);
  255. reg = P54P_READ(int_ident);
  256. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  257. goto out;
  258. }
  259. P54P_WRITE(int_ack, reg);
  260. reg &= P54P_READ(int_enable);
  261. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  262. tasklet_schedule(&priv->tasklet);
  263. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  264. complete(&priv->boot_comp);
  265. out:
  266. spin_unlock(&priv->lock);
  267. return reg ? IRQ_HANDLED : IRQ_NONE;
  268. }
  269. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  270. {
  271. struct p54p_priv *priv = dev->priv;
  272. struct p54p_ring_control *ring_control = priv->ring_control;
  273. unsigned long flags;
  274. struct p54p_desc *desc;
  275. dma_addr_t mapping;
  276. u32 device_idx, idx, i;
  277. spin_lock_irqsave(&priv->lock, flags);
  278. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  279. idx = le32_to_cpu(ring_control->host_idx[1]);
  280. i = idx % ARRAY_SIZE(ring_control->tx_data);
  281. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  282. PCI_DMA_TODEVICE);
  283. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  284. spin_unlock_irqrestore(&priv->lock, flags);
  285. p54_free_skb(dev, skb);
  286. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  287. return ;
  288. }
  289. priv->tx_buf_data[i] = skb;
  290. desc = &ring_control->tx_data[i];
  291. desc->host_addr = cpu_to_le32(mapping);
  292. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  293. desc->len = cpu_to_le16(skb->len);
  294. desc->flags = 0;
  295. wmb();
  296. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  297. spin_unlock_irqrestore(&priv->lock, flags);
  298. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  299. P54P_READ(dev_int);
  300. }
  301. static void p54p_stop(struct ieee80211_hw *dev)
  302. {
  303. struct p54p_priv *priv = dev->priv;
  304. struct p54p_ring_control *ring_control = priv->ring_control;
  305. unsigned int i;
  306. struct p54p_desc *desc;
  307. tasklet_kill(&priv->tasklet);
  308. P54P_WRITE(int_enable, cpu_to_le32(0));
  309. P54P_READ(int_enable);
  310. udelay(10);
  311. free_irq(priv->pdev->irq, dev);
  312. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  313. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  314. desc = &ring_control->rx_data[i];
  315. if (desc->host_addr)
  316. pci_unmap_single(priv->pdev,
  317. le32_to_cpu(desc->host_addr),
  318. priv->common.rx_mtu + 32,
  319. PCI_DMA_FROMDEVICE);
  320. kfree_skb(priv->rx_buf_data[i]);
  321. priv->rx_buf_data[i] = NULL;
  322. }
  323. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  324. desc = &ring_control->rx_mgmt[i];
  325. if (desc->host_addr)
  326. pci_unmap_single(priv->pdev,
  327. le32_to_cpu(desc->host_addr),
  328. priv->common.rx_mtu + 32,
  329. PCI_DMA_FROMDEVICE);
  330. kfree_skb(priv->rx_buf_mgmt[i]);
  331. priv->rx_buf_mgmt[i] = NULL;
  332. }
  333. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  334. desc = &ring_control->tx_data[i];
  335. if (desc->host_addr)
  336. pci_unmap_single(priv->pdev,
  337. le32_to_cpu(desc->host_addr),
  338. le16_to_cpu(desc->len),
  339. PCI_DMA_TODEVICE);
  340. p54_free_skb(dev, priv->tx_buf_data[i]);
  341. priv->tx_buf_data[i] = NULL;
  342. }
  343. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  344. desc = &ring_control->tx_mgmt[i];
  345. if (desc->host_addr)
  346. pci_unmap_single(priv->pdev,
  347. le32_to_cpu(desc->host_addr),
  348. le16_to_cpu(desc->len),
  349. PCI_DMA_TODEVICE);
  350. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  351. priv->tx_buf_mgmt[i] = NULL;
  352. }
  353. memset(ring_control, 0, sizeof(*ring_control));
  354. }
  355. static int p54p_open(struct ieee80211_hw *dev)
  356. {
  357. struct p54p_priv *priv = dev->priv;
  358. int err;
  359. init_completion(&priv->boot_comp);
  360. err = request_irq(priv->pdev->irq, p54p_interrupt,
  361. IRQF_SHARED, "p54pci", dev);
  362. if (err) {
  363. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  364. return err;
  365. }
  366. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  367. err = p54p_upload_firmware(dev);
  368. if (err) {
  369. free_irq(priv->pdev->irq, dev);
  370. return err;
  371. }
  372. priv->rx_idx_data = priv->tx_idx_data = 0;
  373. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  374. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  375. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  376. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  377. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  378. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  379. P54P_READ(ring_control_base);
  380. wmb();
  381. udelay(10);
  382. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  383. P54P_READ(int_enable);
  384. wmb();
  385. udelay(10);
  386. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  387. P54P_READ(dev_int);
  388. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  389. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  390. wiphy_name(dev->wiphy));
  391. p54p_stop(dev);
  392. return -ETIMEDOUT;
  393. }
  394. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  395. P54P_READ(int_enable);
  396. wmb();
  397. udelay(10);
  398. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  399. P54P_READ(dev_int);
  400. wmb();
  401. udelay(10);
  402. return 0;
  403. }
  404. static int __devinit p54p_probe(struct pci_dev *pdev,
  405. const struct pci_device_id *id)
  406. {
  407. struct p54p_priv *priv;
  408. struct ieee80211_hw *dev;
  409. unsigned long mem_addr, mem_len;
  410. int err;
  411. err = pci_enable_device(pdev);
  412. if (err) {
  413. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  414. return err;
  415. }
  416. mem_addr = pci_resource_start(pdev, 0);
  417. mem_len = pci_resource_len(pdev, 0);
  418. if (mem_len < sizeof(struct p54p_csr)) {
  419. dev_err(&pdev->dev, "Too short PCI resources\n");
  420. goto err_disable_dev;
  421. }
  422. err = pci_request_regions(pdev, "p54pci");
  423. if (err) {
  424. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  425. goto err_disable_dev;
  426. }
  427. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  428. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  429. dev_err(&pdev->dev, "No suitable DMA available\n");
  430. goto err_free_reg;
  431. }
  432. pci_set_master(pdev);
  433. pci_try_set_mwi(pdev);
  434. pci_write_config_byte(pdev, 0x40, 0);
  435. pci_write_config_byte(pdev, 0x41, 0);
  436. dev = p54_init_common(sizeof(*priv));
  437. if (!dev) {
  438. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  439. err = -ENOMEM;
  440. goto err_free_reg;
  441. }
  442. priv = dev->priv;
  443. priv->pdev = pdev;
  444. SET_IEEE80211_DEV(dev, &pdev->dev);
  445. pci_set_drvdata(pdev, dev);
  446. priv->map = ioremap(mem_addr, mem_len);
  447. if (!priv->map) {
  448. dev_err(&pdev->dev, "Cannot map device memory\n");
  449. err = -ENOMEM;
  450. goto err_free_dev;
  451. }
  452. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  453. &priv->ring_control_dma);
  454. if (!priv->ring_control) {
  455. dev_err(&pdev->dev, "Cannot allocate rings\n");
  456. err = -ENOMEM;
  457. goto err_iounmap;
  458. }
  459. priv->common.open = p54p_open;
  460. priv->common.stop = p54p_stop;
  461. priv->common.tx = p54p_tx;
  462. spin_lock_init(&priv->lock);
  463. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  464. err = request_firmware(&priv->firmware, "isl3886pci",
  465. &priv->pdev->dev);
  466. if (err) {
  467. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  468. err = request_firmware(&priv->firmware, "isl3886",
  469. &priv->pdev->dev);
  470. if (err)
  471. goto err_free_common;
  472. }
  473. err = p54p_open(dev);
  474. if (err)
  475. goto err_free_common;
  476. err = p54_read_eeprom(dev);
  477. p54p_stop(dev);
  478. if (err)
  479. goto err_free_common;
  480. err = p54_register_common(dev, &pdev->dev);
  481. if (err)
  482. goto err_free_common;
  483. return 0;
  484. err_free_common:
  485. release_firmware(priv->firmware);
  486. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  487. priv->ring_control, priv->ring_control_dma);
  488. err_iounmap:
  489. iounmap(priv->map);
  490. err_free_dev:
  491. pci_set_drvdata(pdev, NULL);
  492. p54_free_common(dev);
  493. err_free_reg:
  494. pci_release_regions(pdev);
  495. err_disable_dev:
  496. pci_disable_device(pdev);
  497. return err;
  498. }
  499. static void __devexit p54p_remove(struct pci_dev *pdev)
  500. {
  501. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  502. struct p54p_priv *priv;
  503. if (!dev)
  504. return;
  505. p54_unregister_common(dev);
  506. priv = dev->priv;
  507. release_firmware(priv->firmware);
  508. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  509. priv->ring_control, priv->ring_control_dma);
  510. iounmap(priv->map);
  511. pci_release_regions(pdev);
  512. pci_disable_device(pdev);
  513. p54_free_common(dev);
  514. }
  515. #ifdef CONFIG_PM
  516. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  517. {
  518. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  519. struct p54p_priv *priv = dev->priv;
  520. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  521. ieee80211_stop_queues(dev);
  522. p54p_stop(dev);
  523. }
  524. pci_save_state(pdev);
  525. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  526. return 0;
  527. }
  528. static int p54p_resume(struct pci_dev *pdev)
  529. {
  530. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  531. struct p54p_priv *priv = dev->priv;
  532. pci_set_power_state(pdev, PCI_D0);
  533. pci_restore_state(pdev);
  534. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  535. p54p_open(dev);
  536. ieee80211_wake_queues(dev);
  537. }
  538. return 0;
  539. }
  540. #endif /* CONFIG_PM */
  541. static struct pci_driver p54p_driver = {
  542. .name = "p54pci",
  543. .id_table = p54p_table,
  544. .probe = p54p_probe,
  545. .remove = __devexit_p(p54p_remove),
  546. #ifdef CONFIG_PM
  547. .suspend = p54p_suspend,
  548. .resume = p54p_resume,
  549. #endif /* CONFIG_PM */
  550. };
  551. static int __init p54p_init(void)
  552. {
  553. return pci_register_driver(&p54p_driver);
  554. }
  555. static void __exit p54p_exit(void)
  556. {
  557. pci_unregister_driver(&p54p_driver);
  558. }
  559. module_init(p54p_init);
  560. module_exit(p54p_exit);