r8a66597-udc.c 41 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/err.h>
  29. #include <linux/usb/ch9.h>
  30. #include <linux/usb/gadget.h>
  31. #include "r8a66597-udc.h"
  32. #define DRIVER_VERSION "2009-08-18"
  33. static const char udc_name[] = "r8a66597_udc";
  34. static const char *r8a66597_ep_name[] = {
  35. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  36. "ep8", "ep9",
  37. };
  38. static void disable_controller(struct r8a66597 *r8a66597);
  39. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  40. static void irq_packet_write(struct r8a66597_ep *ep,
  41. struct r8a66597_request *req);
  42. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  43. gfp_t gfp_flags);
  44. static void transfer_complete(struct r8a66597_ep *ep,
  45. struct r8a66597_request *req, int status);
  46. /*-------------------------------------------------------------------------*/
  47. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  48. {
  49. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  50. }
  51. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  52. unsigned long reg)
  53. {
  54. u16 tmp;
  55. tmp = r8a66597_read(r8a66597, INTENB0);
  56. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  57. INTENB0);
  58. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  59. r8a66597_write(r8a66597, tmp, INTENB0);
  60. }
  61. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  62. unsigned long reg)
  63. {
  64. u16 tmp;
  65. tmp = r8a66597_read(r8a66597, INTENB0);
  66. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  67. INTENB0);
  68. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  69. r8a66597_write(r8a66597, tmp, INTENB0);
  70. }
  71. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  72. {
  73. r8a66597_bset(r8a66597, CTRE, INTENB0);
  74. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  75. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  76. }
  77. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  78. __releases(r8a66597->lock)
  79. __acquires(r8a66597->lock)
  80. {
  81. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  82. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  83. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  84. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  85. spin_unlock(&r8a66597->lock);
  86. r8a66597->driver->disconnect(&r8a66597->gadget);
  87. spin_lock(&r8a66597->lock);
  88. disable_controller(r8a66597);
  89. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  90. }
  91. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  92. {
  93. u16 pid = 0;
  94. unsigned long offset;
  95. if (pipenum == 0)
  96. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  97. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  98. offset = get_pipectr_addr(pipenum);
  99. pid = r8a66597_read(r8a66597, offset) & PID;
  100. } else
  101. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  102. return pid;
  103. }
  104. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  105. u16 pid)
  106. {
  107. unsigned long offset;
  108. if (pipenum == 0)
  109. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  110. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  111. offset = get_pipectr_addr(pipenum);
  112. r8a66597_mdfy(r8a66597, pid, PID, offset);
  113. } else
  114. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  115. }
  116. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  117. {
  118. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  119. }
  120. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  121. {
  122. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  123. }
  124. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  125. {
  126. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  127. }
  128. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  129. {
  130. u16 ret = 0;
  131. unsigned long offset;
  132. if (pipenum == 0)
  133. ret = r8a66597_read(r8a66597, DCPCTR);
  134. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  135. offset = get_pipectr_addr(pipenum);
  136. ret = r8a66597_read(r8a66597, offset);
  137. } else
  138. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  139. return ret;
  140. }
  141. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  142. {
  143. unsigned long offset;
  144. pipe_stop(r8a66597, pipenum);
  145. if (pipenum == 0)
  146. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  147. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  148. offset = get_pipectr_addr(pipenum);
  149. r8a66597_bset(r8a66597, SQCLR, offset);
  150. } else
  151. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  152. }
  153. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  154. {
  155. u16 tmp;
  156. int size;
  157. if (pipenum == 0) {
  158. tmp = r8a66597_read(r8a66597, DCPCFG);
  159. if ((tmp & R8A66597_CNTMD) != 0)
  160. size = 256;
  161. else {
  162. tmp = r8a66597_read(r8a66597, DCPMAXP);
  163. size = tmp & MAXP;
  164. }
  165. } else {
  166. r8a66597_write(r8a66597, pipenum, PIPESEL);
  167. tmp = r8a66597_read(r8a66597, PIPECFG);
  168. if ((tmp & R8A66597_CNTMD) != 0) {
  169. tmp = r8a66597_read(r8a66597, PIPEBUF);
  170. size = ((tmp >> 10) + 1) * 64;
  171. } else {
  172. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  173. size = tmp & MXPS;
  174. }
  175. }
  176. return size;
  177. }
  178. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  179. {
  180. if (r8a66597->pdata->on_chip)
  181. return MBW_32;
  182. else
  183. return MBW_16;
  184. }
  185. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  186. {
  187. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  188. if (ep->use_dma)
  189. return;
  190. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  191. ndelay(450);
  192. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  193. }
  194. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  195. struct r8a66597_pipe_info *info)
  196. {
  197. u16 bufnum = 0, buf_bsize = 0;
  198. u16 pipecfg = 0;
  199. if (info->pipe == 0)
  200. return -EINVAL;
  201. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  202. if (info->dir_in)
  203. pipecfg |= R8A66597_DIR;
  204. pipecfg |= info->type;
  205. pipecfg |= info->epnum;
  206. switch (info->type) {
  207. case R8A66597_INT:
  208. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  209. buf_bsize = 0;
  210. break;
  211. case R8A66597_BULK:
  212. /* isochronous pipes may be used as bulk pipes */
  213. if (info->pipe > R8A66597_BASE_PIPENUM_BULK)
  214. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  215. else
  216. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  217. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  218. buf_bsize = 7;
  219. pipecfg |= R8A66597_DBLB;
  220. if (!info->dir_in)
  221. pipecfg |= R8A66597_SHTNAK;
  222. break;
  223. case R8A66597_ISO:
  224. bufnum = R8A66597_BASE_BUFNUM +
  225. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  226. buf_bsize = 7;
  227. break;
  228. }
  229. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  230. pr_err(KERN_ERR "r8a66597 pipe memory is insufficient\n");
  231. return -ENOMEM;
  232. }
  233. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  234. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  235. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  236. if (info->interval)
  237. info->interval--;
  238. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  239. return 0;
  240. }
  241. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  242. struct r8a66597_pipe_info *info)
  243. {
  244. if (info->pipe == 0)
  245. return;
  246. if (is_bulk_pipe(info->pipe))
  247. r8a66597->bulk--;
  248. else if (is_interrupt_pipe(info->pipe))
  249. r8a66597->interrupt--;
  250. else if (is_isoc_pipe(info->pipe)) {
  251. r8a66597->isochronous--;
  252. if (info->type == R8A66597_BULK)
  253. r8a66597->bulk--;
  254. } else
  255. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  256. info->pipe);
  257. }
  258. static void pipe_initialize(struct r8a66597_ep *ep)
  259. {
  260. struct r8a66597 *r8a66597 = ep->r8a66597;
  261. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  262. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  263. r8a66597_write(r8a66597, 0, ep->pipectr);
  264. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  265. if (ep->use_dma) {
  266. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  267. ndelay(450);
  268. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  269. }
  270. }
  271. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  272. struct r8a66597_ep *ep,
  273. const struct usb_endpoint_descriptor *desc,
  274. u16 pipenum, int dma)
  275. {
  276. ep->use_dma = 0;
  277. ep->fifoaddr = CFIFO;
  278. ep->fifosel = CFIFOSEL;
  279. ep->fifoctr = CFIFOCTR;
  280. ep->fifotrn = 0;
  281. ep->pipectr = get_pipectr_addr(pipenum);
  282. ep->pipenum = pipenum;
  283. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  284. r8a66597->pipenum2ep[pipenum] = ep;
  285. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  286. = ep;
  287. INIT_LIST_HEAD(&ep->queue);
  288. }
  289. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  290. {
  291. struct r8a66597 *r8a66597 = ep->r8a66597;
  292. u16 pipenum = ep->pipenum;
  293. if (pipenum == 0)
  294. return;
  295. if (ep->use_dma)
  296. r8a66597->num_dma--;
  297. ep->pipenum = 0;
  298. ep->busy = 0;
  299. ep->use_dma = 0;
  300. }
  301. static int alloc_pipe_config(struct r8a66597_ep *ep,
  302. const struct usb_endpoint_descriptor *desc)
  303. {
  304. struct r8a66597 *r8a66597 = ep->r8a66597;
  305. struct r8a66597_pipe_info info;
  306. int dma = 0;
  307. unsigned char *counter;
  308. int ret;
  309. ep->desc = desc;
  310. if (ep->pipenum) /* already allocated pipe */
  311. return 0;
  312. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  313. case USB_ENDPOINT_XFER_BULK:
  314. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  315. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  316. printk(KERN_ERR "bulk pipe is insufficient\n");
  317. return -ENODEV;
  318. } else {
  319. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  320. + r8a66597->isochronous;
  321. counter = &r8a66597->isochronous;
  322. }
  323. } else {
  324. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  325. counter = &r8a66597->bulk;
  326. }
  327. info.type = R8A66597_BULK;
  328. dma = 1;
  329. break;
  330. case USB_ENDPOINT_XFER_INT:
  331. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  332. printk(KERN_ERR "interrupt pipe is insufficient\n");
  333. return -ENODEV;
  334. }
  335. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  336. info.type = R8A66597_INT;
  337. counter = &r8a66597->interrupt;
  338. break;
  339. case USB_ENDPOINT_XFER_ISOC:
  340. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  341. printk(KERN_ERR "isochronous pipe is insufficient\n");
  342. return -ENODEV;
  343. }
  344. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  345. info.type = R8A66597_ISO;
  346. counter = &r8a66597->isochronous;
  347. break;
  348. default:
  349. printk(KERN_ERR "unexpect xfer type\n");
  350. return -EINVAL;
  351. }
  352. ep->type = info.type;
  353. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  354. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  355. info.interval = desc->bInterval;
  356. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  357. info.dir_in = 1;
  358. else
  359. info.dir_in = 0;
  360. ret = pipe_buffer_setting(r8a66597, &info);
  361. if (ret < 0) {
  362. printk(KERN_ERR "pipe_buffer_setting fail\n");
  363. return ret;
  364. }
  365. (*counter)++;
  366. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  367. r8a66597->bulk++;
  368. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  369. pipe_initialize(ep);
  370. return 0;
  371. }
  372. static int free_pipe_config(struct r8a66597_ep *ep)
  373. {
  374. struct r8a66597 *r8a66597 = ep->r8a66597;
  375. struct r8a66597_pipe_info info;
  376. info.pipe = ep->pipenum;
  377. info.type = ep->type;
  378. pipe_buffer_release(r8a66597, &info);
  379. r8a66597_ep_release(ep);
  380. return 0;
  381. }
  382. /*-------------------------------------------------------------------------*/
  383. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  384. {
  385. enable_irq_ready(r8a66597, pipenum);
  386. enable_irq_nrdy(r8a66597, pipenum);
  387. }
  388. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  389. {
  390. disable_irq_ready(r8a66597, pipenum);
  391. disable_irq_nrdy(r8a66597, pipenum);
  392. }
  393. /* if complete is true, gadget driver complete function is not call */
  394. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  395. {
  396. r8a66597->ep[0].internal_ccpl = ccpl;
  397. pipe_start(r8a66597, 0);
  398. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  399. }
  400. static void start_ep0_write(struct r8a66597_ep *ep,
  401. struct r8a66597_request *req)
  402. {
  403. struct r8a66597 *r8a66597 = ep->r8a66597;
  404. pipe_change(r8a66597, ep->pipenum);
  405. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  406. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  407. if (req->req.length == 0) {
  408. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  409. pipe_start(r8a66597, 0);
  410. transfer_complete(ep, req, 0);
  411. } else {
  412. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  413. irq_ep0_write(ep, req);
  414. }
  415. }
  416. static void start_packet_write(struct r8a66597_ep *ep,
  417. struct r8a66597_request *req)
  418. {
  419. struct r8a66597 *r8a66597 = ep->r8a66597;
  420. u16 tmp;
  421. pipe_change(r8a66597, ep->pipenum);
  422. disable_irq_empty(r8a66597, ep->pipenum);
  423. pipe_start(r8a66597, ep->pipenum);
  424. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  425. if (unlikely((tmp & FRDY) == 0))
  426. pipe_irq_enable(r8a66597, ep->pipenum);
  427. else
  428. irq_packet_write(ep, req);
  429. }
  430. static void start_packet_read(struct r8a66597_ep *ep,
  431. struct r8a66597_request *req)
  432. {
  433. struct r8a66597 *r8a66597 = ep->r8a66597;
  434. u16 pipenum = ep->pipenum;
  435. if (ep->pipenum == 0) {
  436. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  437. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  438. pipe_start(r8a66597, pipenum);
  439. pipe_irq_enable(r8a66597, pipenum);
  440. } else {
  441. if (ep->use_dma) {
  442. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  443. pipe_change(r8a66597, pipenum);
  444. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  445. r8a66597_write(r8a66597,
  446. (req->req.length + ep->ep.maxpacket - 1)
  447. / ep->ep.maxpacket,
  448. ep->fifotrn);
  449. }
  450. pipe_start(r8a66597, pipenum); /* trigger once */
  451. pipe_irq_enable(r8a66597, pipenum);
  452. }
  453. }
  454. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  455. {
  456. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  457. start_packet_write(ep, req);
  458. else
  459. start_packet_read(ep, req);
  460. }
  461. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  462. {
  463. u16 ctsq;
  464. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  465. switch (ctsq) {
  466. case CS_RDDS:
  467. start_ep0_write(ep, req);
  468. break;
  469. case CS_WRDS:
  470. start_packet_read(ep, req);
  471. break;
  472. case CS_WRND:
  473. control_end(ep->r8a66597, 0);
  474. break;
  475. default:
  476. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  477. break;
  478. }
  479. }
  480. static void init_controller(struct r8a66597 *r8a66597)
  481. {
  482. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  483. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  484. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  485. if (r8a66597->pdata->on_chip) {
  486. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  487. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  488. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  489. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  490. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  491. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  492. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  493. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  494. DMA0CFG);
  495. } else {
  496. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  497. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  498. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  499. XTAL, SYSCFG0);
  500. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  501. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  502. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  503. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  504. msleep(3);
  505. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  506. msleep(1);
  507. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  508. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  509. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  510. DMA0CFG);
  511. }
  512. }
  513. static void disable_controller(struct r8a66597 *r8a66597)
  514. {
  515. if (r8a66597->pdata->on_chip) {
  516. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  517. /* disable interrupts */
  518. r8a66597_write(r8a66597, 0, INTENB0);
  519. r8a66597_write(r8a66597, 0, INTENB1);
  520. r8a66597_write(r8a66597, 0, BRDYENB);
  521. r8a66597_write(r8a66597, 0, BEMPENB);
  522. r8a66597_write(r8a66597, 0, NRDYENB);
  523. /* clear status */
  524. r8a66597_write(r8a66597, 0, BRDYSTS);
  525. r8a66597_write(r8a66597, 0, NRDYSTS);
  526. r8a66597_write(r8a66597, 0, BEMPSTS);
  527. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  528. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  529. } else {
  530. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  531. udelay(1);
  532. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  533. udelay(1);
  534. udelay(1);
  535. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  536. }
  537. }
  538. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  539. {
  540. u16 tmp;
  541. if (!r8a66597->pdata->on_chip) {
  542. tmp = r8a66597_read(r8a66597, SYSCFG0);
  543. if (!(tmp & XCKE))
  544. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  545. }
  546. }
  547. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  548. {
  549. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  550. }
  551. /*-------------------------------------------------------------------------*/
  552. static void transfer_complete(struct r8a66597_ep *ep,
  553. struct r8a66597_request *req, int status)
  554. __releases(r8a66597->lock)
  555. __acquires(r8a66597->lock)
  556. {
  557. int restart = 0;
  558. if (unlikely(ep->pipenum == 0)) {
  559. if (ep->internal_ccpl) {
  560. ep->internal_ccpl = 0;
  561. return;
  562. }
  563. }
  564. list_del_init(&req->queue);
  565. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  566. req->req.status = -ESHUTDOWN;
  567. else
  568. req->req.status = status;
  569. if (!list_empty(&ep->queue))
  570. restart = 1;
  571. spin_unlock(&ep->r8a66597->lock);
  572. req->req.complete(&ep->ep, &req->req);
  573. spin_lock(&ep->r8a66597->lock);
  574. if (restart) {
  575. req = get_request_from_ep(ep);
  576. if (ep->desc)
  577. start_packet(ep, req);
  578. }
  579. }
  580. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  581. {
  582. int i;
  583. u16 tmp;
  584. unsigned bufsize;
  585. size_t size;
  586. void *buf;
  587. u16 pipenum = ep->pipenum;
  588. struct r8a66597 *r8a66597 = ep->r8a66597;
  589. pipe_change(r8a66597, pipenum);
  590. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  591. i = 0;
  592. do {
  593. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  594. if (i++ > 100000) {
  595. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  596. "conflict. please power off this controller.");
  597. return;
  598. }
  599. ndelay(1);
  600. } while ((tmp & FRDY) == 0);
  601. /* prepare parameters */
  602. bufsize = get_buffer_size(r8a66597, pipenum);
  603. buf = req->req.buf + req->req.actual;
  604. size = min(bufsize, req->req.length - req->req.actual);
  605. /* write fifo */
  606. if (req->req.buf) {
  607. if (size > 0)
  608. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  609. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  610. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  611. }
  612. /* update parameters */
  613. req->req.actual += size;
  614. /* check transfer finish */
  615. if ((!req->req.zero && (req->req.actual == req->req.length))
  616. || (size % ep->ep.maxpacket)
  617. || (size == 0)) {
  618. disable_irq_ready(r8a66597, pipenum);
  619. disable_irq_empty(r8a66597, pipenum);
  620. } else {
  621. disable_irq_ready(r8a66597, pipenum);
  622. enable_irq_empty(r8a66597, pipenum);
  623. }
  624. pipe_start(r8a66597, pipenum);
  625. }
  626. static void irq_packet_write(struct r8a66597_ep *ep,
  627. struct r8a66597_request *req)
  628. {
  629. u16 tmp;
  630. unsigned bufsize;
  631. size_t size;
  632. void *buf;
  633. u16 pipenum = ep->pipenum;
  634. struct r8a66597 *r8a66597 = ep->r8a66597;
  635. pipe_change(r8a66597, pipenum);
  636. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  637. if (unlikely((tmp & FRDY) == 0)) {
  638. pipe_stop(r8a66597, pipenum);
  639. pipe_irq_disable(r8a66597, pipenum);
  640. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  641. return;
  642. }
  643. /* prepare parameters */
  644. bufsize = get_buffer_size(r8a66597, pipenum);
  645. buf = req->req.buf + req->req.actual;
  646. size = min(bufsize, req->req.length - req->req.actual);
  647. /* write fifo */
  648. if (req->req.buf) {
  649. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  650. if ((size == 0)
  651. || ((size % ep->ep.maxpacket) != 0)
  652. || ((bufsize != ep->ep.maxpacket)
  653. && (bufsize > size)))
  654. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  655. }
  656. /* update parameters */
  657. req->req.actual += size;
  658. /* check transfer finish */
  659. if ((!req->req.zero && (req->req.actual == req->req.length))
  660. || (size % ep->ep.maxpacket)
  661. || (size == 0)) {
  662. disable_irq_ready(r8a66597, pipenum);
  663. enable_irq_empty(r8a66597, pipenum);
  664. } else {
  665. disable_irq_empty(r8a66597, pipenum);
  666. pipe_irq_enable(r8a66597, pipenum);
  667. }
  668. }
  669. static void irq_packet_read(struct r8a66597_ep *ep,
  670. struct r8a66597_request *req)
  671. {
  672. u16 tmp;
  673. int rcv_len, bufsize, req_len;
  674. int size;
  675. void *buf;
  676. u16 pipenum = ep->pipenum;
  677. struct r8a66597 *r8a66597 = ep->r8a66597;
  678. int finish = 0;
  679. pipe_change(r8a66597, pipenum);
  680. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  681. if (unlikely((tmp & FRDY) == 0)) {
  682. req->req.status = -EPIPE;
  683. pipe_stop(r8a66597, pipenum);
  684. pipe_irq_disable(r8a66597, pipenum);
  685. printk(KERN_ERR "read fifo not ready");
  686. return;
  687. }
  688. /* prepare parameters */
  689. rcv_len = tmp & DTLN;
  690. bufsize = get_buffer_size(r8a66597, pipenum);
  691. buf = req->req.buf + req->req.actual;
  692. req_len = req->req.length - req->req.actual;
  693. if (rcv_len < bufsize)
  694. size = min(rcv_len, req_len);
  695. else
  696. size = min(bufsize, req_len);
  697. /* update parameters */
  698. req->req.actual += size;
  699. /* check transfer finish */
  700. if ((!req->req.zero && (req->req.actual == req->req.length))
  701. || (size % ep->ep.maxpacket)
  702. || (size == 0)) {
  703. pipe_stop(r8a66597, pipenum);
  704. pipe_irq_disable(r8a66597, pipenum);
  705. finish = 1;
  706. }
  707. /* read fifo */
  708. if (req->req.buf) {
  709. if (size == 0)
  710. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  711. else
  712. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  713. }
  714. if ((ep->pipenum != 0) && finish)
  715. transfer_complete(ep, req, 0);
  716. }
  717. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  718. {
  719. u16 check;
  720. u16 pipenum;
  721. struct r8a66597_ep *ep;
  722. struct r8a66597_request *req;
  723. if ((status & BRDY0) && (enb & BRDY0)) {
  724. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  725. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  726. ep = &r8a66597->ep[0];
  727. req = get_request_from_ep(ep);
  728. irq_packet_read(ep, req);
  729. } else {
  730. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  731. check = 1 << pipenum;
  732. if ((status & check) && (enb & check)) {
  733. r8a66597_write(r8a66597, ~check, BRDYSTS);
  734. ep = r8a66597->pipenum2ep[pipenum];
  735. req = get_request_from_ep(ep);
  736. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  737. irq_packet_write(ep, req);
  738. else
  739. irq_packet_read(ep, req);
  740. }
  741. }
  742. }
  743. }
  744. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  745. {
  746. u16 tmp;
  747. u16 check;
  748. u16 pipenum;
  749. struct r8a66597_ep *ep;
  750. struct r8a66597_request *req;
  751. if ((status & BEMP0) && (enb & BEMP0)) {
  752. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  753. ep = &r8a66597->ep[0];
  754. req = get_request_from_ep(ep);
  755. irq_ep0_write(ep, req);
  756. } else {
  757. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  758. check = 1 << pipenum;
  759. if ((status & check) && (enb & check)) {
  760. r8a66597_write(r8a66597, ~check, BEMPSTS);
  761. tmp = control_reg_get(r8a66597, pipenum);
  762. if ((tmp & INBUFM) == 0) {
  763. disable_irq_empty(r8a66597, pipenum);
  764. pipe_irq_disable(r8a66597, pipenum);
  765. pipe_stop(r8a66597, pipenum);
  766. ep = r8a66597->pipenum2ep[pipenum];
  767. req = get_request_from_ep(ep);
  768. if (!list_empty(&ep->queue))
  769. transfer_complete(ep, req, 0);
  770. }
  771. }
  772. }
  773. }
  774. }
  775. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  776. __releases(r8a66597->lock)
  777. __acquires(r8a66597->lock)
  778. {
  779. struct r8a66597_ep *ep;
  780. u16 pid;
  781. u16 status = 0;
  782. u16 w_index = le16_to_cpu(ctrl->wIndex);
  783. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  784. case USB_RECIP_DEVICE:
  785. status = 1 << USB_DEVICE_SELF_POWERED;
  786. break;
  787. case USB_RECIP_INTERFACE:
  788. status = 0;
  789. break;
  790. case USB_RECIP_ENDPOINT:
  791. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  792. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  793. if (pid == PID_STALL)
  794. status = 1 << USB_ENDPOINT_HALT;
  795. else
  796. status = 0;
  797. break;
  798. default:
  799. pipe_stall(r8a66597, 0);
  800. return; /* exit */
  801. }
  802. r8a66597->ep0_data = cpu_to_le16(status);
  803. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  804. r8a66597->ep0_req->length = 2;
  805. /* AV: what happens if we get called again before that gets through? */
  806. spin_unlock(&r8a66597->lock);
  807. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  808. spin_lock(&r8a66597->lock);
  809. }
  810. static void clear_feature(struct r8a66597 *r8a66597,
  811. struct usb_ctrlrequest *ctrl)
  812. {
  813. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  814. case USB_RECIP_DEVICE:
  815. control_end(r8a66597, 1);
  816. break;
  817. case USB_RECIP_INTERFACE:
  818. control_end(r8a66597, 1);
  819. break;
  820. case USB_RECIP_ENDPOINT: {
  821. struct r8a66597_ep *ep;
  822. struct r8a66597_request *req;
  823. u16 w_index = le16_to_cpu(ctrl->wIndex);
  824. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  825. if (!ep->wedge) {
  826. pipe_stop(r8a66597, ep->pipenum);
  827. control_reg_sqclr(r8a66597, ep->pipenum);
  828. spin_unlock(&r8a66597->lock);
  829. usb_ep_clear_halt(&ep->ep);
  830. spin_lock(&r8a66597->lock);
  831. }
  832. control_end(r8a66597, 1);
  833. req = get_request_from_ep(ep);
  834. if (ep->busy) {
  835. ep->busy = 0;
  836. if (list_empty(&ep->queue))
  837. break;
  838. start_packet(ep, req);
  839. } else if (!list_empty(&ep->queue))
  840. pipe_start(r8a66597, ep->pipenum);
  841. }
  842. break;
  843. default:
  844. pipe_stall(r8a66597, 0);
  845. break;
  846. }
  847. }
  848. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  849. {
  850. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  851. case USB_RECIP_DEVICE:
  852. control_end(r8a66597, 1);
  853. break;
  854. case USB_RECIP_INTERFACE:
  855. control_end(r8a66597, 1);
  856. break;
  857. case USB_RECIP_ENDPOINT: {
  858. struct r8a66597_ep *ep;
  859. u16 w_index = le16_to_cpu(ctrl->wIndex);
  860. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  861. pipe_stall(r8a66597, ep->pipenum);
  862. control_end(r8a66597, 1);
  863. }
  864. break;
  865. default:
  866. pipe_stall(r8a66597, 0);
  867. break;
  868. }
  869. }
  870. /* if return value is true, call class driver's setup() */
  871. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  872. {
  873. u16 *p = (u16 *)ctrl;
  874. unsigned long offset = USBREQ;
  875. int i, ret = 0;
  876. /* read fifo */
  877. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  878. for (i = 0; i < 4; i++)
  879. p[i] = r8a66597_read(r8a66597, offset + i*2);
  880. /* check request */
  881. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  882. switch (ctrl->bRequest) {
  883. case USB_REQ_GET_STATUS:
  884. get_status(r8a66597, ctrl);
  885. break;
  886. case USB_REQ_CLEAR_FEATURE:
  887. clear_feature(r8a66597, ctrl);
  888. break;
  889. case USB_REQ_SET_FEATURE:
  890. set_feature(r8a66597, ctrl);
  891. break;
  892. default:
  893. ret = 1;
  894. break;
  895. }
  896. } else
  897. ret = 1;
  898. return ret;
  899. }
  900. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  901. {
  902. u16 speed = get_usb_speed(r8a66597);
  903. switch (speed) {
  904. case HSMODE:
  905. r8a66597->gadget.speed = USB_SPEED_HIGH;
  906. break;
  907. case FSMODE:
  908. r8a66597->gadget.speed = USB_SPEED_FULL;
  909. break;
  910. default:
  911. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  912. printk(KERN_ERR "USB speed unknown\n");
  913. }
  914. }
  915. static void irq_device_state(struct r8a66597 *r8a66597)
  916. {
  917. u16 dvsq;
  918. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  919. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  920. if (dvsq == DS_DFLT) {
  921. /* bus reset */
  922. r8a66597->driver->disconnect(&r8a66597->gadget);
  923. r8a66597_update_usb_speed(r8a66597);
  924. }
  925. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  926. r8a66597_update_usb_speed(r8a66597);
  927. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  928. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  929. r8a66597_update_usb_speed(r8a66597);
  930. r8a66597->old_dvsq = dvsq;
  931. }
  932. static void irq_control_stage(struct r8a66597 *r8a66597)
  933. __releases(r8a66597->lock)
  934. __acquires(r8a66597->lock)
  935. {
  936. struct usb_ctrlrequest ctrl;
  937. u16 ctsq;
  938. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  939. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  940. switch (ctsq) {
  941. case CS_IDST: {
  942. struct r8a66597_ep *ep;
  943. struct r8a66597_request *req;
  944. ep = &r8a66597->ep[0];
  945. req = get_request_from_ep(ep);
  946. transfer_complete(ep, req, 0);
  947. }
  948. break;
  949. case CS_RDDS:
  950. case CS_WRDS:
  951. case CS_WRND:
  952. if (setup_packet(r8a66597, &ctrl)) {
  953. spin_unlock(&r8a66597->lock);
  954. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  955. < 0)
  956. pipe_stall(r8a66597, 0);
  957. spin_lock(&r8a66597->lock);
  958. }
  959. break;
  960. case CS_RDSS:
  961. case CS_WRSS:
  962. control_end(r8a66597, 0);
  963. break;
  964. default:
  965. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  966. break;
  967. }
  968. }
  969. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  970. {
  971. struct r8a66597 *r8a66597 = _r8a66597;
  972. u16 intsts0;
  973. u16 intenb0;
  974. u16 brdysts, nrdysts, bempsts;
  975. u16 brdyenb, nrdyenb, bempenb;
  976. u16 savepipe;
  977. u16 mask0;
  978. spin_lock(&r8a66597->lock);
  979. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  980. intenb0 = r8a66597_read(r8a66597, INTENB0);
  981. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  982. mask0 = intsts0 & intenb0;
  983. if (mask0) {
  984. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  985. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  986. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  987. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  988. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  989. bempenb = r8a66597_read(r8a66597, BEMPENB);
  990. if (mask0 & VBINT) {
  991. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  992. INTSTS0);
  993. r8a66597_start_xclock(r8a66597);
  994. /* start vbus sampling */
  995. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  996. & VBSTS;
  997. r8a66597->scount = R8A66597_MAX_SAMPLING;
  998. mod_timer(&r8a66597->timer,
  999. jiffies + msecs_to_jiffies(50));
  1000. }
  1001. if (intsts0 & DVSQ)
  1002. irq_device_state(r8a66597);
  1003. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1004. && (brdysts & brdyenb))
  1005. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1006. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1007. && (bempsts & bempenb))
  1008. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1009. if (intsts0 & CTRT)
  1010. irq_control_stage(r8a66597);
  1011. }
  1012. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1013. spin_unlock(&r8a66597->lock);
  1014. return IRQ_HANDLED;
  1015. }
  1016. static void r8a66597_timer(unsigned long _r8a66597)
  1017. {
  1018. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1019. unsigned long flags;
  1020. u16 tmp;
  1021. spin_lock_irqsave(&r8a66597->lock, flags);
  1022. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1023. if (r8a66597->scount > 0) {
  1024. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1025. if (tmp == r8a66597->old_vbus) {
  1026. r8a66597->scount--;
  1027. if (r8a66597->scount == 0) {
  1028. if (tmp == VBSTS)
  1029. r8a66597_usb_connect(r8a66597);
  1030. else
  1031. r8a66597_usb_disconnect(r8a66597);
  1032. } else {
  1033. mod_timer(&r8a66597->timer,
  1034. jiffies + msecs_to_jiffies(50));
  1035. }
  1036. } else {
  1037. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1038. r8a66597->old_vbus = tmp;
  1039. mod_timer(&r8a66597->timer,
  1040. jiffies + msecs_to_jiffies(50));
  1041. }
  1042. }
  1043. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1044. }
  1045. /*-------------------------------------------------------------------------*/
  1046. static int r8a66597_enable(struct usb_ep *_ep,
  1047. const struct usb_endpoint_descriptor *desc)
  1048. {
  1049. struct r8a66597_ep *ep;
  1050. ep = container_of(_ep, struct r8a66597_ep, ep);
  1051. return alloc_pipe_config(ep, desc);
  1052. }
  1053. static int r8a66597_disable(struct usb_ep *_ep)
  1054. {
  1055. struct r8a66597_ep *ep;
  1056. struct r8a66597_request *req;
  1057. unsigned long flags;
  1058. ep = container_of(_ep, struct r8a66597_ep, ep);
  1059. BUG_ON(!ep);
  1060. while (!list_empty(&ep->queue)) {
  1061. req = get_request_from_ep(ep);
  1062. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1063. transfer_complete(ep, req, -ECONNRESET);
  1064. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1065. }
  1066. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1067. return free_pipe_config(ep);
  1068. }
  1069. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1070. gfp_t gfp_flags)
  1071. {
  1072. struct r8a66597_request *req;
  1073. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1074. if (!req)
  1075. return NULL;
  1076. INIT_LIST_HEAD(&req->queue);
  1077. return &req->req;
  1078. }
  1079. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1080. {
  1081. struct r8a66597_request *req;
  1082. req = container_of(_req, struct r8a66597_request, req);
  1083. kfree(req);
  1084. }
  1085. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1086. gfp_t gfp_flags)
  1087. {
  1088. struct r8a66597_ep *ep;
  1089. struct r8a66597_request *req;
  1090. unsigned long flags;
  1091. int request = 0;
  1092. ep = container_of(_ep, struct r8a66597_ep, ep);
  1093. req = container_of(_req, struct r8a66597_request, req);
  1094. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1095. return -ESHUTDOWN;
  1096. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1097. if (list_empty(&ep->queue))
  1098. request = 1;
  1099. list_add_tail(&req->queue, &ep->queue);
  1100. req->req.actual = 0;
  1101. req->req.status = -EINPROGRESS;
  1102. if (ep->desc == NULL) /* control */
  1103. start_ep0(ep, req);
  1104. else {
  1105. if (request && !ep->busy)
  1106. start_packet(ep, req);
  1107. }
  1108. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1109. return 0;
  1110. }
  1111. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1112. {
  1113. struct r8a66597_ep *ep;
  1114. struct r8a66597_request *req;
  1115. unsigned long flags;
  1116. ep = container_of(_ep, struct r8a66597_ep, ep);
  1117. req = container_of(_req, struct r8a66597_request, req);
  1118. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1119. if (!list_empty(&ep->queue))
  1120. transfer_complete(ep, req, -ECONNRESET);
  1121. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1122. return 0;
  1123. }
  1124. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1125. {
  1126. struct r8a66597_ep *ep;
  1127. struct r8a66597_request *req;
  1128. unsigned long flags;
  1129. int ret = 0;
  1130. ep = container_of(_ep, struct r8a66597_ep, ep);
  1131. req = get_request_from_ep(ep);
  1132. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1133. if (!list_empty(&ep->queue)) {
  1134. ret = -EAGAIN;
  1135. goto out;
  1136. }
  1137. if (value) {
  1138. ep->busy = 1;
  1139. pipe_stall(ep->r8a66597, ep->pipenum);
  1140. } else {
  1141. ep->busy = 0;
  1142. ep->wedge = 0;
  1143. pipe_stop(ep->r8a66597, ep->pipenum);
  1144. }
  1145. out:
  1146. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1147. return ret;
  1148. }
  1149. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1150. {
  1151. struct r8a66597_ep *ep;
  1152. unsigned long flags;
  1153. ep = container_of(_ep, struct r8a66597_ep, ep);
  1154. if (!ep || !ep->desc)
  1155. return -EINVAL;
  1156. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1157. ep->wedge = 1;
  1158. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1159. return usb_ep_set_halt(_ep);
  1160. }
  1161. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1162. {
  1163. struct r8a66597_ep *ep;
  1164. unsigned long flags;
  1165. ep = container_of(_ep, struct r8a66597_ep, ep);
  1166. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1167. if (list_empty(&ep->queue) && !ep->busy) {
  1168. pipe_stop(ep->r8a66597, ep->pipenum);
  1169. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1170. }
  1171. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1172. }
  1173. static struct usb_ep_ops r8a66597_ep_ops = {
  1174. .enable = r8a66597_enable,
  1175. .disable = r8a66597_disable,
  1176. .alloc_request = r8a66597_alloc_request,
  1177. .free_request = r8a66597_free_request,
  1178. .queue = r8a66597_queue,
  1179. .dequeue = r8a66597_dequeue,
  1180. .set_halt = r8a66597_set_halt,
  1181. .set_wedge = r8a66597_set_wedge,
  1182. .fifo_flush = r8a66597_fifo_flush,
  1183. };
  1184. /*-------------------------------------------------------------------------*/
  1185. static struct r8a66597 *the_controller;
  1186. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1187. {
  1188. struct r8a66597 *r8a66597 = the_controller;
  1189. int retval;
  1190. if (!driver
  1191. || driver->speed != USB_SPEED_HIGH
  1192. || !driver->bind
  1193. || !driver->setup)
  1194. return -EINVAL;
  1195. if (!r8a66597)
  1196. return -ENODEV;
  1197. if (r8a66597->driver)
  1198. return -EBUSY;
  1199. /* hook up the driver */
  1200. driver->driver.bus = NULL;
  1201. r8a66597->driver = driver;
  1202. r8a66597->gadget.dev.driver = &driver->driver;
  1203. retval = device_add(&r8a66597->gadget.dev);
  1204. if (retval) {
  1205. printk(KERN_ERR "device_add error (%d)\n", retval);
  1206. goto error;
  1207. }
  1208. retval = driver->bind(&r8a66597->gadget);
  1209. if (retval) {
  1210. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1211. device_del(&r8a66597->gadget.dev);
  1212. goto error;
  1213. }
  1214. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1215. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1216. r8a66597_start_xclock(r8a66597);
  1217. /* start vbus sampling */
  1218. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1219. INTSTS0) & VBSTS;
  1220. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1221. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1222. }
  1223. return 0;
  1224. error:
  1225. r8a66597->driver = NULL;
  1226. r8a66597->gadget.dev.driver = NULL;
  1227. return retval;
  1228. }
  1229. EXPORT_SYMBOL(usb_gadget_register_driver);
  1230. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1231. {
  1232. struct r8a66597 *r8a66597 = the_controller;
  1233. unsigned long flags;
  1234. if (driver != r8a66597->driver || !driver->unbind)
  1235. return -EINVAL;
  1236. spin_lock_irqsave(&r8a66597->lock, flags);
  1237. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1238. r8a66597_usb_disconnect(r8a66597);
  1239. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1240. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1241. driver->unbind(&r8a66597->gadget);
  1242. init_controller(r8a66597);
  1243. disable_controller(r8a66597);
  1244. device_del(&r8a66597->gadget.dev);
  1245. r8a66597->driver = NULL;
  1246. return 0;
  1247. }
  1248. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1249. /*-------------------------------------------------------------------------*/
  1250. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1251. {
  1252. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1253. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1254. }
  1255. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1256. .get_frame = r8a66597_get_frame,
  1257. };
  1258. static int __exit r8a66597_remove(struct platform_device *pdev)
  1259. {
  1260. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1261. del_timer_sync(&r8a66597->timer);
  1262. iounmap((void *)r8a66597->reg);
  1263. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1264. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1265. #ifdef CONFIG_HAVE_CLK
  1266. if (r8a66597->pdata->on_chip) {
  1267. clk_disable(r8a66597->clk);
  1268. clk_put(r8a66597->clk);
  1269. }
  1270. #endif
  1271. kfree(r8a66597);
  1272. return 0;
  1273. }
  1274. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1275. {
  1276. }
  1277. static int __init r8a66597_probe(struct platform_device *pdev)
  1278. {
  1279. #ifdef CONFIG_HAVE_CLK
  1280. char clk_name[8];
  1281. #endif
  1282. struct resource *res, *ires;
  1283. int irq;
  1284. void __iomem *reg = NULL;
  1285. struct r8a66597 *r8a66597 = NULL;
  1286. int ret = 0;
  1287. int i;
  1288. unsigned long irq_trigger;
  1289. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1290. if (!res) {
  1291. ret = -ENODEV;
  1292. printk(KERN_ERR "platform_get_resource error.\n");
  1293. goto clean_up;
  1294. }
  1295. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1296. irq = ires->start;
  1297. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1298. if (irq < 0) {
  1299. ret = -ENODEV;
  1300. printk(KERN_ERR "platform_get_irq error.\n");
  1301. goto clean_up;
  1302. }
  1303. reg = ioremap(res->start, resource_size(res));
  1304. if (reg == NULL) {
  1305. ret = -ENOMEM;
  1306. printk(KERN_ERR "ioremap error.\n");
  1307. goto clean_up;
  1308. }
  1309. /* initialize ucd */
  1310. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1311. if (r8a66597 == NULL) {
  1312. printk(KERN_ERR "kzalloc error\n");
  1313. goto clean_up;
  1314. }
  1315. spin_lock_init(&r8a66597->lock);
  1316. dev_set_drvdata(&pdev->dev, r8a66597);
  1317. r8a66597->pdata = pdev->dev.platform_data;
  1318. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1319. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1320. device_initialize(&r8a66597->gadget.dev);
  1321. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1322. r8a66597->gadget.is_dualspeed = 1;
  1323. r8a66597->gadget.dev.parent = &pdev->dev;
  1324. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1325. r8a66597->gadget.dev.release = pdev->dev.release;
  1326. r8a66597->gadget.name = udc_name;
  1327. init_timer(&r8a66597->timer);
  1328. r8a66597->timer.function = r8a66597_timer;
  1329. r8a66597->timer.data = (unsigned long)r8a66597;
  1330. r8a66597->reg = (unsigned long)reg;
  1331. #ifdef CONFIG_HAVE_CLK
  1332. if (r8a66597->pdata->on_chip) {
  1333. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1334. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1335. if (IS_ERR(r8a66597->clk)) {
  1336. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1337. clk_name);
  1338. ret = PTR_ERR(r8a66597->clk);
  1339. goto clean_up;
  1340. }
  1341. clk_enable(r8a66597->clk);
  1342. }
  1343. #endif
  1344. disable_controller(r8a66597); /* make sure controller is disabled */
  1345. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1346. udc_name, r8a66597);
  1347. if (ret < 0) {
  1348. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1349. goto clean_up2;
  1350. }
  1351. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1352. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1353. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1354. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1355. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1356. if (i != 0) {
  1357. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1358. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1359. &r8a66597->gadget.ep_list);
  1360. }
  1361. ep->r8a66597 = r8a66597;
  1362. INIT_LIST_HEAD(&ep->queue);
  1363. ep->ep.name = r8a66597_ep_name[i];
  1364. ep->ep.ops = &r8a66597_ep_ops;
  1365. ep->ep.maxpacket = 512;
  1366. }
  1367. r8a66597->ep[0].ep.maxpacket = 64;
  1368. r8a66597->ep[0].pipenum = 0;
  1369. r8a66597->ep[0].fifoaddr = CFIFO;
  1370. r8a66597->ep[0].fifosel = CFIFOSEL;
  1371. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1372. r8a66597->ep[0].fifotrn = 0;
  1373. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1374. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1375. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1376. the_controller = r8a66597;
  1377. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1378. GFP_KERNEL);
  1379. if (r8a66597->ep0_req == NULL)
  1380. goto clean_up3;
  1381. r8a66597->ep0_req->complete = nop_completion;
  1382. init_controller(r8a66597);
  1383. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1384. return 0;
  1385. clean_up3:
  1386. free_irq(irq, r8a66597);
  1387. clean_up2:
  1388. #ifdef CONFIG_HAVE_CLK
  1389. if (r8a66597->pdata->on_chip) {
  1390. clk_disable(r8a66597->clk);
  1391. clk_put(r8a66597->clk);
  1392. }
  1393. #endif
  1394. clean_up:
  1395. if (r8a66597) {
  1396. if (r8a66597->ep0_req)
  1397. r8a66597_free_request(&r8a66597->ep[0].ep,
  1398. r8a66597->ep0_req);
  1399. kfree(r8a66597);
  1400. }
  1401. if (reg)
  1402. iounmap(reg);
  1403. return ret;
  1404. }
  1405. /*-------------------------------------------------------------------------*/
  1406. static struct platform_driver r8a66597_driver = {
  1407. .remove = __exit_p(r8a66597_remove),
  1408. .driver = {
  1409. .name = (char *) udc_name,
  1410. },
  1411. };
  1412. static int __init r8a66597_udc_init(void)
  1413. {
  1414. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1415. }
  1416. module_init(r8a66597_udc_init);
  1417. static void __exit r8a66597_udc_cleanup(void)
  1418. {
  1419. platform_driver_unregister(&r8a66597_driver);
  1420. }
  1421. module_exit(r8a66597_udc_cleanup);
  1422. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1423. MODULE_LICENSE("GPL");
  1424. MODULE_AUTHOR("Yoshihiro Shimoda");