main.c 32 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/ssb/ssb.h>
  14. #include <linux/ssb/ssb_regs.h>
  15. #include <linux/ssb/ssb_driver_gige.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/pci.h>
  18. #include <linux/mmc/sdio_func.h>
  19. #include <pcmcia/cs_types.h>
  20. #include <pcmcia/cs.h>
  21. #include <pcmcia/cistpl.h>
  22. #include <pcmcia/ds.h>
  23. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  24. MODULE_LICENSE("GPL");
  25. /* Temporary list of yet-to-be-attached buses */
  26. static LIST_HEAD(attach_queue);
  27. /* List if running buses */
  28. static LIST_HEAD(buses);
  29. /* Software ID counter */
  30. static unsigned int next_busnumber;
  31. /* buses_mutes locks the two buslists and the next_busnumber.
  32. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  33. static DEFINE_MUTEX(buses_mutex);
  34. /* There are differences in the codeflow, if the bus is
  35. * initialized from early boot, as various needed services
  36. * are not available early. This is a mechanism to delay
  37. * these initializations to after early boot has finished.
  38. * It's also used to avoid mutex locking, as that's not
  39. * available and needed early. */
  40. static bool ssb_is_early_boot = 1;
  41. static void ssb_buses_lock(void);
  42. static void ssb_buses_unlock(void);
  43. #ifdef CONFIG_SSB_PCIHOST
  44. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  45. {
  46. struct ssb_bus *bus;
  47. ssb_buses_lock();
  48. list_for_each_entry(bus, &buses, list) {
  49. if (bus->bustype == SSB_BUSTYPE_PCI &&
  50. bus->host_pci == pdev)
  51. goto found;
  52. }
  53. bus = NULL;
  54. found:
  55. ssb_buses_unlock();
  56. return bus;
  57. }
  58. #endif /* CONFIG_SSB_PCIHOST */
  59. #ifdef CONFIG_SSB_PCMCIAHOST
  60. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  61. {
  62. struct ssb_bus *bus;
  63. ssb_buses_lock();
  64. list_for_each_entry(bus, &buses, list) {
  65. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  66. bus->host_pcmcia == pdev)
  67. goto found;
  68. }
  69. bus = NULL;
  70. found:
  71. ssb_buses_unlock();
  72. return bus;
  73. }
  74. #endif /* CONFIG_SSB_PCMCIAHOST */
  75. #ifdef CONFIG_SSB_SDIOHOST
  76. struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
  77. {
  78. struct ssb_bus *bus;
  79. ssb_buses_lock();
  80. list_for_each_entry(bus, &buses, list) {
  81. if (bus->bustype == SSB_BUSTYPE_SDIO &&
  82. bus->host_sdio == func)
  83. goto found;
  84. }
  85. bus = NULL;
  86. found:
  87. ssb_buses_unlock();
  88. return bus;
  89. }
  90. #endif /* CONFIG_SSB_SDIOHOST */
  91. int ssb_for_each_bus_call(unsigned long data,
  92. int (*func)(struct ssb_bus *bus, unsigned long data))
  93. {
  94. struct ssb_bus *bus;
  95. int res;
  96. ssb_buses_lock();
  97. list_for_each_entry(bus, &buses, list) {
  98. res = func(bus, data);
  99. if (res >= 0) {
  100. ssb_buses_unlock();
  101. return res;
  102. }
  103. }
  104. ssb_buses_unlock();
  105. return -ENODEV;
  106. }
  107. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  108. {
  109. if (dev)
  110. get_device(dev->dev);
  111. return dev;
  112. }
  113. static void ssb_device_put(struct ssb_device *dev)
  114. {
  115. if (dev)
  116. put_device(dev->dev);
  117. }
  118. static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
  119. {
  120. if (drv)
  121. get_driver(&drv->drv);
  122. return drv;
  123. }
  124. static inline void ssb_driver_put(struct ssb_driver *drv)
  125. {
  126. if (drv)
  127. put_driver(&drv->drv);
  128. }
  129. static int ssb_device_resume(struct device *dev)
  130. {
  131. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  132. struct ssb_driver *ssb_drv;
  133. int err = 0;
  134. if (dev->driver) {
  135. ssb_drv = drv_to_ssb_drv(dev->driver);
  136. if (ssb_drv && ssb_drv->resume)
  137. err = ssb_drv->resume(ssb_dev);
  138. if (err)
  139. goto out;
  140. }
  141. out:
  142. return err;
  143. }
  144. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  145. {
  146. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  147. struct ssb_driver *ssb_drv;
  148. int err = 0;
  149. if (dev->driver) {
  150. ssb_drv = drv_to_ssb_drv(dev->driver);
  151. if (ssb_drv && ssb_drv->suspend)
  152. err = ssb_drv->suspend(ssb_dev, state);
  153. if (err)
  154. goto out;
  155. }
  156. out:
  157. return err;
  158. }
  159. int ssb_bus_resume(struct ssb_bus *bus)
  160. {
  161. int err;
  162. /* Reset HW state information in memory, so that HW is
  163. * completely reinitialized. */
  164. bus->mapped_device = NULL;
  165. #ifdef CONFIG_SSB_DRIVER_PCICORE
  166. bus->pcicore.setup_done = 0;
  167. #endif
  168. err = ssb_bus_powerup(bus, 0);
  169. if (err)
  170. return err;
  171. err = ssb_pcmcia_hardware_setup(bus);
  172. if (err) {
  173. ssb_bus_may_powerdown(bus);
  174. return err;
  175. }
  176. ssb_chipco_resume(&bus->chipco);
  177. ssb_bus_may_powerdown(bus);
  178. return 0;
  179. }
  180. EXPORT_SYMBOL(ssb_bus_resume);
  181. int ssb_bus_suspend(struct ssb_bus *bus)
  182. {
  183. ssb_chipco_suspend(&bus->chipco);
  184. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  185. return 0;
  186. }
  187. EXPORT_SYMBOL(ssb_bus_suspend);
  188. #ifdef CONFIG_SSB_SPROM
  189. /** ssb_devices_freeze - Freeze all devices on the bus.
  190. *
  191. * After freezing no device driver will be handling a device
  192. * on this bus anymore. ssb_devices_thaw() must be called after
  193. * a successful freeze to reactivate the devices.
  194. *
  195. * @bus: The bus.
  196. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  197. */
  198. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  199. {
  200. struct ssb_device *sdev;
  201. struct ssb_driver *sdrv;
  202. unsigned int i;
  203. memset(ctx, 0, sizeof(*ctx));
  204. ctx->bus = bus;
  205. SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  206. for (i = 0; i < bus->nr_devices; i++) {
  207. sdev = ssb_device_get(&bus->devices[i]);
  208. if (!sdev->dev || !sdev->dev->driver ||
  209. !device_is_registered(sdev->dev)) {
  210. ssb_device_put(sdev);
  211. continue;
  212. }
  213. sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
  214. if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
  215. ssb_device_put(sdev);
  216. continue;
  217. }
  218. sdrv->remove(sdev);
  219. ctx->device_frozen[i] = 1;
  220. }
  221. return 0;
  222. }
  223. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  224. *
  225. * This will re-attach the device drivers and re-init the devices.
  226. *
  227. * @ctx: The context structure from ssb_devices_freeze()
  228. */
  229. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  230. {
  231. struct ssb_bus *bus = ctx->bus;
  232. struct ssb_device *sdev;
  233. struct ssb_driver *sdrv;
  234. unsigned int i;
  235. int err, result = 0;
  236. for (i = 0; i < bus->nr_devices; i++) {
  237. if (!ctx->device_frozen[i])
  238. continue;
  239. sdev = &bus->devices[i];
  240. if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
  241. continue;
  242. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  243. if (SSB_WARN_ON(!sdrv || !sdrv->probe))
  244. continue;
  245. err = sdrv->probe(sdev, &sdev->id);
  246. if (err) {
  247. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  248. dev_name(sdev->dev));
  249. result = err;
  250. }
  251. ssb_driver_put(sdrv);
  252. ssb_device_put(sdev);
  253. }
  254. return result;
  255. }
  256. #endif /* CONFIG_SSB_SPROM */
  257. static void ssb_device_shutdown(struct device *dev)
  258. {
  259. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  260. struct ssb_driver *ssb_drv;
  261. if (!dev->driver)
  262. return;
  263. ssb_drv = drv_to_ssb_drv(dev->driver);
  264. if (ssb_drv && ssb_drv->shutdown)
  265. ssb_drv->shutdown(ssb_dev);
  266. }
  267. static int ssb_device_remove(struct device *dev)
  268. {
  269. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  270. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  271. if (ssb_drv && ssb_drv->remove)
  272. ssb_drv->remove(ssb_dev);
  273. ssb_device_put(ssb_dev);
  274. return 0;
  275. }
  276. static int ssb_device_probe(struct device *dev)
  277. {
  278. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  279. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  280. int err = 0;
  281. ssb_device_get(ssb_dev);
  282. if (ssb_drv && ssb_drv->probe)
  283. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  284. if (err)
  285. ssb_device_put(ssb_dev);
  286. return err;
  287. }
  288. static int ssb_match_devid(const struct ssb_device_id *tabid,
  289. const struct ssb_device_id *devid)
  290. {
  291. if ((tabid->vendor != devid->vendor) &&
  292. tabid->vendor != SSB_ANY_VENDOR)
  293. return 0;
  294. if ((tabid->coreid != devid->coreid) &&
  295. tabid->coreid != SSB_ANY_ID)
  296. return 0;
  297. if ((tabid->revision != devid->revision) &&
  298. tabid->revision != SSB_ANY_REV)
  299. return 0;
  300. return 1;
  301. }
  302. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  303. {
  304. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  305. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  306. const struct ssb_device_id *id;
  307. for (id = ssb_drv->id_table;
  308. id->vendor || id->coreid || id->revision;
  309. id++) {
  310. if (ssb_match_devid(id, &ssb_dev->id))
  311. return 1; /* found */
  312. }
  313. return 0;
  314. }
  315. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  316. {
  317. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  318. if (!dev)
  319. return -ENODEV;
  320. return add_uevent_var(env,
  321. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  322. ssb_dev->id.vendor, ssb_dev->id.coreid,
  323. ssb_dev->id.revision);
  324. }
  325. static struct bus_type ssb_bustype = {
  326. .name = "ssb",
  327. .match = ssb_bus_match,
  328. .probe = ssb_device_probe,
  329. .remove = ssb_device_remove,
  330. .shutdown = ssb_device_shutdown,
  331. .suspend = ssb_device_suspend,
  332. .resume = ssb_device_resume,
  333. .uevent = ssb_device_uevent,
  334. };
  335. static void ssb_buses_lock(void)
  336. {
  337. /* See the comment at the ssb_is_early_boot definition */
  338. if (!ssb_is_early_boot)
  339. mutex_lock(&buses_mutex);
  340. }
  341. static void ssb_buses_unlock(void)
  342. {
  343. /* See the comment at the ssb_is_early_boot definition */
  344. if (!ssb_is_early_boot)
  345. mutex_unlock(&buses_mutex);
  346. }
  347. static void ssb_devices_unregister(struct ssb_bus *bus)
  348. {
  349. struct ssb_device *sdev;
  350. int i;
  351. for (i = bus->nr_devices - 1; i >= 0; i--) {
  352. sdev = &(bus->devices[i]);
  353. if (sdev->dev)
  354. device_unregister(sdev->dev);
  355. }
  356. }
  357. void ssb_bus_unregister(struct ssb_bus *bus)
  358. {
  359. ssb_buses_lock();
  360. ssb_devices_unregister(bus);
  361. list_del(&bus->list);
  362. ssb_buses_unlock();
  363. ssb_pcmcia_exit(bus);
  364. ssb_pci_exit(bus);
  365. ssb_iounmap(bus);
  366. }
  367. EXPORT_SYMBOL(ssb_bus_unregister);
  368. static void ssb_release_dev(struct device *dev)
  369. {
  370. struct __ssb_dev_wrapper *devwrap;
  371. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  372. kfree(devwrap);
  373. }
  374. static int ssb_devices_register(struct ssb_bus *bus)
  375. {
  376. struct ssb_device *sdev;
  377. struct device *dev;
  378. struct __ssb_dev_wrapper *devwrap;
  379. int i, err = 0;
  380. int dev_idx = 0;
  381. for (i = 0; i < bus->nr_devices; i++) {
  382. sdev = &(bus->devices[i]);
  383. /* We don't register SSB-system devices to the kernel,
  384. * as the drivers for them are built into SSB. */
  385. switch (sdev->id.coreid) {
  386. case SSB_DEV_CHIPCOMMON:
  387. case SSB_DEV_PCI:
  388. case SSB_DEV_PCIE:
  389. case SSB_DEV_PCMCIA:
  390. case SSB_DEV_MIPS:
  391. case SSB_DEV_MIPS_3302:
  392. case SSB_DEV_EXTIF:
  393. continue;
  394. }
  395. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  396. if (!devwrap) {
  397. ssb_printk(KERN_ERR PFX
  398. "Could not allocate device\n");
  399. err = -ENOMEM;
  400. goto error;
  401. }
  402. dev = &devwrap->dev;
  403. devwrap->sdev = sdev;
  404. dev->release = ssb_release_dev;
  405. dev->bus = &ssb_bustype;
  406. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  407. switch (bus->bustype) {
  408. case SSB_BUSTYPE_PCI:
  409. #ifdef CONFIG_SSB_PCIHOST
  410. sdev->irq = bus->host_pci->irq;
  411. dev->parent = &bus->host_pci->dev;
  412. #endif
  413. break;
  414. case SSB_BUSTYPE_PCMCIA:
  415. #ifdef CONFIG_SSB_PCMCIAHOST
  416. sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
  417. dev->parent = &bus->host_pcmcia->dev;
  418. #endif
  419. break;
  420. case SSB_BUSTYPE_SDIO:
  421. #ifdef CONFIG_SSB_SDIOHOST
  422. dev->parent = &bus->host_sdio->dev;
  423. #endif
  424. break;
  425. case SSB_BUSTYPE_SSB:
  426. dev->dma_mask = &dev->coherent_dma_mask;
  427. break;
  428. }
  429. sdev->dev = dev;
  430. err = device_register(dev);
  431. if (err) {
  432. ssb_printk(KERN_ERR PFX
  433. "Could not register %s\n",
  434. dev_name(dev));
  435. /* Set dev to NULL to not unregister
  436. * dev on error unwinding. */
  437. sdev->dev = NULL;
  438. kfree(devwrap);
  439. goto error;
  440. }
  441. dev_idx++;
  442. }
  443. return 0;
  444. error:
  445. /* Unwind the already registered devices. */
  446. ssb_devices_unregister(bus);
  447. return err;
  448. }
  449. /* Needs ssb_buses_lock() */
  450. static int ssb_attach_queued_buses(void)
  451. {
  452. struct ssb_bus *bus, *n;
  453. int err = 0;
  454. int drop_them_all = 0;
  455. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  456. if (drop_them_all) {
  457. list_del(&bus->list);
  458. continue;
  459. }
  460. /* Can't init the PCIcore in ssb_bus_register(), as that
  461. * is too early in boot for embedded systems
  462. * (no udelay() available). So do it here in attach stage.
  463. */
  464. err = ssb_bus_powerup(bus, 0);
  465. if (err)
  466. goto error;
  467. ssb_pcicore_init(&bus->pcicore);
  468. ssb_bus_may_powerdown(bus);
  469. err = ssb_devices_register(bus);
  470. error:
  471. if (err) {
  472. drop_them_all = 1;
  473. list_del(&bus->list);
  474. continue;
  475. }
  476. list_move_tail(&bus->list, &buses);
  477. }
  478. return err;
  479. }
  480. static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
  481. {
  482. struct ssb_bus *bus = dev->bus;
  483. offset += dev->core_index * SSB_CORE_SIZE;
  484. return readb(bus->mmio + offset);
  485. }
  486. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  487. {
  488. struct ssb_bus *bus = dev->bus;
  489. offset += dev->core_index * SSB_CORE_SIZE;
  490. return readw(bus->mmio + offset);
  491. }
  492. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  493. {
  494. struct ssb_bus *bus = dev->bus;
  495. offset += dev->core_index * SSB_CORE_SIZE;
  496. return readl(bus->mmio + offset);
  497. }
  498. #ifdef CONFIG_SSB_BLOCKIO
  499. static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
  500. size_t count, u16 offset, u8 reg_width)
  501. {
  502. struct ssb_bus *bus = dev->bus;
  503. void __iomem *addr;
  504. offset += dev->core_index * SSB_CORE_SIZE;
  505. addr = bus->mmio + offset;
  506. switch (reg_width) {
  507. case sizeof(u8): {
  508. u8 *buf = buffer;
  509. while (count) {
  510. *buf = __raw_readb(addr);
  511. buf++;
  512. count--;
  513. }
  514. break;
  515. }
  516. case sizeof(u16): {
  517. __le16 *buf = buffer;
  518. SSB_WARN_ON(count & 1);
  519. while (count) {
  520. *buf = (__force __le16)__raw_readw(addr);
  521. buf++;
  522. count -= 2;
  523. }
  524. break;
  525. }
  526. case sizeof(u32): {
  527. __le32 *buf = buffer;
  528. SSB_WARN_ON(count & 3);
  529. while (count) {
  530. *buf = (__force __le32)__raw_readl(addr);
  531. buf++;
  532. count -= 4;
  533. }
  534. break;
  535. }
  536. default:
  537. SSB_WARN_ON(1);
  538. }
  539. }
  540. #endif /* CONFIG_SSB_BLOCKIO */
  541. static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
  542. {
  543. struct ssb_bus *bus = dev->bus;
  544. offset += dev->core_index * SSB_CORE_SIZE;
  545. writeb(value, bus->mmio + offset);
  546. }
  547. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  548. {
  549. struct ssb_bus *bus = dev->bus;
  550. offset += dev->core_index * SSB_CORE_SIZE;
  551. writew(value, bus->mmio + offset);
  552. }
  553. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  554. {
  555. struct ssb_bus *bus = dev->bus;
  556. offset += dev->core_index * SSB_CORE_SIZE;
  557. writel(value, bus->mmio + offset);
  558. }
  559. #ifdef CONFIG_SSB_BLOCKIO
  560. static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
  561. size_t count, u16 offset, u8 reg_width)
  562. {
  563. struct ssb_bus *bus = dev->bus;
  564. void __iomem *addr;
  565. offset += dev->core_index * SSB_CORE_SIZE;
  566. addr = bus->mmio + offset;
  567. switch (reg_width) {
  568. case sizeof(u8): {
  569. const u8 *buf = buffer;
  570. while (count) {
  571. __raw_writeb(*buf, addr);
  572. buf++;
  573. count--;
  574. }
  575. break;
  576. }
  577. case sizeof(u16): {
  578. const __le16 *buf = buffer;
  579. SSB_WARN_ON(count & 1);
  580. while (count) {
  581. __raw_writew((__force u16)(*buf), addr);
  582. buf++;
  583. count -= 2;
  584. }
  585. break;
  586. }
  587. case sizeof(u32): {
  588. const __le32 *buf = buffer;
  589. SSB_WARN_ON(count & 3);
  590. while (count) {
  591. __raw_writel((__force u32)(*buf), addr);
  592. buf++;
  593. count -= 4;
  594. }
  595. break;
  596. }
  597. default:
  598. SSB_WARN_ON(1);
  599. }
  600. }
  601. #endif /* CONFIG_SSB_BLOCKIO */
  602. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  603. static const struct ssb_bus_ops ssb_ssb_ops = {
  604. .read8 = ssb_ssb_read8,
  605. .read16 = ssb_ssb_read16,
  606. .read32 = ssb_ssb_read32,
  607. .write8 = ssb_ssb_write8,
  608. .write16 = ssb_ssb_write16,
  609. .write32 = ssb_ssb_write32,
  610. #ifdef CONFIG_SSB_BLOCKIO
  611. .block_read = ssb_ssb_block_read,
  612. .block_write = ssb_ssb_block_write,
  613. #endif
  614. };
  615. static int ssb_fetch_invariants(struct ssb_bus *bus,
  616. ssb_invariants_func_t get_invariants)
  617. {
  618. struct ssb_init_invariants iv;
  619. int err;
  620. memset(&iv, 0, sizeof(iv));
  621. err = get_invariants(bus, &iv);
  622. if (err)
  623. goto out;
  624. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  625. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  626. bus->has_cardbus_slot = iv.has_cardbus_slot;
  627. out:
  628. return err;
  629. }
  630. static int ssb_bus_register(struct ssb_bus *bus,
  631. ssb_invariants_func_t get_invariants,
  632. unsigned long baseaddr)
  633. {
  634. int err;
  635. spin_lock_init(&bus->bar_lock);
  636. INIT_LIST_HEAD(&bus->list);
  637. #ifdef CONFIG_SSB_EMBEDDED
  638. spin_lock_init(&bus->gpio_lock);
  639. #endif
  640. /* Powerup the bus */
  641. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  642. if (err)
  643. goto out;
  644. /* Init SDIO-host device (if any), before the scan */
  645. err = ssb_sdio_init(bus);
  646. if (err)
  647. goto err_disable_xtal;
  648. ssb_buses_lock();
  649. bus->busnumber = next_busnumber;
  650. /* Scan for devices (cores) */
  651. err = ssb_bus_scan(bus, baseaddr);
  652. if (err)
  653. goto err_sdio_exit;
  654. /* Init PCI-host device (if any) */
  655. err = ssb_pci_init(bus);
  656. if (err)
  657. goto err_unmap;
  658. /* Init PCMCIA-host device (if any) */
  659. err = ssb_pcmcia_init(bus);
  660. if (err)
  661. goto err_pci_exit;
  662. /* Initialize basic system devices (if available) */
  663. err = ssb_bus_powerup(bus, 0);
  664. if (err)
  665. goto err_pcmcia_exit;
  666. ssb_chipcommon_init(&bus->chipco);
  667. ssb_mipscore_init(&bus->mipscore);
  668. err = ssb_fetch_invariants(bus, get_invariants);
  669. if (err) {
  670. ssb_bus_may_powerdown(bus);
  671. goto err_pcmcia_exit;
  672. }
  673. ssb_bus_may_powerdown(bus);
  674. /* Queue it for attach.
  675. * See the comment at the ssb_is_early_boot definition. */
  676. list_add_tail(&bus->list, &attach_queue);
  677. if (!ssb_is_early_boot) {
  678. /* This is not early boot, so we must attach the bus now */
  679. err = ssb_attach_queued_buses();
  680. if (err)
  681. goto err_dequeue;
  682. }
  683. next_busnumber++;
  684. ssb_buses_unlock();
  685. out:
  686. return err;
  687. err_dequeue:
  688. list_del(&bus->list);
  689. err_pcmcia_exit:
  690. ssb_pcmcia_exit(bus);
  691. err_pci_exit:
  692. ssb_pci_exit(bus);
  693. err_unmap:
  694. ssb_iounmap(bus);
  695. err_sdio_exit:
  696. ssb_sdio_exit(bus);
  697. err_disable_xtal:
  698. ssb_buses_unlock();
  699. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  700. return err;
  701. }
  702. #ifdef CONFIG_SSB_PCIHOST
  703. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  704. struct pci_dev *host_pci)
  705. {
  706. int err;
  707. bus->bustype = SSB_BUSTYPE_PCI;
  708. bus->host_pci = host_pci;
  709. bus->ops = &ssb_pci_ops;
  710. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  711. if (!err) {
  712. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  713. "PCI device %s\n", dev_name(&host_pci->dev));
  714. }
  715. return err;
  716. }
  717. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  718. #endif /* CONFIG_SSB_PCIHOST */
  719. #ifdef CONFIG_SSB_PCMCIAHOST
  720. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  721. struct pcmcia_device *pcmcia_dev,
  722. unsigned long baseaddr)
  723. {
  724. int err;
  725. bus->bustype = SSB_BUSTYPE_PCMCIA;
  726. bus->host_pcmcia = pcmcia_dev;
  727. bus->ops = &ssb_pcmcia_ops;
  728. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  729. if (!err) {
  730. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  731. "PCMCIA device %s\n", pcmcia_dev->devname);
  732. }
  733. return err;
  734. }
  735. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  736. #endif /* CONFIG_SSB_PCMCIAHOST */
  737. #ifdef CONFIG_SSB_SDIOHOST
  738. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  739. unsigned int quirks)
  740. {
  741. int err;
  742. bus->bustype = SSB_BUSTYPE_SDIO;
  743. bus->host_sdio = func;
  744. bus->ops = &ssb_sdio_ops;
  745. bus->quirks = quirks;
  746. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  747. if (!err) {
  748. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  749. "SDIO device %s\n", sdio_func_id(func));
  750. }
  751. return err;
  752. }
  753. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  754. #endif /* CONFIG_SSB_PCMCIAHOST */
  755. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  756. unsigned long baseaddr,
  757. ssb_invariants_func_t get_invariants)
  758. {
  759. int err;
  760. bus->bustype = SSB_BUSTYPE_SSB;
  761. bus->ops = &ssb_ssb_ops;
  762. err = ssb_bus_register(bus, get_invariants, baseaddr);
  763. if (!err) {
  764. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  765. "address 0x%08lX\n", baseaddr);
  766. }
  767. return err;
  768. }
  769. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  770. {
  771. drv->drv.name = drv->name;
  772. drv->drv.bus = &ssb_bustype;
  773. drv->drv.owner = owner;
  774. return driver_register(&drv->drv);
  775. }
  776. EXPORT_SYMBOL(__ssb_driver_register);
  777. void ssb_driver_unregister(struct ssb_driver *drv)
  778. {
  779. driver_unregister(&drv->drv);
  780. }
  781. EXPORT_SYMBOL(ssb_driver_unregister);
  782. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  783. {
  784. struct ssb_bus *bus = dev->bus;
  785. struct ssb_device *ent;
  786. int i;
  787. for (i = 0; i < bus->nr_devices; i++) {
  788. ent = &(bus->devices[i]);
  789. if (ent->id.vendor != dev->id.vendor)
  790. continue;
  791. if (ent->id.coreid != dev->id.coreid)
  792. continue;
  793. ent->devtypedata = data;
  794. }
  795. }
  796. EXPORT_SYMBOL(ssb_set_devtypedata);
  797. static u32 clkfactor_f6_resolve(u32 v)
  798. {
  799. /* map the magic values */
  800. switch (v) {
  801. case SSB_CHIPCO_CLK_F6_2:
  802. return 2;
  803. case SSB_CHIPCO_CLK_F6_3:
  804. return 3;
  805. case SSB_CHIPCO_CLK_F6_4:
  806. return 4;
  807. case SSB_CHIPCO_CLK_F6_5:
  808. return 5;
  809. case SSB_CHIPCO_CLK_F6_6:
  810. return 6;
  811. case SSB_CHIPCO_CLK_F6_7:
  812. return 7;
  813. }
  814. return 0;
  815. }
  816. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  817. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  818. {
  819. u32 n1, n2, clock, m1, m2, m3, mc;
  820. n1 = (n & SSB_CHIPCO_CLK_N1);
  821. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  822. switch (plltype) {
  823. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  824. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  825. return SSB_CHIPCO_CLK_T6_M0;
  826. return SSB_CHIPCO_CLK_T6_M1;
  827. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  828. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  829. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  830. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  831. n1 = clkfactor_f6_resolve(n1);
  832. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  833. break;
  834. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  835. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  836. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  837. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  838. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  839. break;
  840. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  841. return 100000000;
  842. default:
  843. SSB_WARN_ON(1);
  844. }
  845. switch (plltype) {
  846. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  847. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  848. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  849. break;
  850. default:
  851. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  852. }
  853. if (!clock)
  854. return 0;
  855. m1 = (m & SSB_CHIPCO_CLK_M1);
  856. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  857. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  858. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  859. switch (plltype) {
  860. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  861. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  862. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  863. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  864. m1 = clkfactor_f6_resolve(m1);
  865. if ((plltype == SSB_PLLTYPE_1) ||
  866. (plltype == SSB_PLLTYPE_3))
  867. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  868. else
  869. m2 = clkfactor_f6_resolve(m2);
  870. m3 = clkfactor_f6_resolve(m3);
  871. switch (mc) {
  872. case SSB_CHIPCO_CLK_MC_BYPASS:
  873. return clock;
  874. case SSB_CHIPCO_CLK_MC_M1:
  875. return (clock / m1);
  876. case SSB_CHIPCO_CLK_MC_M1M2:
  877. return (clock / (m1 * m2));
  878. case SSB_CHIPCO_CLK_MC_M1M2M3:
  879. return (clock / (m1 * m2 * m3));
  880. case SSB_CHIPCO_CLK_MC_M1M3:
  881. return (clock / (m1 * m3));
  882. }
  883. return 0;
  884. case SSB_PLLTYPE_2:
  885. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  886. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  887. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  888. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  889. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  890. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  891. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  892. clock /= m1;
  893. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  894. clock /= m2;
  895. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  896. clock /= m3;
  897. return clock;
  898. default:
  899. SSB_WARN_ON(1);
  900. }
  901. return 0;
  902. }
  903. /* Get the current speed the backplane is running at */
  904. u32 ssb_clockspeed(struct ssb_bus *bus)
  905. {
  906. u32 rate;
  907. u32 plltype;
  908. u32 clkctl_n, clkctl_m;
  909. if (ssb_extif_available(&bus->extif))
  910. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  911. &clkctl_n, &clkctl_m);
  912. else if (bus->chipco.dev)
  913. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  914. &clkctl_n, &clkctl_m);
  915. else
  916. return 0;
  917. if (bus->chip_id == 0x5365) {
  918. rate = 100000000;
  919. } else {
  920. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  921. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  922. rate /= 2;
  923. }
  924. return rate;
  925. }
  926. EXPORT_SYMBOL(ssb_clockspeed);
  927. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  928. {
  929. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  930. /* The REJECT bit changed position in TMSLOW between
  931. * Backplane revisions. */
  932. switch (rev) {
  933. case SSB_IDLOW_SSBREV_22:
  934. return SSB_TMSLOW_REJECT_22;
  935. case SSB_IDLOW_SSBREV_23:
  936. return SSB_TMSLOW_REJECT_23;
  937. case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
  938. case SSB_IDLOW_SSBREV_25: /* same here */
  939. case SSB_IDLOW_SSBREV_26: /* same here */
  940. case SSB_IDLOW_SSBREV_27: /* same here */
  941. return SSB_TMSLOW_REJECT_23; /* this is a guess */
  942. default:
  943. printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  944. WARN_ON(1);
  945. }
  946. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  947. }
  948. int ssb_device_is_enabled(struct ssb_device *dev)
  949. {
  950. u32 val;
  951. u32 reject;
  952. reject = ssb_tmslow_reject_bitmask(dev);
  953. val = ssb_read32(dev, SSB_TMSLOW);
  954. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  955. return (val == SSB_TMSLOW_CLOCK);
  956. }
  957. EXPORT_SYMBOL(ssb_device_is_enabled);
  958. static void ssb_flush_tmslow(struct ssb_device *dev)
  959. {
  960. /* Make _really_ sure the device has finished the TMSLOW
  961. * register write transaction, as we risk running into
  962. * a machine check exception otherwise.
  963. * Do this by reading the register back to commit the
  964. * PCI write and delay an additional usec for the device
  965. * to react to the change. */
  966. ssb_read32(dev, SSB_TMSLOW);
  967. udelay(1);
  968. }
  969. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  970. {
  971. u32 val;
  972. ssb_device_disable(dev, core_specific_flags);
  973. ssb_write32(dev, SSB_TMSLOW,
  974. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  975. SSB_TMSLOW_FGC | core_specific_flags);
  976. ssb_flush_tmslow(dev);
  977. /* Clear SERR if set. This is a hw bug workaround. */
  978. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  979. ssb_write32(dev, SSB_TMSHIGH, 0);
  980. val = ssb_read32(dev, SSB_IMSTATE);
  981. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  982. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  983. ssb_write32(dev, SSB_IMSTATE, val);
  984. }
  985. ssb_write32(dev, SSB_TMSLOW,
  986. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  987. core_specific_flags);
  988. ssb_flush_tmslow(dev);
  989. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  990. core_specific_flags);
  991. ssb_flush_tmslow(dev);
  992. }
  993. EXPORT_SYMBOL(ssb_device_enable);
  994. /* Wait for a bit in a register to get set or unset.
  995. * timeout is in units of ten-microseconds */
  996. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  997. int timeout, int set)
  998. {
  999. int i;
  1000. u32 val;
  1001. for (i = 0; i < timeout; i++) {
  1002. val = ssb_read32(dev, reg);
  1003. if (set) {
  1004. if (val & bitmask)
  1005. return 0;
  1006. } else {
  1007. if (!(val & bitmask))
  1008. return 0;
  1009. }
  1010. udelay(10);
  1011. }
  1012. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  1013. "register %04X to %s.\n",
  1014. bitmask, reg, (set ? "set" : "clear"));
  1015. return -ETIMEDOUT;
  1016. }
  1017. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  1018. {
  1019. u32 reject;
  1020. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  1021. return;
  1022. reject = ssb_tmslow_reject_bitmask(dev);
  1023. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  1024. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  1025. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  1026. ssb_write32(dev, SSB_TMSLOW,
  1027. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  1028. reject | SSB_TMSLOW_RESET |
  1029. core_specific_flags);
  1030. ssb_flush_tmslow(dev);
  1031. ssb_write32(dev, SSB_TMSLOW,
  1032. reject | SSB_TMSLOW_RESET |
  1033. core_specific_flags);
  1034. ssb_flush_tmslow(dev);
  1035. }
  1036. EXPORT_SYMBOL(ssb_device_disable);
  1037. u32 ssb_dma_translation(struct ssb_device *dev)
  1038. {
  1039. switch (dev->bus->bustype) {
  1040. case SSB_BUSTYPE_SSB:
  1041. return 0;
  1042. case SSB_BUSTYPE_PCI:
  1043. return SSB_PCI_DMA;
  1044. default:
  1045. __ssb_dma_not_implemented(dev);
  1046. }
  1047. return 0;
  1048. }
  1049. EXPORT_SYMBOL(ssb_dma_translation);
  1050. int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
  1051. {
  1052. #ifdef CONFIG_SSB_PCIHOST
  1053. int err;
  1054. #endif
  1055. switch (dev->bus->bustype) {
  1056. case SSB_BUSTYPE_PCI:
  1057. #ifdef CONFIG_SSB_PCIHOST
  1058. err = pci_set_dma_mask(dev->bus->host_pci, mask);
  1059. if (err)
  1060. return err;
  1061. err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
  1062. return err;
  1063. #endif
  1064. case SSB_BUSTYPE_SSB:
  1065. return dma_set_mask(dev->dev, mask);
  1066. default:
  1067. __ssb_dma_not_implemented(dev);
  1068. }
  1069. return -ENOSYS;
  1070. }
  1071. EXPORT_SYMBOL(ssb_dma_set_mask);
  1072. void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
  1073. dma_addr_t *dma_handle, gfp_t gfp_flags)
  1074. {
  1075. switch (dev->bus->bustype) {
  1076. case SSB_BUSTYPE_PCI:
  1077. #ifdef CONFIG_SSB_PCIHOST
  1078. if (gfp_flags & GFP_DMA) {
  1079. /* Workaround: The PCI API does not support passing
  1080. * a GFP flag. */
  1081. return dma_alloc_coherent(&dev->bus->host_pci->dev,
  1082. size, dma_handle, gfp_flags);
  1083. }
  1084. return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
  1085. #endif
  1086. case SSB_BUSTYPE_SSB:
  1087. return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
  1088. default:
  1089. __ssb_dma_not_implemented(dev);
  1090. }
  1091. return NULL;
  1092. }
  1093. EXPORT_SYMBOL(ssb_dma_alloc_consistent);
  1094. void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
  1095. void *vaddr, dma_addr_t dma_handle,
  1096. gfp_t gfp_flags)
  1097. {
  1098. switch (dev->bus->bustype) {
  1099. case SSB_BUSTYPE_PCI:
  1100. #ifdef CONFIG_SSB_PCIHOST
  1101. if (gfp_flags & GFP_DMA) {
  1102. /* Workaround: The PCI API does not support passing
  1103. * a GFP flag. */
  1104. dma_free_coherent(&dev->bus->host_pci->dev,
  1105. size, vaddr, dma_handle);
  1106. return;
  1107. }
  1108. pci_free_consistent(dev->bus->host_pci, size,
  1109. vaddr, dma_handle);
  1110. return;
  1111. #endif
  1112. case SSB_BUSTYPE_SSB:
  1113. dma_free_coherent(dev->dev, size, vaddr, dma_handle);
  1114. return;
  1115. default:
  1116. __ssb_dma_not_implemented(dev);
  1117. }
  1118. }
  1119. EXPORT_SYMBOL(ssb_dma_free_consistent);
  1120. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  1121. {
  1122. struct ssb_chipcommon *cc;
  1123. int err = 0;
  1124. /* On buses where more than one core may be working
  1125. * at a time, we must not powerdown stuff if there are
  1126. * still cores that may want to run. */
  1127. if (bus->bustype == SSB_BUSTYPE_SSB)
  1128. goto out;
  1129. cc = &bus->chipco;
  1130. if (!cc->dev)
  1131. goto out;
  1132. if (cc->dev->id.revision < 5)
  1133. goto out;
  1134. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1135. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1136. if (err)
  1137. goto error;
  1138. out:
  1139. #ifdef CONFIG_SSB_DEBUG
  1140. bus->powered_up = 0;
  1141. #endif
  1142. return err;
  1143. error:
  1144. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  1145. goto out;
  1146. }
  1147. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1148. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1149. {
  1150. struct ssb_chipcommon *cc;
  1151. int err;
  1152. enum ssb_clkmode mode;
  1153. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1154. if (err)
  1155. goto error;
  1156. cc = &bus->chipco;
  1157. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1158. ssb_chipco_set_clockmode(cc, mode);
  1159. #ifdef CONFIG_SSB_DEBUG
  1160. bus->powered_up = 1;
  1161. #endif
  1162. return 0;
  1163. error:
  1164. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  1165. return err;
  1166. }
  1167. EXPORT_SYMBOL(ssb_bus_powerup);
  1168. u32 ssb_admatch_base(u32 adm)
  1169. {
  1170. u32 base = 0;
  1171. switch (adm & SSB_ADM_TYPE) {
  1172. case SSB_ADM_TYPE0:
  1173. base = (adm & SSB_ADM_BASE0);
  1174. break;
  1175. case SSB_ADM_TYPE1:
  1176. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1177. base = (adm & SSB_ADM_BASE1);
  1178. break;
  1179. case SSB_ADM_TYPE2:
  1180. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1181. base = (adm & SSB_ADM_BASE2);
  1182. break;
  1183. default:
  1184. SSB_WARN_ON(1);
  1185. }
  1186. return base;
  1187. }
  1188. EXPORT_SYMBOL(ssb_admatch_base);
  1189. u32 ssb_admatch_size(u32 adm)
  1190. {
  1191. u32 size = 0;
  1192. switch (adm & SSB_ADM_TYPE) {
  1193. case SSB_ADM_TYPE0:
  1194. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1195. break;
  1196. case SSB_ADM_TYPE1:
  1197. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1198. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1199. break;
  1200. case SSB_ADM_TYPE2:
  1201. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1202. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1203. break;
  1204. default:
  1205. SSB_WARN_ON(1);
  1206. }
  1207. size = (1 << (size + 1));
  1208. return size;
  1209. }
  1210. EXPORT_SYMBOL(ssb_admatch_size);
  1211. static int __init ssb_modinit(void)
  1212. {
  1213. int err;
  1214. /* See the comment at the ssb_is_early_boot definition */
  1215. ssb_is_early_boot = 0;
  1216. err = bus_register(&ssb_bustype);
  1217. if (err)
  1218. return err;
  1219. /* Maybe we already registered some buses at early boot.
  1220. * Check for this and attach them
  1221. */
  1222. ssb_buses_lock();
  1223. err = ssb_attach_queued_buses();
  1224. ssb_buses_unlock();
  1225. if (err) {
  1226. bus_unregister(&ssb_bustype);
  1227. goto out;
  1228. }
  1229. err = b43_pci_ssb_bridge_init();
  1230. if (err) {
  1231. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  1232. "initialization failed\n");
  1233. /* don't fail SSB init because of this */
  1234. err = 0;
  1235. }
  1236. err = ssb_gige_init();
  1237. if (err) {
  1238. ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
  1239. "driver initialization failed\n");
  1240. /* don't fail SSB init because of this */
  1241. err = 0;
  1242. }
  1243. out:
  1244. return err;
  1245. }
  1246. /* ssb must be initialized after PCI but before the ssb drivers.
  1247. * That means we must use some initcall between subsys_initcall
  1248. * and device_initcall. */
  1249. fs_initcall(ssb_modinit);
  1250. static void __exit ssb_modexit(void)
  1251. {
  1252. ssb_gige_exit();
  1253. b43_pci_ssb_bridge_exit();
  1254. bus_unregister(&ssb_bustype);
  1255. }
  1256. module_exit(ssb_modexit)