qeth_core_main.c 129 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include "qeth_core.h"
  24. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  25. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  26. /* N P A M L V H */
  27. [QETH_DBF_SETUP] = {"qeth_setup",
  28. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  29. [QETH_DBF_QERR] = {"qeth_qerr",
  30. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_TRACE] = {"qeth_trace",
  32. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_SENSE] = {"qeth_sense",
  36. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  37. [QETH_DBF_MISC] = {"qeth_misc",
  38. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_CTRL] = {"qeth_control",
  40. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  41. };
  42. EXPORT_SYMBOL_GPL(qeth_dbf);
  43. struct qeth_card_list_struct qeth_core_card_list;
  44. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  45. struct kmem_cache *qeth_core_header_cache;
  46. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  47. static struct device *qeth_core_root_dev;
  48. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  49. static struct lock_class_key qdio_out_skb_queue_key;
  50. static void qeth_send_control_data_cb(struct qeth_channel *,
  51. struct qeth_cmd_buffer *);
  52. static int qeth_issue_next_read(struct qeth_card *);
  53. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  54. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  55. static void qeth_free_buffer_pool(struct qeth_card *);
  56. static int qeth_qdio_establish(struct qeth_card *);
  57. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  58. struct qdio_buffer *buffer, int is_tso,
  59. int *next_element_to_fill)
  60. {
  61. struct skb_frag_struct *frag;
  62. int fragno;
  63. unsigned long addr;
  64. int element, cnt, dlen;
  65. fragno = skb_shinfo(skb)->nr_frags;
  66. element = *next_element_to_fill;
  67. dlen = 0;
  68. if (is_tso)
  69. buffer->element[element].flags =
  70. SBAL_FLAGS_MIDDLE_FRAG;
  71. else
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_FIRST_FRAG;
  74. dlen = skb->len - skb->data_len;
  75. if (dlen) {
  76. buffer->element[element].addr = skb->data;
  77. buffer->element[element].length = dlen;
  78. element++;
  79. }
  80. for (cnt = 0; cnt < fragno; cnt++) {
  81. frag = &skb_shinfo(skb)->frags[cnt];
  82. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  83. frag->page_offset;
  84. buffer->element[element].addr = (char *)addr;
  85. buffer->element[element].length = frag->size;
  86. if (cnt < (fragno - 1))
  87. buffer->element[element].flags =
  88. SBAL_FLAGS_MIDDLE_FRAG;
  89. else
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_LAST_FRAG;
  92. element++;
  93. }
  94. *next_element_to_fill = element;
  95. }
  96. static inline const char *qeth_get_cardname(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSAE:
  101. return " Guest LAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return " Guest LAN Hiper";
  104. default:
  105. return " unknown";
  106. }
  107. } else {
  108. switch (card->info.type) {
  109. case QETH_CARD_TYPE_OSAE:
  110. return " OSD Express";
  111. case QETH_CARD_TYPE_IQD:
  112. return " HiperSockets";
  113. case QETH_CARD_TYPE_OSN:
  114. return " OSN QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSAE:
  127. return "GuestLAN QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "GuestLAN Hiper";
  130. default:
  131. return "unknown";
  132. }
  133. } else {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSAE:
  136. switch (card->info.link_type) {
  137. case QETH_LINK_TYPE_FAST_ETH:
  138. return "OSD_100";
  139. case QETH_LINK_TYPE_HSTR:
  140. return "HSTR";
  141. case QETH_LINK_TYPE_GBIT_ETH:
  142. return "OSD_1000";
  143. case QETH_LINK_TYPE_10GBIT_ETH:
  144. return "OSD_10GIG";
  145. case QETH_LINK_TYPE_LANE_ETH100:
  146. return "OSD_FE_LANE";
  147. case QETH_LINK_TYPE_LANE_TR:
  148. return "OSD_TR_LANE";
  149. case QETH_LINK_TYPE_LANE_ETH1000:
  150. return "OSD_GbE_LANE";
  151. case QETH_LINK_TYPE_LANE:
  152. return "OSD_ATM_LANE";
  153. default:
  154. return "OSD_Express";
  155. }
  156. case QETH_CARD_TYPE_IQD:
  157. return "HiperSockets";
  158. case QETH_CARD_TYPE_OSN:
  159. return "OSN";
  160. default:
  161. return "unknown";
  162. }
  163. }
  164. return "n/a";
  165. }
  166. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  167. int clear_start_mask)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&card->thread_mask_lock, flags);
  171. card->thread_allowed_mask = threads;
  172. if (clear_start_mask)
  173. card->thread_start_mask &= threads;
  174. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  175. wake_up(&card->wait_q);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  178. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  179. {
  180. unsigned long flags;
  181. int rc = 0;
  182. spin_lock_irqsave(&card->thread_mask_lock, flags);
  183. rc = (card->thread_running_mask & threads);
  184. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  185. return rc;
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_threads_running);
  188. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  189. {
  190. return wait_event_interruptible(card->wait_q,
  191. qeth_threads_running(card, threads) == 0);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  194. void qeth_clear_working_pool_list(struct qeth_card *card)
  195. {
  196. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  197. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  198. list_for_each_entry_safe(pool_entry, tmp,
  199. &card->qdio.in_buf_pool.entry_list, list){
  200. list_del(&pool_entry->list);
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  204. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  205. {
  206. struct qeth_buffer_pool_entry *pool_entry;
  207. void *ptr;
  208. int i, j;
  209. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  210. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  211. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  212. if (!pool_entry) {
  213. qeth_free_buffer_pool(card);
  214. return -ENOMEM;
  215. }
  216. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  217. ptr = (void *) __get_free_page(GFP_KERNEL);
  218. if (!ptr) {
  219. while (j > 0)
  220. free_page((unsigned long)
  221. pool_entry->elements[--j]);
  222. kfree(pool_entry);
  223. qeth_free_buffer_pool(card);
  224. return -ENOMEM;
  225. }
  226. pool_entry->elements[j] = ptr;
  227. }
  228. list_add(&pool_entry->init_list,
  229. &card->qdio.init_pool.entry_list);
  230. }
  231. return 0;
  232. }
  233. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  234. {
  235. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  236. if ((card->state != CARD_STATE_DOWN) &&
  237. (card->state != CARD_STATE_RECOVER))
  238. return -EPERM;
  239. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  240. qeth_clear_working_pool_list(card);
  241. qeth_free_buffer_pool(card);
  242. card->qdio.in_buf_pool.buf_count = bufcnt;
  243. card->qdio.init_pool.buf_count = bufcnt;
  244. return qeth_alloc_buffer_pool(card);
  245. }
  246. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  247. static int qeth_issue_next_read(struct qeth_card *card)
  248. {
  249. int rc;
  250. struct qeth_cmd_buffer *iob;
  251. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  252. if (card->read.state != CH_STATE_UP)
  253. return -EIO;
  254. iob = qeth_get_buffer(&card->read);
  255. if (!iob) {
  256. dev_warn(&card->gdev->dev, "The qeth device driver "
  257. "failed to recover an error on the device\n");
  258. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  259. "available\n", dev_name(&card->gdev->dev));
  260. return -ENOMEM;
  261. }
  262. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  263. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  264. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  265. (addr_t) iob, 0, 0);
  266. if (rc) {
  267. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  268. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  269. atomic_set(&card->read.irq_pending, 0);
  270. qeth_schedule_recovery(card);
  271. wake_up(&card->wait_q);
  272. }
  273. return rc;
  274. }
  275. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  276. {
  277. struct qeth_reply *reply;
  278. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  279. if (reply) {
  280. atomic_set(&reply->refcnt, 1);
  281. atomic_set(&reply->received, 0);
  282. reply->card = card;
  283. };
  284. return reply;
  285. }
  286. static void qeth_get_reply(struct qeth_reply *reply)
  287. {
  288. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  289. atomic_inc(&reply->refcnt);
  290. }
  291. static void qeth_put_reply(struct qeth_reply *reply)
  292. {
  293. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  294. if (atomic_dec_and_test(&reply->refcnt))
  295. kfree(reply);
  296. }
  297. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  298. struct qeth_card *card)
  299. {
  300. char *ipa_name;
  301. int com = cmd->hdr.command;
  302. ipa_name = qeth_get_ipa_cmd_name(com);
  303. if (rc)
  304. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  305. ipa_name, com, QETH_CARD_IFNAME(card),
  306. rc, qeth_get_ipa_msg(rc));
  307. else
  308. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  309. ipa_name, com, QETH_CARD_IFNAME(card));
  310. }
  311. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  312. struct qeth_cmd_buffer *iob)
  313. {
  314. struct qeth_ipa_cmd *cmd = NULL;
  315. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  316. if (IS_IPA(iob->data)) {
  317. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  318. if (IS_IPA_REPLY(cmd)) {
  319. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  320. cmd->hdr.command != IPA_CMD_DELCCID &&
  321. cmd->hdr.command != IPA_CMD_MODCCID &&
  322. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  323. qeth_issue_ipa_msg(cmd,
  324. cmd->hdr.return_code, card);
  325. return cmd;
  326. } else {
  327. switch (cmd->hdr.command) {
  328. case IPA_CMD_STOPLAN:
  329. dev_warn(&card->gdev->dev,
  330. "The link for interface %s on CHPID"
  331. " 0x%X failed\n",
  332. QETH_CARD_IFNAME(card),
  333. card->info.chpid);
  334. card->lan_online = 0;
  335. if (card->dev && netif_carrier_ok(card->dev))
  336. netif_carrier_off(card->dev);
  337. return NULL;
  338. case IPA_CMD_STARTLAN:
  339. dev_info(&card->gdev->dev,
  340. "The link for %s on CHPID 0x%X has"
  341. " been restored\n",
  342. QETH_CARD_IFNAME(card),
  343. card->info.chpid);
  344. netif_carrier_on(card->dev);
  345. card->lan_online = 1;
  346. qeth_schedule_recovery(card);
  347. return NULL;
  348. case IPA_CMD_MODCCID:
  349. return cmd;
  350. case IPA_CMD_REGISTER_LOCAL_ADDR:
  351. QETH_DBF_TEXT(TRACE, 3, "irla");
  352. break;
  353. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  354. QETH_DBF_TEXT(TRACE, 3, "urla");
  355. break;
  356. default:
  357. QETH_DBF_MESSAGE(2, "Received data is IPA "
  358. "but not a reply!\n");
  359. break;
  360. }
  361. }
  362. }
  363. return cmd;
  364. }
  365. void qeth_clear_ipacmd_list(struct qeth_card *card)
  366. {
  367. struct qeth_reply *reply, *r;
  368. unsigned long flags;
  369. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  370. spin_lock_irqsave(&card->lock, flags);
  371. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  372. qeth_get_reply(reply);
  373. reply->rc = -EIO;
  374. atomic_inc(&reply->received);
  375. list_del_init(&reply->list);
  376. wake_up(&reply->wait_q);
  377. qeth_put_reply(reply);
  378. }
  379. spin_unlock_irqrestore(&card->lock, flags);
  380. }
  381. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  382. static int qeth_check_idx_response(unsigned char *buffer)
  383. {
  384. if (!buffer)
  385. return 0;
  386. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  387. if ((buffer[2] & 0xc0) == 0xc0) {
  388. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  389. "with cause code 0x%02x%s\n",
  390. buffer[4],
  391. ((buffer[4] == 0x22) ?
  392. " -- try another portname" : ""));
  393. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  394. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  395. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  396. return -EIO;
  397. }
  398. return 0;
  399. }
  400. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  401. __u32 len)
  402. {
  403. struct qeth_card *card;
  404. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  405. card = CARD_FROM_CDEV(channel->ccwdev);
  406. if (channel == &card->read)
  407. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  408. else
  409. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  410. channel->ccw.count = len;
  411. channel->ccw.cda = (__u32) __pa(iob);
  412. }
  413. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  414. {
  415. __u8 index;
  416. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  417. index = channel->io_buf_no;
  418. do {
  419. if (channel->iob[index].state == BUF_STATE_FREE) {
  420. channel->iob[index].state = BUF_STATE_LOCKED;
  421. channel->io_buf_no = (channel->io_buf_no + 1) %
  422. QETH_CMD_BUFFER_NO;
  423. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  424. return channel->iob + index;
  425. }
  426. index = (index + 1) % QETH_CMD_BUFFER_NO;
  427. } while (index != channel->io_buf_no);
  428. return NULL;
  429. }
  430. void qeth_release_buffer(struct qeth_channel *channel,
  431. struct qeth_cmd_buffer *iob)
  432. {
  433. unsigned long flags;
  434. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  435. spin_lock_irqsave(&channel->iob_lock, flags);
  436. memset(iob->data, 0, QETH_BUFSIZE);
  437. iob->state = BUF_STATE_FREE;
  438. iob->callback = qeth_send_control_data_cb;
  439. iob->rc = 0;
  440. spin_unlock_irqrestore(&channel->iob_lock, flags);
  441. }
  442. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  443. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. struct qeth_cmd_buffer *buffer = NULL;
  446. unsigned long flags;
  447. spin_lock_irqsave(&channel->iob_lock, flags);
  448. buffer = __qeth_get_buffer(channel);
  449. spin_unlock_irqrestore(&channel->iob_lock, flags);
  450. return buffer;
  451. }
  452. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  453. {
  454. struct qeth_cmd_buffer *buffer;
  455. wait_event(channel->wait_q,
  456. ((buffer = qeth_get_buffer(channel)) != NULL));
  457. return buffer;
  458. }
  459. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  460. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  461. {
  462. int cnt;
  463. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  464. qeth_release_buffer(channel, &channel->iob[cnt]);
  465. channel->buf_no = 0;
  466. channel->io_buf_no = 0;
  467. }
  468. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  469. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  470. struct qeth_cmd_buffer *iob)
  471. {
  472. struct qeth_card *card;
  473. struct qeth_reply *reply, *r;
  474. struct qeth_ipa_cmd *cmd;
  475. unsigned long flags;
  476. int keep_reply;
  477. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  478. card = CARD_FROM_CDEV(channel->ccwdev);
  479. if (qeth_check_idx_response(iob->data)) {
  480. qeth_clear_ipacmd_list(card);
  481. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  482. dev_err(&card->gdev->dev,
  483. "The qeth device is not configured "
  484. "for the OSI layer required by z/VM\n");
  485. qeth_schedule_recovery(card);
  486. goto out;
  487. }
  488. cmd = qeth_check_ipa_data(card, iob);
  489. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  490. goto out;
  491. /*in case of OSN : check if cmd is set */
  492. if (card->info.type == QETH_CARD_TYPE_OSN &&
  493. cmd &&
  494. cmd->hdr.command != IPA_CMD_STARTLAN &&
  495. card->osn_info.assist_cb != NULL) {
  496. card->osn_info.assist_cb(card->dev, cmd);
  497. goto out;
  498. }
  499. spin_lock_irqsave(&card->lock, flags);
  500. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  501. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  502. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  503. qeth_get_reply(reply);
  504. list_del_init(&reply->list);
  505. spin_unlock_irqrestore(&card->lock, flags);
  506. keep_reply = 0;
  507. if (reply->callback != NULL) {
  508. if (cmd) {
  509. reply->offset = (__u16)((char *)cmd -
  510. (char *)iob->data);
  511. keep_reply = reply->callback(card,
  512. reply,
  513. (unsigned long)cmd);
  514. } else
  515. keep_reply = reply->callback(card,
  516. reply,
  517. (unsigned long)iob);
  518. }
  519. if (cmd)
  520. reply->rc = (u16) cmd->hdr.return_code;
  521. else if (iob->rc)
  522. reply->rc = iob->rc;
  523. if (keep_reply) {
  524. spin_lock_irqsave(&card->lock, flags);
  525. list_add_tail(&reply->list,
  526. &card->cmd_waiter_list);
  527. spin_unlock_irqrestore(&card->lock, flags);
  528. } else {
  529. atomic_inc(&reply->received);
  530. wake_up(&reply->wait_q);
  531. }
  532. qeth_put_reply(reply);
  533. goto out;
  534. }
  535. }
  536. spin_unlock_irqrestore(&card->lock, flags);
  537. out:
  538. memcpy(&card->seqno.pdu_hdr_ack,
  539. QETH_PDU_HEADER_SEQ_NO(iob->data),
  540. QETH_SEQ_NO_LENGTH);
  541. qeth_release_buffer(channel, iob);
  542. }
  543. static int qeth_setup_channel(struct qeth_channel *channel)
  544. {
  545. int cnt;
  546. QETH_DBF_TEXT(SETUP, 2, "setupch");
  547. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  548. channel->iob[cnt].data = (char *)
  549. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  550. if (channel->iob[cnt].data == NULL)
  551. break;
  552. channel->iob[cnt].state = BUF_STATE_FREE;
  553. channel->iob[cnt].channel = channel;
  554. channel->iob[cnt].callback = qeth_send_control_data_cb;
  555. channel->iob[cnt].rc = 0;
  556. }
  557. if (cnt < QETH_CMD_BUFFER_NO) {
  558. while (cnt-- > 0)
  559. kfree(channel->iob[cnt].data);
  560. return -ENOMEM;
  561. }
  562. channel->buf_no = 0;
  563. channel->io_buf_no = 0;
  564. atomic_set(&channel->irq_pending, 0);
  565. spin_lock_init(&channel->iob_lock);
  566. init_waitqueue_head(&channel->wait_q);
  567. return 0;
  568. }
  569. static int qeth_set_thread_start_bit(struct qeth_card *card,
  570. unsigned long thread)
  571. {
  572. unsigned long flags;
  573. spin_lock_irqsave(&card->thread_mask_lock, flags);
  574. if (!(card->thread_allowed_mask & thread) ||
  575. (card->thread_start_mask & thread)) {
  576. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  577. return -EPERM;
  578. }
  579. card->thread_start_mask |= thread;
  580. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  581. return 0;
  582. }
  583. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  584. {
  585. unsigned long flags;
  586. spin_lock_irqsave(&card->thread_mask_lock, flags);
  587. card->thread_start_mask &= ~thread;
  588. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  589. wake_up(&card->wait_q);
  590. }
  591. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  592. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  593. {
  594. unsigned long flags;
  595. spin_lock_irqsave(&card->thread_mask_lock, flags);
  596. card->thread_running_mask &= ~thread;
  597. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  598. wake_up(&card->wait_q);
  599. }
  600. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  601. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  602. {
  603. unsigned long flags;
  604. int rc = 0;
  605. spin_lock_irqsave(&card->thread_mask_lock, flags);
  606. if (card->thread_start_mask & thread) {
  607. if ((card->thread_allowed_mask & thread) &&
  608. !(card->thread_running_mask & thread)) {
  609. rc = 1;
  610. card->thread_start_mask &= ~thread;
  611. card->thread_running_mask |= thread;
  612. } else
  613. rc = -EPERM;
  614. }
  615. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  616. return rc;
  617. }
  618. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  619. {
  620. int rc = 0;
  621. wait_event(card->wait_q,
  622. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  623. return rc;
  624. }
  625. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  626. void qeth_schedule_recovery(struct qeth_card *card)
  627. {
  628. QETH_DBF_TEXT(TRACE, 2, "startrec");
  629. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  630. schedule_work(&card->kernel_thread_starter);
  631. }
  632. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  633. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  634. {
  635. int dstat, cstat;
  636. char *sense;
  637. sense = (char *) irb->ecw;
  638. cstat = irb->scsw.cmd.cstat;
  639. dstat = irb->scsw.cmd.dstat;
  640. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  641. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  642. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  643. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  644. dev_warn(&cdev->dev, "The qeth device driver "
  645. "failed to recover an error on the device\n");
  646. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  647. dev_name(&cdev->dev), dstat, cstat);
  648. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  649. 16, 1, irb, 64, 1);
  650. return 1;
  651. }
  652. if (dstat & DEV_STAT_UNIT_CHECK) {
  653. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  654. SENSE_RESETTING_EVENT_FLAG) {
  655. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  656. return 1;
  657. }
  658. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  659. SENSE_COMMAND_REJECT_FLAG) {
  660. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  661. return 1;
  662. }
  663. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  664. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  665. return 1;
  666. }
  667. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  668. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  669. return 0;
  670. }
  671. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  672. return 1;
  673. }
  674. return 0;
  675. }
  676. static long __qeth_check_irb_error(struct ccw_device *cdev,
  677. unsigned long intparm, struct irb *irb)
  678. {
  679. if (!IS_ERR(irb))
  680. return 0;
  681. switch (PTR_ERR(irb)) {
  682. case -EIO:
  683. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  684. dev_name(&cdev->dev));
  685. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  686. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  687. break;
  688. case -ETIMEDOUT:
  689. dev_warn(&cdev->dev, "A hardware operation timed out"
  690. " on the device\n");
  691. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  692. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  693. if (intparm == QETH_RCD_PARM) {
  694. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  695. if (card && (card->data.ccwdev == cdev)) {
  696. card->data.state = CH_STATE_DOWN;
  697. wake_up(&card->wait_q);
  698. }
  699. }
  700. break;
  701. default:
  702. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  703. dev_name(&cdev->dev), PTR_ERR(irb));
  704. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  705. QETH_DBF_TEXT(TRACE, 2, " rc???");
  706. }
  707. return PTR_ERR(irb);
  708. }
  709. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  710. struct irb *irb)
  711. {
  712. int rc;
  713. int cstat, dstat;
  714. struct qeth_cmd_buffer *buffer;
  715. struct qeth_channel *channel;
  716. struct qeth_card *card;
  717. struct qeth_cmd_buffer *iob;
  718. __u8 index;
  719. QETH_DBF_TEXT(TRACE, 5, "irq");
  720. if (__qeth_check_irb_error(cdev, intparm, irb))
  721. return;
  722. cstat = irb->scsw.cmd.cstat;
  723. dstat = irb->scsw.cmd.dstat;
  724. card = CARD_FROM_CDEV(cdev);
  725. if (!card)
  726. return;
  727. if (card->read.ccwdev == cdev) {
  728. channel = &card->read;
  729. QETH_DBF_TEXT(TRACE, 5, "read");
  730. } else if (card->write.ccwdev == cdev) {
  731. channel = &card->write;
  732. QETH_DBF_TEXT(TRACE, 5, "write");
  733. } else {
  734. channel = &card->data;
  735. QETH_DBF_TEXT(TRACE, 5, "data");
  736. }
  737. atomic_set(&channel->irq_pending, 0);
  738. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  739. channel->state = CH_STATE_STOPPED;
  740. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  741. channel->state = CH_STATE_HALTED;
  742. /*let's wake up immediately on data channel*/
  743. if ((channel == &card->data) && (intparm != 0) &&
  744. (intparm != QETH_RCD_PARM))
  745. goto out;
  746. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  747. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  748. /* we don't have to handle this further */
  749. intparm = 0;
  750. }
  751. if (intparm == QETH_HALT_CHANNEL_PARM) {
  752. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  753. /* we don't have to handle this further */
  754. intparm = 0;
  755. }
  756. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  757. (dstat & DEV_STAT_UNIT_CHECK) ||
  758. (cstat)) {
  759. if (irb->esw.esw0.erw.cons) {
  760. dev_warn(&channel->ccwdev->dev,
  761. "The qeth device driver failed to recover "
  762. "an error on the device\n");
  763. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  764. "0x%X dstat 0x%X\n",
  765. dev_name(&channel->ccwdev->dev), cstat, dstat);
  766. print_hex_dump(KERN_WARNING, "qeth: irb ",
  767. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  768. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  769. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  770. }
  771. if (intparm == QETH_RCD_PARM) {
  772. channel->state = CH_STATE_DOWN;
  773. goto out;
  774. }
  775. rc = qeth_get_problem(cdev, irb);
  776. if (rc) {
  777. qeth_clear_ipacmd_list(card);
  778. qeth_schedule_recovery(card);
  779. goto out;
  780. }
  781. }
  782. if (intparm == QETH_RCD_PARM) {
  783. channel->state = CH_STATE_RCD_DONE;
  784. goto out;
  785. }
  786. if (intparm) {
  787. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  788. buffer->state = BUF_STATE_PROCESSED;
  789. }
  790. if (channel == &card->data)
  791. return;
  792. if (channel == &card->read &&
  793. channel->state == CH_STATE_UP)
  794. qeth_issue_next_read(card);
  795. iob = channel->iob;
  796. index = channel->buf_no;
  797. while (iob[index].state == BUF_STATE_PROCESSED) {
  798. if (iob[index].callback != NULL)
  799. iob[index].callback(channel, iob + index);
  800. index = (index + 1) % QETH_CMD_BUFFER_NO;
  801. }
  802. channel->buf_no = index;
  803. out:
  804. wake_up(&card->wait_q);
  805. return;
  806. }
  807. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  808. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  809. {
  810. int i;
  811. struct sk_buff *skb;
  812. /* is PCI flag set on buffer? */
  813. if (buf->buffer->element[0].flags & 0x40)
  814. atomic_dec(&queue->set_pci_flags_count);
  815. if (!qeth_skip_skb) {
  816. skb = skb_dequeue(&buf->skb_list);
  817. while (skb) {
  818. atomic_dec(&skb->users);
  819. dev_kfree_skb_any(skb);
  820. skb = skb_dequeue(&buf->skb_list);
  821. }
  822. }
  823. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  824. if (buf->buffer->element[i].addr && buf->is_header[i])
  825. kmem_cache_free(qeth_core_header_cache,
  826. buf->buffer->element[i].addr);
  827. buf->is_header[i] = 0;
  828. buf->buffer->element[i].length = 0;
  829. buf->buffer->element[i].addr = NULL;
  830. buf->buffer->element[i].flags = 0;
  831. }
  832. buf->buffer->element[15].flags = 0;
  833. buf->next_element_to_fill = 0;
  834. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  835. }
  836. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  837. struct qeth_qdio_out_buffer *buf)
  838. {
  839. __qeth_clear_output_buffer(queue, buf, 0);
  840. }
  841. void qeth_clear_qdio_buffers(struct qeth_card *card)
  842. {
  843. int i, j;
  844. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  845. /* clear outbound buffers to free skbs */
  846. for (i = 0; i < card->qdio.no_out_queues; ++i)
  847. if (card->qdio.out_qs[i]) {
  848. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  849. qeth_clear_output_buffer(card->qdio.out_qs[i],
  850. &card->qdio.out_qs[i]->bufs[j]);
  851. }
  852. }
  853. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  854. static void qeth_free_buffer_pool(struct qeth_card *card)
  855. {
  856. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  857. int i = 0;
  858. QETH_DBF_TEXT(TRACE, 5, "freepool");
  859. list_for_each_entry_safe(pool_entry, tmp,
  860. &card->qdio.init_pool.entry_list, init_list){
  861. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  862. free_page((unsigned long)pool_entry->elements[i]);
  863. list_del(&pool_entry->init_list);
  864. kfree(pool_entry);
  865. }
  866. }
  867. static void qeth_free_qdio_buffers(struct qeth_card *card)
  868. {
  869. int i, j;
  870. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  871. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  872. QETH_QDIO_UNINITIALIZED)
  873. return;
  874. kfree(card->qdio.in_q);
  875. card->qdio.in_q = NULL;
  876. /* inbound buffer pool */
  877. qeth_free_buffer_pool(card);
  878. /* free outbound qdio_qs */
  879. if (card->qdio.out_qs) {
  880. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  881. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  882. qeth_clear_output_buffer(card->qdio.out_qs[i],
  883. &card->qdio.out_qs[i]->bufs[j]);
  884. kfree(card->qdio.out_qs[i]);
  885. }
  886. kfree(card->qdio.out_qs);
  887. card->qdio.out_qs = NULL;
  888. }
  889. }
  890. static void qeth_clean_channel(struct qeth_channel *channel)
  891. {
  892. int cnt;
  893. QETH_DBF_TEXT(SETUP, 2, "freech");
  894. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  895. kfree(channel->iob[cnt].data);
  896. }
  897. static int qeth_is_1920_device(struct qeth_card *card)
  898. {
  899. int single_queue = 0;
  900. struct ccw_device *ccwdev;
  901. struct channelPath_dsc {
  902. u8 flags;
  903. u8 lsn;
  904. u8 desc;
  905. u8 chpid;
  906. u8 swla;
  907. u8 zeroes;
  908. u8 chla;
  909. u8 chpp;
  910. } *chp_dsc;
  911. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  912. ccwdev = card->data.ccwdev;
  913. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  914. if (chp_dsc != NULL) {
  915. /* CHPP field bit 6 == 1 -> single queue */
  916. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  917. kfree(chp_dsc);
  918. }
  919. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  920. return single_queue;
  921. }
  922. static void qeth_init_qdio_info(struct qeth_card *card)
  923. {
  924. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  925. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  926. /* inbound */
  927. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  928. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  929. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  930. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  931. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  932. }
  933. static void qeth_set_intial_options(struct qeth_card *card)
  934. {
  935. card->options.route4.type = NO_ROUTER;
  936. card->options.route6.type = NO_ROUTER;
  937. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  938. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  939. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  940. card->options.fake_broadcast = 0;
  941. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  942. card->options.performance_stats = 0;
  943. card->options.rx_sg_cb = QETH_RX_SG_CB;
  944. card->options.isolation = ISOLATION_MODE_NONE;
  945. }
  946. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  947. {
  948. unsigned long flags;
  949. int rc = 0;
  950. spin_lock_irqsave(&card->thread_mask_lock, flags);
  951. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  952. (u8) card->thread_start_mask,
  953. (u8) card->thread_allowed_mask,
  954. (u8) card->thread_running_mask);
  955. rc = (card->thread_start_mask & thread);
  956. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  957. return rc;
  958. }
  959. static void qeth_start_kernel_thread(struct work_struct *work)
  960. {
  961. struct qeth_card *card = container_of(work, struct qeth_card,
  962. kernel_thread_starter);
  963. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  964. if (card->read.state != CH_STATE_UP &&
  965. card->write.state != CH_STATE_UP)
  966. return;
  967. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  968. kthread_run(card->discipline.recover, (void *) card,
  969. "qeth_recover");
  970. }
  971. static int qeth_setup_card(struct qeth_card *card)
  972. {
  973. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  974. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  975. card->read.state = CH_STATE_DOWN;
  976. card->write.state = CH_STATE_DOWN;
  977. card->data.state = CH_STATE_DOWN;
  978. card->state = CARD_STATE_DOWN;
  979. card->lan_online = 0;
  980. card->use_hard_stop = 0;
  981. card->dev = NULL;
  982. spin_lock_init(&card->vlanlock);
  983. spin_lock_init(&card->mclock);
  984. card->vlangrp = NULL;
  985. spin_lock_init(&card->lock);
  986. spin_lock_init(&card->ip_lock);
  987. spin_lock_init(&card->thread_mask_lock);
  988. card->thread_start_mask = 0;
  989. card->thread_allowed_mask = 0;
  990. card->thread_running_mask = 0;
  991. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  992. INIT_LIST_HEAD(&card->ip_list);
  993. INIT_LIST_HEAD(card->ip_tbd_list);
  994. INIT_LIST_HEAD(&card->cmd_waiter_list);
  995. init_waitqueue_head(&card->wait_q);
  996. /* intial options */
  997. qeth_set_intial_options(card);
  998. /* IP address takeover */
  999. INIT_LIST_HEAD(&card->ipato.entries);
  1000. card->ipato.enabled = 0;
  1001. card->ipato.invert4 = 0;
  1002. card->ipato.invert6 = 0;
  1003. if (card->info.type == QETH_CARD_TYPE_IQD)
  1004. card->options.checksum_type = NO_CHECKSUMMING;
  1005. /* init QDIO stuff */
  1006. qeth_init_qdio_info(card);
  1007. return 0;
  1008. }
  1009. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1010. {
  1011. struct qeth_card *card = container_of(slr, struct qeth_card,
  1012. qeth_service_level);
  1013. if (card->info.mcl_level[0])
  1014. seq_printf(m, "qeth: %s firmware level %s\n",
  1015. CARD_BUS_ID(card), card->info.mcl_level);
  1016. }
  1017. static struct qeth_card *qeth_alloc_card(void)
  1018. {
  1019. struct qeth_card *card;
  1020. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1021. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1022. if (!card)
  1023. goto out;
  1024. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1025. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1026. if (!card->ip_tbd_list) {
  1027. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1028. goto out_card;
  1029. }
  1030. if (qeth_setup_channel(&card->read))
  1031. goto out_ip;
  1032. if (qeth_setup_channel(&card->write))
  1033. goto out_channel;
  1034. card->options.layer2 = -1;
  1035. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1036. register_service_level(&card->qeth_service_level);
  1037. return card;
  1038. out_channel:
  1039. qeth_clean_channel(&card->read);
  1040. out_ip:
  1041. kfree(card->ip_tbd_list);
  1042. out_card:
  1043. kfree(card);
  1044. out:
  1045. return NULL;
  1046. }
  1047. static int qeth_determine_card_type(struct qeth_card *card)
  1048. {
  1049. int i = 0;
  1050. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1051. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1052. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1053. while (known_devices[i][4]) {
  1054. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1055. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1056. card->info.type = known_devices[i][4];
  1057. card->qdio.no_out_queues = known_devices[i][8];
  1058. card->info.is_multicast_different = known_devices[i][9];
  1059. if (qeth_is_1920_device(card)) {
  1060. dev_info(&card->gdev->dev,
  1061. "Priority Queueing not supported\n");
  1062. card->qdio.no_out_queues = 1;
  1063. card->qdio.default_out_queue = 0;
  1064. }
  1065. return 0;
  1066. }
  1067. i++;
  1068. }
  1069. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1070. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1071. "unknown type\n");
  1072. return -ENOENT;
  1073. }
  1074. static int qeth_clear_channel(struct qeth_channel *channel)
  1075. {
  1076. unsigned long flags;
  1077. struct qeth_card *card;
  1078. int rc;
  1079. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1080. card = CARD_FROM_CDEV(channel->ccwdev);
  1081. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1082. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1083. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1084. if (rc)
  1085. return rc;
  1086. rc = wait_event_interruptible_timeout(card->wait_q,
  1087. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1088. if (rc == -ERESTARTSYS)
  1089. return rc;
  1090. if (channel->state != CH_STATE_STOPPED)
  1091. return -ETIME;
  1092. channel->state = CH_STATE_DOWN;
  1093. return 0;
  1094. }
  1095. static int qeth_halt_channel(struct qeth_channel *channel)
  1096. {
  1097. unsigned long flags;
  1098. struct qeth_card *card;
  1099. int rc;
  1100. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1101. card = CARD_FROM_CDEV(channel->ccwdev);
  1102. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1103. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1104. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1105. if (rc)
  1106. return rc;
  1107. rc = wait_event_interruptible_timeout(card->wait_q,
  1108. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1109. if (rc == -ERESTARTSYS)
  1110. return rc;
  1111. if (channel->state != CH_STATE_HALTED)
  1112. return -ETIME;
  1113. return 0;
  1114. }
  1115. static int qeth_halt_channels(struct qeth_card *card)
  1116. {
  1117. int rc1 = 0, rc2 = 0, rc3 = 0;
  1118. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1119. rc1 = qeth_halt_channel(&card->read);
  1120. rc2 = qeth_halt_channel(&card->write);
  1121. rc3 = qeth_halt_channel(&card->data);
  1122. if (rc1)
  1123. return rc1;
  1124. if (rc2)
  1125. return rc2;
  1126. return rc3;
  1127. }
  1128. static int qeth_clear_channels(struct qeth_card *card)
  1129. {
  1130. int rc1 = 0, rc2 = 0, rc3 = 0;
  1131. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1132. rc1 = qeth_clear_channel(&card->read);
  1133. rc2 = qeth_clear_channel(&card->write);
  1134. rc3 = qeth_clear_channel(&card->data);
  1135. if (rc1)
  1136. return rc1;
  1137. if (rc2)
  1138. return rc2;
  1139. return rc3;
  1140. }
  1141. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1142. {
  1143. int rc = 0;
  1144. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1145. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1146. if (halt)
  1147. rc = qeth_halt_channels(card);
  1148. if (rc)
  1149. return rc;
  1150. return qeth_clear_channels(card);
  1151. }
  1152. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1153. {
  1154. int rc = 0;
  1155. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1156. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1157. QETH_QDIO_CLEANING)) {
  1158. case QETH_QDIO_ESTABLISHED:
  1159. if (card->info.type == QETH_CARD_TYPE_IQD)
  1160. rc = qdio_cleanup(CARD_DDEV(card),
  1161. QDIO_FLAG_CLEANUP_USING_HALT);
  1162. else
  1163. rc = qdio_cleanup(CARD_DDEV(card),
  1164. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1165. if (rc)
  1166. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1167. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1168. break;
  1169. case QETH_QDIO_CLEANING:
  1170. return rc;
  1171. default:
  1172. break;
  1173. }
  1174. rc = qeth_clear_halt_card(card, use_halt);
  1175. if (rc)
  1176. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1177. card->state = CARD_STATE_DOWN;
  1178. return rc;
  1179. }
  1180. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1181. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1182. int *length)
  1183. {
  1184. struct ciw *ciw;
  1185. char *rcd_buf;
  1186. int ret;
  1187. struct qeth_channel *channel = &card->data;
  1188. unsigned long flags;
  1189. /*
  1190. * scan for RCD command in extended SenseID data
  1191. */
  1192. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1193. if (!ciw || ciw->cmd == 0)
  1194. return -EOPNOTSUPP;
  1195. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1196. if (!rcd_buf)
  1197. return -ENOMEM;
  1198. channel->ccw.cmd_code = ciw->cmd;
  1199. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1200. channel->ccw.count = ciw->count;
  1201. channel->ccw.flags = CCW_FLAG_SLI;
  1202. channel->state = CH_STATE_RCD;
  1203. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1204. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1205. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1206. QETH_RCD_TIMEOUT);
  1207. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1208. if (!ret)
  1209. wait_event(card->wait_q,
  1210. (channel->state == CH_STATE_RCD_DONE ||
  1211. channel->state == CH_STATE_DOWN));
  1212. if (channel->state == CH_STATE_DOWN)
  1213. ret = -EIO;
  1214. else
  1215. channel->state = CH_STATE_DOWN;
  1216. if (ret) {
  1217. kfree(rcd_buf);
  1218. *buffer = NULL;
  1219. *length = 0;
  1220. } else {
  1221. *length = ciw->count;
  1222. *buffer = rcd_buf;
  1223. }
  1224. return ret;
  1225. }
  1226. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1227. {
  1228. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1229. card->info.chpid = prcd[30];
  1230. card->info.unit_addr2 = prcd[31];
  1231. card->info.cula = prcd[63];
  1232. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1233. (prcd[0x11] == _ascebc['M']));
  1234. }
  1235. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1236. {
  1237. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1238. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1239. card->info.blkt.time_total = 250;
  1240. card->info.blkt.inter_packet = 5;
  1241. card->info.blkt.inter_packet_jumbo = 15;
  1242. } else {
  1243. card->info.blkt.time_total = 0;
  1244. card->info.blkt.inter_packet = 0;
  1245. card->info.blkt.inter_packet_jumbo = 0;
  1246. }
  1247. }
  1248. static void qeth_init_tokens(struct qeth_card *card)
  1249. {
  1250. card->token.issuer_rm_w = 0x00010103UL;
  1251. card->token.cm_filter_w = 0x00010108UL;
  1252. card->token.cm_connection_w = 0x0001010aUL;
  1253. card->token.ulp_filter_w = 0x0001010bUL;
  1254. card->token.ulp_connection_w = 0x0001010dUL;
  1255. }
  1256. static void qeth_init_func_level(struct qeth_card *card)
  1257. {
  1258. if (card->ipato.enabled) {
  1259. if (card->info.type == QETH_CARD_TYPE_IQD)
  1260. card->info.func_level =
  1261. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1262. else
  1263. card->info.func_level =
  1264. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1265. } else {
  1266. if (card->info.type == QETH_CARD_TYPE_IQD)
  1267. /*FIXME:why do we have same values for dis and ena for
  1268. osae??? */
  1269. card->info.func_level =
  1270. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1271. else
  1272. card->info.func_level =
  1273. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1274. }
  1275. }
  1276. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1277. void (*idx_reply_cb)(struct qeth_channel *,
  1278. struct qeth_cmd_buffer *))
  1279. {
  1280. struct qeth_cmd_buffer *iob;
  1281. unsigned long flags;
  1282. int rc;
  1283. struct qeth_card *card;
  1284. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1285. card = CARD_FROM_CDEV(channel->ccwdev);
  1286. iob = qeth_get_buffer(channel);
  1287. iob->callback = idx_reply_cb;
  1288. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1289. channel->ccw.count = QETH_BUFSIZE;
  1290. channel->ccw.cda = (__u32) __pa(iob->data);
  1291. wait_event(card->wait_q,
  1292. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1293. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1294. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1295. rc = ccw_device_start(channel->ccwdev,
  1296. &channel->ccw, (addr_t) iob, 0, 0);
  1297. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1298. if (rc) {
  1299. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1300. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1301. atomic_set(&channel->irq_pending, 0);
  1302. wake_up(&card->wait_q);
  1303. return rc;
  1304. }
  1305. rc = wait_event_interruptible_timeout(card->wait_q,
  1306. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1307. if (rc == -ERESTARTSYS)
  1308. return rc;
  1309. if (channel->state != CH_STATE_UP) {
  1310. rc = -ETIME;
  1311. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1312. qeth_clear_cmd_buffers(channel);
  1313. } else
  1314. rc = 0;
  1315. return rc;
  1316. }
  1317. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1318. void (*idx_reply_cb)(struct qeth_channel *,
  1319. struct qeth_cmd_buffer *))
  1320. {
  1321. struct qeth_card *card;
  1322. struct qeth_cmd_buffer *iob;
  1323. unsigned long flags;
  1324. __u16 temp;
  1325. __u8 tmp;
  1326. int rc;
  1327. struct ccw_dev_id temp_devid;
  1328. card = CARD_FROM_CDEV(channel->ccwdev);
  1329. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1330. iob = qeth_get_buffer(channel);
  1331. iob->callback = idx_reply_cb;
  1332. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1333. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1334. channel->ccw.cda = (__u32) __pa(iob->data);
  1335. if (channel == &card->write) {
  1336. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1337. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1338. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1339. card->seqno.trans_hdr++;
  1340. } else {
  1341. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1342. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1343. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1344. }
  1345. tmp = ((__u8)card->info.portno) | 0x80;
  1346. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1347. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1348. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1349. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1350. &card->info.func_level, sizeof(__u16));
  1351. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1352. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1353. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1354. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1355. wait_event(card->wait_q,
  1356. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1357. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1358. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1359. rc = ccw_device_start(channel->ccwdev,
  1360. &channel->ccw, (addr_t) iob, 0, 0);
  1361. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1362. if (rc) {
  1363. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1364. rc);
  1365. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1366. atomic_set(&channel->irq_pending, 0);
  1367. wake_up(&card->wait_q);
  1368. return rc;
  1369. }
  1370. rc = wait_event_interruptible_timeout(card->wait_q,
  1371. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1372. if (rc == -ERESTARTSYS)
  1373. return rc;
  1374. if (channel->state != CH_STATE_ACTIVATING) {
  1375. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1376. " failed to recover an error on the device\n");
  1377. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1378. dev_name(&channel->ccwdev->dev));
  1379. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1380. qeth_clear_cmd_buffers(channel);
  1381. return -ETIME;
  1382. }
  1383. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1384. }
  1385. static int qeth_peer_func_level(int level)
  1386. {
  1387. if ((level & 0xff) == 8)
  1388. return (level & 0xff) + 0x400;
  1389. if (((level >> 8) & 3) == 1)
  1390. return (level & 0xff) + 0x200;
  1391. return level;
  1392. }
  1393. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1394. struct qeth_cmd_buffer *iob)
  1395. {
  1396. struct qeth_card *card;
  1397. __u16 temp;
  1398. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1399. if (channel->state == CH_STATE_DOWN) {
  1400. channel->state = CH_STATE_ACTIVATING;
  1401. goto out;
  1402. }
  1403. card = CARD_FROM_CDEV(channel->ccwdev);
  1404. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1405. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1406. dev_err(&card->write.ccwdev->dev,
  1407. "The adapter is used exclusively by another "
  1408. "host\n");
  1409. else
  1410. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1411. " negative reply\n",
  1412. dev_name(&card->write.ccwdev->dev));
  1413. goto out;
  1414. }
  1415. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1416. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1417. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1418. "function level mismatch (sent: 0x%x, received: "
  1419. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1420. card->info.func_level, temp);
  1421. goto out;
  1422. }
  1423. channel->state = CH_STATE_UP;
  1424. out:
  1425. qeth_release_buffer(channel, iob);
  1426. }
  1427. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1428. struct qeth_cmd_buffer *iob)
  1429. {
  1430. struct qeth_card *card;
  1431. __u16 temp;
  1432. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1433. if (channel->state == CH_STATE_DOWN) {
  1434. channel->state = CH_STATE_ACTIVATING;
  1435. goto out;
  1436. }
  1437. card = CARD_FROM_CDEV(channel->ccwdev);
  1438. if (qeth_check_idx_response(iob->data))
  1439. goto out;
  1440. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1441. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1442. dev_err(&card->write.ccwdev->dev,
  1443. "The adapter is used exclusively by another "
  1444. "host\n");
  1445. else
  1446. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1447. " negative reply\n",
  1448. dev_name(&card->read.ccwdev->dev));
  1449. goto out;
  1450. }
  1451. /**
  1452. * temporary fix for microcode bug
  1453. * to revert it,replace OR by AND
  1454. */
  1455. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1456. (card->info.type == QETH_CARD_TYPE_OSAE))
  1457. card->info.portname_required = 1;
  1458. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1459. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1460. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1461. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1462. dev_name(&card->read.ccwdev->dev),
  1463. card->info.func_level, temp);
  1464. goto out;
  1465. }
  1466. memcpy(&card->token.issuer_rm_r,
  1467. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1468. QETH_MPC_TOKEN_LENGTH);
  1469. memcpy(&card->info.mcl_level[0],
  1470. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1471. channel->state = CH_STATE_UP;
  1472. out:
  1473. qeth_release_buffer(channel, iob);
  1474. }
  1475. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1476. struct qeth_cmd_buffer *iob)
  1477. {
  1478. qeth_setup_ccw(&card->write, iob->data, len);
  1479. iob->callback = qeth_release_buffer;
  1480. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1481. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1482. card->seqno.trans_hdr++;
  1483. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1484. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1485. card->seqno.pdu_hdr++;
  1486. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1487. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1488. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1489. }
  1490. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1491. int qeth_send_control_data(struct qeth_card *card, int len,
  1492. struct qeth_cmd_buffer *iob,
  1493. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1494. unsigned long),
  1495. void *reply_param)
  1496. {
  1497. int rc;
  1498. unsigned long flags;
  1499. struct qeth_reply *reply = NULL;
  1500. unsigned long timeout, event_timeout;
  1501. struct qeth_ipa_cmd *cmd;
  1502. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1503. reply = qeth_alloc_reply(card);
  1504. if (!reply) {
  1505. return -ENOMEM;
  1506. }
  1507. reply->callback = reply_cb;
  1508. reply->param = reply_param;
  1509. if (card->state == CARD_STATE_DOWN)
  1510. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1511. else
  1512. reply->seqno = card->seqno.ipa++;
  1513. init_waitqueue_head(&reply->wait_q);
  1514. spin_lock_irqsave(&card->lock, flags);
  1515. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1516. spin_unlock_irqrestore(&card->lock, flags);
  1517. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1518. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1519. qeth_prepare_control_data(card, len, iob);
  1520. if (IS_IPA(iob->data))
  1521. event_timeout = QETH_IPA_TIMEOUT;
  1522. else
  1523. event_timeout = QETH_TIMEOUT;
  1524. timeout = jiffies + event_timeout;
  1525. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1526. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1527. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1528. (addr_t) iob, 0, 0);
  1529. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1530. if (rc) {
  1531. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1532. "ccw_device_start rc = %i\n",
  1533. dev_name(&card->write.ccwdev->dev), rc);
  1534. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1535. spin_lock_irqsave(&card->lock, flags);
  1536. list_del_init(&reply->list);
  1537. qeth_put_reply(reply);
  1538. spin_unlock_irqrestore(&card->lock, flags);
  1539. qeth_release_buffer(iob->channel, iob);
  1540. atomic_set(&card->write.irq_pending, 0);
  1541. wake_up(&card->wait_q);
  1542. return rc;
  1543. }
  1544. /* we have only one long running ipassist, since we can ensure
  1545. process context of this command we can sleep */
  1546. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1547. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1548. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1549. if (!wait_event_timeout(reply->wait_q,
  1550. atomic_read(&reply->received), event_timeout))
  1551. goto time_err;
  1552. } else {
  1553. while (!atomic_read(&reply->received)) {
  1554. if (time_after(jiffies, timeout))
  1555. goto time_err;
  1556. cpu_relax();
  1557. };
  1558. }
  1559. rc = reply->rc;
  1560. qeth_put_reply(reply);
  1561. return rc;
  1562. time_err:
  1563. spin_lock_irqsave(&reply->card->lock, flags);
  1564. list_del_init(&reply->list);
  1565. spin_unlock_irqrestore(&reply->card->lock, flags);
  1566. reply->rc = -ETIME;
  1567. atomic_inc(&reply->received);
  1568. wake_up(&reply->wait_q);
  1569. rc = reply->rc;
  1570. qeth_put_reply(reply);
  1571. return rc;
  1572. }
  1573. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1574. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1575. unsigned long data)
  1576. {
  1577. struct qeth_cmd_buffer *iob;
  1578. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1579. iob = (struct qeth_cmd_buffer *) data;
  1580. memcpy(&card->token.cm_filter_r,
  1581. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1582. QETH_MPC_TOKEN_LENGTH);
  1583. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1584. return 0;
  1585. }
  1586. static int qeth_cm_enable(struct qeth_card *card)
  1587. {
  1588. int rc;
  1589. struct qeth_cmd_buffer *iob;
  1590. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1591. iob = qeth_wait_for_buffer(&card->write);
  1592. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1593. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1594. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1595. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1596. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1597. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1598. qeth_cm_enable_cb, NULL);
  1599. return rc;
  1600. }
  1601. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1602. unsigned long data)
  1603. {
  1604. struct qeth_cmd_buffer *iob;
  1605. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1606. iob = (struct qeth_cmd_buffer *) data;
  1607. memcpy(&card->token.cm_connection_r,
  1608. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1609. QETH_MPC_TOKEN_LENGTH);
  1610. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1611. return 0;
  1612. }
  1613. static int qeth_cm_setup(struct qeth_card *card)
  1614. {
  1615. int rc;
  1616. struct qeth_cmd_buffer *iob;
  1617. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1618. iob = qeth_wait_for_buffer(&card->write);
  1619. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1620. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1621. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1622. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1623. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1624. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1625. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1626. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1627. qeth_cm_setup_cb, NULL);
  1628. return rc;
  1629. }
  1630. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1631. {
  1632. switch (card->info.type) {
  1633. case QETH_CARD_TYPE_UNKNOWN:
  1634. return 1500;
  1635. case QETH_CARD_TYPE_IQD:
  1636. return card->info.max_mtu;
  1637. case QETH_CARD_TYPE_OSAE:
  1638. switch (card->info.link_type) {
  1639. case QETH_LINK_TYPE_HSTR:
  1640. case QETH_LINK_TYPE_LANE_TR:
  1641. return 2000;
  1642. default:
  1643. return 1492;
  1644. }
  1645. default:
  1646. return 1500;
  1647. }
  1648. }
  1649. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1650. {
  1651. switch (cardtype) {
  1652. case QETH_CARD_TYPE_UNKNOWN:
  1653. case QETH_CARD_TYPE_OSAE:
  1654. case QETH_CARD_TYPE_OSN:
  1655. return 61440;
  1656. case QETH_CARD_TYPE_IQD:
  1657. return 57344;
  1658. default:
  1659. return 1500;
  1660. }
  1661. }
  1662. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1663. {
  1664. switch (cardtype) {
  1665. case QETH_CARD_TYPE_IQD:
  1666. return 1;
  1667. default:
  1668. return 0;
  1669. }
  1670. }
  1671. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1672. {
  1673. switch (framesize) {
  1674. case 0x4000:
  1675. return 8192;
  1676. case 0x6000:
  1677. return 16384;
  1678. case 0xa000:
  1679. return 32768;
  1680. case 0xffff:
  1681. return 57344;
  1682. default:
  1683. return 0;
  1684. }
  1685. }
  1686. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1687. {
  1688. switch (card->info.type) {
  1689. case QETH_CARD_TYPE_OSAE:
  1690. return ((mtu >= 576) && (mtu <= 61440));
  1691. case QETH_CARD_TYPE_IQD:
  1692. return ((mtu >= 576) &&
  1693. (mtu <= card->info.max_mtu + 4096 - 32));
  1694. case QETH_CARD_TYPE_OSN:
  1695. case QETH_CARD_TYPE_UNKNOWN:
  1696. default:
  1697. return 1;
  1698. }
  1699. }
  1700. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1701. unsigned long data)
  1702. {
  1703. __u16 mtu, framesize;
  1704. __u16 len;
  1705. __u8 link_type;
  1706. struct qeth_cmd_buffer *iob;
  1707. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1708. iob = (struct qeth_cmd_buffer *) data;
  1709. memcpy(&card->token.ulp_filter_r,
  1710. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1711. QETH_MPC_TOKEN_LENGTH);
  1712. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1713. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1714. mtu = qeth_get_mtu_outof_framesize(framesize);
  1715. if (!mtu) {
  1716. iob->rc = -EINVAL;
  1717. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1718. return 0;
  1719. }
  1720. card->info.max_mtu = mtu;
  1721. card->info.initial_mtu = mtu;
  1722. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1723. } else {
  1724. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1725. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1726. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1727. }
  1728. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1729. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1730. memcpy(&link_type,
  1731. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1732. card->info.link_type = link_type;
  1733. } else
  1734. card->info.link_type = 0;
  1735. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1736. return 0;
  1737. }
  1738. static int qeth_ulp_enable(struct qeth_card *card)
  1739. {
  1740. int rc;
  1741. char prot_type;
  1742. struct qeth_cmd_buffer *iob;
  1743. /*FIXME: trace view callbacks*/
  1744. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1745. iob = qeth_wait_for_buffer(&card->write);
  1746. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1747. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1748. (__u8) card->info.portno;
  1749. if (card->options.layer2)
  1750. if (card->info.type == QETH_CARD_TYPE_OSN)
  1751. prot_type = QETH_PROT_OSN2;
  1752. else
  1753. prot_type = QETH_PROT_LAYER2;
  1754. else
  1755. prot_type = QETH_PROT_TCPIP;
  1756. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1757. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1758. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1759. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1760. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1761. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1762. card->info.portname, 9);
  1763. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1764. qeth_ulp_enable_cb, NULL);
  1765. return rc;
  1766. }
  1767. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1768. unsigned long data)
  1769. {
  1770. struct qeth_cmd_buffer *iob;
  1771. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1772. iob = (struct qeth_cmd_buffer *) data;
  1773. memcpy(&card->token.ulp_connection_r,
  1774. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1775. QETH_MPC_TOKEN_LENGTH);
  1776. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1777. return 0;
  1778. }
  1779. static int qeth_ulp_setup(struct qeth_card *card)
  1780. {
  1781. int rc;
  1782. __u16 temp;
  1783. struct qeth_cmd_buffer *iob;
  1784. struct ccw_dev_id dev_id;
  1785. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1786. iob = qeth_wait_for_buffer(&card->write);
  1787. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1788. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1789. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1790. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1791. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1792. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1793. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1794. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1795. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1796. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1797. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1798. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1799. qeth_ulp_setup_cb, NULL);
  1800. return rc;
  1801. }
  1802. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1803. {
  1804. int i, j;
  1805. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1806. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1807. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1808. return 0;
  1809. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1810. GFP_KERNEL);
  1811. if (!card->qdio.in_q)
  1812. goto out_nomem;
  1813. QETH_DBF_TEXT(SETUP, 2, "inq");
  1814. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1815. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1816. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1817. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1818. card->qdio.in_q->bufs[i].buffer =
  1819. &card->qdio.in_q->qdio_bufs[i];
  1820. /* inbound buffer pool */
  1821. if (qeth_alloc_buffer_pool(card))
  1822. goto out_freeinq;
  1823. /* outbound */
  1824. card->qdio.out_qs =
  1825. kmalloc(card->qdio.no_out_queues *
  1826. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1827. if (!card->qdio.out_qs)
  1828. goto out_freepool;
  1829. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1830. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1831. GFP_KERNEL);
  1832. if (!card->qdio.out_qs[i])
  1833. goto out_freeoutq;
  1834. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1835. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1836. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1837. card->qdio.out_qs[i]->queue_no = i;
  1838. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1839. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1840. card->qdio.out_qs[i]->bufs[j].buffer =
  1841. &card->qdio.out_qs[i]->qdio_bufs[j];
  1842. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1843. skb_list);
  1844. lockdep_set_class(
  1845. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1846. &qdio_out_skb_queue_key);
  1847. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1848. }
  1849. }
  1850. return 0;
  1851. out_freeoutq:
  1852. while (i > 0)
  1853. kfree(card->qdio.out_qs[--i]);
  1854. kfree(card->qdio.out_qs);
  1855. card->qdio.out_qs = NULL;
  1856. out_freepool:
  1857. qeth_free_buffer_pool(card);
  1858. out_freeinq:
  1859. kfree(card->qdio.in_q);
  1860. card->qdio.in_q = NULL;
  1861. out_nomem:
  1862. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1863. return -ENOMEM;
  1864. }
  1865. static void qeth_create_qib_param_field(struct qeth_card *card,
  1866. char *param_field)
  1867. {
  1868. param_field[0] = _ascebc['P'];
  1869. param_field[1] = _ascebc['C'];
  1870. param_field[2] = _ascebc['I'];
  1871. param_field[3] = _ascebc['T'];
  1872. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1873. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1874. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1875. }
  1876. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1877. char *param_field)
  1878. {
  1879. param_field[16] = _ascebc['B'];
  1880. param_field[17] = _ascebc['L'];
  1881. param_field[18] = _ascebc['K'];
  1882. param_field[19] = _ascebc['T'];
  1883. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1884. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1885. *((unsigned int *) (&param_field[28])) =
  1886. card->info.blkt.inter_packet_jumbo;
  1887. }
  1888. static int qeth_qdio_activate(struct qeth_card *card)
  1889. {
  1890. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1891. return qdio_activate(CARD_DDEV(card));
  1892. }
  1893. static int qeth_dm_act(struct qeth_card *card)
  1894. {
  1895. int rc;
  1896. struct qeth_cmd_buffer *iob;
  1897. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1898. iob = qeth_wait_for_buffer(&card->write);
  1899. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1900. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1901. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1902. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1903. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1904. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1905. return rc;
  1906. }
  1907. static int qeth_mpc_initialize(struct qeth_card *card)
  1908. {
  1909. int rc;
  1910. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1911. rc = qeth_issue_next_read(card);
  1912. if (rc) {
  1913. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1914. return rc;
  1915. }
  1916. rc = qeth_cm_enable(card);
  1917. if (rc) {
  1918. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1919. goto out_qdio;
  1920. }
  1921. rc = qeth_cm_setup(card);
  1922. if (rc) {
  1923. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1924. goto out_qdio;
  1925. }
  1926. rc = qeth_ulp_enable(card);
  1927. if (rc) {
  1928. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1929. goto out_qdio;
  1930. }
  1931. rc = qeth_ulp_setup(card);
  1932. if (rc) {
  1933. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1934. goto out_qdio;
  1935. }
  1936. rc = qeth_alloc_qdio_buffers(card);
  1937. if (rc) {
  1938. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1939. goto out_qdio;
  1940. }
  1941. rc = qeth_qdio_establish(card);
  1942. if (rc) {
  1943. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1944. qeth_free_qdio_buffers(card);
  1945. goto out_qdio;
  1946. }
  1947. rc = qeth_qdio_activate(card);
  1948. if (rc) {
  1949. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1950. goto out_qdio;
  1951. }
  1952. rc = qeth_dm_act(card);
  1953. if (rc) {
  1954. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1955. goto out_qdio;
  1956. }
  1957. return 0;
  1958. out_qdio:
  1959. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1960. return rc;
  1961. }
  1962. static void qeth_print_status_with_portname(struct qeth_card *card)
  1963. {
  1964. char dbf_text[15];
  1965. int i;
  1966. sprintf(dbf_text, "%s", card->info.portname + 1);
  1967. for (i = 0; i < 8; i++)
  1968. dbf_text[i] =
  1969. (char) _ebcasc[(__u8) dbf_text[i]];
  1970. dbf_text[8] = 0;
  1971. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1972. "with link type %s (portname: %s)\n",
  1973. qeth_get_cardname(card),
  1974. (card->info.mcl_level[0]) ? " (level: " : "",
  1975. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1976. (card->info.mcl_level[0]) ? ")" : "",
  1977. qeth_get_cardname_short(card),
  1978. dbf_text);
  1979. }
  1980. static void qeth_print_status_no_portname(struct qeth_card *card)
  1981. {
  1982. if (card->info.portname[0])
  1983. dev_info(&card->gdev->dev, "Device is a%s "
  1984. "card%s%s%s\nwith link type %s "
  1985. "(no portname needed by interface).\n",
  1986. qeth_get_cardname(card),
  1987. (card->info.mcl_level[0]) ? " (level: " : "",
  1988. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1989. (card->info.mcl_level[0]) ? ")" : "",
  1990. qeth_get_cardname_short(card));
  1991. else
  1992. dev_info(&card->gdev->dev, "Device is a%s "
  1993. "card%s%s%s\nwith link type %s.\n",
  1994. qeth_get_cardname(card),
  1995. (card->info.mcl_level[0]) ? " (level: " : "",
  1996. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1997. (card->info.mcl_level[0]) ? ")" : "",
  1998. qeth_get_cardname_short(card));
  1999. }
  2000. void qeth_print_status_message(struct qeth_card *card)
  2001. {
  2002. switch (card->info.type) {
  2003. case QETH_CARD_TYPE_OSAE:
  2004. /* VM will use a non-zero first character
  2005. * to indicate a HiperSockets like reporting
  2006. * of the level OSA sets the first character to zero
  2007. * */
  2008. if (!card->info.mcl_level[0]) {
  2009. sprintf(card->info.mcl_level, "%02x%02x",
  2010. card->info.mcl_level[2],
  2011. card->info.mcl_level[3]);
  2012. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2013. break;
  2014. }
  2015. /* fallthrough */
  2016. case QETH_CARD_TYPE_IQD:
  2017. if ((card->info.guestlan) ||
  2018. (card->info.mcl_level[0] & 0x80)) {
  2019. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2020. card->info.mcl_level[0]];
  2021. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2022. card->info.mcl_level[1]];
  2023. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2024. card->info.mcl_level[2]];
  2025. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2026. card->info.mcl_level[3]];
  2027. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2028. }
  2029. break;
  2030. default:
  2031. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2032. }
  2033. if (card->info.portname_required)
  2034. qeth_print_status_with_portname(card);
  2035. else
  2036. qeth_print_status_no_portname(card);
  2037. }
  2038. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2039. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2040. {
  2041. struct qeth_buffer_pool_entry *entry;
  2042. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2043. list_for_each_entry(entry,
  2044. &card->qdio.init_pool.entry_list, init_list) {
  2045. qeth_put_buffer_pool_entry(card, entry);
  2046. }
  2047. }
  2048. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2049. struct qeth_card *card)
  2050. {
  2051. struct list_head *plh;
  2052. struct qeth_buffer_pool_entry *entry;
  2053. int i, free;
  2054. struct page *page;
  2055. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2056. return NULL;
  2057. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2058. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2059. free = 1;
  2060. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2061. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2062. free = 0;
  2063. break;
  2064. }
  2065. }
  2066. if (free) {
  2067. list_del_init(&entry->list);
  2068. return entry;
  2069. }
  2070. }
  2071. /* no free buffer in pool so take first one and swap pages */
  2072. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2073. struct qeth_buffer_pool_entry, list);
  2074. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2075. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2076. page = alloc_page(GFP_ATOMIC);
  2077. if (!page) {
  2078. return NULL;
  2079. } else {
  2080. free_page((unsigned long)entry->elements[i]);
  2081. entry->elements[i] = page_address(page);
  2082. if (card->options.performance_stats)
  2083. card->perf_stats.sg_alloc_page_rx++;
  2084. }
  2085. }
  2086. }
  2087. list_del_init(&entry->list);
  2088. return entry;
  2089. }
  2090. static int qeth_init_input_buffer(struct qeth_card *card,
  2091. struct qeth_qdio_buffer *buf)
  2092. {
  2093. struct qeth_buffer_pool_entry *pool_entry;
  2094. int i;
  2095. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2096. if (!pool_entry)
  2097. return 1;
  2098. /*
  2099. * since the buffer is accessed only from the input_tasklet
  2100. * there shouldn't be a need to synchronize; also, since we use
  2101. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2102. * buffers
  2103. */
  2104. buf->pool_entry = pool_entry;
  2105. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2106. buf->buffer->element[i].length = PAGE_SIZE;
  2107. buf->buffer->element[i].addr = pool_entry->elements[i];
  2108. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2109. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2110. else
  2111. buf->buffer->element[i].flags = 0;
  2112. }
  2113. return 0;
  2114. }
  2115. int qeth_init_qdio_queues(struct qeth_card *card)
  2116. {
  2117. int i, j;
  2118. int rc;
  2119. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2120. /* inbound queue */
  2121. memset(card->qdio.in_q->qdio_bufs, 0,
  2122. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2123. qeth_initialize_working_pool_list(card);
  2124. /*give only as many buffers to hardware as we have buffer pool entries*/
  2125. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2126. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2127. card->qdio.in_q->next_buf_to_init =
  2128. card->qdio.in_buf_pool.buf_count - 1;
  2129. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2130. card->qdio.in_buf_pool.buf_count - 1);
  2131. if (rc) {
  2132. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2133. return rc;
  2134. }
  2135. /* outbound queue */
  2136. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2137. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2138. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2139. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2140. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2141. &card->qdio.out_qs[i]->bufs[j]);
  2142. }
  2143. card->qdio.out_qs[i]->card = card;
  2144. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2145. card->qdio.out_qs[i]->do_pack = 0;
  2146. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2147. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2148. atomic_set(&card->qdio.out_qs[i]->state,
  2149. QETH_OUT_Q_UNLOCKED);
  2150. }
  2151. return 0;
  2152. }
  2153. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2154. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2155. {
  2156. switch (link_type) {
  2157. case QETH_LINK_TYPE_HSTR:
  2158. return 2;
  2159. default:
  2160. return 1;
  2161. }
  2162. }
  2163. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2164. struct qeth_ipa_cmd *cmd, __u8 command,
  2165. enum qeth_prot_versions prot)
  2166. {
  2167. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2168. cmd->hdr.command = command;
  2169. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2170. cmd->hdr.seqno = card->seqno.ipa;
  2171. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2172. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2173. if (card->options.layer2)
  2174. cmd->hdr.prim_version_no = 2;
  2175. else
  2176. cmd->hdr.prim_version_no = 1;
  2177. cmd->hdr.param_count = 1;
  2178. cmd->hdr.prot_version = prot;
  2179. cmd->hdr.ipa_supported = 0;
  2180. cmd->hdr.ipa_enabled = 0;
  2181. }
  2182. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2183. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2184. {
  2185. struct qeth_cmd_buffer *iob;
  2186. struct qeth_ipa_cmd *cmd;
  2187. iob = qeth_wait_for_buffer(&card->write);
  2188. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2189. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2190. return iob;
  2191. }
  2192. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2193. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2194. char prot_type)
  2195. {
  2196. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2197. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2198. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2199. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2200. }
  2201. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2202. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2203. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2204. unsigned long),
  2205. void *reply_param)
  2206. {
  2207. int rc;
  2208. char prot_type;
  2209. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2210. if (card->options.layer2)
  2211. if (card->info.type == QETH_CARD_TYPE_OSN)
  2212. prot_type = QETH_PROT_OSN2;
  2213. else
  2214. prot_type = QETH_PROT_LAYER2;
  2215. else
  2216. prot_type = QETH_PROT_TCPIP;
  2217. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2218. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2219. iob, reply_cb, reply_param);
  2220. return rc;
  2221. }
  2222. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2223. static int qeth_send_startstoplan(struct qeth_card *card,
  2224. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2225. {
  2226. int rc;
  2227. struct qeth_cmd_buffer *iob;
  2228. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2229. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2230. return rc;
  2231. }
  2232. int qeth_send_startlan(struct qeth_card *card)
  2233. {
  2234. int rc;
  2235. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2236. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2237. return rc;
  2238. }
  2239. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2240. int qeth_send_stoplan(struct qeth_card *card)
  2241. {
  2242. int rc = 0;
  2243. /*
  2244. * TODO: according to the IPA format document page 14,
  2245. * TCP/IP (we!) never issue a STOPLAN
  2246. * is this right ?!?
  2247. */
  2248. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2249. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2250. return rc;
  2251. }
  2252. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2253. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2254. struct qeth_reply *reply, unsigned long data)
  2255. {
  2256. struct qeth_ipa_cmd *cmd;
  2257. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2258. cmd = (struct qeth_ipa_cmd *) data;
  2259. if (cmd->hdr.return_code == 0)
  2260. cmd->hdr.return_code =
  2261. cmd->data.setadapterparms.hdr.return_code;
  2262. return 0;
  2263. }
  2264. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2265. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2266. struct qeth_reply *reply, unsigned long data)
  2267. {
  2268. struct qeth_ipa_cmd *cmd;
  2269. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2270. cmd = (struct qeth_ipa_cmd *) data;
  2271. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2272. card->info.link_type =
  2273. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2274. card->options.adp.supported_funcs =
  2275. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2276. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2277. }
  2278. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2279. __u32 command, __u32 cmdlen)
  2280. {
  2281. struct qeth_cmd_buffer *iob;
  2282. struct qeth_ipa_cmd *cmd;
  2283. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2284. QETH_PROT_IPV4);
  2285. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2286. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2287. cmd->data.setadapterparms.hdr.command_code = command;
  2288. cmd->data.setadapterparms.hdr.used_total = 1;
  2289. cmd->data.setadapterparms.hdr.seq_no = 1;
  2290. return iob;
  2291. }
  2292. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2293. int qeth_query_setadapterparms(struct qeth_card *card)
  2294. {
  2295. int rc;
  2296. struct qeth_cmd_buffer *iob;
  2297. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2298. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2299. sizeof(struct qeth_ipacmd_setadpparms));
  2300. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2301. return rc;
  2302. }
  2303. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2304. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2305. unsigned int qdio_error, const char *dbftext)
  2306. {
  2307. if (qdio_error) {
  2308. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2309. QETH_DBF_TEXT(QERR, 2, dbftext);
  2310. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2311. buf->element[15].flags & 0xff);
  2312. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2313. buf->element[14].flags & 0xff);
  2314. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2315. if ((buf->element[15].flags & 0xff) == 0x12) {
  2316. card->stats.rx_dropped++;
  2317. return 0;
  2318. } else
  2319. return 1;
  2320. }
  2321. return 0;
  2322. }
  2323. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2324. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2325. {
  2326. struct qeth_qdio_q *queue = card->qdio.in_q;
  2327. int count;
  2328. int i;
  2329. int rc;
  2330. int newcount = 0;
  2331. count = (index < queue->next_buf_to_init)?
  2332. card->qdio.in_buf_pool.buf_count -
  2333. (queue->next_buf_to_init - index) :
  2334. card->qdio.in_buf_pool.buf_count -
  2335. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2336. /* only requeue at a certain threshold to avoid SIGAs */
  2337. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2338. for (i = queue->next_buf_to_init;
  2339. i < queue->next_buf_to_init + count; ++i) {
  2340. if (qeth_init_input_buffer(card,
  2341. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2342. break;
  2343. } else {
  2344. newcount++;
  2345. }
  2346. }
  2347. if (newcount < count) {
  2348. /* we are in memory shortage so we switch back to
  2349. traditional skb allocation and drop packages */
  2350. atomic_set(&card->force_alloc_skb, 3);
  2351. count = newcount;
  2352. } else {
  2353. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2354. }
  2355. /*
  2356. * according to old code it should be avoided to requeue all
  2357. * 128 buffers in order to benefit from PCI avoidance.
  2358. * this function keeps at least one buffer (the buffer at
  2359. * 'index') un-requeued -> this buffer is the first buffer that
  2360. * will be requeued the next time
  2361. */
  2362. if (card->options.performance_stats) {
  2363. card->perf_stats.inbound_do_qdio_cnt++;
  2364. card->perf_stats.inbound_do_qdio_start_time =
  2365. qeth_get_micros();
  2366. }
  2367. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2368. queue->next_buf_to_init, count);
  2369. if (card->options.performance_stats)
  2370. card->perf_stats.inbound_do_qdio_time +=
  2371. qeth_get_micros() -
  2372. card->perf_stats.inbound_do_qdio_start_time;
  2373. if (rc) {
  2374. dev_warn(&card->gdev->dev,
  2375. "QDIO reported an error, rc=%i\n", rc);
  2376. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2377. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2378. }
  2379. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2380. QDIO_MAX_BUFFERS_PER_Q;
  2381. }
  2382. }
  2383. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2384. static int qeth_handle_send_error(struct qeth_card *card,
  2385. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2386. {
  2387. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2388. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2389. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2390. if (sbalf15 == 0) {
  2391. qdio_err = 0;
  2392. } else {
  2393. qdio_err = 1;
  2394. }
  2395. }
  2396. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2397. if (!qdio_err)
  2398. return QETH_SEND_ERROR_NONE;
  2399. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2400. return QETH_SEND_ERROR_RETRY;
  2401. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2402. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2403. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2404. (u16)qdio_err, (u8)sbalf15);
  2405. return QETH_SEND_ERROR_LINK_FAILURE;
  2406. }
  2407. /*
  2408. * Switched to packing state if the number of used buffers on a queue
  2409. * reaches a certain limit.
  2410. */
  2411. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2412. {
  2413. if (!queue->do_pack) {
  2414. if (atomic_read(&queue->used_buffers)
  2415. >= QETH_HIGH_WATERMARK_PACK){
  2416. /* switch non-PACKING -> PACKING */
  2417. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2418. if (queue->card->options.performance_stats)
  2419. queue->card->perf_stats.sc_dp_p++;
  2420. queue->do_pack = 1;
  2421. }
  2422. }
  2423. }
  2424. /*
  2425. * Switches from packing to non-packing mode. If there is a packing
  2426. * buffer on the queue this buffer will be prepared to be flushed.
  2427. * In that case 1 is returned to inform the caller. If no buffer
  2428. * has to be flushed, zero is returned.
  2429. */
  2430. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2431. {
  2432. struct qeth_qdio_out_buffer *buffer;
  2433. int flush_count = 0;
  2434. if (queue->do_pack) {
  2435. if (atomic_read(&queue->used_buffers)
  2436. <= QETH_LOW_WATERMARK_PACK) {
  2437. /* switch PACKING -> non-PACKING */
  2438. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2439. if (queue->card->options.performance_stats)
  2440. queue->card->perf_stats.sc_p_dp++;
  2441. queue->do_pack = 0;
  2442. /* flush packing buffers */
  2443. buffer = &queue->bufs[queue->next_buf_to_fill];
  2444. if ((atomic_read(&buffer->state) ==
  2445. QETH_QDIO_BUF_EMPTY) &&
  2446. (buffer->next_element_to_fill > 0)) {
  2447. atomic_set(&buffer->state,
  2448. QETH_QDIO_BUF_PRIMED);
  2449. flush_count++;
  2450. queue->next_buf_to_fill =
  2451. (queue->next_buf_to_fill + 1) %
  2452. QDIO_MAX_BUFFERS_PER_Q;
  2453. }
  2454. }
  2455. }
  2456. return flush_count;
  2457. }
  2458. /*
  2459. * Called to flush a packing buffer if no more pci flags are on the queue.
  2460. * Checks if there is a packing buffer and prepares it to be flushed.
  2461. * In that case returns 1, otherwise zero.
  2462. */
  2463. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2464. {
  2465. struct qeth_qdio_out_buffer *buffer;
  2466. buffer = &queue->bufs[queue->next_buf_to_fill];
  2467. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2468. (buffer->next_element_to_fill > 0)) {
  2469. /* it's a packing buffer */
  2470. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2471. queue->next_buf_to_fill =
  2472. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2473. return 1;
  2474. }
  2475. return 0;
  2476. }
  2477. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2478. int count)
  2479. {
  2480. struct qeth_qdio_out_buffer *buf;
  2481. int rc;
  2482. int i;
  2483. unsigned int qdio_flags;
  2484. for (i = index; i < index + count; ++i) {
  2485. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2486. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2487. SBAL_FLAGS_LAST_ENTRY;
  2488. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2489. continue;
  2490. if (!queue->do_pack) {
  2491. if ((atomic_read(&queue->used_buffers) >=
  2492. (QETH_HIGH_WATERMARK_PACK -
  2493. QETH_WATERMARK_PACK_FUZZ)) &&
  2494. !atomic_read(&queue->set_pci_flags_count)) {
  2495. /* it's likely that we'll go to packing
  2496. * mode soon */
  2497. atomic_inc(&queue->set_pci_flags_count);
  2498. buf->buffer->element[0].flags |= 0x40;
  2499. }
  2500. } else {
  2501. if (!atomic_read(&queue->set_pci_flags_count)) {
  2502. /*
  2503. * there's no outstanding PCI any more, so we
  2504. * have to request a PCI to be sure the the PCI
  2505. * will wake at some time in the future then we
  2506. * can flush packed buffers that might still be
  2507. * hanging around, which can happen if no
  2508. * further send was requested by the stack
  2509. */
  2510. atomic_inc(&queue->set_pci_flags_count);
  2511. buf->buffer->element[0].flags |= 0x40;
  2512. }
  2513. }
  2514. }
  2515. queue->sync_iqdio_error = 0;
  2516. queue->card->dev->trans_start = jiffies;
  2517. if (queue->card->options.performance_stats) {
  2518. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2519. queue->card->perf_stats.outbound_do_qdio_start_time =
  2520. qeth_get_micros();
  2521. }
  2522. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2523. if (atomic_read(&queue->set_pci_flags_count))
  2524. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2525. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2526. queue->queue_no, index, count);
  2527. if (queue->card->options.performance_stats)
  2528. queue->card->perf_stats.outbound_do_qdio_time +=
  2529. qeth_get_micros() -
  2530. queue->card->perf_stats.outbound_do_qdio_start_time;
  2531. if (rc > 0) {
  2532. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2533. queue->sync_iqdio_error = rc & 3;
  2534. }
  2535. if (rc) {
  2536. queue->card->stats.tx_errors += count;
  2537. /* ignore temporary SIGA errors without busy condition */
  2538. if (rc == QDIO_ERROR_SIGA_TARGET)
  2539. return;
  2540. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2541. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2542. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2543. /* this must not happen under normal circumstances. if it
  2544. * happens something is really wrong -> recover */
  2545. qeth_schedule_recovery(queue->card);
  2546. return;
  2547. }
  2548. atomic_add(count, &queue->used_buffers);
  2549. if (queue->card->options.performance_stats)
  2550. queue->card->perf_stats.bufs_sent += count;
  2551. }
  2552. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2553. {
  2554. int index;
  2555. int flush_cnt = 0;
  2556. int q_was_packing = 0;
  2557. /*
  2558. * check if weed have to switch to non-packing mode or if
  2559. * we have to get a pci flag out on the queue
  2560. */
  2561. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2562. !atomic_read(&queue->set_pci_flags_count)) {
  2563. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2564. QETH_OUT_Q_UNLOCKED) {
  2565. /*
  2566. * If we get in here, there was no action in
  2567. * do_send_packet. So, we check if there is a
  2568. * packing buffer to be flushed here.
  2569. */
  2570. netif_stop_queue(queue->card->dev);
  2571. index = queue->next_buf_to_fill;
  2572. q_was_packing = queue->do_pack;
  2573. /* queue->do_pack may change */
  2574. barrier();
  2575. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2576. if (!flush_cnt &&
  2577. !atomic_read(&queue->set_pci_flags_count))
  2578. flush_cnt +=
  2579. qeth_flush_buffers_on_no_pci(queue);
  2580. if (queue->card->options.performance_stats &&
  2581. q_was_packing)
  2582. queue->card->perf_stats.bufs_sent_pack +=
  2583. flush_cnt;
  2584. if (flush_cnt)
  2585. qeth_flush_buffers(queue, index, flush_cnt);
  2586. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2587. }
  2588. }
  2589. }
  2590. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2591. unsigned int qdio_error, int __queue, int first_element,
  2592. int count, unsigned long card_ptr)
  2593. {
  2594. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2595. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2596. struct qeth_qdio_out_buffer *buffer;
  2597. int i;
  2598. unsigned qeth_send_err;
  2599. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2600. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2601. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2602. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2603. netif_stop_queue(card->dev);
  2604. qeth_schedule_recovery(card);
  2605. return;
  2606. }
  2607. if (card->options.performance_stats) {
  2608. card->perf_stats.outbound_handler_cnt++;
  2609. card->perf_stats.outbound_handler_start_time =
  2610. qeth_get_micros();
  2611. }
  2612. for (i = first_element; i < (first_element + count); ++i) {
  2613. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2614. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2615. __qeth_clear_output_buffer(queue, buffer,
  2616. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2617. }
  2618. atomic_sub(count, &queue->used_buffers);
  2619. /* check if we need to do something on this outbound queue */
  2620. if (card->info.type != QETH_CARD_TYPE_IQD)
  2621. qeth_check_outbound_queue(queue);
  2622. netif_wake_queue(queue->card->dev);
  2623. if (card->options.performance_stats)
  2624. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2625. card->perf_stats.outbound_handler_start_time;
  2626. }
  2627. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2628. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2629. int ipv, int cast_type)
  2630. {
  2631. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2632. return card->qdio.default_out_queue;
  2633. switch (card->qdio.no_out_queues) {
  2634. case 4:
  2635. if (cast_type && card->info.is_multicast_different)
  2636. return card->info.is_multicast_different &
  2637. (card->qdio.no_out_queues - 1);
  2638. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2639. const u8 tos = ip_hdr(skb)->tos;
  2640. if (card->qdio.do_prio_queueing ==
  2641. QETH_PRIO_Q_ING_TOS) {
  2642. if (tos & IP_TOS_NOTIMPORTANT)
  2643. return 3;
  2644. if (tos & IP_TOS_HIGHRELIABILITY)
  2645. return 2;
  2646. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2647. return 1;
  2648. if (tos & IP_TOS_LOWDELAY)
  2649. return 0;
  2650. }
  2651. if (card->qdio.do_prio_queueing ==
  2652. QETH_PRIO_Q_ING_PREC)
  2653. return 3 - (tos >> 6);
  2654. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2655. /* TODO: IPv6!!! */
  2656. }
  2657. return card->qdio.default_out_queue;
  2658. case 1: /* fallthrough for single-out-queue 1920-device */
  2659. default:
  2660. return card->qdio.default_out_queue;
  2661. }
  2662. }
  2663. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2664. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2665. struct sk_buff *skb, int elems)
  2666. {
  2667. int elements_needed = 0;
  2668. if (skb_shinfo(skb)->nr_frags > 0)
  2669. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2670. if (elements_needed == 0)
  2671. elements_needed = 1 + (((((unsigned long) skb->data) %
  2672. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2673. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2674. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2675. "(Number=%d / Length=%d). Discarded.\n",
  2676. (elements_needed+elems), skb->len);
  2677. return 0;
  2678. }
  2679. return elements_needed;
  2680. }
  2681. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2682. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2683. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2684. int offset)
  2685. {
  2686. int length = skb->len;
  2687. int length_here;
  2688. int element;
  2689. char *data;
  2690. int first_lap ;
  2691. element = *next_element_to_fill;
  2692. data = skb->data;
  2693. first_lap = (is_tso == 0 ? 1 : 0);
  2694. if (offset >= 0) {
  2695. data = skb->data + offset;
  2696. length -= offset;
  2697. first_lap = 0;
  2698. }
  2699. while (length > 0) {
  2700. /* length_here is the remaining amount of data in this page */
  2701. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2702. if (length < length_here)
  2703. length_here = length;
  2704. buffer->element[element].addr = data;
  2705. buffer->element[element].length = length_here;
  2706. length -= length_here;
  2707. if (!length) {
  2708. if (first_lap)
  2709. buffer->element[element].flags = 0;
  2710. else
  2711. buffer->element[element].flags =
  2712. SBAL_FLAGS_LAST_FRAG;
  2713. } else {
  2714. if (first_lap)
  2715. buffer->element[element].flags =
  2716. SBAL_FLAGS_FIRST_FRAG;
  2717. else
  2718. buffer->element[element].flags =
  2719. SBAL_FLAGS_MIDDLE_FRAG;
  2720. }
  2721. data += length_here;
  2722. element++;
  2723. first_lap = 0;
  2724. }
  2725. *next_element_to_fill = element;
  2726. }
  2727. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2728. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2729. struct qeth_hdr *hdr, int offset, int hd_len)
  2730. {
  2731. struct qdio_buffer *buffer;
  2732. int flush_cnt = 0, hdr_len, large_send = 0;
  2733. buffer = buf->buffer;
  2734. atomic_inc(&skb->users);
  2735. skb_queue_tail(&buf->skb_list, skb);
  2736. /*check first on TSO ....*/
  2737. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2738. int element = buf->next_element_to_fill;
  2739. hdr_len = sizeof(struct qeth_hdr_tso) +
  2740. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2741. /*fill first buffer entry only with header information */
  2742. buffer->element[element].addr = skb->data;
  2743. buffer->element[element].length = hdr_len;
  2744. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2745. buf->next_element_to_fill++;
  2746. skb->data += hdr_len;
  2747. skb->len -= hdr_len;
  2748. large_send = 1;
  2749. }
  2750. if (offset >= 0) {
  2751. int element = buf->next_element_to_fill;
  2752. buffer->element[element].addr = hdr;
  2753. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2754. hd_len;
  2755. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2756. buf->is_header[element] = 1;
  2757. buf->next_element_to_fill++;
  2758. }
  2759. if (skb_shinfo(skb)->nr_frags == 0)
  2760. __qeth_fill_buffer(skb, buffer, large_send,
  2761. (int *)&buf->next_element_to_fill, offset);
  2762. else
  2763. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2764. (int *)&buf->next_element_to_fill);
  2765. if (!queue->do_pack) {
  2766. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2767. /* set state to PRIMED -> will be flushed */
  2768. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2769. flush_cnt = 1;
  2770. } else {
  2771. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2772. if (queue->card->options.performance_stats)
  2773. queue->card->perf_stats.skbs_sent_pack++;
  2774. if (buf->next_element_to_fill >=
  2775. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2776. /*
  2777. * packed buffer if full -> set state PRIMED
  2778. * -> will be flushed
  2779. */
  2780. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2781. flush_cnt = 1;
  2782. }
  2783. }
  2784. return flush_cnt;
  2785. }
  2786. int qeth_do_send_packet_fast(struct qeth_card *card,
  2787. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2788. struct qeth_hdr *hdr, int elements_needed,
  2789. int offset, int hd_len)
  2790. {
  2791. struct qeth_qdio_out_buffer *buffer;
  2792. struct sk_buff *skb1;
  2793. struct qeth_skb_data *retry_ctrl;
  2794. int index;
  2795. int rc;
  2796. /* spin until we get the queue ... */
  2797. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2798. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2799. /* ... now we've got the queue */
  2800. index = queue->next_buf_to_fill;
  2801. buffer = &queue->bufs[queue->next_buf_to_fill];
  2802. /*
  2803. * check if buffer is empty to make sure that we do not 'overtake'
  2804. * ourselves and try to fill a buffer that is already primed
  2805. */
  2806. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2807. goto out;
  2808. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2809. QDIO_MAX_BUFFERS_PER_Q;
  2810. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2811. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2812. qeth_flush_buffers(queue, index, 1);
  2813. if (queue->sync_iqdio_error == 2) {
  2814. skb1 = skb_dequeue(&buffer->skb_list);
  2815. while (skb1) {
  2816. atomic_dec(&skb1->users);
  2817. skb1 = skb_dequeue(&buffer->skb_list);
  2818. }
  2819. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2820. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2821. retry_ctrl->magic = QETH_SKB_MAGIC;
  2822. retry_ctrl->count = 0;
  2823. }
  2824. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2825. retry_ctrl->count++;
  2826. rc = dev_queue_xmit(skb);
  2827. } else {
  2828. dev_kfree_skb_any(skb);
  2829. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2830. }
  2831. }
  2832. return 0;
  2833. out:
  2834. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2835. return -EBUSY;
  2836. }
  2837. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2838. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2839. struct sk_buff *skb, struct qeth_hdr *hdr,
  2840. int elements_needed)
  2841. {
  2842. struct qeth_qdio_out_buffer *buffer;
  2843. int start_index;
  2844. int flush_count = 0;
  2845. int do_pack = 0;
  2846. int tmp;
  2847. int rc = 0;
  2848. /* spin until we get the queue ... */
  2849. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2850. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2851. start_index = queue->next_buf_to_fill;
  2852. buffer = &queue->bufs[queue->next_buf_to_fill];
  2853. /*
  2854. * check if buffer is empty to make sure that we do not 'overtake'
  2855. * ourselves and try to fill a buffer that is already primed
  2856. */
  2857. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2858. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2859. return -EBUSY;
  2860. }
  2861. /* check if we need to switch packing state of this queue */
  2862. qeth_switch_to_packing_if_needed(queue);
  2863. if (queue->do_pack) {
  2864. do_pack = 1;
  2865. /* does packet fit in current buffer? */
  2866. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2867. buffer->next_element_to_fill) < elements_needed) {
  2868. /* ... no -> set state PRIMED */
  2869. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2870. flush_count++;
  2871. queue->next_buf_to_fill =
  2872. (queue->next_buf_to_fill + 1) %
  2873. QDIO_MAX_BUFFERS_PER_Q;
  2874. buffer = &queue->bufs[queue->next_buf_to_fill];
  2875. /* we did a step forward, so check buffer state
  2876. * again */
  2877. if (atomic_read(&buffer->state) !=
  2878. QETH_QDIO_BUF_EMPTY) {
  2879. qeth_flush_buffers(queue, start_index,
  2880. flush_count);
  2881. atomic_set(&queue->state,
  2882. QETH_OUT_Q_UNLOCKED);
  2883. return -EBUSY;
  2884. }
  2885. }
  2886. }
  2887. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2888. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2889. QDIO_MAX_BUFFERS_PER_Q;
  2890. flush_count += tmp;
  2891. if (flush_count)
  2892. qeth_flush_buffers(queue, start_index, flush_count);
  2893. else if (!atomic_read(&queue->set_pci_flags_count))
  2894. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2895. /*
  2896. * queue->state will go from LOCKED -> UNLOCKED or from
  2897. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2898. * (switch packing state or flush buffer to get another pci flag out).
  2899. * In that case we will enter this loop
  2900. */
  2901. while (atomic_dec_return(&queue->state)) {
  2902. flush_count = 0;
  2903. start_index = queue->next_buf_to_fill;
  2904. /* check if we can go back to non-packing state */
  2905. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2906. /*
  2907. * check if we need to flush a packing buffer to get a pci
  2908. * flag out on the queue
  2909. */
  2910. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2911. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2912. if (flush_count)
  2913. qeth_flush_buffers(queue, start_index, flush_count);
  2914. }
  2915. /* at this point the queue is UNLOCKED again */
  2916. if (queue->card->options.performance_stats && do_pack)
  2917. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2918. return rc;
  2919. }
  2920. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2921. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2922. struct qeth_reply *reply, unsigned long data)
  2923. {
  2924. struct qeth_ipa_cmd *cmd;
  2925. struct qeth_ipacmd_setadpparms *setparms;
  2926. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2927. cmd = (struct qeth_ipa_cmd *) data;
  2928. setparms = &(cmd->data.setadapterparms);
  2929. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2930. if (cmd->hdr.return_code) {
  2931. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2932. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2933. }
  2934. card->info.promisc_mode = setparms->data.mode;
  2935. return 0;
  2936. }
  2937. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2938. {
  2939. enum qeth_ipa_promisc_modes mode;
  2940. struct net_device *dev = card->dev;
  2941. struct qeth_cmd_buffer *iob;
  2942. struct qeth_ipa_cmd *cmd;
  2943. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2944. if (((dev->flags & IFF_PROMISC) &&
  2945. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2946. (!(dev->flags & IFF_PROMISC) &&
  2947. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2948. return;
  2949. mode = SET_PROMISC_MODE_OFF;
  2950. if (dev->flags & IFF_PROMISC)
  2951. mode = SET_PROMISC_MODE_ON;
  2952. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2953. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2954. sizeof(struct qeth_ipacmd_setadpparms));
  2955. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2956. cmd->data.setadapterparms.data.mode = mode;
  2957. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2958. }
  2959. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2960. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2961. {
  2962. struct qeth_card *card;
  2963. char dbf_text[15];
  2964. card = dev->ml_priv;
  2965. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2966. sprintf(dbf_text, "%8x", new_mtu);
  2967. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2968. if (new_mtu < 64)
  2969. return -EINVAL;
  2970. if (new_mtu > 65535)
  2971. return -EINVAL;
  2972. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2973. (!qeth_mtu_is_valid(card, new_mtu)))
  2974. return -EINVAL;
  2975. dev->mtu = new_mtu;
  2976. return 0;
  2977. }
  2978. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2979. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2980. {
  2981. struct qeth_card *card;
  2982. card = dev->ml_priv;
  2983. QETH_DBF_TEXT(TRACE, 5, "getstat");
  2984. return &card->stats;
  2985. }
  2986. EXPORT_SYMBOL_GPL(qeth_get_stats);
  2987. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  2988. struct qeth_reply *reply, unsigned long data)
  2989. {
  2990. struct qeth_ipa_cmd *cmd;
  2991. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  2992. cmd = (struct qeth_ipa_cmd *) data;
  2993. if (!card->options.layer2 ||
  2994. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  2995. memcpy(card->dev->dev_addr,
  2996. &cmd->data.setadapterparms.data.change_addr.addr,
  2997. OSA_ADDR_LEN);
  2998. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  2999. }
  3000. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3001. return 0;
  3002. }
  3003. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3004. {
  3005. int rc;
  3006. struct qeth_cmd_buffer *iob;
  3007. struct qeth_ipa_cmd *cmd;
  3008. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3009. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3010. sizeof(struct qeth_ipacmd_setadpparms));
  3011. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3012. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3013. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3014. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3015. card->dev->dev_addr, OSA_ADDR_LEN);
  3016. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3017. NULL);
  3018. return rc;
  3019. }
  3020. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3021. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3022. struct qeth_reply *reply, unsigned long data)
  3023. {
  3024. struct qeth_ipa_cmd *cmd;
  3025. struct qeth_set_access_ctrl *access_ctrl_req;
  3026. int rc;
  3027. QETH_DBF_TEXT(TRACE, 4, "setaccb");
  3028. cmd = (struct qeth_ipa_cmd *) data;
  3029. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3030. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3031. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3032. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3033. cmd->data.setadapterparms.hdr.return_code);
  3034. switch (cmd->data.setadapterparms.hdr.return_code) {
  3035. case SET_ACCESS_CTRL_RC_SUCCESS:
  3036. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3037. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3038. {
  3039. card->options.isolation = access_ctrl_req->subcmd_code;
  3040. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3041. dev_info(&card->gdev->dev,
  3042. "QDIO data connection isolation is deactivated\n");
  3043. } else {
  3044. dev_info(&card->gdev->dev,
  3045. "QDIO data connection isolation is activated\n");
  3046. }
  3047. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3048. card->gdev->dev.kobj.name,
  3049. access_ctrl_req->subcmd_code,
  3050. cmd->data.setadapterparms.hdr.return_code);
  3051. rc = 0;
  3052. break;
  3053. }
  3054. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3055. {
  3056. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3057. card->gdev->dev.kobj.name,
  3058. access_ctrl_req->subcmd_code,
  3059. cmd->data.setadapterparms.hdr.return_code);
  3060. dev_err(&card->gdev->dev, "Adapter does not "
  3061. "support QDIO data connection isolation\n");
  3062. /* ensure isolation mode is "none" */
  3063. card->options.isolation = ISOLATION_MODE_NONE;
  3064. rc = -EOPNOTSUPP;
  3065. break;
  3066. }
  3067. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3068. {
  3069. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3070. card->gdev->dev.kobj.name,
  3071. access_ctrl_req->subcmd_code,
  3072. cmd->data.setadapterparms.hdr.return_code);
  3073. dev_err(&card->gdev->dev,
  3074. "Adapter is dedicated. "
  3075. "QDIO data connection isolation not supported\n");
  3076. /* ensure isolation mode is "none" */
  3077. card->options.isolation = ISOLATION_MODE_NONE;
  3078. rc = -EOPNOTSUPP;
  3079. break;
  3080. }
  3081. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3082. {
  3083. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3084. card->gdev->dev.kobj.name,
  3085. access_ctrl_req->subcmd_code,
  3086. cmd->data.setadapterparms.hdr.return_code);
  3087. dev_err(&card->gdev->dev,
  3088. "TSO does not permit QDIO data connection isolation\n");
  3089. /* ensure isolation mode is "none" */
  3090. card->options.isolation = ISOLATION_MODE_NONE;
  3091. rc = -EPERM;
  3092. break;
  3093. }
  3094. default:
  3095. {
  3096. /* this should never happen */
  3097. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3098. "==UNKNOWN\n",
  3099. card->gdev->dev.kobj.name,
  3100. access_ctrl_req->subcmd_code,
  3101. cmd->data.setadapterparms.hdr.return_code);
  3102. /* ensure isolation mode is "none" */
  3103. card->options.isolation = ISOLATION_MODE_NONE;
  3104. rc = 0;
  3105. break;
  3106. }
  3107. }
  3108. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3109. return rc;
  3110. }
  3111. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3112. enum qeth_ipa_isolation_modes isolation)
  3113. {
  3114. int rc;
  3115. struct qeth_cmd_buffer *iob;
  3116. struct qeth_ipa_cmd *cmd;
  3117. struct qeth_set_access_ctrl *access_ctrl_req;
  3118. QETH_DBF_TEXT(TRACE, 4, "setacctl");
  3119. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3120. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3121. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3122. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3123. sizeof(struct qeth_set_access_ctrl));
  3124. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3125. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3126. access_ctrl_req->subcmd_code = isolation;
  3127. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3128. NULL);
  3129. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3130. return rc;
  3131. }
  3132. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3133. {
  3134. int rc = 0;
  3135. QETH_DBF_TEXT(TRACE, 4, "setactlo");
  3136. if (card->info.type == QETH_CARD_TYPE_OSAE &&
  3137. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3138. rc = qeth_setadpparms_set_access_ctrl(card,
  3139. card->options.isolation);
  3140. if (rc) {
  3141. QETH_DBF_MESSAGE(3,
  3142. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed",
  3143. card->gdev->dev.kobj.name,
  3144. rc);
  3145. }
  3146. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3147. card->options.isolation = ISOLATION_MODE_NONE;
  3148. dev_err(&card->gdev->dev, "Adapter does not "
  3149. "support QDIO data connection isolation\n");
  3150. rc = -EOPNOTSUPP;
  3151. }
  3152. return rc;
  3153. }
  3154. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3155. void qeth_tx_timeout(struct net_device *dev)
  3156. {
  3157. struct qeth_card *card;
  3158. QETH_DBF_TEXT(TRACE, 4, "txtimeo");
  3159. card = dev->ml_priv;
  3160. card->stats.tx_errors++;
  3161. qeth_schedule_recovery(card);
  3162. }
  3163. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3164. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3165. {
  3166. struct qeth_card *card = dev->ml_priv;
  3167. int rc = 0;
  3168. switch (regnum) {
  3169. case MII_BMCR: /* Basic mode control register */
  3170. rc = BMCR_FULLDPLX;
  3171. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3172. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3173. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3174. rc |= BMCR_SPEED100;
  3175. break;
  3176. case MII_BMSR: /* Basic mode status register */
  3177. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3178. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3179. BMSR_100BASE4;
  3180. break;
  3181. case MII_PHYSID1: /* PHYS ID 1 */
  3182. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3183. dev->dev_addr[2];
  3184. rc = (rc >> 5) & 0xFFFF;
  3185. break;
  3186. case MII_PHYSID2: /* PHYS ID 2 */
  3187. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3188. break;
  3189. case MII_ADVERTISE: /* Advertisement control reg */
  3190. rc = ADVERTISE_ALL;
  3191. break;
  3192. case MII_LPA: /* Link partner ability reg */
  3193. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3194. LPA_100BASE4 | LPA_LPACK;
  3195. break;
  3196. case MII_EXPANSION: /* Expansion register */
  3197. break;
  3198. case MII_DCOUNTER: /* disconnect counter */
  3199. break;
  3200. case MII_FCSCOUNTER: /* false carrier counter */
  3201. break;
  3202. case MII_NWAYTEST: /* N-way auto-neg test register */
  3203. break;
  3204. case MII_RERRCOUNTER: /* rx error counter */
  3205. rc = card->stats.rx_errors;
  3206. break;
  3207. case MII_SREVISION: /* silicon revision */
  3208. break;
  3209. case MII_RESV1: /* reserved 1 */
  3210. break;
  3211. case MII_LBRERROR: /* loopback, rx, bypass error */
  3212. break;
  3213. case MII_PHYADDR: /* physical address */
  3214. break;
  3215. case MII_RESV2: /* reserved 2 */
  3216. break;
  3217. case MII_TPISTATUS: /* TPI status for 10mbps */
  3218. break;
  3219. case MII_NCONFIG: /* network interface config */
  3220. break;
  3221. default:
  3222. break;
  3223. }
  3224. return rc;
  3225. }
  3226. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3227. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3228. struct qeth_cmd_buffer *iob, int len,
  3229. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3230. unsigned long),
  3231. void *reply_param)
  3232. {
  3233. u16 s1, s2;
  3234. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3235. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3236. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3237. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3238. /* adjust PDU length fields in IPA_PDU_HEADER */
  3239. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3240. s2 = (u32) len;
  3241. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3242. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3243. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3244. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3245. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3246. reply_cb, reply_param);
  3247. }
  3248. static int qeth_snmp_command_cb(struct qeth_card *card,
  3249. struct qeth_reply *reply, unsigned long sdata)
  3250. {
  3251. struct qeth_ipa_cmd *cmd;
  3252. struct qeth_arp_query_info *qinfo;
  3253. struct qeth_snmp_cmd *snmp;
  3254. unsigned char *data;
  3255. __u16 data_len;
  3256. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3257. cmd = (struct qeth_ipa_cmd *) sdata;
  3258. data = (unsigned char *)((char *)cmd - reply->offset);
  3259. qinfo = (struct qeth_arp_query_info *) reply->param;
  3260. snmp = &cmd->data.setadapterparms.data.snmp;
  3261. if (cmd->hdr.return_code) {
  3262. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3263. return 0;
  3264. }
  3265. if (cmd->data.setadapterparms.hdr.return_code) {
  3266. cmd->hdr.return_code =
  3267. cmd->data.setadapterparms.hdr.return_code;
  3268. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3269. return 0;
  3270. }
  3271. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3272. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3273. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3274. else
  3275. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3276. /* check if there is enough room in userspace */
  3277. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3278. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3279. cmd->hdr.return_code = -ENOMEM;
  3280. return 0;
  3281. }
  3282. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3283. cmd->data.setadapterparms.hdr.used_total);
  3284. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3285. cmd->data.setadapterparms.hdr.seq_no);
  3286. /*copy entries to user buffer*/
  3287. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3288. memcpy(qinfo->udata + qinfo->udata_offset,
  3289. (char *)snmp,
  3290. data_len + offsetof(struct qeth_snmp_cmd, data));
  3291. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3292. } else {
  3293. memcpy(qinfo->udata + qinfo->udata_offset,
  3294. (char *)&snmp->request, data_len);
  3295. }
  3296. qinfo->udata_offset += data_len;
  3297. /* check if all replies received ... */
  3298. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3299. cmd->data.setadapterparms.hdr.used_total);
  3300. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3301. cmd->data.setadapterparms.hdr.seq_no);
  3302. if (cmd->data.setadapterparms.hdr.seq_no <
  3303. cmd->data.setadapterparms.hdr.used_total)
  3304. return 1;
  3305. return 0;
  3306. }
  3307. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3308. {
  3309. struct qeth_cmd_buffer *iob;
  3310. struct qeth_ipa_cmd *cmd;
  3311. struct qeth_snmp_ureq *ureq;
  3312. int req_len;
  3313. struct qeth_arp_query_info qinfo = {0, };
  3314. int rc = 0;
  3315. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3316. if (card->info.guestlan)
  3317. return -EOPNOTSUPP;
  3318. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3319. (!card->options.layer2)) {
  3320. return -EOPNOTSUPP;
  3321. }
  3322. /* skip 4 bytes (data_len struct member) to get req_len */
  3323. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3324. return -EFAULT;
  3325. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3326. if (!ureq) {
  3327. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3328. return -ENOMEM;
  3329. }
  3330. if (copy_from_user(ureq, udata,
  3331. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3332. kfree(ureq);
  3333. return -EFAULT;
  3334. }
  3335. qinfo.udata_len = ureq->hdr.data_len;
  3336. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3337. if (!qinfo.udata) {
  3338. kfree(ureq);
  3339. return -ENOMEM;
  3340. }
  3341. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3342. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3343. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3344. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3345. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3346. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3347. qeth_snmp_command_cb, (void *)&qinfo);
  3348. if (rc)
  3349. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3350. QETH_CARD_IFNAME(card), rc);
  3351. else {
  3352. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3353. rc = -EFAULT;
  3354. }
  3355. kfree(ureq);
  3356. kfree(qinfo.udata);
  3357. return rc;
  3358. }
  3359. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3360. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3361. {
  3362. switch (card->info.type) {
  3363. case QETH_CARD_TYPE_IQD:
  3364. return 2;
  3365. default:
  3366. return 0;
  3367. }
  3368. }
  3369. static int qeth_qdio_establish(struct qeth_card *card)
  3370. {
  3371. struct qdio_initialize init_data;
  3372. char *qib_param_field;
  3373. struct qdio_buffer **in_sbal_ptrs;
  3374. struct qdio_buffer **out_sbal_ptrs;
  3375. int i, j, k;
  3376. int rc = 0;
  3377. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3378. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3379. GFP_KERNEL);
  3380. if (!qib_param_field)
  3381. return -ENOMEM;
  3382. qeth_create_qib_param_field(card, qib_param_field);
  3383. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3384. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3385. GFP_KERNEL);
  3386. if (!in_sbal_ptrs) {
  3387. kfree(qib_param_field);
  3388. return -ENOMEM;
  3389. }
  3390. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3391. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3392. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3393. out_sbal_ptrs =
  3394. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3395. sizeof(void *), GFP_KERNEL);
  3396. if (!out_sbal_ptrs) {
  3397. kfree(in_sbal_ptrs);
  3398. kfree(qib_param_field);
  3399. return -ENOMEM;
  3400. }
  3401. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3402. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3403. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3404. card->qdio.out_qs[i]->bufs[j].buffer);
  3405. }
  3406. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3407. init_data.cdev = CARD_DDEV(card);
  3408. init_data.q_format = qeth_get_qdio_q_format(card);
  3409. init_data.qib_param_field_format = 0;
  3410. init_data.qib_param_field = qib_param_field;
  3411. init_data.no_input_qs = 1;
  3412. init_data.no_output_qs = card->qdio.no_out_queues;
  3413. init_data.input_handler = card->discipline.input_handler;
  3414. init_data.output_handler = card->discipline.output_handler;
  3415. init_data.int_parm = (unsigned long) card;
  3416. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3417. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3418. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3419. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3420. rc = qdio_initialize(&init_data);
  3421. if (rc)
  3422. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3423. }
  3424. kfree(out_sbal_ptrs);
  3425. kfree(in_sbal_ptrs);
  3426. kfree(qib_param_field);
  3427. return rc;
  3428. }
  3429. static void qeth_core_free_card(struct qeth_card *card)
  3430. {
  3431. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3432. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3433. qeth_clean_channel(&card->read);
  3434. qeth_clean_channel(&card->write);
  3435. if (card->dev)
  3436. free_netdev(card->dev);
  3437. kfree(card->ip_tbd_list);
  3438. qeth_free_qdio_buffers(card);
  3439. unregister_service_level(&card->qeth_service_level);
  3440. kfree(card);
  3441. }
  3442. static struct ccw_device_id qeth_ids[] = {
  3443. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3444. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3445. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3446. {},
  3447. };
  3448. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3449. static struct ccw_driver qeth_ccw_driver = {
  3450. .name = "qeth",
  3451. .ids = qeth_ids,
  3452. .probe = ccwgroup_probe_ccwdev,
  3453. .remove = ccwgroup_remove_ccwdev,
  3454. };
  3455. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3456. unsigned long driver_id)
  3457. {
  3458. return ccwgroup_create_from_string(root_dev, driver_id,
  3459. &qeth_ccw_driver, 3, buf);
  3460. }
  3461. int qeth_core_hardsetup_card(struct qeth_card *card)
  3462. {
  3463. int retries = 0;
  3464. int rc;
  3465. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3466. atomic_set(&card->force_alloc_skb, 0);
  3467. retry:
  3468. if (retries)
  3469. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3470. dev_name(&card->gdev->dev));
  3471. ccw_device_set_offline(CARD_DDEV(card));
  3472. ccw_device_set_offline(CARD_WDEV(card));
  3473. ccw_device_set_offline(CARD_RDEV(card));
  3474. rc = ccw_device_set_online(CARD_RDEV(card));
  3475. if (rc)
  3476. goto retriable;
  3477. rc = ccw_device_set_online(CARD_WDEV(card));
  3478. if (rc)
  3479. goto retriable;
  3480. rc = ccw_device_set_online(CARD_DDEV(card));
  3481. if (rc)
  3482. goto retriable;
  3483. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3484. retriable:
  3485. if (rc == -ERESTARTSYS) {
  3486. QETH_DBF_TEXT(SETUP, 2, "break1");
  3487. return rc;
  3488. } else if (rc) {
  3489. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3490. if (++retries > 3)
  3491. goto out;
  3492. else
  3493. goto retry;
  3494. }
  3495. qeth_init_tokens(card);
  3496. qeth_init_func_level(card);
  3497. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3498. if (rc == -ERESTARTSYS) {
  3499. QETH_DBF_TEXT(SETUP, 2, "break2");
  3500. return rc;
  3501. } else if (rc) {
  3502. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3503. if (--retries < 0)
  3504. goto out;
  3505. else
  3506. goto retry;
  3507. }
  3508. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3509. if (rc == -ERESTARTSYS) {
  3510. QETH_DBF_TEXT(SETUP, 2, "break3");
  3511. return rc;
  3512. } else if (rc) {
  3513. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3514. if (--retries < 0)
  3515. goto out;
  3516. else
  3517. goto retry;
  3518. }
  3519. rc = qeth_mpc_initialize(card);
  3520. if (rc) {
  3521. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3522. goto out;
  3523. }
  3524. return 0;
  3525. out:
  3526. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3527. "an error on the device\n");
  3528. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3529. dev_name(&card->gdev->dev), rc);
  3530. return rc;
  3531. }
  3532. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3533. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3534. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3535. {
  3536. struct page *page = virt_to_page(element->addr);
  3537. if (*pskb == NULL) {
  3538. /* the upper protocol layers assume that there is data in the
  3539. * skb itself. Copy a small amount (64 bytes) to make them
  3540. * happy. */
  3541. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3542. if (!(*pskb))
  3543. return -ENOMEM;
  3544. skb_reserve(*pskb, ETH_HLEN);
  3545. if (data_len <= 64) {
  3546. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3547. data_len);
  3548. } else {
  3549. get_page(page);
  3550. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3551. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3552. data_len - 64);
  3553. (*pskb)->data_len += data_len - 64;
  3554. (*pskb)->len += data_len - 64;
  3555. (*pskb)->truesize += data_len - 64;
  3556. (*pfrag)++;
  3557. }
  3558. } else {
  3559. get_page(page);
  3560. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3561. (*pskb)->data_len += data_len;
  3562. (*pskb)->len += data_len;
  3563. (*pskb)->truesize += data_len;
  3564. (*pfrag)++;
  3565. }
  3566. return 0;
  3567. }
  3568. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3569. struct qdio_buffer *buffer,
  3570. struct qdio_buffer_element **__element, int *__offset,
  3571. struct qeth_hdr **hdr)
  3572. {
  3573. struct qdio_buffer_element *element = *__element;
  3574. int offset = *__offset;
  3575. struct sk_buff *skb = NULL;
  3576. int skb_len = 0;
  3577. void *data_ptr;
  3578. int data_len;
  3579. int headroom = 0;
  3580. int use_rx_sg = 0;
  3581. int frag = 0;
  3582. /* qeth_hdr must not cross element boundaries */
  3583. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3584. if (qeth_is_last_sbale(element))
  3585. return NULL;
  3586. element++;
  3587. offset = 0;
  3588. if (element->length < sizeof(struct qeth_hdr))
  3589. return NULL;
  3590. }
  3591. *hdr = element->addr + offset;
  3592. offset += sizeof(struct qeth_hdr);
  3593. switch ((*hdr)->hdr.l2.id) {
  3594. case QETH_HEADER_TYPE_LAYER2:
  3595. skb_len = (*hdr)->hdr.l2.pkt_length;
  3596. break;
  3597. case QETH_HEADER_TYPE_LAYER3:
  3598. skb_len = (*hdr)->hdr.l3.length;
  3599. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3600. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3601. headroom = TR_HLEN;
  3602. else
  3603. headroom = ETH_HLEN;
  3604. break;
  3605. case QETH_HEADER_TYPE_OSN:
  3606. skb_len = (*hdr)->hdr.osn.pdu_length;
  3607. headroom = sizeof(struct qeth_hdr);
  3608. break;
  3609. default:
  3610. break;
  3611. }
  3612. if (!skb_len)
  3613. return NULL;
  3614. if ((skb_len >= card->options.rx_sg_cb) &&
  3615. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3616. (!atomic_read(&card->force_alloc_skb))) {
  3617. use_rx_sg = 1;
  3618. } else {
  3619. skb = dev_alloc_skb(skb_len + headroom);
  3620. if (!skb)
  3621. goto no_mem;
  3622. if (headroom)
  3623. skb_reserve(skb, headroom);
  3624. }
  3625. data_ptr = element->addr + offset;
  3626. while (skb_len) {
  3627. data_len = min(skb_len, (int)(element->length - offset));
  3628. if (data_len) {
  3629. if (use_rx_sg) {
  3630. if (qeth_create_skb_frag(element, &skb, offset,
  3631. &frag, data_len))
  3632. goto no_mem;
  3633. } else {
  3634. memcpy(skb_put(skb, data_len), data_ptr,
  3635. data_len);
  3636. }
  3637. }
  3638. skb_len -= data_len;
  3639. if (skb_len) {
  3640. if (qeth_is_last_sbale(element)) {
  3641. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3642. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3643. CARD_BUS_ID(card));
  3644. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3645. QETH_DBF_TEXT_(QERR, 2, "%s",
  3646. CARD_BUS_ID(card));
  3647. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3648. dev_kfree_skb_any(skb);
  3649. card->stats.rx_errors++;
  3650. return NULL;
  3651. }
  3652. element++;
  3653. offset = 0;
  3654. data_ptr = element->addr;
  3655. } else {
  3656. offset += data_len;
  3657. }
  3658. }
  3659. *__element = element;
  3660. *__offset = offset;
  3661. if (use_rx_sg && card->options.performance_stats) {
  3662. card->perf_stats.sg_skbs_rx++;
  3663. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3664. }
  3665. return skb;
  3666. no_mem:
  3667. if (net_ratelimit()) {
  3668. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3669. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3670. }
  3671. card->stats.rx_dropped++;
  3672. return NULL;
  3673. }
  3674. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3675. static void qeth_unregister_dbf_views(void)
  3676. {
  3677. int x;
  3678. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3679. debug_unregister(qeth_dbf[x].id);
  3680. qeth_dbf[x].id = NULL;
  3681. }
  3682. }
  3683. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3684. {
  3685. char dbf_txt_buf[32];
  3686. va_list args;
  3687. if (level > (qeth_dbf[dbf_nix].id)->level)
  3688. return;
  3689. va_start(args, fmt);
  3690. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3691. va_end(args);
  3692. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3693. }
  3694. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3695. static int qeth_register_dbf_views(void)
  3696. {
  3697. int ret;
  3698. int x;
  3699. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3700. /* register the areas */
  3701. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3702. qeth_dbf[x].pages,
  3703. qeth_dbf[x].areas,
  3704. qeth_dbf[x].len);
  3705. if (qeth_dbf[x].id == NULL) {
  3706. qeth_unregister_dbf_views();
  3707. return -ENOMEM;
  3708. }
  3709. /* register a view */
  3710. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3711. if (ret) {
  3712. qeth_unregister_dbf_views();
  3713. return ret;
  3714. }
  3715. /* set a passing level */
  3716. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3717. }
  3718. return 0;
  3719. }
  3720. int qeth_core_load_discipline(struct qeth_card *card,
  3721. enum qeth_discipline_id discipline)
  3722. {
  3723. int rc = 0;
  3724. switch (discipline) {
  3725. case QETH_DISCIPLINE_LAYER3:
  3726. card->discipline.ccwgdriver = try_then_request_module(
  3727. symbol_get(qeth_l3_ccwgroup_driver),
  3728. "qeth_l3");
  3729. break;
  3730. case QETH_DISCIPLINE_LAYER2:
  3731. card->discipline.ccwgdriver = try_then_request_module(
  3732. symbol_get(qeth_l2_ccwgroup_driver),
  3733. "qeth_l2");
  3734. break;
  3735. }
  3736. if (!card->discipline.ccwgdriver) {
  3737. dev_err(&card->gdev->dev, "There is no kernel module to "
  3738. "support discipline %d\n", discipline);
  3739. rc = -EINVAL;
  3740. }
  3741. return rc;
  3742. }
  3743. void qeth_core_free_discipline(struct qeth_card *card)
  3744. {
  3745. if (card->options.layer2)
  3746. symbol_put(qeth_l2_ccwgroup_driver);
  3747. else
  3748. symbol_put(qeth_l3_ccwgroup_driver);
  3749. card->discipline.ccwgdriver = NULL;
  3750. }
  3751. static void qeth_determine_capabilities(struct qeth_card *card)
  3752. {
  3753. int rc;
  3754. int length;
  3755. char *prcd;
  3756. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3757. rc = ccw_device_set_online(CARD_DDEV(card));
  3758. if (rc) {
  3759. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3760. goto out;
  3761. }
  3762. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3763. if (rc) {
  3764. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3765. dev_name(&card->gdev->dev), rc);
  3766. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3767. goto out_offline;
  3768. }
  3769. qeth_configure_unitaddr(card, prcd);
  3770. qeth_configure_blkt_default(card, prcd);
  3771. kfree(prcd);
  3772. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3773. if (rc)
  3774. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3775. out_offline:
  3776. ccw_device_set_offline(CARD_DDEV(card));
  3777. out:
  3778. return;
  3779. }
  3780. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3781. {
  3782. struct qeth_card *card;
  3783. struct device *dev;
  3784. int rc;
  3785. unsigned long flags;
  3786. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3787. dev = &gdev->dev;
  3788. if (!get_device(dev))
  3789. return -ENODEV;
  3790. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3791. card = qeth_alloc_card();
  3792. if (!card) {
  3793. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3794. rc = -ENOMEM;
  3795. goto err_dev;
  3796. }
  3797. card->read.ccwdev = gdev->cdev[0];
  3798. card->write.ccwdev = gdev->cdev[1];
  3799. card->data.ccwdev = gdev->cdev[2];
  3800. dev_set_drvdata(&gdev->dev, card);
  3801. card->gdev = gdev;
  3802. gdev->cdev[0]->handler = qeth_irq;
  3803. gdev->cdev[1]->handler = qeth_irq;
  3804. gdev->cdev[2]->handler = qeth_irq;
  3805. rc = qeth_determine_card_type(card);
  3806. if (rc) {
  3807. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3808. goto err_card;
  3809. }
  3810. rc = qeth_setup_card(card);
  3811. if (rc) {
  3812. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3813. goto err_card;
  3814. }
  3815. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3816. rc = qeth_core_create_osn_attributes(dev);
  3817. if (rc)
  3818. goto err_card;
  3819. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3820. if (rc) {
  3821. qeth_core_remove_osn_attributes(dev);
  3822. goto err_card;
  3823. }
  3824. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3825. if (rc) {
  3826. qeth_core_free_discipline(card);
  3827. qeth_core_remove_osn_attributes(dev);
  3828. goto err_card;
  3829. }
  3830. } else {
  3831. rc = qeth_core_create_device_attributes(dev);
  3832. if (rc)
  3833. goto err_card;
  3834. }
  3835. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3836. list_add_tail(&card->list, &qeth_core_card_list.list);
  3837. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3838. qeth_determine_capabilities(card);
  3839. return 0;
  3840. err_card:
  3841. qeth_core_free_card(card);
  3842. err_dev:
  3843. put_device(dev);
  3844. return rc;
  3845. }
  3846. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3847. {
  3848. unsigned long flags;
  3849. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3850. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3851. if (card->discipline.ccwgdriver) {
  3852. card->discipline.ccwgdriver->remove(gdev);
  3853. qeth_core_free_discipline(card);
  3854. }
  3855. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3856. qeth_core_remove_osn_attributes(&gdev->dev);
  3857. } else {
  3858. qeth_core_remove_device_attributes(&gdev->dev);
  3859. }
  3860. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3861. list_del(&card->list);
  3862. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3863. qeth_core_free_card(card);
  3864. dev_set_drvdata(&gdev->dev, NULL);
  3865. put_device(&gdev->dev);
  3866. return;
  3867. }
  3868. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3869. {
  3870. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3871. int rc = 0;
  3872. int def_discipline;
  3873. if (!card->discipline.ccwgdriver) {
  3874. if (card->info.type == QETH_CARD_TYPE_IQD)
  3875. def_discipline = QETH_DISCIPLINE_LAYER3;
  3876. else
  3877. def_discipline = QETH_DISCIPLINE_LAYER2;
  3878. rc = qeth_core_load_discipline(card, def_discipline);
  3879. if (rc)
  3880. goto err;
  3881. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3882. if (rc)
  3883. goto err;
  3884. }
  3885. rc = card->discipline.ccwgdriver->set_online(gdev);
  3886. err:
  3887. return rc;
  3888. }
  3889. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3890. {
  3891. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3892. return card->discipline.ccwgdriver->set_offline(gdev);
  3893. }
  3894. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3895. {
  3896. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3897. if (card->discipline.ccwgdriver &&
  3898. card->discipline.ccwgdriver->shutdown)
  3899. card->discipline.ccwgdriver->shutdown(gdev);
  3900. }
  3901. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3902. {
  3903. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3904. if (card->discipline.ccwgdriver &&
  3905. card->discipline.ccwgdriver->prepare)
  3906. return card->discipline.ccwgdriver->prepare(gdev);
  3907. return 0;
  3908. }
  3909. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3910. {
  3911. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3912. if (card->discipline.ccwgdriver &&
  3913. card->discipline.ccwgdriver->complete)
  3914. card->discipline.ccwgdriver->complete(gdev);
  3915. }
  3916. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3917. {
  3918. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3919. if (card->discipline.ccwgdriver &&
  3920. card->discipline.ccwgdriver->freeze)
  3921. return card->discipline.ccwgdriver->freeze(gdev);
  3922. return 0;
  3923. }
  3924. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3925. {
  3926. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3927. if (card->discipline.ccwgdriver &&
  3928. card->discipline.ccwgdriver->thaw)
  3929. return card->discipline.ccwgdriver->thaw(gdev);
  3930. return 0;
  3931. }
  3932. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3933. {
  3934. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3935. if (card->discipline.ccwgdriver &&
  3936. card->discipline.ccwgdriver->restore)
  3937. return card->discipline.ccwgdriver->restore(gdev);
  3938. return 0;
  3939. }
  3940. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3941. .owner = THIS_MODULE,
  3942. .name = "qeth",
  3943. .driver_id = 0xD8C5E3C8,
  3944. .probe = qeth_core_probe_device,
  3945. .remove = qeth_core_remove_device,
  3946. .set_online = qeth_core_set_online,
  3947. .set_offline = qeth_core_set_offline,
  3948. .shutdown = qeth_core_shutdown,
  3949. .prepare = qeth_core_prepare,
  3950. .complete = qeth_core_complete,
  3951. .freeze = qeth_core_freeze,
  3952. .thaw = qeth_core_thaw,
  3953. .restore = qeth_core_restore,
  3954. };
  3955. static ssize_t
  3956. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3957. size_t count)
  3958. {
  3959. int err;
  3960. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3961. qeth_core_ccwgroup_driver.driver_id);
  3962. if (err)
  3963. return err;
  3964. else
  3965. return count;
  3966. }
  3967. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3968. static struct {
  3969. const char str[ETH_GSTRING_LEN];
  3970. } qeth_ethtool_stats_keys[] = {
  3971. /* 0 */{"rx skbs"},
  3972. {"rx buffers"},
  3973. {"tx skbs"},
  3974. {"tx buffers"},
  3975. {"tx skbs no packing"},
  3976. {"tx buffers no packing"},
  3977. {"tx skbs packing"},
  3978. {"tx buffers packing"},
  3979. {"tx sg skbs"},
  3980. {"tx sg frags"},
  3981. /* 10 */{"rx sg skbs"},
  3982. {"rx sg frags"},
  3983. {"rx sg page allocs"},
  3984. {"tx large kbytes"},
  3985. {"tx large count"},
  3986. {"tx pk state ch n->p"},
  3987. {"tx pk state ch p->n"},
  3988. {"tx pk watermark low"},
  3989. {"tx pk watermark high"},
  3990. {"queue 0 buffer usage"},
  3991. /* 20 */{"queue 1 buffer usage"},
  3992. {"queue 2 buffer usage"},
  3993. {"queue 3 buffer usage"},
  3994. {"rx handler time"},
  3995. {"rx handler count"},
  3996. {"rx do_QDIO time"},
  3997. {"rx do_QDIO count"},
  3998. {"tx handler time"},
  3999. {"tx handler count"},
  4000. {"tx time"},
  4001. /* 30 */{"tx count"},
  4002. {"tx do_QDIO time"},
  4003. {"tx do_QDIO count"},
  4004. {"tx csum"},
  4005. {"tx lin"},
  4006. };
  4007. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4008. {
  4009. switch (stringset) {
  4010. case ETH_SS_STATS:
  4011. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4012. default:
  4013. return -EINVAL;
  4014. }
  4015. }
  4016. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4017. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4018. struct ethtool_stats *stats, u64 *data)
  4019. {
  4020. struct qeth_card *card = dev->ml_priv;
  4021. data[0] = card->stats.rx_packets -
  4022. card->perf_stats.initial_rx_packets;
  4023. data[1] = card->perf_stats.bufs_rec;
  4024. data[2] = card->stats.tx_packets -
  4025. card->perf_stats.initial_tx_packets;
  4026. data[3] = card->perf_stats.bufs_sent;
  4027. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4028. - card->perf_stats.skbs_sent_pack;
  4029. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4030. data[6] = card->perf_stats.skbs_sent_pack;
  4031. data[7] = card->perf_stats.bufs_sent_pack;
  4032. data[8] = card->perf_stats.sg_skbs_sent;
  4033. data[9] = card->perf_stats.sg_frags_sent;
  4034. data[10] = card->perf_stats.sg_skbs_rx;
  4035. data[11] = card->perf_stats.sg_frags_rx;
  4036. data[12] = card->perf_stats.sg_alloc_page_rx;
  4037. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4038. data[14] = card->perf_stats.large_send_cnt;
  4039. data[15] = card->perf_stats.sc_dp_p;
  4040. data[16] = card->perf_stats.sc_p_dp;
  4041. data[17] = QETH_LOW_WATERMARK_PACK;
  4042. data[18] = QETH_HIGH_WATERMARK_PACK;
  4043. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4044. data[20] = (card->qdio.no_out_queues > 1) ?
  4045. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4046. data[21] = (card->qdio.no_out_queues > 2) ?
  4047. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4048. data[22] = (card->qdio.no_out_queues > 3) ?
  4049. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4050. data[23] = card->perf_stats.inbound_time;
  4051. data[24] = card->perf_stats.inbound_cnt;
  4052. data[25] = card->perf_stats.inbound_do_qdio_time;
  4053. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4054. data[27] = card->perf_stats.outbound_handler_time;
  4055. data[28] = card->perf_stats.outbound_handler_cnt;
  4056. data[29] = card->perf_stats.outbound_time;
  4057. data[30] = card->perf_stats.outbound_cnt;
  4058. data[31] = card->perf_stats.outbound_do_qdio_time;
  4059. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4060. data[33] = card->perf_stats.tx_csum;
  4061. data[34] = card->perf_stats.tx_lin;
  4062. }
  4063. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4064. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4065. {
  4066. switch (stringset) {
  4067. case ETH_SS_STATS:
  4068. memcpy(data, &qeth_ethtool_stats_keys,
  4069. sizeof(qeth_ethtool_stats_keys));
  4070. break;
  4071. default:
  4072. WARN_ON(1);
  4073. break;
  4074. }
  4075. }
  4076. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4077. void qeth_core_get_drvinfo(struct net_device *dev,
  4078. struct ethtool_drvinfo *info)
  4079. {
  4080. struct qeth_card *card = dev->ml_priv;
  4081. if (card->options.layer2)
  4082. strcpy(info->driver, "qeth_l2");
  4083. else
  4084. strcpy(info->driver, "qeth_l3");
  4085. strcpy(info->version, "1.0");
  4086. strcpy(info->fw_version, card->info.mcl_level);
  4087. sprintf(info->bus_info, "%s/%s/%s",
  4088. CARD_RDEV_ID(card),
  4089. CARD_WDEV_ID(card),
  4090. CARD_DDEV_ID(card));
  4091. }
  4092. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4093. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4094. struct ethtool_cmd *ecmd)
  4095. {
  4096. struct qeth_card *card = netdev->ml_priv;
  4097. enum qeth_link_types link_type;
  4098. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4099. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4100. else
  4101. link_type = card->info.link_type;
  4102. ecmd->transceiver = XCVR_INTERNAL;
  4103. ecmd->supported = SUPPORTED_Autoneg;
  4104. ecmd->advertising = ADVERTISED_Autoneg;
  4105. ecmd->duplex = DUPLEX_FULL;
  4106. ecmd->autoneg = AUTONEG_ENABLE;
  4107. switch (link_type) {
  4108. case QETH_LINK_TYPE_FAST_ETH:
  4109. case QETH_LINK_TYPE_LANE_ETH100:
  4110. ecmd->supported |= SUPPORTED_10baseT_Half |
  4111. SUPPORTED_10baseT_Full |
  4112. SUPPORTED_100baseT_Half |
  4113. SUPPORTED_100baseT_Full |
  4114. SUPPORTED_TP;
  4115. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4116. ADVERTISED_10baseT_Full |
  4117. ADVERTISED_100baseT_Half |
  4118. ADVERTISED_100baseT_Full |
  4119. ADVERTISED_TP;
  4120. ecmd->speed = SPEED_100;
  4121. ecmd->port = PORT_TP;
  4122. break;
  4123. case QETH_LINK_TYPE_GBIT_ETH:
  4124. case QETH_LINK_TYPE_LANE_ETH1000:
  4125. ecmd->supported |= SUPPORTED_10baseT_Half |
  4126. SUPPORTED_10baseT_Full |
  4127. SUPPORTED_100baseT_Half |
  4128. SUPPORTED_100baseT_Full |
  4129. SUPPORTED_1000baseT_Half |
  4130. SUPPORTED_1000baseT_Full |
  4131. SUPPORTED_FIBRE;
  4132. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4133. ADVERTISED_10baseT_Full |
  4134. ADVERTISED_100baseT_Half |
  4135. ADVERTISED_100baseT_Full |
  4136. ADVERTISED_1000baseT_Half |
  4137. ADVERTISED_1000baseT_Full |
  4138. ADVERTISED_FIBRE;
  4139. ecmd->speed = SPEED_1000;
  4140. ecmd->port = PORT_FIBRE;
  4141. break;
  4142. case QETH_LINK_TYPE_10GBIT_ETH:
  4143. ecmd->supported |= SUPPORTED_10baseT_Half |
  4144. SUPPORTED_10baseT_Full |
  4145. SUPPORTED_100baseT_Half |
  4146. SUPPORTED_100baseT_Full |
  4147. SUPPORTED_1000baseT_Half |
  4148. SUPPORTED_1000baseT_Full |
  4149. SUPPORTED_10000baseT_Full |
  4150. SUPPORTED_FIBRE;
  4151. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4152. ADVERTISED_10baseT_Full |
  4153. ADVERTISED_100baseT_Half |
  4154. ADVERTISED_100baseT_Full |
  4155. ADVERTISED_1000baseT_Half |
  4156. ADVERTISED_1000baseT_Full |
  4157. ADVERTISED_10000baseT_Full |
  4158. ADVERTISED_FIBRE;
  4159. ecmd->speed = SPEED_10000;
  4160. ecmd->port = PORT_FIBRE;
  4161. break;
  4162. default:
  4163. ecmd->supported |= SUPPORTED_10baseT_Half |
  4164. SUPPORTED_10baseT_Full |
  4165. SUPPORTED_TP;
  4166. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4167. ADVERTISED_10baseT_Full |
  4168. ADVERTISED_TP;
  4169. ecmd->speed = SPEED_10;
  4170. ecmd->port = PORT_TP;
  4171. }
  4172. return 0;
  4173. }
  4174. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4175. static int __init qeth_core_init(void)
  4176. {
  4177. int rc;
  4178. pr_info("loading core functions\n");
  4179. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4180. rwlock_init(&qeth_core_card_list.rwlock);
  4181. rc = qeth_register_dbf_views();
  4182. if (rc)
  4183. goto out_err;
  4184. rc = ccw_driver_register(&qeth_ccw_driver);
  4185. if (rc)
  4186. goto ccw_err;
  4187. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4188. if (rc)
  4189. goto ccwgroup_err;
  4190. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4191. &driver_attr_group);
  4192. if (rc)
  4193. goto driver_err;
  4194. qeth_core_root_dev = root_device_register("qeth");
  4195. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4196. if (rc)
  4197. goto register_err;
  4198. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4199. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4200. if (!qeth_core_header_cache) {
  4201. rc = -ENOMEM;
  4202. goto slab_err;
  4203. }
  4204. return 0;
  4205. slab_err:
  4206. root_device_unregister(qeth_core_root_dev);
  4207. register_err:
  4208. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4209. &driver_attr_group);
  4210. driver_err:
  4211. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4212. ccwgroup_err:
  4213. ccw_driver_unregister(&qeth_ccw_driver);
  4214. ccw_err:
  4215. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4216. qeth_unregister_dbf_views();
  4217. out_err:
  4218. pr_err("Initializing the qeth device driver failed\n");
  4219. return rc;
  4220. }
  4221. static void __exit qeth_core_exit(void)
  4222. {
  4223. root_device_unregister(qeth_core_root_dev);
  4224. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4225. &driver_attr_group);
  4226. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4227. ccw_driver_unregister(&qeth_ccw_driver);
  4228. kmem_cache_destroy(qeth_core_header_cache);
  4229. qeth_unregister_dbf_views();
  4230. pr_info("core functions removed\n");
  4231. }
  4232. module_init(qeth_core_init);
  4233. module_exit(qeth_core_exit);
  4234. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4235. MODULE_DESCRIPTION("qeth core functions");
  4236. MODULE_LICENSE("GPL");