p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <net/mac80211.h>
  21. #include "p54.h"
  22. #include "lmac.h"
  23. #include "p54pci.h"
  24. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  25. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  26. MODULE_LICENSE("GPL");
  27. MODULE_ALIAS("prism54pci");
  28. MODULE_FIRMWARE("isl3886pci");
  29. static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  30. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  31. { PCI_DEVICE(0x1260, 0x3890) },
  32. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  33. { PCI_DEVICE(0x10b7, 0x6001) },
  34. /* Intersil PRISM Indigo Wireless LAN adapter */
  35. { PCI_DEVICE(0x1260, 0x3877) },
  36. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  37. { PCI_DEVICE(0x1260, 0x3886) },
  38. { },
  39. };
  40. MODULE_DEVICE_TABLE(pci, p54p_table);
  41. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  42. {
  43. struct p54p_priv *priv = dev->priv;
  44. __le32 reg;
  45. int err;
  46. __le32 *data;
  47. u32 remains, left, device_addr;
  48. P54P_WRITE(int_enable, cpu_to_le32(0));
  49. P54P_READ(int_enable);
  50. udelay(10);
  51. reg = P54P_READ(ctrl_stat);
  52. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  53. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  54. P54P_WRITE(ctrl_stat, reg);
  55. P54P_READ(ctrl_stat);
  56. udelay(10);
  57. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  58. P54P_WRITE(ctrl_stat, reg);
  59. wmb();
  60. udelay(10);
  61. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  62. P54P_WRITE(ctrl_stat, reg);
  63. wmb();
  64. /* wait for the firmware to reset properly */
  65. mdelay(10);
  66. err = p54_parse_firmware(dev, priv->firmware);
  67. if (err)
  68. return err;
  69. if (priv->common.fw_interface != FW_LM86) {
  70. dev_err(&priv->pdev->dev, "wrong firmware, "
  71. "please get a LM86(PCI) firmware a try again.\n");
  72. return -EINVAL;
  73. }
  74. data = (__le32 *) priv->firmware->data;
  75. remains = priv->firmware->size;
  76. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  77. while (remains) {
  78. u32 i = 0;
  79. left = min((u32)0x1000, remains);
  80. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  81. P54P_READ(int_enable);
  82. device_addr += 0x1000;
  83. while (i < left) {
  84. P54P_WRITE(direct_mem_win[i], *data++);
  85. i += sizeof(u32);
  86. }
  87. remains -= left;
  88. P54P_READ(int_enable);
  89. }
  90. reg = P54P_READ(ctrl_stat);
  91. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  92. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  93. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  94. P54P_WRITE(ctrl_stat, reg);
  95. P54P_READ(ctrl_stat);
  96. udelay(10);
  97. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  98. P54P_WRITE(ctrl_stat, reg);
  99. wmb();
  100. udelay(10);
  101. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  102. P54P_WRITE(ctrl_stat, reg);
  103. wmb();
  104. udelay(10);
  105. /* wait for the firmware to boot properly */
  106. mdelay(100);
  107. return 0;
  108. }
  109. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  110. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  111. struct sk_buff **rx_buf)
  112. {
  113. struct p54p_priv *priv = dev->priv;
  114. struct p54p_ring_control *ring_control = priv->ring_control;
  115. u32 limit, idx, i;
  116. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  117. limit = idx;
  118. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  119. limit = ring_limit - limit;
  120. i = idx % ring_limit;
  121. while (limit-- > 1) {
  122. struct p54p_desc *desc = &ring[i];
  123. if (!desc->host_addr) {
  124. struct sk_buff *skb;
  125. dma_addr_t mapping;
  126. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  127. if (!skb)
  128. break;
  129. mapping = pci_map_single(priv->pdev,
  130. skb_tail_pointer(skb),
  131. priv->common.rx_mtu + 32,
  132. PCI_DMA_FROMDEVICE);
  133. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  134. dev_kfree_skb_any(skb);
  135. dev_err(&priv->pdev->dev,
  136. "RX DMA Mapping error\n");
  137. break;
  138. }
  139. desc->host_addr = cpu_to_le32(mapping);
  140. desc->device_addr = 0; // FIXME: necessary?
  141. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  142. desc->flags = 0;
  143. rx_buf[i] = skb;
  144. }
  145. i++;
  146. idx++;
  147. i %= ring_limit;
  148. }
  149. wmb();
  150. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  151. }
  152. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  153. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  154. struct sk_buff **rx_buf)
  155. {
  156. struct p54p_priv *priv = dev->priv;
  157. struct p54p_ring_control *ring_control = priv->ring_control;
  158. struct p54p_desc *desc;
  159. u32 idx, i;
  160. i = (*index) % ring_limit;
  161. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  162. idx %= ring_limit;
  163. while (i != idx) {
  164. u16 len;
  165. struct sk_buff *skb;
  166. desc = &ring[i];
  167. len = le16_to_cpu(desc->len);
  168. skb = rx_buf[i];
  169. if (!skb) {
  170. i++;
  171. i %= ring_limit;
  172. continue;
  173. }
  174. if (unlikely(len > priv->common.rx_mtu)) {
  175. if (net_ratelimit())
  176. dev_err(&priv->pdev->dev, "rx'd frame size "
  177. "exceeds length threshold.\n");
  178. len = priv->common.rx_mtu;
  179. }
  180. skb_put(skb, len);
  181. if (p54_rx(dev, skb)) {
  182. pci_unmap_single(priv->pdev,
  183. le32_to_cpu(desc->host_addr),
  184. priv->common.rx_mtu + 32,
  185. PCI_DMA_FROMDEVICE);
  186. rx_buf[i] = NULL;
  187. desc->host_addr = 0;
  188. } else {
  189. skb_trim(skb, 0);
  190. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  191. }
  192. i++;
  193. i %= ring_limit;
  194. }
  195. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  196. }
  197. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  198. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  199. struct sk_buff **tx_buf)
  200. {
  201. struct p54p_priv *priv = dev->priv;
  202. struct p54p_ring_control *ring_control = priv->ring_control;
  203. struct p54p_desc *desc;
  204. struct sk_buff *skb;
  205. u32 idx, i;
  206. i = (*index) % ring_limit;
  207. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  208. idx %= ring_limit;
  209. while (i != idx) {
  210. desc = &ring[i];
  211. skb = tx_buf[i];
  212. tx_buf[i] = NULL;
  213. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  214. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  215. desc->host_addr = 0;
  216. desc->device_addr = 0;
  217. desc->len = 0;
  218. desc->flags = 0;
  219. if (skb && FREE_AFTER_TX(skb))
  220. p54_free_skb(dev, skb);
  221. i++;
  222. i %= ring_limit;
  223. }
  224. }
  225. static void p54p_tasklet(unsigned long dev_id)
  226. {
  227. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  228. struct p54p_priv *priv = dev->priv;
  229. struct p54p_ring_control *ring_control = priv->ring_control;
  230. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  231. ARRAY_SIZE(ring_control->tx_mgmt),
  232. priv->tx_buf_mgmt);
  233. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  234. ARRAY_SIZE(ring_control->tx_data),
  235. priv->tx_buf_data);
  236. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  237. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  238. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  239. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  240. wmb();
  241. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  242. }
  243. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  244. {
  245. struct ieee80211_hw *dev = dev_id;
  246. struct p54p_priv *priv = dev->priv;
  247. __le32 reg;
  248. reg = P54P_READ(int_ident);
  249. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  250. goto out;
  251. }
  252. P54P_WRITE(int_ack, reg);
  253. reg &= P54P_READ(int_enable);
  254. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  255. tasklet_schedule(&priv->tasklet);
  256. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  257. complete(&priv->boot_comp);
  258. out:
  259. return reg ? IRQ_HANDLED : IRQ_NONE;
  260. }
  261. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  262. {
  263. unsigned long flags;
  264. struct p54p_priv *priv = dev->priv;
  265. struct p54p_ring_control *ring_control = priv->ring_control;
  266. struct p54p_desc *desc;
  267. dma_addr_t mapping;
  268. u32 device_idx, idx, i;
  269. spin_lock_irqsave(&priv->lock, flags);
  270. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  271. idx = le32_to_cpu(ring_control->host_idx[1]);
  272. i = idx % ARRAY_SIZE(ring_control->tx_data);
  273. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  274. PCI_DMA_TODEVICE);
  275. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  276. spin_unlock_irqrestore(&priv->lock, flags);
  277. p54_free_skb(dev, skb);
  278. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  279. return ;
  280. }
  281. priv->tx_buf_data[i] = skb;
  282. desc = &ring_control->tx_data[i];
  283. desc->host_addr = cpu_to_le32(mapping);
  284. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  285. desc->len = cpu_to_le16(skb->len);
  286. desc->flags = 0;
  287. wmb();
  288. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  289. spin_unlock_irqrestore(&priv->lock, flags);
  290. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  291. P54P_READ(dev_int);
  292. }
  293. static void p54p_stop(struct ieee80211_hw *dev)
  294. {
  295. struct p54p_priv *priv = dev->priv;
  296. struct p54p_ring_control *ring_control = priv->ring_control;
  297. unsigned int i;
  298. struct p54p_desc *desc;
  299. P54P_WRITE(int_enable, cpu_to_le32(0));
  300. P54P_READ(int_enable);
  301. udelay(10);
  302. free_irq(priv->pdev->irq, dev);
  303. tasklet_kill(&priv->tasklet);
  304. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  305. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  306. desc = &ring_control->rx_data[i];
  307. if (desc->host_addr)
  308. pci_unmap_single(priv->pdev,
  309. le32_to_cpu(desc->host_addr),
  310. priv->common.rx_mtu + 32,
  311. PCI_DMA_FROMDEVICE);
  312. kfree_skb(priv->rx_buf_data[i]);
  313. priv->rx_buf_data[i] = NULL;
  314. }
  315. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  316. desc = &ring_control->rx_mgmt[i];
  317. if (desc->host_addr)
  318. pci_unmap_single(priv->pdev,
  319. le32_to_cpu(desc->host_addr),
  320. priv->common.rx_mtu + 32,
  321. PCI_DMA_FROMDEVICE);
  322. kfree_skb(priv->rx_buf_mgmt[i]);
  323. priv->rx_buf_mgmt[i] = NULL;
  324. }
  325. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  326. desc = &ring_control->tx_data[i];
  327. if (desc->host_addr)
  328. pci_unmap_single(priv->pdev,
  329. le32_to_cpu(desc->host_addr),
  330. le16_to_cpu(desc->len),
  331. PCI_DMA_TODEVICE);
  332. p54_free_skb(dev, priv->tx_buf_data[i]);
  333. priv->tx_buf_data[i] = NULL;
  334. }
  335. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  336. desc = &ring_control->tx_mgmt[i];
  337. if (desc->host_addr)
  338. pci_unmap_single(priv->pdev,
  339. le32_to_cpu(desc->host_addr),
  340. le16_to_cpu(desc->len),
  341. PCI_DMA_TODEVICE);
  342. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  343. priv->tx_buf_mgmt[i] = NULL;
  344. }
  345. memset(ring_control, 0, sizeof(*ring_control));
  346. }
  347. static int p54p_open(struct ieee80211_hw *dev)
  348. {
  349. struct p54p_priv *priv = dev->priv;
  350. int err;
  351. init_completion(&priv->boot_comp);
  352. err = request_irq(priv->pdev->irq, p54p_interrupt,
  353. IRQF_SHARED, "p54pci", dev);
  354. if (err) {
  355. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  356. return err;
  357. }
  358. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  359. err = p54p_upload_firmware(dev);
  360. if (err) {
  361. free_irq(priv->pdev->irq, dev);
  362. return err;
  363. }
  364. priv->rx_idx_data = priv->tx_idx_data = 0;
  365. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  366. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  367. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  368. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  369. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  370. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  371. P54P_READ(ring_control_base);
  372. wmb();
  373. udelay(10);
  374. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  375. P54P_READ(int_enable);
  376. wmb();
  377. udelay(10);
  378. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  379. P54P_READ(dev_int);
  380. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  381. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  382. wiphy_name(dev->wiphy));
  383. p54p_stop(dev);
  384. return -ETIMEDOUT;
  385. }
  386. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  387. P54P_READ(int_enable);
  388. wmb();
  389. udelay(10);
  390. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  391. P54P_READ(dev_int);
  392. wmb();
  393. udelay(10);
  394. return 0;
  395. }
  396. static int __devinit p54p_probe(struct pci_dev *pdev,
  397. const struct pci_device_id *id)
  398. {
  399. struct p54p_priv *priv;
  400. struct ieee80211_hw *dev;
  401. unsigned long mem_addr, mem_len;
  402. int err;
  403. err = pci_enable_device(pdev);
  404. if (err) {
  405. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  406. return err;
  407. }
  408. mem_addr = pci_resource_start(pdev, 0);
  409. mem_len = pci_resource_len(pdev, 0);
  410. if (mem_len < sizeof(struct p54p_csr)) {
  411. dev_err(&pdev->dev, "Too short PCI resources\n");
  412. goto err_disable_dev;
  413. }
  414. err = pci_request_regions(pdev, "p54pci");
  415. if (err) {
  416. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  417. goto err_disable_dev;
  418. }
  419. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  420. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  421. dev_err(&pdev->dev, "No suitable DMA available\n");
  422. goto err_free_reg;
  423. }
  424. pci_set_master(pdev);
  425. pci_try_set_mwi(pdev);
  426. pci_write_config_byte(pdev, 0x40, 0);
  427. pci_write_config_byte(pdev, 0x41, 0);
  428. dev = p54_init_common(sizeof(*priv));
  429. if (!dev) {
  430. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  431. err = -ENOMEM;
  432. goto err_free_reg;
  433. }
  434. priv = dev->priv;
  435. priv->pdev = pdev;
  436. SET_IEEE80211_DEV(dev, &pdev->dev);
  437. pci_set_drvdata(pdev, dev);
  438. priv->map = ioremap(mem_addr, mem_len);
  439. if (!priv->map) {
  440. dev_err(&pdev->dev, "Cannot map device memory\n");
  441. err = -ENOMEM;
  442. goto err_free_dev;
  443. }
  444. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  445. &priv->ring_control_dma);
  446. if (!priv->ring_control) {
  447. dev_err(&pdev->dev, "Cannot allocate rings\n");
  448. err = -ENOMEM;
  449. goto err_iounmap;
  450. }
  451. priv->common.open = p54p_open;
  452. priv->common.stop = p54p_stop;
  453. priv->common.tx = p54p_tx;
  454. spin_lock_init(&priv->lock);
  455. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  456. err = request_firmware(&priv->firmware, "isl3886pci",
  457. &priv->pdev->dev);
  458. if (err) {
  459. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  460. err = request_firmware(&priv->firmware, "isl3886",
  461. &priv->pdev->dev);
  462. if (err)
  463. goto err_free_common;
  464. }
  465. err = p54p_open(dev);
  466. if (err)
  467. goto err_free_common;
  468. err = p54_read_eeprom(dev);
  469. p54p_stop(dev);
  470. if (err)
  471. goto err_free_common;
  472. err = p54_register_common(dev, &pdev->dev);
  473. if (err)
  474. goto err_free_common;
  475. return 0;
  476. err_free_common:
  477. release_firmware(priv->firmware);
  478. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  479. priv->ring_control, priv->ring_control_dma);
  480. err_iounmap:
  481. iounmap(priv->map);
  482. err_free_dev:
  483. pci_set_drvdata(pdev, NULL);
  484. p54_free_common(dev);
  485. err_free_reg:
  486. pci_release_regions(pdev);
  487. err_disable_dev:
  488. pci_disable_device(pdev);
  489. return err;
  490. }
  491. static void __devexit p54p_remove(struct pci_dev *pdev)
  492. {
  493. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  494. struct p54p_priv *priv;
  495. if (!dev)
  496. return;
  497. p54_unregister_common(dev);
  498. priv = dev->priv;
  499. release_firmware(priv->firmware);
  500. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  501. priv->ring_control, priv->ring_control_dma);
  502. iounmap(priv->map);
  503. pci_release_regions(pdev);
  504. pci_disable_device(pdev);
  505. p54_free_common(dev);
  506. }
  507. #ifdef CONFIG_PM
  508. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  509. {
  510. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  511. struct p54p_priv *priv = dev->priv;
  512. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  513. ieee80211_stop_queues(dev);
  514. p54p_stop(dev);
  515. }
  516. pci_save_state(pdev);
  517. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  518. return 0;
  519. }
  520. static int p54p_resume(struct pci_dev *pdev)
  521. {
  522. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  523. struct p54p_priv *priv = dev->priv;
  524. pci_set_power_state(pdev, PCI_D0);
  525. pci_restore_state(pdev);
  526. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  527. p54p_open(dev);
  528. ieee80211_wake_queues(dev);
  529. }
  530. return 0;
  531. }
  532. #endif /* CONFIG_PM */
  533. static struct pci_driver p54p_driver = {
  534. .name = "p54pci",
  535. .id_table = p54p_table,
  536. .probe = p54p_probe,
  537. .remove = __devexit_p(p54p_remove),
  538. #ifdef CONFIG_PM
  539. .suspend = p54p_suspend,
  540. .resume = p54p_resume,
  541. #endif /* CONFIG_PM */
  542. };
  543. static int __init p54p_init(void)
  544. {
  545. return pci_register_driver(&p54p_driver);
  546. }
  547. static void __exit p54p_exit(void)
  548. {
  549. pci_unregister_driver(&p54p_driver);
  550. }
  551. module_init(p54p_init);
  552. module_exit(p54p_exit);