mcdi.c 30 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2009 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. /* Software-defined structure to the shared-memory */
  23. #define CMD_NOTIFY_PORT0 0
  24. #define CMD_NOTIFY_PORT1 4
  25. #define CMD_PDU_PORT0 0x008
  26. #define CMD_PDU_PORT1 0x108
  27. #define REBOOT_FLAG_PORT0 0x3f8
  28. #define REBOOT_FLAG_PORT1 0x3fc
  29. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  30. #define MCDI_PDU(efx) \
  31. (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
  32. #define MCDI_DOORBELL(efx) \
  33. (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
  34. #define MCDI_REBOOT_FLAG(efx) \
  35. (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= 0x100);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= 0x100);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned int time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = get_seconds();
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time >= finish)
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. EFX_ERR(efx, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. EFX_ERR(efx, "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  143. respseq, mcdi->seqno);
  144. rc = EIO;
  145. } else if (error) {
  146. efx_readd(efx, &reg, pdu + 4);
  147. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  148. #define TRANSLATE_ERROR(name) \
  149. case MC_CMD_ERR_ ## name: \
  150. rc = name; \
  151. break
  152. TRANSLATE_ERROR(ENOENT);
  153. TRANSLATE_ERROR(EINTR);
  154. TRANSLATE_ERROR(EACCES);
  155. TRANSLATE_ERROR(EBUSY);
  156. TRANSLATE_ERROR(EINVAL);
  157. TRANSLATE_ERROR(EDEADLK);
  158. TRANSLATE_ERROR(ENOSYS);
  159. TRANSLATE_ERROR(ETIME);
  160. #undef TRANSLATE_ERROR
  161. default:
  162. rc = EIO;
  163. break;
  164. }
  165. } else
  166. rc = 0;
  167. out:
  168. mcdi->resprc = rc;
  169. if (rc)
  170. mcdi->resplen = 0;
  171. /* Return rc=0 like wait_event_timeout() */
  172. return 0;
  173. }
  174. /* Test and clear MC-rebooted flag for this port/function */
  175. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  176. {
  177. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
  178. efx_dword_t reg;
  179. uint32_t value;
  180. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  181. return false;
  182. efx_readd(efx, &reg, addr);
  183. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  184. if (value == 0)
  185. return 0;
  186. EFX_ZERO_DWORD(reg);
  187. efx_writed(efx, &reg, addr);
  188. if (value == MC_STATUS_DWORD_ASSERT)
  189. return -EINTR;
  190. else
  191. return -EIO;
  192. }
  193. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  194. {
  195. /* Wait until the interface becomes QUIESCENT and we win the race
  196. * to mark it RUNNING. */
  197. wait_event(mcdi->wq,
  198. atomic_cmpxchg(&mcdi->state,
  199. MCDI_STATE_QUIESCENT,
  200. MCDI_STATE_RUNNING)
  201. == MCDI_STATE_QUIESCENT);
  202. }
  203. static int efx_mcdi_await_completion(struct efx_nic *efx)
  204. {
  205. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  206. if (wait_event_timeout(
  207. mcdi->wq,
  208. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  209. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  210. return -ETIMEDOUT;
  211. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  212. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  213. * completed the request first, then we'll just end up completing the
  214. * request again, which is safe.
  215. *
  216. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  217. * wait_event_timeout() implicitly provides.
  218. */
  219. if (mcdi->mode == MCDI_MODE_POLL)
  220. return efx_mcdi_poll(efx);
  221. return 0;
  222. }
  223. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  224. {
  225. /* If the interface is RUNNING, then move to COMPLETED and wake any
  226. * waiters. If the interface isn't in RUNNING then we've received a
  227. * duplicate completion after we've already transitioned back to
  228. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  229. * have failed the seqno check].
  230. */
  231. if (atomic_cmpxchg(&mcdi->state,
  232. MCDI_STATE_RUNNING,
  233. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  234. wake_up(&mcdi->wq);
  235. return true;
  236. }
  237. return false;
  238. }
  239. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  240. {
  241. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  242. wake_up(&mcdi->wq);
  243. }
  244. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  245. unsigned int datalen, unsigned int errno)
  246. {
  247. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  248. bool wake = false;
  249. spin_lock(&mcdi->iface_lock);
  250. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  251. if (mcdi->credits)
  252. /* The request has been cancelled */
  253. --mcdi->credits;
  254. else
  255. EFX_ERR(efx, "MC response mismatch tx seq 0x%x rx "
  256. "seq 0x%x\n", seqno, mcdi->seqno);
  257. } else {
  258. mcdi->resprc = errno;
  259. mcdi->resplen = datalen;
  260. wake = true;
  261. }
  262. spin_unlock(&mcdi->iface_lock);
  263. if (wake)
  264. efx_mcdi_complete(mcdi);
  265. }
  266. /* Issue the given command by writing the data into the shared memory PDU,
  267. * ring the doorbell and wait for completion. Copyout the result. */
  268. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  269. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  270. size_t *outlen_actual)
  271. {
  272. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  273. int rc;
  274. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  275. efx_mcdi_acquire(mcdi);
  276. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  277. spin_lock_bh(&mcdi->iface_lock);
  278. ++mcdi->seqno;
  279. spin_unlock_bh(&mcdi->iface_lock);
  280. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  281. if (mcdi->mode == MCDI_MODE_POLL)
  282. rc = efx_mcdi_poll(efx);
  283. else
  284. rc = efx_mcdi_await_completion(efx);
  285. if (rc != 0) {
  286. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  287. * and completing a request we've just cancelled, by ensuring
  288. * that the seqno check therein fails.
  289. */
  290. spin_lock_bh(&mcdi->iface_lock);
  291. ++mcdi->seqno;
  292. ++mcdi->credits;
  293. spin_unlock_bh(&mcdi->iface_lock);
  294. EFX_ERR(efx, "MC command 0x%x inlen %d mode %d timed out\n",
  295. cmd, (int)inlen, mcdi->mode);
  296. } else {
  297. size_t resplen;
  298. /* At the very least we need a memory barrier here to ensure
  299. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  300. * a spurious efx_mcdi_ev_cpl() running concurrently by
  301. * acquiring the iface_lock. */
  302. spin_lock_bh(&mcdi->iface_lock);
  303. rc = -mcdi->resprc;
  304. resplen = mcdi->resplen;
  305. spin_unlock_bh(&mcdi->iface_lock);
  306. if (rc == 0) {
  307. efx_mcdi_copyout(efx, outbuf,
  308. min(outlen, mcdi->resplen + 3) & ~0x3);
  309. if (outlen_actual != NULL)
  310. *outlen_actual = resplen;
  311. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  312. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  313. else if (rc == -EIO || rc == -EINTR) {
  314. EFX_ERR(efx, "MC fatal error %d\n", -rc);
  315. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  316. } else
  317. EFX_ERR(efx, "MC command 0x%x inlen %d failed rc=%d\n",
  318. cmd, (int)inlen, -rc);
  319. }
  320. efx_mcdi_release(mcdi);
  321. return rc;
  322. }
  323. void efx_mcdi_mode_poll(struct efx_nic *efx)
  324. {
  325. struct efx_mcdi_iface *mcdi;
  326. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  327. return;
  328. mcdi = efx_mcdi(efx);
  329. if (mcdi->mode == MCDI_MODE_POLL)
  330. return;
  331. /* We can switch from event completion to polled completion, because
  332. * mcdi requests are always completed in shared memory. We do this by
  333. * switching the mode to POLL'd then completing the request.
  334. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  335. *
  336. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  337. * which efx_mcdi_complete() provides for us.
  338. */
  339. mcdi->mode = MCDI_MODE_POLL;
  340. efx_mcdi_complete(mcdi);
  341. }
  342. void efx_mcdi_mode_event(struct efx_nic *efx)
  343. {
  344. struct efx_mcdi_iface *mcdi;
  345. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  346. return;
  347. mcdi = efx_mcdi(efx);
  348. if (mcdi->mode == MCDI_MODE_EVENTS)
  349. return;
  350. /* We can't switch from polled to event completion in the middle of a
  351. * request, because the completion method is specified in the request.
  352. * So acquire the interface to serialise the requestors. We don't need
  353. * to acquire the iface_lock to change the mode here, but we do need a
  354. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  355. * efx_mcdi_acquire() provides.
  356. */
  357. efx_mcdi_acquire(mcdi);
  358. mcdi->mode = MCDI_MODE_EVENTS;
  359. efx_mcdi_release(mcdi);
  360. }
  361. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  362. {
  363. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  364. /* If there is an outstanding MCDI request, it has been terminated
  365. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  366. * in polled mode, then do nothing because the MC reboot handler will
  367. * set the header correctly. However, if the mcdi interface is waiting
  368. * for a CMDDONE event it won't receive it [and since all MCDI events
  369. * are sent to the same queue, we can't be racing with
  370. * efx_mcdi_ev_cpl()]
  371. *
  372. * There's a race here with efx_mcdi_rpc(), because we might receive
  373. * a REBOOT event *before* the request has been copied out. In polled
  374. * mode (during startup) this is irrelevent, because efx_mcdi_complete()
  375. * is ignored. In event mode, this condition is just an edge-case of
  376. * receiving a REBOOT event after posting the MCDI request. Did the mc
  377. * reboot before or after the copyout? The best we can do always is
  378. * just return failure.
  379. */
  380. spin_lock(&mcdi->iface_lock);
  381. if (efx_mcdi_complete(mcdi)) {
  382. if (mcdi->mode == MCDI_MODE_EVENTS) {
  383. mcdi->resprc = rc;
  384. mcdi->resplen = 0;
  385. }
  386. } else
  387. /* Nobody was waiting for an MCDI request, so trigger a reset */
  388. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  389. spin_unlock(&mcdi->iface_lock);
  390. }
  391. static unsigned int efx_mcdi_event_link_speed[] = {
  392. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  393. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  394. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  395. };
  396. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  397. {
  398. u32 flags, fcntl, speed, lpa;
  399. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  400. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  401. speed = efx_mcdi_event_link_speed[speed];
  402. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  403. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  404. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  405. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  406. * which is only run after flushing the event queues. Therefore, it
  407. * is safe to modify the link state outside of the mac_lock here.
  408. */
  409. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  410. efx_mcdi_phy_check_fcntl(efx, lpa);
  411. efx_link_status_changed(efx);
  412. }
  413. static const char *sensor_names[] = {
  414. [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
  415. [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
  416. [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
  417. [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
  418. [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
  419. [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
  420. [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
  421. [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
  422. [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
  423. [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
  424. [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
  425. [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
  426. [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
  427. };
  428. static const char *sensor_status_names[] = {
  429. [MC_CMD_SENSOR_STATE_OK] = "OK",
  430. [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
  431. [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
  432. [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
  433. };
  434. static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
  435. {
  436. unsigned int monitor, state, value;
  437. const char *name, *state_txt;
  438. monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
  439. state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
  440. value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
  441. /* Deal gracefully with the board having more drivers than we
  442. * know about, but do not expect new sensor states. */
  443. name = (monitor >= ARRAY_SIZE(sensor_names))
  444. ? "No sensor name available" :
  445. sensor_names[monitor];
  446. EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
  447. state_txt = sensor_status_names[state];
  448. EFX_ERR(efx, "Sensor %d (%s) reports condition '%s' for raw value %d\n",
  449. monitor, name, state_txt, value);
  450. }
  451. /* Called from falcon_process_eventq for MCDI events */
  452. void efx_mcdi_process_event(struct efx_channel *channel,
  453. efx_qword_t *event)
  454. {
  455. struct efx_nic *efx = channel->efx;
  456. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  457. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  458. switch (code) {
  459. case MCDI_EVENT_CODE_BADSSERT:
  460. EFX_ERR(efx, "MC watchdog or assertion failure at 0x%x\n", data);
  461. efx_mcdi_ev_death(efx, EINTR);
  462. break;
  463. case MCDI_EVENT_CODE_PMNOTICE:
  464. EFX_INFO(efx, "MCDI PM event.\n");
  465. break;
  466. case MCDI_EVENT_CODE_CMDDONE:
  467. efx_mcdi_ev_cpl(efx,
  468. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  469. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  470. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  471. break;
  472. case MCDI_EVENT_CODE_LINKCHANGE:
  473. efx_mcdi_process_link_change(efx, event);
  474. break;
  475. case MCDI_EVENT_CODE_SENSOREVT:
  476. efx_mcdi_sensor_event(efx, event);
  477. break;
  478. case MCDI_EVENT_CODE_SCHEDERR:
  479. EFX_INFO(efx, "MC Scheduler error address=0x%x\n", data);
  480. break;
  481. case MCDI_EVENT_CODE_REBOOT:
  482. EFX_INFO(efx, "MC Reboot\n");
  483. efx_mcdi_ev_death(efx, EIO);
  484. break;
  485. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  486. /* MAC stats are gather lazily. We can ignore this. */
  487. break;
  488. default:
  489. EFX_ERR(efx, "Unknown MCDI event 0x%x\n", code);
  490. }
  491. }
  492. /**************************************************************************
  493. *
  494. * Specific request functions
  495. *
  496. **************************************************************************
  497. */
  498. int efx_mcdi_fwver(struct efx_nic *efx, u64 *version, u32 *build)
  499. {
  500. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
  501. size_t outlength;
  502. const __le16 *ver_words;
  503. int rc;
  504. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  505. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  506. outbuf, sizeof(outbuf), &outlength);
  507. if (rc)
  508. goto fail;
  509. if (outlength == MC_CMD_GET_VERSION_V0_OUT_LEN) {
  510. *version = 0;
  511. *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
  512. return 0;
  513. }
  514. if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
  515. rc = -EMSGSIZE;
  516. goto fail;
  517. }
  518. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  519. *version = (((u64)le16_to_cpu(ver_words[0]) << 48) |
  520. ((u64)le16_to_cpu(ver_words[1]) << 32) |
  521. ((u64)le16_to_cpu(ver_words[2]) << 16) |
  522. le16_to_cpu(ver_words[3]));
  523. *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
  524. return 0;
  525. fail:
  526. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  527. return rc;
  528. }
  529. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  530. bool *was_attached)
  531. {
  532. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  533. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  534. size_t outlen;
  535. int rc;
  536. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  537. driver_operating ? 1 : 0);
  538. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  539. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  540. outbuf, sizeof(outbuf), &outlen);
  541. if (rc)
  542. goto fail;
  543. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN)
  544. goto fail;
  545. if (was_attached != NULL)
  546. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  547. return 0;
  548. fail:
  549. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  550. return rc;
  551. }
  552. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  553. u16 *fw_subtype_list)
  554. {
  555. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
  556. size_t outlen;
  557. int port_num = efx_port_num(efx);
  558. int offset;
  559. int rc;
  560. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  561. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  562. outbuf, sizeof(outbuf), &outlen);
  563. if (rc)
  564. goto fail;
  565. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
  566. rc = -EMSGSIZE;
  567. goto fail;
  568. }
  569. offset = (port_num)
  570. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  571. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  572. if (mac_address)
  573. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  574. if (fw_subtype_list)
  575. memcpy(fw_subtype_list,
  576. outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
  577. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
  578. return 0;
  579. fail:
  580. EFX_ERR(efx, "%s: failed rc=%d len=%d\n", __func__, rc, (int)outlen);
  581. return rc;
  582. }
  583. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  584. {
  585. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  586. u32 dest = 0;
  587. int rc;
  588. if (uart)
  589. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  590. if (evq)
  591. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  592. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  593. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  594. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  595. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  596. NULL, 0, NULL);
  597. if (rc)
  598. goto fail;
  599. return 0;
  600. fail:
  601. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  602. return rc;
  603. }
  604. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  605. {
  606. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  607. size_t outlen;
  608. int rc;
  609. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  610. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  611. outbuf, sizeof(outbuf), &outlen);
  612. if (rc)
  613. goto fail;
  614. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN)
  615. goto fail;
  616. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  617. return 0;
  618. fail:
  619. EFX_ERR(efx, "%s: failed rc=%d\n",
  620. __func__, rc);
  621. return rc;
  622. }
  623. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  624. size_t *size_out, size_t *erase_size_out,
  625. bool *protected_out)
  626. {
  627. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  628. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  629. size_t outlen;
  630. int rc;
  631. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  632. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  633. outbuf, sizeof(outbuf), &outlen);
  634. if (rc)
  635. goto fail;
  636. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN)
  637. goto fail;
  638. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  639. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  640. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  641. (1 << MC_CMD_NVRAM_PROTECTED_LBN));
  642. return 0;
  643. fail:
  644. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  645. return rc;
  646. }
  647. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  648. {
  649. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  650. int rc;
  651. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  652. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  653. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  654. NULL, 0, NULL);
  655. if (rc)
  656. goto fail;
  657. return 0;
  658. fail:
  659. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  660. return rc;
  661. }
  662. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  663. loff_t offset, u8 *buffer, size_t length)
  664. {
  665. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  666. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  667. size_t outlen;
  668. int rc;
  669. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  670. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  671. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  672. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  673. outbuf, sizeof(outbuf), &outlen);
  674. if (rc)
  675. goto fail;
  676. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  677. return 0;
  678. fail:
  679. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  680. return rc;
  681. }
  682. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  683. loff_t offset, const u8 *buffer, size_t length)
  684. {
  685. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  686. int rc;
  687. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  688. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  689. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  690. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  691. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  692. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  693. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  694. NULL, 0, NULL);
  695. if (rc)
  696. goto fail;
  697. return 0;
  698. fail:
  699. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  700. return rc;
  701. }
  702. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  703. loff_t offset, size_t length)
  704. {
  705. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  706. int rc;
  707. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  708. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  709. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  710. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  711. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  712. NULL, 0, NULL);
  713. if (rc)
  714. goto fail;
  715. return 0;
  716. fail:
  717. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  718. return rc;
  719. }
  720. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  721. {
  722. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  723. int rc;
  724. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  725. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  726. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  727. NULL, 0, NULL);
  728. if (rc)
  729. goto fail;
  730. return 0;
  731. fail:
  732. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  733. return rc;
  734. }
  735. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  736. {
  737. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  738. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  739. int rc;
  740. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  741. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  742. outbuf, sizeof(outbuf), NULL);
  743. if (rc)
  744. return rc;
  745. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  746. case MC_CMD_NVRAM_TEST_PASS:
  747. case MC_CMD_NVRAM_TEST_NOTSUPP:
  748. return 0;
  749. default:
  750. return -EIO;
  751. }
  752. }
  753. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  754. {
  755. u32 nvram_types;
  756. unsigned int type;
  757. int rc;
  758. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  759. if (rc)
  760. return rc;
  761. type = 0;
  762. while (nvram_types != 0) {
  763. if (nvram_types & 1) {
  764. rc = efx_mcdi_nvram_test(efx, type);
  765. if (rc)
  766. return rc;
  767. }
  768. type++;
  769. nvram_types >>= 1;
  770. }
  771. return 0;
  772. }
  773. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  774. {
  775. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  776. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  777. unsigned int flags, index, ofst;
  778. const char *reason;
  779. size_t outlen;
  780. int retry;
  781. int rc;
  782. /* Attempt to read any stored assertion state before we reboot
  783. * the mcfw out of the assertion handler. Retry twice, once
  784. * because a boot-time assertion might cause this command to fail
  785. * with EINTR. And once again because GET_ASSERTS can race with
  786. * MC_CMD_REBOOT running on the other port. */
  787. retry = 2;
  788. do {
  789. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  790. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  791. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  792. outbuf, sizeof(outbuf), &outlen);
  793. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  794. if (rc)
  795. return rc;
  796. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  797. return -EINVAL;
  798. /* Print out any recorded assertion state */
  799. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  800. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  801. return 0;
  802. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  803. ? "system-level assertion"
  804. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  805. ? "thread-level assertion"
  806. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  807. ? "watchdog reset"
  808. : "unknown assertion";
  809. EFX_ERR(efx, "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  810. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  811. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  812. /* Print out the registers */
  813. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  814. for (index = 1; index < 32; index++) {
  815. EFX_ERR(efx, "R%.2d (?): 0x%.8x\n", index,
  816. MCDI_DWORD2(outbuf, ofst));
  817. ofst += sizeof(efx_dword_t);
  818. }
  819. return 0;
  820. }
  821. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  822. {
  823. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  824. /* Atomically reboot the mcfw out of the assertion handler */
  825. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  826. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  827. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  828. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  829. NULL, 0, NULL);
  830. }
  831. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  832. {
  833. int rc;
  834. rc = efx_mcdi_read_assertion(efx);
  835. if (rc)
  836. return rc;
  837. efx_mcdi_exit_assertion(efx);
  838. return 0;
  839. }
  840. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  841. {
  842. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  843. int rc;
  844. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  845. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  846. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  847. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  848. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  849. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  850. NULL, 0, NULL);
  851. if (rc)
  852. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  853. }
  854. int efx_mcdi_reset_port(struct efx_nic *efx)
  855. {
  856. int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
  857. if (rc)
  858. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  859. return rc;
  860. }
  861. int efx_mcdi_reset_mc(struct efx_nic *efx)
  862. {
  863. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  864. int rc;
  865. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  866. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  867. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  868. NULL, 0, NULL);
  869. /* White is black, and up is down */
  870. if (rc == -EIO)
  871. return 0;
  872. if (rc == 0)
  873. rc = -EIO;
  874. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  875. return rc;
  876. }
  877. int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  878. const u8 *mac, int *id_out)
  879. {
  880. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  881. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  882. size_t outlen;
  883. int rc;
  884. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  885. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  886. MC_CMD_FILTER_MODE_SIMPLE);
  887. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  888. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  889. outbuf, sizeof(outbuf), &outlen);
  890. if (rc)
  891. goto fail;
  892. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  893. rc = -EMSGSIZE;
  894. goto fail;
  895. }
  896. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  897. return 0;
  898. fail:
  899. *id_out = -1;
  900. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  901. return rc;
  902. }
  903. int
  904. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  905. {
  906. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  907. }
  908. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  909. {
  910. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  911. size_t outlen;
  912. int rc;
  913. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  914. outbuf, sizeof(outbuf), &outlen);
  915. if (rc)
  916. goto fail;
  917. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  918. rc = -EMSGSIZE;
  919. goto fail;
  920. }
  921. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  922. return 0;
  923. fail:
  924. *id_out = -1;
  925. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  926. return rc;
  927. }
  928. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  929. {
  930. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  931. int rc;
  932. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  933. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  934. NULL, 0, NULL);
  935. if (rc)
  936. goto fail;
  937. return 0;
  938. fail:
  939. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  940. return rc;
  941. }
  942. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  943. {
  944. int rc;
  945. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  946. if (rc)
  947. goto fail;
  948. return 0;
  949. fail:
  950. EFX_ERR(efx, "%s: failed rc=%d\n", __func__, rc);
  951. return rc;
  952. }