qlge_mpi.c 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305
  1. #include "qlge.h"
  2. int ql_unpause_mpi_risc(struct ql_adapter *qdev)
  3. {
  4. u32 tmp;
  5. /* Un-pause the RISC */
  6. tmp = ql_read32(qdev, CSR);
  7. if (!(tmp & CSR_RP))
  8. return -EIO;
  9. ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE);
  10. return 0;
  11. }
  12. int ql_pause_mpi_risc(struct ql_adapter *qdev)
  13. {
  14. u32 tmp;
  15. int count = UDELAY_COUNT;
  16. /* Pause the RISC */
  17. ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE);
  18. do {
  19. tmp = ql_read32(qdev, CSR);
  20. if (tmp & CSR_RP)
  21. break;
  22. mdelay(UDELAY_DELAY);
  23. count--;
  24. } while (count);
  25. return (count == 0) ? -ETIMEDOUT : 0;
  26. }
  27. int ql_hard_reset_mpi_risc(struct ql_adapter *qdev)
  28. {
  29. u32 tmp;
  30. int count = UDELAY_COUNT;
  31. /* Reset the RISC */
  32. ql_write32(qdev, CSR, CSR_CMD_SET_RST);
  33. do {
  34. tmp = ql_read32(qdev, CSR);
  35. if (tmp & CSR_RR) {
  36. ql_write32(qdev, CSR, CSR_CMD_CLR_RST);
  37. break;
  38. }
  39. mdelay(UDELAY_DELAY);
  40. count--;
  41. } while (count);
  42. return (count == 0) ? -ETIMEDOUT : 0;
  43. }
  44. int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
  45. {
  46. int status;
  47. /* wait for reg to come ready */
  48. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  49. if (status)
  50. goto exit;
  51. /* set up for reg read */
  52. ql_write32(qdev, PROC_ADDR, reg | PROC_ADDR_R);
  53. /* wait for reg to come ready */
  54. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  55. if (status)
  56. goto exit;
  57. /* get the data */
  58. *data = ql_read32(qdev, PROC_DATA);
  59. exit:
  60. return status;
  61. }
  62. int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data)
  63. {
  64. int status = 0;
  65. /* wait for reg to come ready */
  66. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  67. if (status)
  68. goto exit;
  69. /* write the data to the data reg */
  70. ql_write32(qdev, PROC_DATA, data);
  71. /* trigger the write */
  72. ql_write32(qdev, PROC_ADDR, reg);
  73. /* wait for reg to come ready */
  74. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  75. if (status)
  76. goto exit;
  77. exit:
  78. return status;
  79. }
  80. int ql_soft_reset_mpi_risc(struct ql_adapter *qdev)
  81. {
  82. int status;
  83. status = ql_write_mpi_reg(qdev, 0x00001010, 1);
  84. return status;
  85. }
  86. /* Determine if we are in charge of the firwmare. If
  87. * we are the lower of the 2 NIC pcie functions, or if
  88. * we are the higher function and the lower function
  89. * is not enabled.
  90. */
  91. int ql_own_firmware(struct ql_adapter *qdev)
  92. {
  93. u32 temp;
  94. /* If we are the lower of the 2 NIC functions
  95. * on the chip the we are responsible for
  96. * core dump and firmware reset after an error.
  97. */
  98. if (qdev->func < qdev->alt_func)
  99. return 1;
  100. /* If we are the higher of the 2 NIC functions
  101. * on the chip and the lower function is not
  102. * enabled, then we are responsible for
  103. * core dump and firmware reset after an error.
  104. */
  105. temp = ql_read32(qdev, STS);
  106. if (!(temp & (1 << (8 + qdev->alt_func))))
  107. return 1;
  108. return 0;
  109. }
  110. static int ql_get_mb_sts(struct ql_adapter *qdev, struct mbox_params *mbcp)
  111. {
  112. int i, status;
  113. status = ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
  114. if (status)
  115. return -EBUSY;
  116. for (i = 0; i < mbcp->out_count; i++) {
  117. status =
  118. ql_read_mpi_reg(qdev, qdev->mailbox_out + i,
  119. &mbcp->mbox_out[i]);
  120. if (status) {
  121. netif_err(qdev, drv, qdev->ndev, "Failed mailbox read.\n");
  122. break;
  123. }
  124. }
  125. ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
  126. return status;
  127. }
  128. /* Wait for a single mailbox command to complete.
  129. * Returns zero on success.
  130. */
  131. static int ql_wait_mbx_cmd_cmplt(struct ql_adapter *qdev)
  132. {
  133. int count = 100;
  134. u32 value;
  135. do {
  136. value = ql_read32(qdev, STS);
  137. if (value & STS_PI)
  138. return 0;
  139. mdelay(UDELAY_DELAY); /* 100ms */
  140. } while (--count);
  141. return -ETIMEDOUT;
  142. }
  143. /* Execute a single mailbox command.
  144. * Caller must hold PROC_ADDR semaphore.
  145. */
  146. static int ql_exec_mb_cmd(struct ql_adapter *qdev, struct mbox_params *mbcp)
  147. {
  148. int i, status;
  149. /*
  150. * Make sure there's nothing pending.
  151. * This shouldn't happen.
  152. */
  153. if (ql_read32(qdev, CSR) & CSR_HRI)
  154. return -EIO;
  155. status = ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
  156. if (status)
  157. return status;
  158. /*
  159. * Fill the outbound mailboxes.
  160. */
  161. for (i = 0; i < mbcp->in_count; i++) {
  162. status = ql_write_mpi_reg(qdev, qdev->mailbox_in + i,
  163. mbcp->mbox_in[i]);
  164. if (status)
  165. goto end;
  166. }
  167. /*
  168. * Wake up the MPI firmware.
  169. */
  170. ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT);
  171. end:
  172. ql_sem_unlock(qdev, SEM_PROC_REG_MASK);
  173. return status;
  174. }
  175. /* We are being asked by firmware to accept
  176. * a change to the port. This is only
  177. * a change to max frame sizes (Tx/Rx), pause
  178. * parameters, or loopback mode. We wake up a worker
  179. * to handler processing this since a mailbox command
  180. * will need to be sent to ACK the request.
  181. */
  182. static int ql_idc_req_aen(struct ql_adapter *qdev)
  183. {
  184. int status;
  185. struct mbox_params *mbcp = &qdev->idc_mbc;
  186. netif_err(qdev, drv, qdev->ndev, "Enter!\n");
  187. /* Get the status data and start up a thread to
  188. * handle the request.
  189. */
  190. mbcp = &qdev->idc_mbc;
  191. mbcp->out_count = 4;
  192. status = ql_get_mb_sts(qdev, mbcp);
  193. if (status) {
  194. netif_err(qdev, drv, qdev->ndev,
  195. "Could not read MPI, resetting ASIC!\n");
  196. ql_queue_asic_error(qdev);
  197. } else {
  198. /* Begin polled mode early so
  199. * we don't get another interrupt
  200. * when we leave mpi_worker.
  201. */
  202. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  203. queue_delayed_work(qdev->workqueue, &qdev->mpi_idc_work, 0);
  204. }
  205. return status;
  206. }
  207. /* Process an inter-device event completion.
  208. * If good, signal the caller's completion.
  209. */
  210. static int ql_idc_cmplt_aen(struct ql_adapter *qdev)
  211. {
  212. int status;
  213. struct mbox_params *mbcp = &qdev->idc_mbc;
  214. mbcp->out_count = 4;
  215. status = ql_get_mb_sts(qdev, mbcp);
  216. if (status) {
  217. netif_err(qdev, drv, qdev->ndev,
  218. "Could not read MPI, resetting RISC!\n");
  219. ql_queue_fw_error(qdev);
  220. } else
  221. /* Wake up the sleeping mpi_idc_work thread that is
  222. * waiting for this event.
  223. */
  224. complete(&qdev->ide_completion);
  225. return status;
  226. }
  227. static void ql_link_up(struct ql_adapter *qdev, struct mbox_params *mbcp)
  228. {
  229. int status;
  230. mbcp->out_count = 2;
  231. status = ql_get_mb_sts(qdev, mbcp);
  232. if (status) {
  233. netif_err(qdev, drv, qdev->ndev,
  234. "%s: Could not get mailbox status.\n", __func__);
  235. return;
  236. }
  237. qdev->link_status = mbcp->mbox_out[1];
  238. netif_err(qdev, drv, qdev->ndev, "Link Up.\n");
  239. /* If we're coming back from an IDC event
  240. * then set up the CAM and frame routing.
  241. */
  242. if (test_bit(QL_CAM_RT_SET, &qdev->flags)) {
  243. status = ql_cam_route_initialize(qdev);
  244. if (status) {
  245. netif_err(qdev, ifup, qdev->ndev,
  246. "Failed to init CAM/Routing tables.\n");
  247. return;
  248. } else
  249. clear_bit(QL_CAM_RT_SET, &qdev->flags);
  250. }
  251. /* Queue up a worker to check the frame
  252. * size information, and fix it if it's not
  253. * to our liking.
  254. */
  255. if (!test_bit(QL_PORT_CFG, &qdev->flags)) {
  256. netif_err(qdev, drv, qdev->ndev, "Queue Port Config Worker!\n");
  257. set_bit(QL_PORT_CFG, &qdev->flags);
  258. /* Begin polled mode early so
  259. * we don't get another interrupt
  260. * when we leave mpi_worker dpc.
  261. */
  262. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  263. queue_delayed_work(qdev->workqueue,
  264. &qdev->mpi_port_cfg_work, 0);
  265. }
  266. ql_link_on(qdev);
  267. }
  268. static void ql_link_down(struct ql_adapter *qdev, struct mbox_params *mbcp)
  269. {
  270. int status;
  271. mbcp->out_count = 3;
  272. status = ql_get_mb_sts(qdev, mbcp);
  273. if (status)
  274. netif_err(qdev, drv, qdev->ndev, "Link down AEN broken!\n");
  275. ql_link_off(qdev);
  276. }
  277. static int ql_sfp_in(struct ql_adapter *qdev, struct mbox_params *mbcp)
  278. {
  279. int status;
  280. mbcp->out_count = 5;
  281. status = ql_get_mb_sts(qdev, mbcp);
  282. if (status)
  283. netif_err(qdev, drv, qdev->ndev, "SFP in AEN broken!\n");
  284. else
  285. netif_err(qdev, drv, qdev->ndev, "SFP insertion detected.\n");
  286. return status;
  287. }
  288. static int ql_sfp_out(struct ql_adapter *qdev, struct mbox_params *mbcp)
  289. {
  290. int status;
  291. mbcp->out_count = 1;
  292. status = ql_get_mb_sts(qdev, mbcp);
  293. if (status)
  294. netif_err(qdev, drv, qdev->ndev, "SFP out AEN broken!\n");
  295. else
  296. netif_err(qdev, drv, qdev->ndev, "SFP removal detected.\n");
  297. return status;
  298. }
  299. static int ql_aen_lost(struct ql_adapter *qdev, struct mbox_params *mbcp)
  300. {
  301. int status;
  302. mbcp->out_count = 6;
  303. status = ql_get_mb_sts(qdev, mbcp);
  304. if (status)
  305. netif_err(qdev, drv, qdev->ndev, "Lost AEN broken!\n");
  306. else {
  307. int i;
  308. netif_err(qdev, drv, qdev->ndev, "Lost AEN detected.\n");
  309. for (i = 0; i < mbcp->out_count; i++)
  310. netif_err(qdev, drv, qdev->ndev, "mbox_out[%d] = 0x%.08x.\n",
  311. i, mbcp->mbox_out[i]);
  312. }
  313. return status;
  314. }
  315. static void ql_init_fw_done(struct ql_adapter *qdev, struct mbox_params *mbcp)
  316. {
  317. int status;
  318. mbcp->out_count = 2;
  319. status = ql_get_mb_sts(qdev, mbcp);
  320. if (status) {
  321. netif_err(qdev, drv, qdev->ndev, "Firmware did not initialize!\n");
  322. } else {
  323. netif_err(qdev, drv, qdev->ndev, "Firmware Revision = 0x%.08x.\n",
  324. mbcp->mbox_out[1]);
  325. qdev->fw_rev_id = mbcp->mbox_out[1];
  326. status = ql_cam_route_initialize(qdev);
  327. if (status)
  328. netif_err(qdev, ifup, qdev->ndev,
  329. "Failed to init CAM/Routing tables.\n");
  330. }
  331. }
  332. /* Process an async event and clear it unless it's an
  333. * error condition.
  334. * This can get called iteratively from the mpi_work thread
  335. * when events arrive via an interrupt.
  336. * It also gets called when a mailbox command is polling for
  337. * it's completion. */
  338. static int ql_mpi_handler(struct ql_adapter *qdev, struct mbox_params *mbcp)
  339. {
  340. int status;
  341. int orig_count = mbcp->out_count;
  342. /* Just get mailbox zero for now. */
  343. mbcp->out_count = 1;
  344. status = ql_get_mb_sts(qdev, mbcp);
  345. if (status) {
  346. netif_err(qdev, drv, qdev->ndev,
  347. "Could not read MPI, resetting ASIC!\n");
  348. ql_queue_asic_error(qdev);
  349. goto end;
  350. }
  351. switch (mbcp->mbox_out[0]) {
  352. /* This case is only active when we arrive here
  353. * as a result of issuing a mailbox command to
  354. * the firmware.
  355. */
  356. case MB_CMD_STS_INTRMDT:
  357. case MB_CMD_STS_GOOD:
  358. case MB_CMD_STS_INVLD_CMD:
  359. case MB_CMD_STS_XFC_ERR:
  360. case MB_CMD_STS_CSUM_ERR:
  361. case MB_CMD_STS_ERR:
  362. case MB_CMD_STS_PARAM_ERR:
  363. /* We can only get mailbox status if we're polling from an
  364. * unfinished command. Get the rest of the status data and
  365. * return back to the caller.
  366. * We only end up here when we're polling for a mailbox
  367. * command completion.
  368. */
  369. mbcp->out_count = orig_count;
  370. status = ql_get_mb_sts(qdev, mbcp);
  371. return status;
  372. /* We are being asked by firmware to accept
  373. * a change to the port. This is only
  374. * a change to max frame sizes (Tx/Rx), pause
  375. * parameters, or loopback mode.
  376. */
  377. case AEN_IDC_REQ:
  378. status = ql_idc_req_aen(qdev);
  379. break;
  380. /* Process and inbound IDC event.
  381. * This will happen when we're trying to
  382. * change tx/rx max frame size, change pause
  383. * parameters or loopback mode.
  384. */
  385. case AEN_IDC_CMPLT:
  386. case AEN_IDC_EXT:
  387. status = ql_idc_cmplt_aen(qdev);
  388. break;
  389. case AEN_LINK_UP:
  390. ql_link_up(qdev, mbcp);
  391. break;
  392. case AEN_LINK_DOWN:
  393. ql_link_down(qdev, mbcp);
  394. break;
  395. case AEN_FW_INIT_DONE:
  396. /* If we're in process on executing the firmware,
  397. * then convert the status to normal mailbox status.
  398. */
  399. if (mbcp->mbox_in[0] == MB_CMD_EX_FW) {
  400. mbcp->out_count = orig_count;
  401. status = ql_get_mb_sts(qdev, mbcp);
  402. mbcp->mbox_out[0] = MB_CMD_STS_GOOD;
  403. return status;
  404. }
  405. ql_init_fw_done(qdev, mbcp);
  406. break;
  407. case AEN_AEN_SFP_IN:
  408. ql_sfp_in(qdev, mbcp);
  409. break;
  410. case AEN_AEN_SFP_OUT:
  411. ql_sfp_out(qdev, mbcp);
  412. break;
  413. /* This event can arrive at boot time or after an
  414. * MPI reset if the firmware failed to initialize.
  415. */
  416. case AEN_FW_INIT_FAIL:
  417. /* If we're in process on executing the firmware,
  418. * then convert the status to normal mailbox status.
  419. */
  420. if (mbcp->mbox_in[0] == MB_CMD_EX_FW) {
  421. mbcp->out_count = orig_count;
  422. status = ql_get_mb_sts(qdev, mbcp);
  423. mbcp->mbox_out[0] = MB_CMD_STS_ERR;
  424. return status;
  425. }
  426. netif_err(qdev, drv, qdev->ndev,
  427. "Firmware initialization failed.\n");
  428. status = -EIO;
  429. ql_queue_fw_error(qdev);
  430. break;
  431. case AEN_SYS_ERR:
  432. netif_err(qdev, drv, qdev->ndev, "System Error.\n");
  433. ql_queue_fw_error(qdev);
  434. status = -EIO;
  435. break;
  436. case AEN_AEN_LOST:
  437. ql_aen_lost(qdev, mbcp);
  438. break;
  439. case AEN_DCBX_CHG:
  440. /* Need to support AEN 8110 */
  441. break;
  442. default:
  443. netif_err(qdev, drv, qdev->ndev,
  444. "Unsupported AE %.08x.\n", mbcp->mbox_out[0]);
  445. /* Clear the MPI firmware status. */
  446. }
  447. end:
  448. ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
  449. /* Restore the original mailbox count to
  450. * what the caller asked for. This can get
  451. * changed when a mailbox command is waiting
  452. * for a response and an AEN arrives and
  453. * is handled.
  454. * */
  455. mbcp->out_count = orig_count;
  456. return status;
  457. }
  458. /* Execute a single mailbox command.
  459. * mbcp is a pointer to an array of u32. Each
  460. * element in the array contains the value for it's
  461. * respective mailbox register.
  462. */
  463. static int ql_mailbox_command(struct ql_adapter *qdev, struct mbox_params *mbcp)
  464. {
  465. int status;
  466. unsigned long count;
  467. /* Begin polled mode for MPI */
  468. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  469. /* Load the mailbox registers and wake up MPI RISC. */
  470. status = ql_exec_mb_cmd(qdev, mbcp);
  471. if (status)
  472. goto end;
  473. /* If we're generating a system error, then there's nothing
  474. * to wait for.
  475. */
  476. if (mbcp->mbox_in[0] == MB_CMD_MAKE_SYS_ERR)
  477. goto end;
  478. /* Wait for the command to complete. We loop
  479. * here because some AEN might arrive while
  480. * we're waiting for the mailbox command to
  481. * complete. If more than 5 seconds expire we can
  482. * assume something is wrong. */
  483. count = jiffies + HZ * MAILBOX_TIMEOUT;
  484. do {
  485. /* Wait for the interrupt to come in. */
  486. status = ql_wait_mbx_cmd_cmplt(qdev);
  487. if (status)
  488. continue;
  489. /* Process the event. If it's an AEN, it
  490. * will be handled in-line or a worker
  491. * will be spawned. If it's our completion
  492. * we will catch it below.
  493. */
  494. status = ql_mpi_handler(qdev, mbcp);
  495. if (status)
  496. goto end;
  497. /* It's either the completion for our mailbox
  498. * command complete or an AEN. If it's our
  499. * completion then get out.
  500. */
  501. if (((mbcp->mbox_out[0] & 0x0000f000) ==
  502. MB_CMD_STS_GOOD) ||
  503. ((mbcp->mbox_out[0] & 0x0000f000) ==
  504. MB_CMD_STS_INTRMDT))
  505. goto done;
  506. } while (time_before(jiffies, count));
  507. netif_err(qdev, drv, qdev->ndev,
  508. "Timed out waiting for mailbox complete.\n");
  509. status = -ETIMEDOUT;
  510. goto end;
  511. done:
  512. /* Now we can clear the interrupt condition
  513. * and look at our status.
  514. */
  515. ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
  516. if (((mbcp->mbox_out[0] & 0x0000f000) !=
  517. MB_CMD_STS_GOOD) &&
  518. ((mbcp->mbox_out[0] & 0x0000f000) !=
  519. MB_CMD_STS_INTRMDT)) {
  520. status = -EIO;
  521. }
  522. end:
  523. /* End polled mode for MPI */
  524. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
  525. return status;
  526. }
  527. int ql_mb_sys_err(struct ql_adapter *qdev)
  528. {
  529. struct mbox_params mbc;
  530. struct mbox_params *mbcp = &mbc;
  531. int status;
  532. memset(mbcp, 0, sizeof(struct mbox_params));
  533. mbcp->in_count = 1;
  534. mbcp->out_count = 0;
  535. mbcp->mbox_in[0] = MB_CMD_MAKE_SYS_ERR;
  536. status = ql_mailbox_command(qdev, mbcp);
  537. return status;
  538. }
  539. /* Get MPI firmware version. This will be used for
  540. * driver banner and for ethtool info.
  541. * Returns zero on success.
  542. */
  543. int ql_mb_about_fw(struct ql_adapter *qdev)
  544. {
  545. struct mbox_params mbc;
  546. struct mbox_params *mbcp = &mbc;
  547. int status = 0;
  548. memset(mbcp, 0, sizeof(struct mbox_params));
  549. mbcp->in_count = 1;
  550. mbcp->out_count = 3;
  551. mbcp->mbox_in[0] = MB_CMD_ABOUT_FW;
  552. status = ql_mailbox_command(qdev, mbcp);
  553. if (status)
  554. return status;
  555. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  556. netif_err(qdev, drv, qdev->ndev,
  557. "Failed about firmware command\n");
  558. status = -EIO;
  559. }
  560. /* Store the firmware version */
  561. qdev->fw_rev_id = mbcp->mbox_out[1];
  562. return status;
  563. }
  564. /* Get functional state for MPI firmware.
  565. * Returns zero on success.
  566. */
  567. int ql_mb_get_fw_state(struct ql_adapter *qdev)
  568. {
  569. struct mbox_params mbc;
  570. struct mbox_params *mbcp = &mbc;
  571. int status = 0;
  572. memset(mbcp, 0, sizeof(struct mbox_params));
  573. mbcp->in_count = 1;
  574. mbcp->out_count = 2;
  575. mbcp->mbox_in[0] = MB_CMD_GET_FW_STATE;
  576. status = ql_mailbox_command(qdev, mbcp);
  577. if (status)
  578. return status;
  579. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  580. netif_err(qdev, drv, qdev->ndev,
  581. "Failed Get Firmware State.\n");
  582. status = -EIO;
  583. }
  584. /* If bit zero is set in mbx 1 then the firmware is
  585. * running, but not initialized. This should never
  586. * happen.
  587. */
  588. if (mbcp->mbox_out[1] & 1) {
  589. netif_err(qdev, drv, qdev->ndev,
  590. "Firmware waiting for initialization.\n");
  591. status = -EIO;
  592. }
  593. return status;
  594. }
  595. /* Send and ACK mailbox command to the firmware to
  596. * let it continue with the change.
  597. */
  598. int ql_mb_idc_ack(struct ql_adapter *qdev)
  599. {
  600. struct mbox_params mbc;
  601. struct mbox_params *mbcp = &mbc;
  602. int status = 0;
  603. memset(mbcp, 0, sizeof(struct mbox_params));
  604. mbcp->in_count = 5;
  605. mbcp->out_count = 1;
  606. mbcp->mbox_in[0] = MB_CMD_IDC_ACK;
  607. mbcp->mbox_in[1] = qdev->idc_mbc.mbox_out[1];
  608. mbcp->mbox_in[2] = qdev->idc_mbc.mbox_out[2];
  609. mbcp->mbox_in[3] = qdev->idc_mbc.mbox_out[3];
  610. mbcp->mbox_in[4] = qdev->idc_mbc.mbox_out[4];
  611. status = ql_mailbox_command(qdev, mbcp);
  612. if (status)
  613. return status;
  614. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  615. netif_err(qdev, drv, qdev->ndev, "Failed IDC ACK send.\n");
  616. status = -EIO;
  617. }
  618. return status;
  619. }
  620. /* Get link settings and maximum frame size settings
  621. * for the current port.
  622. * Most likely will block.
  623. */
  624. int ql_mb_set_port_cfg(struct ql_adapter *qdev)
  625. {
  626. struct mbox_params mbc;
  627. struct mbox_params *mbcp = &mbc;
  628. int status = 0;
  629. memset(mbcp, 0, sizeof(struct mbox_params));
  630. mbcp->in_count = 3;
  631. mbcp->out_count = 1;
  632. mbcp->mbox_in[0] = MB_CMD_SET_PORT_CFG;
  633. mbcp->mbox_in[1] = qdev->link_config;
  634. mbcp->mbox_in[2] = qdev->max_frame_size;
  635. status = ql_mailbox_command(qdev, mbcp);
  636. if (status)
  637. return status;
  638. if (mbcp->mbox_out[0] == MB_CMD_STS_INTRMDT) {
  639. netif_err(qdev, drv, qdev->ndev,
  640. "Port Config sent, wait for IDC.\n");
  641. } else if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  642. netif_err(qdev, drv, qdev->ndev,
  643. "Failed Set Port Configuration.\n");
  644. status = -EIO;
  645. }
  646. return status;
  647. }
  648. int ql_mb_dump_ram(struct ql_adapter *qdev, u64 req_dma, u32 addr,
  649. u32 size)
  650. {
  651. int status = 0;
  652. struct mbox_params mbc;
  653. struct mbox_params *mbcp = &mbc;
  654. memset(mbcp, 0, sizeof(struct mbox_params));
  655. mbcp->in_count = 9;
  656. mbcp->out_count = 1;
  657. mbcp->mbox_in[0] = MB_CMD_DUMP_RISC_RAM;
  658. mbcp->mbox_in[1] = LSW(addr);
  659. mbcp->mbox_in[2] = MSW(req_dma);
  660. mbcp->mbox_in[3] = LSW(req_dma);
  661. mbcp->mbox_in[4] = MSW(size);
  662. mbcp->mbox_in[5] = LSW(size);
  663. mbcp->mbox_in[6] = MSW(MSD(req_dma));
  664. mbcp->mbox_in[7] = LSW(MSD(req_dma));
  665. mbcp->mbox_in[8] = MSW(addr);
  666. status = ql_mailbox_command(qdev, mbcp);
  667. if (status)
  668. return status;
  669. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  670. netif_err(qdev, drv, qdev->ndev, "Failed to dump risc RAM.\n");
  671. status = -EIO;
  672. }
  673. return status;
  674. }
  675. /* Issue a mailbox command to dump RISC RAM. */
  676. int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
  677. u32 ram_addr, int word_count)
  678. {
  679. int status;
  680. char *my_buf;
  681. dma_addr_t buf_dma;
  682. my_buf = pci_alloc_consistent(qdev->pdev, word_count * sizeof(u32),
  683. &buf_dma);
  684. if (!my_buf)
  685. return -EIO;
  686. status = ql_mb_dump_ram(qdev, buf_dma, ram_addr, word_count);
  687. if (!status)
  688. memcpy(buf, my_buf, word_count * sizeof(u32));
  689. pci_free_consistent(qdev->pdev, word_count * sizeof(u32), my_buf,
  690. buf_dma);
  691. return status;
  692. }
  693. /* Get link settings and maximum frame size settings
  694. * for the current port.
  695. * Most likely will block.
  696. */
  697. int ql_mb_get_port_cfg(struct ql_adapter *qdev)
  698. {
  699. struct mbox_params mbc;
  700. struct mbox_params *mbcp = &mbc;
  701. int status = 0;
  702. memset(mbcp, 0, sizeof(struct mbox_params));
  703. mbcp->in_count = 1;
  704. mbcp->out_count = 3;
  705. mbcp->mbox_in[0] = MB_CMD_GET_PORT_CFG;
  706. status = ql_mailbox_command(qdev, mbcp);
  707. if (status)
  708. return status;
  709. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  710. netif_err(qdev, drv, qdev->ndev,
  711. "Failed Get Port Configuration.\n");
  712. status = -EIO;
  713. } else {
  714. netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
  715. "Passed Get Port Configuration.\n");
  716. qdev->link_config = mbcp->mbox_out[1];
  717. qdev->max_frame_size = mbcp->mbox_out[2];
  718. }
  719. return status;
  720. }
  721. int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol)
  722. {
  723. struct mbox_params mbc;
  724. struct mbox_params *mbcp = &mbc;
  725. int status;
  726. memset(mbcp, 0, sizeof(struct mbox_params));
  727. mbcp->in_count = 2;
  728. mbcp->out_count = 1;
  729. mbcp->mbox_in[0] = MB_CMD_SET_WOL_MODE;
  730. mbcp->mbox_in[1] = wol;
  731. status = ql_mailbox_command(qdev, mbcp);
  732. if (status)
  733. return status;
  734. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  735. netif_err(qdev, drv, qdev->ndev, "Failed to set WOL mode.\n");
  736. status = -EIO;
  737. }
  738. return status;
  739. }
  740. int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol)
  741. {
  742. struct mbox_params mbc;
  743. struct mbox_params *mbcp = &mbc;
  744. int status;
  745. u8 *addr = qdev->ndev->dev_addr;
  746. memset(mbcp, 0, sizeof(struct mbox_params));
  747. mbcp->in_count = 8;
  748. mbcp->out_count = 1;
  749. mbcp->mbox_in[0] = MB_CMD_SET_WOL_MAGIC;
  750. if (enable_wol) {
  751. mbcp->mbox_in[1] = (u32)addr[0];
  752. mbcp->mbox_in[2] = (u32)addr[1];
  753. mbcp->mbox_in[3] = (u32)addr[2];
  754. mbcp->mbox_in[4] = (u32)addr[3];
  755. mbcp->mbox_in[5] = (u32)addr[4];
  756. mbcp->mbox_in[6] = (u32)addr[5];
  757. mbcp->mbox_in[7] = 0;
  758. } else {
  759. mbcp->mbox_in[1] = 0;
  760. mbcp->mbox_in[2] = 1;
  761. mbcp->mbox_in[3] = 1;
  762. mbcp->mbox_in[4] = 1;
  763. mbcp->mbox_in[5] = 1;
  764. mbcp->mbox_in[6] = 1;
  765. mbcp->mbox_in[7] = 0;
  766. }
  767. status = ql_mailbox_command(qdev, mbcp);
  768. if (status)
  769. return status;
  770. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  771. netif_err(qdev, drv, qdev->ndev, "Failed to set WOL mode.\n");
  772. status = -EIO;
  773. }
  774. return status;
  775. }
  776. /* IDC - Inter Device Communication...
  777. * Some firmware commands require consent of adjacent FCOE
  778. * function. This function waits for the OK, or a
  779. * counter-request for a little more time.i
  780. * The firmware will complete the request if the other
  781. * function doesn't respond.
  782. */
  783. static int ql_idc_wait(struct ql_adapter *qdev)
  784. {
  785. int status = -ETIMEDOUT;
  786. long wait_time = 1 * HZ;
  787. struct mbox_params *mbcp = &qdev->idc_mbc;
  788. do {
  789. /* Wait here for the command to complete
  790. * via the IDC process.
  791. */
  792. wait_time =
  793. wait_for_completion_timeout(&qdev->ide_completion,
  794. wait_time);
  795. if (!wait_time) {
  796. netif_err(qdev, drv, qdev->ndev, "IDC Timeout.\n");
  797. break;
  798. }
  799. /* Now examine the response from the IDC process.
  800. * We might have a good completion or a request for
  801. * more wait time.
  802. */
  803. if (mbcp->mbox_out[0] == AEN_IDC_EXT) {
  804. netif_err(qdev, drv, qdev->ndev,
  805. "IDC Time Extension from function.\n");
  806. wait_time += (mbcp->mbox_out[1] >> 8) & 0x0000000f;
  807. } else if (mbcp->mbox_out[0] == AEN_IDC_CMPLT) {
  808. netif_err(qdev, drv, qdev->ndev, "IDC Success.\n");
  809. status = 0;
  810. break;
  811. } else {
  812. netif_err(qdev, drv, qdev->ndev,
  813. "IDC: Invalid State 0x%.04x.\n",
  814. mbcp->mbox_out[0]);
  815. status = -EIO;
  816. break;
  817. }
  818. } while (wait_time);
  819. return status;
  820. }
  821. int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config)
  822. {
  823. struct mbox_params mbc;
  824. struct mbox_params *mbcp = &mbc;
  825. int status;
  826. memset(mbcp, 0, sizeof(struct mbox_params));
  827. mbcp->in_count = 2;
  828. mbcp->out_count = 1;
  829. mbcp->mbox_in[0] = MB_CMD_SET_LED_CFG;
  830. mbcp->mbox_in[1] = led_config;
  831. status = ql_mailbox_command(qdev, mbcp);
  832. if (status)
  833. return status;
  834. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  835. netif_err(qdev, drv, qdev->ndev,
  836. "Failed to set LED Configuration.\n");
  837. status = -EIO;
  838. }
  839. return status;
  840. }
  841. int ql_mb_get_led_cfg(struct ql_adapter *qdev)
  842. {
  843. struct mbox_params mbc;
  844. struct mbox_params *mbcp = &mbc;
  845. int status;
  846. memset(mbcp, 0, sizeof(struct mbox_params));
  847. mbcp->in_count = 1;
  848. mbcp->out_count = 2;
  849. mbcp->mbox_in[0] = MB_CMD_GET_LED_CFG;
  850. status = ql_mailbox_command(qdev, mbcp);
  851. if (status)
  852. return status;
  853. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  854. netif_err(qdev, drv, qdev->ndev,
  855. "Failed to get LED Configuration.\n");
  856. status = -EIO;
  857. } else
  858. qdev->led_config = mbcp->mbox_out[1];
  859. return status;
  860. }
  861. int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control)
  862. {
  863. struct mbox_params mbc;
  864. struct mbox_params *mbcp = &mbc;
  865. int status;
  866. memset(mbcp, 0, sizeof(struct mbox_params));
  867. mbcp->in_count = 1;
  868. mbcp->out_count = 2;
  869. mbcp->mbox_in[0] = MB_CMD_SET_MGMNT_TFK_CTL;
  870. mbcp->mbox_in[1] = control;
  871. status = ql_mailbox_command(qdev, mbcp);
  872. if (status)
  873. return status;
  874. if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD)
  875. return status;
  876. if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
  877. netif_err(qdev, drv, qdev->ndev,
  878. "Command not supported by firmware.\n");
  879. status = -EINVAL;
  880. } else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
  881. /* This indicates that the firmware is
  882. * already in the state we are trying to
  883. * change it to.
  884. */
  885. netif_err(qdev, drv, qdev->ndev,
  886. "Command parameters make no change.\n");
  887. }
  888. return status;
  889. }
  890. /* Returns a negative error code or the mailbox command status. */
  891. static int ql_mb_get_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 *control)
  892. {
  893. struct mbox_params mbc;
  894. struct mbox_params *mbcp = &mbc;
  895. int status;
  896. memset(mbcp, 0, sizeof(struct mbox_params));
  897. *control = 0;
  898. mbcp->in_count = 1;
  899. mbcp->out_count = 1;
  900. mbcp->mbox_in[0] = MB_CMD_GET_MGMNT_TFK_CTL;
  901. status = ql_mailbox_command(qdev, mbcp);
  902. if (status)
  903. return status;
  904. if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD) {
  905. *control = mbcp->mbox_in[1];
  906. return status;
  907. }
  908. if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
  909. netif_err(qdev, drv, qdev->ndev,
  910. "Command not supported by firmware.\n");
  911. status = -EINVAL;
  912. } else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
  913. netif_err(qdev, drv, qdev->ndev,
  914. "Failed to get MPI traffic control.\n");
  915. status = -EIO;
  916. }
  917. return status;
  918. }
  919. int ql_wait_fifo_empty(struct ql_adapter *qdev)
  920. {
  921. int count = 5;
  922. u32 mgmnt_fifo_empty;
  923. u32 nic_fifo_empty;
  924. do {
  925. nic_fifo_empty = ql_read32(qdev, STS) & STS_NFE;
  926. ql_mb_get_mgmnt_traffic_ctl(qdev, &mgmnt_fifo_empty);
  927. mgmnt_fifo_empty &= MB_GET_MPI_TFK_FIFO_EMPTY;
  928. if (nic_fifo_empty && mgmnt_fifo_empty)
  929. return 0;
  930. msleep(100);
  931. } while (count-- > 0);
  932. return -ETIMEDOUT;
  933. }
  934. /* API called in work thread context to set new TX/RX
  935. * maximum frame size values to match MTU.
  936. */
  937. static int ql_set_port_cfg(struct ql_adapter *qdev)
  938. {
  939. int status;
  940. rtnl_lock();
  941. status = ql_mb_set_port_cfg(qdev);
  942. rtnl_unlock();
  943. if (status)
  944. return status;
  945. status = ql_idc_wait(qdev);
  946. return status;
  947. }
  948. /* The following routines are worker threads that process
  949. * events that may sleep waiting for completion.
  950. */
  951. /* This thread gets the maximum TX and RX frame size values
  952. * from the firmware and, if necessary, changes them to match
  953. * the MTU setting.
  954. */
  955. void ql_mpi_port_cfg_work(struct work_struct *work)
  956. {
  957. struct ql_adapter *qdev =
  958. container_of(work, struct ql_adapter, mpi_port_cfg_work.work);
  959. int status;
  960. rtnl_lock();
  961. status = ql_mb_get_port_cfg(qdev);
  962. rtnl_unlock();
  963. if (status) {
  964. netif_err(qdev, drv, qdev->ndev,
  965. "Bug: Failed to get port config data.\n");
  966. goto err;
  967. }
  968. if (qdev->link_config & CFG_JUMBO_FRAME_SIZE &&
  969. qdev->max_frame_size ==
  970. CFG_DEFAULT_MAX_FRAME_SIZE)
  971. goto end;
  972. qdev->link_config |= CFG_JUMBO_FRAME_SIZE;
  973. qdev->max_frame_size = CFG_DEFAULT_MAX_FRAME_SIZE;
  974. status = ql_set_port_cfg(qdev);
  975. if (status) {
  976. netif_err(qdev, drv, qdev->ndev,
  977. "Bug: Failed to set port config data.\n");
  978. goto err;
  979. }
  980. end:
  981. clear_bit(QL_PORT_CFG, &qdev->flags);
  982. return;
  983. err:
  984. ql_queue_fw_error(qdev);
  985. goto end;
  986. }
  987. /* Process an inter-device request. This is issues by
  988. * the firmware in response to another function requesting
  989. * a change to the port. We set a flag to indicate a change
  990. * has been made and then send a mailbox command ACKing
  991. * the change request.
  992. */
  993. void ql_mpi_idc_work(struct work_struct *work)
  994. {
  995. struct ql_adapter *qdev =
  996. container_of(work, struct ql_adapter, mpi_idc_work.work);
  997. int status;
  998. struct mbox_params *mbcp = &qdev->idc_mbc;
  999. u32 aen;
  1000. int timeout;
  1001. rtnl_lock();
  1002. aen = mbcp->mbox_out[1] >> 16;
  1003. timeout = (mbcp->mbox_out[1] >> 8) & 0xf;
  1004. switch (aen) {
  1005. default:
  1006. netif_err(qdev, drv, qdev->ndev,
  1007. "Bug: Unhandled IDC action.\n");
  1008. break;
  1009. case MB_CMD_PORT_RESET:
  1010. case MB_CMD_STOP_FW:
  1011. ql_link_off(qdev);
  1012. case MB_CMD_SET_PORT_CFG:
  1013. /* Signal the resulting link up AEN
  1014. * that the frame routing and mac addr
  1015. * needs to be set.
  1016. * */
  1017. set_bit(QL_CAM_RT_SET, &qdev->flags);
  1018. /* Do ACK if required */
  1019. if (timeout) {
  1020. status = ql_mb_idc_ack(qdev);
  1021. if (status)
  1022. netif_err(qdev, drv, qdev->ndev,
  1023. "Bug: No pending IDC!\n");
  1024. } else {
  1025. netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
  1026. "IDC ACK not required\n");
  1027. status = 0; /* success */
  1028. }
  1029. break;
  1030. /* These sub-commands issued by another (FCoE)
  1031. * function are requesting to do an operation
  1032. * on the shared resource (MPI environment).
  1033. * We currently don't issue these so we just
  1034. * ACK the request.
  1035. */
  1036. case MB_CMD_IOP_RESTART_MPI:
  1037. case MB_CMD_IOP_PREP_LINK_DOWN:
  1038. /* Drop the link, reload the routing
  1039. * table when link comes up.
  1040. */
  1041. ql_link_off(qdev);
  1042. set_bit(QL_CAM_RT_SET, &qdev->flags);
  1043. /* Fall through. */
  1044. case MB_CMD_IOP_DVR_START:
  1045. case MB_CMD_IOP_FLASH_ACC:
  1046. case MB_CMD_IOP_CORE_DUMP_MPI:
  1047. case MB_CMD_IOP_PREP_UPDATE_MPI:
  1048. case MB_CMD_IOP_COMP_UPDATE_MPI:
  1049. case MB_CMD_IOP_NONE: /* an IDC without params */
  1050. /* Do ACK if required */
  1051. if (timeout) {
  1052. status = ql_mb_idc_ack(qdev);
  1053. if (status)
  1054. netif_err(qdev, drv, qdev->ndev,
  1055. "Bug: No pending IDC!\n");
  1056. } else {
  1057. netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
  1058. "IDC ACK not required\n");
  1059. status = 0; /* success */
  1060. }
  1061. break;
  1062. }
  1063. rtnl_unlock();
  1064. }
  1065. void ql_mpi_work(struct work_struct *work)
  1066. {
  1067. struct ql_adapter *qdev =
  1068. container_of(work, struct ql_adapter, mpi_work.work);
  1069. struct mbox_params mbc;
  1070. struct mbox_params *mbcp = &mbc;
  1071. int err = 0;
  1072. rtnl_lock();
  1073. /* Begin polled mode for MPI */
  1074. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  1075. while (ql_read32(qdev, STS) & STS_PI) {
  1076. memset(mbcp, 0, sizeof(struct mbox_params));
  1077. mbcp->out_count = 1;
  1078. /* Don't continue if an async event
  1079. * did not complete properly.
  1080. */
  1081. err = ql_mpi_handler(qdev, mbcp);
  1082. if (err)
  1083. break;
  1084. }
  1085. /* End polled mode for MPI */
  1086. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
  1087. rtnl_unlock();
  1088. ql_enable_completion_interrupt(qdev, 0);
  1089. }
  1090. void ql_mpi_reset_work(struct work_struct *work)
  1091. {
  1092. struct ql_adapter *qdev =
  1093. container_of(work, struct ql_adapter, mpi_reset_work.work);
  1094. cancel_delayed_work_sync(&qdev->mpi_work);
  1095. cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
  1096. cancel_delayed_work_sync(&qdev->mpi_idc_work);
  1097. /* If we're not the dominant NIC function,
  1098. * then there is nothing to do.
  1099. */
  1100. if (!ql_own_firmware(qdev)) {
  1101. netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n");
  1102. return;
  1103. }
  1104. if (!ql_core_dump(qdev, qdev->mpi_coredump)) {
  1105. netif_err(qdev, drv, qdev->ndev, "Core is dumped!\n");
  1106. qdev->core_is_dumped = 1;
  1107. queue_delayed_work(qdev->workqueue,
  1108. &qdev->mpi_core_to_log, 5 * HZ);
  1109. }
  1110. ql_soft_reset_mpi_risc(qdev);
  1111. }