marvell.c 15 KB

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  1. /*
  2. * drivers/net/phy/marvell.c
  3. *
  4. * Driver for Marvell PHYs
  5. *
  6. * Author: Andy Fleming
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/slab.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/skbuff.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/mm.h>
  29. #include <linux/module.h>
  30. #include <linux/mii.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/phy.h>
  33. #include <asm/io.h>
  34. #include <asm/irq.h>
  35. #include <asm/uaccess.h>
  36. #define MII_M1011_IEVENT 0x13
  37. #define MII_M1011_IEVENT_CLEAR 0x0000
  38. #define MII_M1011_IMASK 0x12
  39. #define MII_M1011_IMASK_INIT 0x6400
  40. #define MII_M1011_IMASK_CLEAR 0x0000
  41. #define MII_M1011_PHY_SCR 0x10
  42. #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
  43. #define MII_M1145_PHY_EXT_CR 0x14
  44. #define MII_M1145_RGMII_RX_DELAY 0x0080
  45. #define MII_M1145_RGMII_TX_DELAY 0x0002
  46. #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
  47. #define MII_M1111_PHY_LED_CONTROL 0x18
  48. #define MII_M1111_PHY_LED_DIRECT 0x4100
  49. #define MII_M1111_PHY_LED_COMBINE 0x411c
  50. #define MII_M1111_PHY_EXT_CR 0x14
  51. #define MII_M1111_RX_DELAY 0x80
  52. #define MII_M1111_TX_DELAY 0x2
  53. #define MII_M1111_PHY_EXT_SR 0x1b
  54. #define MII_M1111_HWCFG_MODE_MASK 0xf
  55. #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
  56. #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
  57. #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
  58. #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
  59. #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
  60. #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
  61. #define MII_M1111_COPPER 0
  62. #define MII_M1111_FIBER 1
  63. #define MII_88E1121_PHY_LED_CTRL 16
  64. #define MII_88E1121_PHY_LED_PAGE 3
  65. #define MII_88E1121_PHY_LED_DEF 0x0030
  66. #define MII_88E1121_PHY_PAGE 22
  67. #define MII_M1011_PHY_STATUS 0x11
  68. #define MII_M1011_PHY_STATUS_1000 0x8000
  69. #define MII_M1011_PHY_STATUS_100 0x4000
  70. #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
  71. #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
  72. #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
  73. #define MII_M1011_PHY_STATUS_LINK 0x0400
  74. MODULE_DESCRIPTION("Marvell PHY driver");
  75. MODULE_AUTHOR("Andy Fleming");
  76. MODULE_LICENSE("GPL");
  77. static int marvell_ack_interrupt(struct phy_device *phydev)
  78. {
  79. int err;
  80. /* Clear the interrupts by reading the reg */
  81. err = phy_read(phydev, MII_M1011_IEVENT);
  82. if (err < 0)
  83. return err;
  84. return 0;
  85. }
  86. static int marvell_config_intr(struct phy_device *phydev)
  87. {
  88. int err;
  89. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  90. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  91. else
  92. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
  93. return err;
  94. }
  95. static int marvell_config_aneg(struct phy_device *phydev)
  96. {
  97. int err;
  98. /* The Marvell PHY has an errata which requires
  99. * that certain registers get written in order
  100. * to restart autonegotiation */
  101. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  102. if (err < 0)
  103. return err;
  104. err = phy_write(phydev, 0x1d, 0x1f);
  105. if (err < 0)
  106. return err;
  107. err = phy_write(phydev, 0x1e, 0x200c);
  108. if (err < 0)
  109. return err;
  110. err = phy_write(phydev, 0x1d, 0x5);
  111. if (err < 0)
  112. return err;
  113. err = phy_write(phydev, 0x1e, 0);
  114. if (err < 0)
  115. return err;
  116. err = phy_write(phydev, 0x1e, 0x100);
  117. if (err < 0)
  118. return err;
  119. err = phy_write(phydev, MII_M1011_PHY_SCR,
  120. MII_M1011_PHY_SCR_AUTO_CROSS);
  121. if (err < 0)
  122. return err;
  123. err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
  124. MII_M1111_PHY_LED_DIRECT);
  125. if (err < 0)
  126. return err;
  127. err = genphy_config_aneg(phydev);
  128. if (err < 0)
  129. return err;
  130. if (phydev->autoneg != AUTONEG_ENABLE) {
  131. int bmcr;
  132. /*
  133. * A write to speed/duplex bits (that is performed by
  134. * genphy_config_aneg() call above) must be followed by
  135. * a software reset. Otherwise, the write has no effect.
  136. */
  137. bmcr = phy_read(phydev, MII_BMCR);
  138. if (bmcr < 0)
  139. return bmcr;
  140. err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
  141. if (err < 0)
  142. return err;
  143. }
  144. return 0;
  145. }
  146. static int m88e1121_config_aneg(struct phy_device *phydev)
  147. {
  148. int err, temp;
  149. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  150. if (err < 0)
  151. return err;
  152. err = phy_write(phydev, MII_M1011_PHY_SCR,
  153. MII_M1011_PHY_SCR_AUTO_CROSS);
  154. if (err < 0)
  155. return err;
  156. temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
  157. phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
  158. phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
  159. phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
  160. err = genphy_config_aneg(phydev);
  161. return err;
  162. }
  163. static int m88e1111_config_init(struct phy_device *phydev)
  164. {
  165. int err;
  166. int temp;
  167. /* Enable Fiber/Copper auto selection */
  168. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  169. temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  170. phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  171. temp = phy_read(phydev, MII_BMCR);
  172. temp |= BMCR_RESET;
  173. phy_write(phydev, MII_BMCR, temp);
  174. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  175. (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  176. (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
  177. (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  178. temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
  179. if (temp < 0)
  180. return temp;
  181. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  182. temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
  183. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  184. temp &= ~MII_M1111_TX_DELAY;
  185. temp |= MII_M1111_RX_DELAY;
  186. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  187. temp &= ~MII_M1111_RX_DELAY;
  188. temp |= MII_M1111_TX_DELAY;
  189. }
  190. err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
  191. if (err < 0)
  192. return err;
  193. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  194. if (temp < 0)
  195. return temp;
  196. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  197. if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
  198. temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
  199. else
  200. temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
  201. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  202. if (err < 0)
  203. return err;
  204. }
  205. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  206. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  207. if (temp < 0)
  208. return temp;
  209. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  210. temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
  211. temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  212. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  213. if (err < 0)
  214. return err;
  215. }
  216. if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
  217. temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
  218. if (temp < 0)
  219. return temp;
  220. temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
  221. err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
  222. if (err < 0)
  223. return err;
  224. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  225. if (temp < 0)
  226. return temp;
  227. temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
  228. temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  229. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  230. if (err < 0)
  231. return err;
  232. /* soft reset */
  233. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  234. if (err < 0)
  235. return err;
  236. do
  237. temp = phy_read(phydev, MII_BMCR);
  238. while (temp & BMCR_RESET);
  239. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  240. if (temp < 0)
  241. return temp;
  242. temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
  243. temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  244. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  245. if (err < 0)
  246. return err;
  247. }
  248. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  249. if (err < 0)
  250. return err;
  251. return 0;
  252. }
  253. static int m88e1118_config_aneg(struct phy_device *phydev)
  254. {
  255. int err;
  256. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  257. if (err < 0)
  258. return err;
  259. err = phy_write(phydev, MII_M1011_PHY_SCR,
  260. MII_M1011_PHY_SCR_AUTO_CROSS);
  261. if (err < 0)
  262. return err;
  263. err = genphy_config_aneg(phydev);
  264. return 0;
  265. }
  266. static int m88e1118_config_init(struct phy_device *phydev)
  267. {
  268. int err;
  269. /* Change address */
  270. err = phy_write(phydev, 0x16, 0x0002);
  271. if (err < 0)
  272. return err;
  273. /* Enable 1000 Mbit */
  274. err = phy_write(phydev, 0x15, 0x1070);
  275. if (err < 0)
  276. return err;
  277. /* Change address */
  278. err = phy_write(phydev, 0x16, 0x0003);
  279. if (err < 0)
  280. return err;
  281. /* Adjust LED Control */
  282. err = phy_write(phydev, 0x10, 0x021e);
  283. if (err < 0)
  284. return err;
  285. /* Reset address */
  286. err = phy_write(phydev, 0x16, 0x0);
  287. if (err < 0)
  288. return err;
  289. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  290. if (err < 0)
  291. return err;
  292. return 0;
  293. }
  294. static int m88e1145_config_init(struct phy_device *phydev)
  295. {
  296. int err;
  297. /* Take care of errata E0 & E1 */
  298. err = phy_write(phydev, 0x1d, 0x001b);
  299. if (err < 0)
  300. return err;
  301. err = phy_write(phydev, 0x1e, 0x418f);
  302. if (err < 0)
  303. return err;
  304. err = phy_write(phydev, 0x1d, 0x0016);
  305. if (err < 0)
  306. return err;
  307. err = phy_write(phydev, 0x1e, 0xa2da);
  308. if (err < 0)
  309. return err;
  310. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  311. int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
  312. if (temp < 0)
  313. return temp;
  314. temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
  315. err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
  316. if (err < 0)
  317. return err;
  318. if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
  319. err = phy_write(phydev, 0x1d, 0x0012);
  320. if (err < 0)
  321. return err;
  322. temp = phy_read(phydev, 0x1e);
  323. if (temp < 0)
  324. return temp;
  325. temp &= 0xf03f;
  326. temp |= 2 << 9; /* 36 ohm */
  327. temp |= 2 << 6; /* 39 ohm */
  328. err = phy_write(phydev, 0x1e, temp);
  329. if (err < 0)
  330. return err;
  331. err = phy_write(phydev, 0x1d, 0x3);
  332. if (err < 0)
  333. return err;
  334. err = phy_write(phydev, 0x1e, 0x8000);
  335. if (err < 0)
  336. return err;
  337. }
  338. }
  339. return 0;
  340. }
  341. /* marvell_read_status
  342. *
  343. * Generic status code does not detect Fiber correctly!
  344. * Description:
  345. * Check the link, then figure out the current state
  346. * by comparing what we advertise with what the link partner
  347. * advertises. Start by checking the gigabit possibilities,
  348. * then move on to 10/100.
  349. */
  350. static int marvell_read_status(struct phy_device *phydev)
  351. {
  352. int adv;
  353. int err;
  354. int lpa;
  355. int status = 0;
  356. /* Update the link, but return if there
  357. * was an error */
  358. err = genphy_update_link(phydev);
  359. if (err)
  360. return err;
  361. if (AUTONEG_ENABLE == phydev->autoneg) {
  362. status = phy_read(phydev, MII_M1011_PHY_STATUS);
  363. if (status < 0)
  364. return status;
  365. lpa = phy_read(phydev, MII_LPA);
  366. if (lpa < 0)
  367. return lpa;
  368. adv = phy_read(phydev, MII_ADVERTISE);
  369. if (adv < 0)
  370. return adv;
  371. lpa &= adv;
  372. if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
  373. phydev->duplex = DUPLEX_FULL;
  374. else
  375. phydev->duplex = DUPLEX_HALF;
  376. status = status & MII_M1011_PHY_STATUS_SPD_MASK;
  377. phydev->pause = phydev->asym_pause = 0;
  378. switch (status) {
  379. case MII_M1011_PHY_STATUS_1000:
  380. phydev->speed = SPEED_1000;
  381. break;
  382. case MII_M1011_PHY_STATUS_100:
  383. phydev->speed = SPEED_100;
  384. break;
  385. default:
  386. phydev->speed = SPEED_10;
  387. break;
  388. }
  389. if (phydev->duplex == DUPLEX_FULL) {
  390. phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
  391. phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
  392. }
  393. } else {
  394. int bmcr = phy_read(phydev, MII_BMCR);
  395. if (bmcr < 0)
  396. return bmcr;
  397. if (bmcr & BMCR_FULLDPLX)
  398. phydev->duplex = DUPLEX_FULL;
  399. else
  400. phydev->duplex = DUPLEX_HALF;
  401. if (bmcr & BMCR_SPEED1000)
  402. phydev->speed = SPEED_1000;
  403. else if (bmcr & BMCR_SPEED100)
  404. phydev->speed = SPEED_100;
  405. else
  406. phydev->speed = SPEED_10;
  407. phydev->pause = phydev->asym_pause = 0;
  408. }
  409. return 0;
  410. }
  411. static int m88e1121_did_interrupt(struct phy_device *phydev)
  412. {
  413. int imask;
  414. imask = phy_read(phydev, MII_M1011_IEVENT);
  415. if (imask & MII_M1011_IMASK_INIT)
  416. return 1;
  417. return 0;
  418. }
  419. static struct phy_driver marvell_drivers[] = {
  420. {
  421. .phy_id = 0x01410c60,
  422. .phy_id_mask = 0xfffffff0,
  423. .name = "Marvell 88E1101",
  424. .features = PHY_GBIT_FEATURES,
  425. .flags = PHY_HAS_INTERRUPT,
  426. .config_aneg = &marvell_config_aneg,
  427. .read_status = &genphy_read_status,
  428. .ack_interrupt = &marvell_ack_interrupt,
  429. .config_intr = &marvell_config_intr,
  430. .driver = { .owner = THIS_MODULE },
  431. },
  432. {
  433. .phy_id = 0x01410c90,
  434. .phy_id_mask = 0xfffffff0,
  435. .name = "Marvell 88E1112",
  436. .features = PHY_GBIT_FEATURES,
  437. .flags = PHY_HAS_INTERRUPT,
  438. .config_init = &m88e1111_config_init,
  439. .config_aneg = &marvell_config_aneg,
  440. .read_status = &genphy_read_status,
  441. .ack_interrupt = &marvell_ack_interrupt,
  442. .config_intr = &marvell_config_intr,
  443. .driver = { .owner = THIS_MODULE },
  444. },
  445. {
  446. .phy_id = 0x01410cc0,
  447. .phy_id_mask = 0xfffffff0,
  448. .name = "Marvell 88E1111",
  449. .features = PHY_GBIT_FEATURES,
  450. .flags = PHY_HAS_INTERRUPT,
  451. .config_init = &m88e1111_config_init,
  452. .config_aneg = &marvell_config_aneg,
  453. .read_status = &marvell_read_status,
  454. .ack_interrupt = &marvell_ack_interrupt,
  455. .config_intr = &marvell_config_intr,
  456. .driver = { .owner = THIS_MODULE },
  457. },
  458. {
  459. .phy_id = 0x01410e10,
  460. .phy_id_mask = 0xfffffff0,
  461. .name = "Marvell 88E1118",
  462. .features = PHY_GBIT_FEATURES,
  463. .flags = PHY_HAS_INTERRUPT,
  464. .config_init = &m88e1118_config_init,
  465. .config_aneg = &m88e1118_config_aneg,
  466. .read_status = &genphy_read_status,
  467. .ack_interrupt = &marvell_ack_interrupt,
  468. .config_intr = &marvell_config_intr,
  469. .driver = {.owner = THIS_MODULE,},
  470. },
  471. {
  472. .phy_id = 0x01410cb0,
  473. .phy_id_mask = 0xfffffff0,
  474. .name = "Marvell 88E1121R",
  475. .features = PHY_GBIT_FEATURES,
  476. .flags = PHY_HAS_INTERRUPT,
  477. .config_aneg = &m88e1121_config_aneg,
  478. .read_status = &marvell_read_status,
  479. .ack_interrupt = &marvell_ack_interrupt,
  480. .config_intr = &marvell_config_intr,
  481. .did_interrupt = &m88e1121_did_interrupt,
  482. .driver = { .owner = THIS_MODULE },
  483. },
  484. {
  485. .phy_id = 0x01410cd0,
  486. .phy_id_mask = 0xfffffff0,
  487. .name = "Marvell 88E1145",
  488. .features = PHY_GBIT_FEATURES,
  489. .flags = PHY_HAS_INTERRUPT,
  490. .config_init = &m88e1145_config_init,
  491. .config_aneg = &marvell_config_aneg,
  492. .read_status = &genphy_read_status,
  493. .ack_interrupt = &marvell_ack_interrupt,
  494. .config_intr = &marvell_config_intr,
  495. .driver = { .owner = THIS_MODULE },
  496. },
  497. {
  498. .phy_id = 0x01410e30,
  499. .phy_id_mask = 0xfffffff0,
  500. .name = "Marvell 88E1240",
  501. .features = PHY_GBIT_FEATURES,
  502. .flags = PHY_HAS_INTERRUPT,
  503. .config_init = &m88e1111_config_init,
  504. .config_aneg = &marvell_config_aneg,
  505. .read_status = &genphy_read_status,
  506. .ack_interrupt = &marvell_ack_interrupt,
  507. .config_intr = &marvell_config_intr,
  508. .driver = { .owner = THIS_MODULE },
  509. },
  510. };
  511. static int __init marvell_init(void)
  512. {
  513. int ret;
  514. int i;
  515. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
  516. ret = phy_driver_register(&marvell_drivers[i]);
  517. if (ret) {
  518. while (i-- > 0)
  519. phy_driver_unregister(&marvell_drivers[i]);
  520. return ret;
  521. }
  522. }
  523. return 0;
  524. }
  525. static void __exit marvell_exit(void)
  526. {
  527. int i;
  528. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
  529. phy_driver_unregister(&marvell_drivers[i]);
  530. }
  531. module_init(marvell_init);
  532. module_exit(marvell_exit);