be_main.c 64 KB

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  1. /*
  2. * Copyright (C) 2005 - 2010 ServerEngines
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@serverengines.com
  12. *
  13. * ServerEngines
  14. * 209 N. Fair Oaks Ave
  15. * Sunnyvale, CA 94085
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. #include <asm/div64.h>
  20. MODULE_VERSION(DRV_VER);
  21. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  22. MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
  23. MODULE_AUTHOR("ServerEngines Corporation");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int rx_frag_size = 2048;
  26. module_param(rx_frag_size, uint, S_IRUGO);
  27. MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
  28. static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
  29. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  30. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  31. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  32. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  33. { 0 }
  34. };
  35. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  36. static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
  37. {
  38. struct be_dma_mem *mem = &q->dma_mem;
  39. if (mem->va)
  40. pci_free_consistent(adapter->pdev, mem->size,
  41. mem->va, mem->dma);
  42. }
  43. static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
  44. u16 len, u16 entry_size)
  45. {
  46. struct be_dma_mem *mem = &q->dma_mem;
  47. memset(q, 0, sizeof(*q));
  48. q->len = len;
  49. q->entry_size = entry_size;
  50. mem->size = len * entry_size;
  51. mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
  52. if (!mem->va)
  53. return -1;
  54. memset(mem->va, 0, mem->size);
  55. return 0;
  56. }
  57. static void be_intr_set(struct be_adapter *adapter, bool enable)
  58. {
  59. u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  60. u32 reg = ioread32(addr);
  61. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  62. if (adapter->eeh_err)
  63. return;
  64. if (!enabled && enable)
  65. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  66. else if (enabled && !enable)
  67. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  68. else
  69. return;
  70. iowrite32(reg, addr);
  71. }
  72. static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  73. {
  74. u32 val = 0;
  75. val |= qid & DB_RQ_RING_ID_MASK;
  76. val |= posted << DB_RQ_NUM_POSTED_SHIFT;
  77. iowrite32(val, adapter->db + DB_RQ_OFFSET);
  78. }
  79. static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  80. {
  81. u32 val = 0;
  82. val |= qid & DB_TXULP_RING_ID_MASK;
  83. val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
  84. iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
  85. }
  86. static void be_eq_notify(struct be_adapter *adapter, u16 qid,
  87. bool arm, bool clear_int, u16 num_popped)
  88. {
  89. u32 val = 0;
  90. val |= qid & DB_EQ_RING_ID_MASK;
  91. if (adapter->eeh_err)
  92. return;
  93. if (arm)
  94. val |= 1 << DB_EQ_REARM_SHIFT;
  95. if (clear_int)
  96. val |= 1 << DB_EQ_CLR_SHIFT;
  97. val |= 1 << DB_EQ_EVNT_SHIFT;
  98. val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
  99. iowrite32(val, adapter->db + DB_EQ_OFFSET);
  100. }
  101. void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
  102. {
  103. u32 val = 0;
  104. val |= qid & DB_CQ_RING_ID_MASK;
  105. if (adapter->eeh_err)
  106. return;
  107. if (arm)
  108. val |= 1 << DB_CQ_REARM_SHIFT;
  109. val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
  110. iowrite32(val, adapter->db + DB_CQ_OFFSET);
  111. }
  112. static int be_mac_addr_set(struct net_device *netdev, void *p)
  113. {
  114. struct be_adapter *adapter = netdev_priv(netdev);
  115. struct sockaddr *addr = p;
  116. int status = 0;
  117. if (!is_valid_ether_addr(addr->sa_data))
  118. return -EADDRNOTAVAIL;
  119. status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
  120. if (status)
  121. return status;
  122. status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
  123. adapter->if_handle, &adapter->pmac_id);
  124. if (!status)
  125. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  126. return status;
  127. }
  128. void netdev_stats_update(struct be_adapter *adapter)
  129. {
  130. struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
  131. struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
  132. struct be_port_rxf_stats *port_stats =
  133. &rxf_stats->port[adapter->port_num];
  134. struct net_device_stats *dev_stats = &adapter->netdev->stats;
  135. struct be_erx_stats *erx_stats = &hw_stats->erx;
  136. dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
  137. dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
  138. dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
  139. dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
  140. /* bad pkts received */
  141. dev_stats->rx_errors = port_stats->rx_crc_errors +
  142. port_stats->rx_alignment_symbol_errors +
  143. port_stats->rx_in_range_errors +
  144. port_stats->rx_out_range_errors +
  145. port_stats->rx_frame_too_long +
  146. port_stats->rx_dropped_too_small +
  147. port_stats->rx_dropped_too_short +
  148. port_stats->rx_dropped_header_too_small +
  149. port_stats->rx_dropped_tcp_length +
  150. port_stats->rx_dropped_runt +
  151. port_stats->rx_tcp_checksum_errs +
  152. port_stats->rx_ip_checksum_errs +
  153. port_stats->rx_udp_checksum_errs;
  154. /* no space in linux buffers: best possible approximation */
  155. dev_stats->rx_dropped =
  156. erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
  157. /* detailed rx errors */
  158. dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
  159. port_stats->rx_out_range_errors +
  160. port_stats->rx_frame_too_long;
  161. /* receive ring buffer overflow */
  162. dev_stats->rx_over_errors = 0;
  163. dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
  164. /* frame alignment errors */
  165. dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
  166. /* receiver fifo overrun */
  167. /* drops_no_pbuf is no per i/f, it's per BE card */
  168. dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
  169. port_stats->rx_input_fifo_overflow +
  170. rxf_stats->rx_drops_no_pbuf;
  171. /* receiver missed packetd */
  172. dev_stats->rx_missed_errors = 0;
  173. /* packet transmit problems */
  174. dev_stats->tx_errors = 0;
  175. /* no space available in linux */
  176. dev_stats->tx_dropped = 0;
  177. dev_stats->multicast = port_stats->rx_multicast_frames;
  178. dev_stats->collisions = 0;
  179. /* detailed tx_errors */
  180. dev_stats->tx_aborted_errors = 0;
  181. dev_stats->tx_carrier_errors = 0;
  182. dev_stats->tx_fifo_errors = 0;
  183. dev_stats->tx_heartbeat_errors = 0;
  184. dev_stats->tx_window_errors = 0;
  185. }
  186. void be_link_status_update(struct be_adapter *adapter, bool link_up)
  187. {
  188. struct net_device *netdev = adapter->netdev;
  189. /* If link came up or went down */
  190. if (adapter->link_up != link_up) {
  191. adapter->link_speed = -1;
  192. if (link_up) {
  193. netif_start_queue(netdev);
  194. netif_carrier_on(netdev);
  195. printk(KERN_INFO "%s: Link up\n", netdev->name);
  196. } else {
  197. netif_stop_queue(netdev);
  198. netif_carrier_off(netdev);
  199. printk(KERN_INFO "%s: Link down\n", netdev->name);
  200. }
  201. adapter->link_up = link_up;
  202. }
  203. }
  204. /* Update the EQ delay n BE based on the RX frags consumed / sec */
  205. static void be_rx_eqd_update(struct be_adapter *adapter)
  206. {
  207. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  208. struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
  209. ulong now = jiffies;
  210. u32 eqd;
  211. if (!rx_eq->enable_aic)
  212. return;
  213. /* Wrapped around */
  214. if (time_before(now, stats->rx_fps_jiffies)) {
  215. stats->rx_fps_jiffies = now;
  216. return;
  217. }
  218. /* Update once a second */
  219. if ((now - stats->rx_fps_jiffies) < HZ)
  220. return;
  221. stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
  222. ((now - stats->rx_fps_jiffies) / HZ);
  223. stats->rx_fps_jiffies = now;
  224. stats->be_prev_rx_frags = stats->be_rx_frags;
  225. eqd = stats->be_rx_fps / 110000;
  226. eqd = eqd << 3;
  227. if (eqd > rx_eq->max_eqd)
  228. eqd = rx_eq->max_eqd;
  229. if (eqd < rx_eq->min_eqd)
  230. eqd = rx_eq->min_eqd;
  231. if (eqd < 10)
  232. eqd = 0;
  233. if (eqd != rx_eq->cur_eqd)
  234. be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
  235. rx_eq->cur_eqd = eqd;
  236. }
  237. static struct net_device_stats *be_get_stats(struct net_device *dev)
  238. {
  239. return &dev->stats;
  240. }
  241. static u32 be_calc_rate(u64 bytes, unsigned long ticks)
  242. {
  243. u64 rate = bytes;
  244. do_div(rate, ticks / HZ);
  245. rate <<= 3; /* bytes/sec -> bits/sec */
  246. do_div(rate, 1000000ul); /* MB/Sec */
  247. return rate;
  248. }
  249. static void be_tx_rate_update(struct be_adapter *adapter)
  250. {
  251. struct be_drvr_stats *stats = drvr_stats(adapter);
  252. ulong now = jiffies;
  253. /* Wrapped around? */
  254. if (time_before(now, stats->be_tx_jiffies)) {
  255. stats->be_tx_jiffies = now;
  256. return;
  257. }
  258. /* Update tx rate once in two seconds */
  259. if ((now - stats->be_tx_jiffies) > 2 * HZ) {
  260. stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
  261. - stats->be_tx_bytes_prev,
  262. now - stats->be_tx_jiffies);
  263. stats->be_tx_jiffies = now;
  264. stats->be_tx_bytes_prev = stats->be_tx_bytes;
  265. }
  266. }
  267. static void be_tx_stats_update(struct be_adapter *adapter,
  268. u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
  269. {
  270. struct be_drvr_stats *stats = drvr_stats(adapter);
  271. stats->be_tx_reqs++;
  272. stats->be_tx_wrbs += wrb_cnt;
  273. stats->be_tx_bytes += copied;
  274. stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
  275. if (stopped)
  276. stats->be_tx_stops++;
  277. }
  278. /* Determine number of WRB entries needed to xmit data in an skb */
  279. static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
  280. {
  281. int cnt = (skb->len > skb->data_len);
  282. cnt += skb_shinfo(skb)->nr_frags;
  283. /* to account for hdr wrb */
  284. cnt++;
  285. if (cnt & 1) {
  286. /* add a dummy to make it an even num */
  287. cnt++;
  288. *dummy = true;
  289. } else
  290. *dummy = false;
  291. BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
  292. return cnt;
  293. }
  294. static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
  295. {
  296. wrb->frag_pa_hi = upper_32_bits(addr);
  297. wrb->frag_pa_lo = addr & 0xFFFFFFFF;
  298. wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
  299. }
  300. static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
  301. bool vlan, u32 wrb_cnt, u32 len)
  302. {
  303. memset(hdr, 0, sizeof(*hdr));
  304. AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
  305. if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
  306. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
  307. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
  308. hdr, skb_shinfo(skb)->gso_size);
  309. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  310. if (is_tcp_pkt(skb))
  311. AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
  312. else if (is_udp_pkt(skb))
  313. AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
  314. }
  315. if (vlan && vlan_tx_tag_present(skb)) {
  316. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
  317. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
  318. hdr, vlan_tx_tag_get(skb));
  319. }
  320. AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
  321. AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
  322. AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
  323. AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
  324. }
  325. static int make_tx_wrbs(struct be_adapter *adapter,
  326. struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
  327. {
  328. u64 busaddr;
  329. u32 i, copied = 0;
  330. struct pci_dev *pdev = adapter->pdev;
  331. struct sk_buff *first_skb = skb;
  332. struct be_queue_info *txq = &adapter->tx_obj.q;
  333. struct be_eth_wrb *wrb;
  334. struct be_eth_hdr_wrb *hdr;
  335. hdr = queue_head_node(txq);
  336. atomic_add(wrb_cnt, &txq->used);
  337. queue_head_inc(txq);
  338. if (skb->len > skb->data_len) {
  339. int len = skb->len - skb->data_len;
  340. busaddr = pci_map_single(pdev, skb->data, len,
  341. PCI_DMA_TODEVICE);
  342. wrb = queue_head_node(txq);
  343. wrb_fill(wrb, busaddr, len);
  344. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  345. queue_head_inc(txq);
  346. copied += len;
  347. }
  348. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  349. struct skb_frag_struct *frag =
  350. &skb_shinfo(skb)->frags[i];
  351. busaddr = pci_map_page(pdev, frag->page,
  352. frag->page_offset,
  353. frag->size, PCI_DMA_TODEVICE);
  354. wrb = queue_head_node(txq);
  355. wrb_fill(wrb, busaddr, frag->size);
  356. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  357. queue_head_inc(txq);
  358. copied += frag->size;
  359. }
  360. if (dummy_wrb) {
  361. wrb = queue_head_node(txq);
  362. wrb_fill(wrb, 0, 0);
  363. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  364. queue_head_inc(txq);
  365. }
  366. wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
  367. wrb_cnt, copied);
  368. be_dws_cpu_to_le(hdr, sizeof(*hdr));
  369. return copied;
  370. }
  371. static netdev_tx_t be_xmit(struct sk_buff *skb,
  372. struct net_device *netdev)
  373. {
  374. struct be_adapter *adapter = netdev_priv(netdev);
  375. struct be_tx_obj *tx_obj = &adapter->tx_obj;
  376. struct be_queue_info *txq = &tx_obj->q;
  377. u32 wrb_cnt = 0, copied = 0;
  378. u32 start = txq->head;
  379. bool dummy_wrb, stopped = false;
  380. wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
  381. copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
  382. if (copied) {
  383. /* record the sent skb in the sent_skb table */
  384. BUG_ON(tx_obj->sent_skb_list[start]);
  385. tx_obj->sent_skb_list[start] = skb;
  386. /* Ensure txq has space for the next skb; Else stop the queue
  387. * *BEFORE* ringing the tx doorbell, so that we serialze the
  388. * tx compls of the current transmit which'll wake up the queue
  389. */
  390. if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
  391. txq->len) {
  392. netif_stop_queue(netdev);
  393. stopped = true;
  394. }
  395. be_txq_notify(adapter, txq->id, wrb_cnt);
  396. be_tx_stats_update(adapter, wrb_cnt, copied,
  397. skb_shinfo(skb)->gso_segs, stopped);
  398. } else {
  399. txq->head = start;
  400. dev_kfree_skb_any(skb);
  401. }
  402. return NETDEV_TX_OK;
  403. }
  404. static int be_change_mtu(struct net_device *netdev, int new_mtu)
  405. {
  406. struct be_adapter *adapter = netdev_priv(netdev);
  407. if (new_mtu < BE_MIN_MTU ||
  408. new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
  409. (ETH_HLEN + ETH_FCS_LEN))) {
  410. dev_info(&adapter->pdev->dev,
  411. "MTU must be between %d and %d bytes\n",
  412. BE_MIN_MTU,
  413. (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
  414. return -EINVAL;
  415. }
  416. dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
  417. netdev->mtu, new_mtu);
  418. netdev->mtu = new_mtu;
  419. return 0;
  420. }
  421. /*
  422. * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
  423. * If the user configures more, place BE in vlan promiscuous mode.
  424. */
  425. static int be_vid_config(struct be_adapter *adapter)
  426. {
  427. u16 vtag[BE_NUM_VLANS_SUPPORTED];
  428. u16 ntags = 0, i;
  429. int status = 0;
  430. if (adapter->vlans_added <= adapter->max_vlans) {
  431. /* Construct VLAN Table to give to HW */
  432. for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
  433. if (adapter->vlan_tag[i]) {
  434. vtag[ntags] = cpu_to_le16(i);
  435. ntags++;
  436. }
  437. }
  438. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  439. vtag, ntags, 1, 0);
  440. } else {
  441. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  442. NULL, 0, 1, 1);
  443. }
  444. return status;
  445. }
  446. static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
  447. {
  448. struct be_adapter *adapter = netdev_priv(netdev);
  449. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  450. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  451. be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
  452. be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
  453. adapter->vlan_grp = grp;
  454. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  455. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  456. }
  457. static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
  458. {
  459. struct be_adapter *adapter = netdev_priv(netdev);
  460. adapter->vlan_tag[vid] = 1;
  461. adapter->vlans_added++;
  462. if (adapter->vlans_added <= (adapter->max_vlans + 1))
  463. be_vid_config(adapter);
  464. }
  465. static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
  466. {
  467. struct be_adapter *adapter = netdev_priv(netdev);
  468. adapter->vlan_tag[vid] = 0;
  469. vlan_group_set_device(adapter->vlan_grp, vid, NULL);
  470. adapter->vlans_added--;
  471. if (adapter->vlans_added <= adapter->max_vlans)
  472. be_vid_config(adapter);
  473. }
  474. static void be_set_multicast_list(struct net_device *netdev)
  475. {
  476. struct be_adapter *adapter = netdev_priv(netdev);
  477. if (netdev->flags & IFF_PROMISC) {
  478. be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
  479. adapter->promiscuous = true;
  480. goto done;
  481. }
  482. /* BE was previously in promiscous mode; disable it */
  483. if (adapter->promiscuous) {
  484. adapter->promiscuous = false;
  485. be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
  486. }
  487. /* Enable multicast promisc if num configured exceeds what we support */
  488. if (netdev->flags & IFF_ALLMULTI ||
  489. netdev_mc_count(netdev) > BE_MAX_MC) {
  490. be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
  491. &adapter->mc_cmd_mem);
  492. goto done;
  493. }
  494. be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
  495. &adapter->mc_cmd_mem);
  496. done:
  497. return;
  498. }
  499. static void be_rx_rate_update(struct be_adapter *adapter)
  500. {
  501. struct be_drvr_stats *stats = drvr_stats(adapter);
  502. ulong now = jiffies;
  503. /* Wrapped around */
  504. if (time_before(now, stats->be_rx_jiffies)) {
  505. stats->be_rx_jiffies = now;
  506. return;
  507. }
  508. /* Update the rate once in two seconds */
  509. if ((now - stats->be_rx_jiffies) < 2 * HZ)
  510. return;
  511. stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
  512. - stats->be_rx_bytes_prev,
  513. now - stats->be_rx_jiffies);
  514. stats->be_rx_jiffies = now;
  515. stats->be_rx_bytes_prev = stats->be_rx_bytes;
  516. }
  517. static void be_rx_stats_update(struct be_adapter *adapter,
  518. u32 pktsize, u16 numfrags)
  519. {
  520. struct be_drvr_stats *stats = drvr_stats(adapter);
  521. stats->be_rx_compl++;
  522. stats->be_rx_frags += numfrags;
  523. stats->be_rx_bytes += pktsize;
  524. stats->be_rx_pkts++;
  525. }
  526. static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
  527. {
  528. u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
  529. l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
  530. ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
  531. ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
  532. if (ip_version) {
  533. tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  534. udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
  535. }
  536. ipv6_chk = (ip_version && (tcpf || udpf));
  537. return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
  538. }
  539. static struct be_rx_page_info *
  540. get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
  541. {
  542. struct be_rx_page_info *rx_page_info;
  543. struct be_queue_info *rxq = &adapter->rx_obj.q;
  544. rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
  545. BUG_ON(!rx_page_info->page);
  546. if (rx_page_info->last_page_user) {
  547. pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
  548. adapter->big_page_size, PCI_DMA_FROMDEVICE);
  549. rx_page_info->last_page_user = false;
  550. }
  551. atomic_dec(&rxq->used);
  552. return rx_page_info;
  553. }
  554. /* Throwaway the data in the Rx completion */
  555. static void be_rx_compl_discard(struct be_adapter *adapter,
  556. struct be_eth_rx_compl *rxcp)
  557. {
  558. struct be_queue_info *rxq = &adapter->rx_obj.q;
  559. struct be_rx_page_info *page_info;
  560. u16 rxq_idx, i, num_rcvd;
  561. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  562. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  563. for (i = 0; i < num_rcvd; i++) {
  564. page_info = get_rx_page_info(adapter, rxq_idx);
  565. put_page(page_info->page);
  566. memset(page_info, 0, sizeof(*page_info));
  567. index_inc(&rxq_idx, rxq->len);
  568. }
  569. }
  570. /*
  571. * skb_fill_rx_data forms a complete skb for an ether frame
  572. * indicated by rxcp.
  573. */
  574. static void skb_fill_rx_data(struct be_adapter *adapter,
  575. struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
  576. u16 num_rcvd)
  577. {
  578. struct be_queue_info *rxq = &adapter->rx_obj.q;
  579. struct be_rx_page_info *page_info;
  580. u16 rxq_idx, i, j;
  581. u32 pktsize, hdr_len, curr_frag_len, size;
  582. u8 *start;
  583. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  584. pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  585. page_info = get_rx_page_info(adapter, rxq_idx);
  586. start = page_address(page_info->page) + page_info->page_offset;
  587. prefetch(start);
  588. /* Copy data in the first descriptor of this completion */
  589. curr_frag_len = min(pktsize, rx_frag_size);
  590. /* Copy the header portion into skb_data */
  591. hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
  592. memcpy(skb->data, start, hdr_len);
  593. skb->len = curr_frag_len;
  594. if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
  595. /* Complete packet has now been moved to data */
  596. put_page(page_info->page);
  597. skb->data_len = 0;
  598. skb->tail += curr_frag_len;
  599. } else {
  600. skb_shinfo(skb)->nr_frags = 1;
  601. skb_shinfo(skb)->frags[0].page = page_info->page;
  602. skb_shinfo(skb)->frags[0].page_offset =
  603. page_info->page_offset + hdr_len;
  604. skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
  605. skb->data_len = curr_frag_len - hdr_len;
  606. skb->tail += hdr_len;
  607. }
  608. page_info->page = NULL;
  609. if (pktsize <= rx_frag_size) {
  610. BUG_ON(num_rcvd != 1);
  611. goto done;
  612. }
  613. /* More frags present for this completion */
  614. size = pktsize;
  615. for (i = 1, j = 0; i < num_rcvd; i++) {
  616. size -= curr_frag_len;
  617. index_inc(&rxq_idx, rxq->len);
  618. page_info = get_rx_page_info(adapter, rxq_idx);
  619. curr_frag_len = min(size, rx_frag_size);
  620. /* Coalesce all frags from the same physical page in one slot */
  621. if (page_info->page_offset == 0) {
  622. /* Fresh page */
  623. j++;
  624. skb_shinfo(skb)->frags[j].page = page_info->page;
  625. skb_shinfo(skb)->frags[j].page_offset =
  626. page_info->page_offset;
  627. skb_shinfo(skb)->frags[j].size = 0;
  628. skb_shinfo(skb)->nr_frags++;
  629. } else {
  630. put_page(page_info->page);
  631. }
  632. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  633. skb->len += curr_frag_len;
  634. skb->data_len += curr_frag_len;
  635. page_info->page = NULL;
  636. }
  637. BUG_ON(j > MAX_SKB_FRAGS);
  638. done:
  639. be_rx_stats_update(adapter, pktsize, num_rcvd);
  640. return;
  641. }
  642. /* Process the RX completion indicated by rxcp when GRO is disabled */
  643. static void be_rx_compl_process(struct be_adapter *adapter,
  644. struct be_eth_rx_compl *rxcp)
  645. {
  646. struct sk_buff *skb;
  647. u32 vlanf, vid;
  648. u16 num_rcvd;
  649. u8 vtm;
  650. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  651. /* Is it a flush compl that has no data */
  652. if (unlikely(num_rcvd == 0))
  653. return;
  654. skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
  655. if (unlikely(!skb)) {
  656. if (net_ratelimit())
  657. dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
  658. be_rx_compl_discard(adapter, rxcp);
  659. return;
  660. }
  661. skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
  662. if (do_pkt_csum(rxcp, adapter->rx_csum))
  663. skb->ip_summed = CHECKSUM_NONE;
  664. else
  665. skb->ip_summed = CHECKSUM_UNNECESSARY;
  666. skb->truesize = skb->len + sizeof(struct sk_buff);
  667. skb->protocol = eth_type_trans(skb, adapter->netdev);
  668. skb->dev = adapter->netdev;
  669. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  670. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  671. /* vlanf could be wrongly set in some cards.
  672. * ignore if vtm is not set */
  673. if ((adapter->cap & 0x400) && !vtm)
  674. vlanf = 0;
  675. if (unlikely(vlanf)) {
  676. if (!adapter->vlan_grp || adapter->vlans_added == 0) {
  677. kfree_skb(skb);
  678. return;
  679. }
  680. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  681. vid = be16_to_cpu(vid);
  682. vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
  683. } else {
  684. netif_receive_skb(skb);
  685. }
  686. return;
  687. }
  688. /* Process the RX completion indicated by rxcp when GRO is enabled */
  689. static void be_rx_compl_process_gro(struct be_adapter *adapter,
  690. struct be_eth_rx_compl *rxcp)
  691. {
  692. struct be_rx_page_info *page_info;
  693. struct sk_buff *skb = NULL;
  694. struct be_queue_info *rxq = &adapter->rx_obj.q;
  695. struct be_eq_obj *eq_obj = &adapter->rx_eq;
  696. u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
  697. u16 i, rxq_idx = 0, vid, j;
  698. u8 vtm;
  699. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  700. /* Is it a flush compl that has no data */
  701. if (unlikely(num_rcvd == 0))
  702. return;
  703. pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  704. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  705. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  706. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  707. /* vlanf could be wrongly set in some cards.
  708. * ignore if vtm is not set */
  709. if ((adapter->cap & 0x400) && !vtm)
  710. vlanf = 0;
  711. skb = napi_get_frags(&eq_obj->napi);
  712. if (!skb) {
  713. be_rx_compl_discard(adapter, rxcp);
  714. return;
  715. }
  716. remaining = pkt_size;
  717. for (i = 0, j = -1; i < num_rcvd; i++) {
  718. page_info = get_rx_page_info(adapter, rxq_idx);
  719. curr_frag_len = min(remaining, rx_frag_size);
  720. /* Coalesce all frags from the same physical page in one slot */
  721. if (i == 0 || page_info->page_offset == 0) {
  722. /* First frag or Fresh page */
  723. j++;
  724. skb_shinfo(skb)->frags[j].page = page_info->page;
  725. skb_shinfo(skb)->frags[j].page_offset =
  726. page_info->page_offset;
  727. skb_shinfo(skb)->frags[j].size = 0;
  728. } else {
  729. put_page(page_info->page);
  730. }
  731. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  732. remaining -= curr_frag_len;
  733. index_inc(&rxq_idx, rxq->len);
  734. memset(page_info, 0, sizeof(*page_info));
  735. }
  736. BUG_ON(j > MAX_SKB_FRAGS);
  737. skb_shinfo(skb)->nr_frags = j + 1;
  738. skb->len = pkt_size;
  739. skb->data_len = pkt_size;
  740. skb->truesize += pkt_size;
  741. skb->ip_summed = CHECKSUM_UNNECESSARY;
  742. if (likely(!vlanf)) {
  743. napi_gro_frags(&eq_obj->napi);
  744. } else {
  745. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  746. vid = be16_to_cpu(vid);
  747. if (!adapter->vlan_grp || adapter->vlans_added == 0)
  748. return;
  749. vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
  750. }
  751. be_rx_stats_update(adapter, pkt_size, num_rcvd);
  752. return;
  753. }
  754. static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
  755. {
  756. struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
  757. if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
  758. return NULL;
  759. be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
  760. queue_tail_inc(&adapter->rx_obj.cq);
  761. return rxcp;
  762. }
  763. /* To reset the valid bit, we need to reset the whole word as
  764. * when walking the queue the valid entries are little-endian
  765. * and invalid entries are host endian
  766. */
  767. static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
  768. {
  769. rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
  770. }
  771. static inline struct page *be_alloc_pages(u32 size)
  772. {
  773. gfp_t alloc_flags = GFP_ATOMIC;
  774. u32 order = get_order(size);
  775. if (order > 0)
  776. alloc_flags |= __GFP_COMP;
  777. return alloc_pages(alloc_flags, order);
  778. }
  779. /*
  780. * Allocate a page, split it to fragments of size rx_frag_size and post as
  781. * receive buffers to BE
  782. */
  783. static void be_post_rx_frags(struct be_adapter *adapter)
  784. {
  785. struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
  786. struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
  787. struct be_queue_info *rxq = &adapter->rx_obj.q;
  788. struct page *pagep = NULL;
  789. struct be_eth_rx_d *rxd;
  790. u64 page_dmaaddr = 0, frag_dmaaddr;
  791. u32 posted, page_offset = 0;
  792. page_info = &page_info_tbl[rxq->head];
  793. for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
  794. if (!pagep) {
  795. pagep = be_alloc_pages(adapter->big_page_size);
  796. if (unlikely(!pagep)) {
  797. drvr_stats(adapter)->be_ethrx_post_fail++;
  798. break;
  799. }
  800. page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
  801. adapter->big_page_size,
  802. PCI_DMA_FROMDEVICE);
  803. page_info->page_offset = 0;
  804. } else {
  805. get_page(pagep);
  806. page_info->page_offset = page_offset + rx_frag_size;
  807. }
  808. page_offset = page_info->page_offset;
  809. page_info->page = pagep;
  810. pci_unmap_addr_set(page_info, bus, page_dmaaddr);
  811. frag_dmaaddr = page_dmaaddr + page_info->page_offset;
  812. rxd = queue_head_node(rxq);
  813. rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
  814. rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
  815. /* Any space left in the current big page for another frag? */
  816. if ((page_offset + rx_frag_size + rx_frag_size) >
  817. adapter->big_page_size) {
  818. pagep = NULL;
  819. page_info->last_page_user = true;
  820. }
  821. prev_page_info = page_info;
  822. queue_head_inc(rxq);
  823. page_info = &page_info_tbl[rxq->head];
  824. }
  825. if (pagep)
  826. prev_page_info->last_page_user = true;
  827. if (posted) {
  828. atomic_add(posted, &rxq->used);
  829. be_rxq_notify(adapter, rxq->id, posted);
  830. } else if (atomic_read(&rxq->used) == 0) {
  831. /* Let be_worker replenish when memory is available */
  832. adapter->rx_post_starved = true;
  833. }
  834. return;
  835. }
  836. static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
  837. {
  838. struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
  839. if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
  840. return NULL;
  841. be_dws_le_to_cpu(txcp, sizeof(*txcp));
  842. txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
  843. queue_tail_inc(tx_cq);
  844. return txcp;
  845. }
  846. static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
  847. {
  848. struct be_queue_info *txq = &adapter->tx_obj.q;
  849. struct be_eth_wrb *wrb;
  850. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  851. struct sk_buff *sent_skb;
  852. u64 busaddr;
  853. u16 cur_index, num_wrbs = 0;
  854. cur_index = txq->tail;
  855. sent_skb = sent_skbs[cur_index];
  856. BUG_ON(!sent_skb);
  857. sent_skbs[cur_index] = NULL;
  858. wrb = queue_tail_node(txq);
  859. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  860. busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
  861. if (busaddr != 0) {
  862. pci_unmap_single(adapter->pdev, busaddr,
  863. wrb->frag_len, PCI_DMA_TODEVICE);
  864. }
  865. num_wrbs++;
  866. queue_tail_inc(txq);
  867. while (cur_index != last_index) {
  868. cur_index = txq->tail;
  869. wrb = queue_tail_node(txq);
  870. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  871. busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
  872. if (busaddr != 0) {
  873. pci_unmap_page(adapter->pdev, busaddr,
  874. wrb->frag_len, PCI_DMA_TODEVICE);
  875. }
  876. num_wrbs++;
  877. queue_tail_inc(txq);
  878. }
  879. atomic_sub(num_wrbs, &txq->used);
  880. kfree_skb(sent_skb);
  881. }
  882. static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
  883. {
  884. struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
  885. if (!eqe->evt)
  886. return NULL;
  887. eqe->evt = le32_to_cpu(eqe->evt);
  888. queue_tail_inc(&eq_obj->q);
  889. return eqe;
  890. }
  891. static int event_handle(struct be_adapter *adapter,
  892. struct be_eq_obj *eq_obj)
  893. {
  894. struct be_eq_entry *eqe;
  895. u16 num = 0;
  896. while ((eqe = event_get(eq_obj)) != NULL) {
  897. eqe->evt = 0;
  898. num++;
  899. }
  900. /* Deal with any spurious interrupts that come
  901. * without events
  902. */
  903. be_eq_notify(adapter, eq_obj->q.id, true, true, num);
  904. if (num)
  905. napi_schedule(&eq_obj->napi);
  906. return num;
  907. }
  908. /* Just read and notify events without processing them.
  909. * Used at the time of destroying event queues */
  910. static void be_eq_clean(struct be_adapter *adapter,
  911. struct be_eq_obj *eq_obj)
  912. {
  913. struct be_eq_entry *eqe;
  914. u16 num = 0;
  915. while ((eqe = event_get(eq_obj)) != NULL) {
  916. eqe->evt = 0;
  917. num++;
  918. }
  919. if (num)
  920. be_eq_notify(adapter, eq_obj->q.id, false, true, num);
  921. }
  922. static void be_rx_q_clean(struct be_adapter *adapter)
  923. {
  924. struct be_rx_page_info *page_info;
  925. struct be_queue_info *rxq = &adapter->rx_obj.q;
  926. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  927. struct be_eth_rx_compl *rxcp;
  928. u16 tail;
  929. /* First cleanup pending rx completions */
  930. while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
  931. be_rx_compl_discard(adapter, rxcp);
  932. be_rx_compl_reset(rxcp);
  933. be_cq_notify(adapter, rx_cq->id, true, 1);
  934. }
  935. /* Then free posted rx buffer that were not used */
  936. tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
  937. for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
  938. page_info = get_rx_page_info(adapter, tail);
  939. put_page(page_info->page);
  940. memset(page_info, 0, sizeof(*page_info));
  941. }
  942. BUG_ON(atomic_read(&rxq->used));
  943. }
  944. static void be_tx_compl_clean(struct be_adapter *adapter)
  945. {
  946. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  947. struct be_queue_info *txq = &adapter->tx_obj.q;
  948. struct be_eth_tx_compl *txcp;
  949. u16 end_idx, cmpl = 0, timeo = 0;
  950. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  951. struct sk_buff *sent_skb;
  952. bool dummy_wrb;
  953. /* Wait for a max of 200ms for all the tx-completions to arrive. */
  954. do {
  955. while ((txcp = be_tx_compl_get(tx_cq))) {
  956. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  957. wrb_index, txcp);
  958. be_tx_compl_process(adapter, end_idx);
  959. cmpl++;
  960. }
  961. if (cmpl) {
  962. be_cq_notify(adapter, tx_cq->id, false, cmpl);
  963. cmpl = 0;
  964. }
  965. if (atomic_read(&txq->used) == 0 || ++timeo > 200)
  966. break;
  967. mdelay(1);
  968. } while (true);
  969. if (atomic_read(&txq->used))
  970. dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
  971. atomic_read(&txq->used));
  972. /* free posted tx for which compls will never arrive */
  973. while (atomic_read(&txq->used)) {
  974. sent_skb = sent_skbs[txq->tail];
  975. end_idx = txq->tail;
  976. index_adv(&end_idx,
  977. wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
  978. be_tx_compl_process(adapter, end_idx);
  979. }
  980. }
  981. static void be_mcc_queues_destroy(struct be_adapter *adapter)
  982. {
  983. struct be_queue_info *q;
  984. q = &adapter->mcc_obj.q;
  985. if (q->created)
  986. be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
  987. be_queue_free(adapter, q);
  988. q = &adapter->mcc_obj.cq;
  989. if (q->created)
  990. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  991. be_queue_free(adapter, q);
  992. }
  993. /* Must be called only after TX qs are created as MCC shares TX EQ */
  994. static int be_mcc_queues_create(struct be_adapter *adapter)
  995. {
  996. struct be_queue_info *q, *cq;
  997. /* Alloc MCC compl queue */
  998. cq = &adapter->mcc_obj.cq;
  999. if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
  1000. sizeof(struct be_mcc_compl)))
  1001. goto err;
  1002. /* Ask BE to create MCC compl queue; share TX's eq */
  1003. if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
  1004. goto mcc_cq_free;
  1005. /* Alloc MCC queue */
  1006. q = &adapter->mcc_obj.q;
  1007. if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  1008. goto mcc_cq_destroy;
  1009. /* Ask BE to create MCC queue */
  1010. if (be_cmd_mccq_create(adapter, q, cq))
  1011. goto mcc_q_free;
  1012. return 0;
  1013. mcc_q_free:
  1014. be_queue_free(adapter, q);
  1015. mcc_cq_destroy:
  1016. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1017. mcc_cq_free:
  1018. be_queue_free(adapter, cq);
  1019. err:
  1020. return -1;
  1021. }
  1022. static void be_tx_queues_destroy(struct be_adapter *adapter)
  1023. {
  1024. struct be_queue_info *q;
  1025. q = &adapter->tx_obj.q;
  1026. if (q->created)
  1027. be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
  1028. be_queue_free(adapter, q);
  1029. q = &adapter->tx_obj.cq;
  1030. if (q->created)
  1031. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1032. be_queue_free(adapter, q);
  1033. /* Clear any residual events */
  1034. be_eq_clean(adapter, &adapter->tx_eq);
  1035. q = &adapter->tx_eq.q;
  1036. if (q->created)
  1037. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1038. be_queue_free(adapter, q);
  1039. }
  1040. static int be_tx_queues_create(struct be_adapter *adapter)
  1041. {
  1042. struct be_queue_info *eq, *q, *cq;
  1043. adapter->tx_eq.max_eqd = 0;
  1044. adapter->tx_eq.min_eqd = 0;
  1045. adapter->tx_eq.cur_eqd = 96;
  1046. adapter->tx_eq.enable_aic = false;
  1047. /* Alloc Tx Event queue */
  1048. eq = &adapter->tx_eq.q;
  1049. if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
  1050. return -1;
  1051. /* Ask BE to create Tx Event queue */
  1052. if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
  1053. goto tx_eq_free;
  1054. /* Alloc TX eth compl queue */
  1055. cq = &adapter->tx_obj.cq;
  1056. if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
  1057. sizeof(struct be_eth_tx_compl)))
  1058. goto tx_eq_destroy;
  1059. /* Ask BE to create Tx eth compl queue */
  1060. if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
  1061. goto tx_cq_free;
  1062. /* Alloc TX eth queue */
  1063. q = &adapter->tx_obj.q;
  1064. if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
  1065. goto tx_cq_destroy;
  1066. /* Ask BE to create Tx eth queue */
  1067. if (be_cmd_txq_create(adapter, q, cq))
  1068. goto tx_q_free;
  1069. return 0;
  1070. tx_q_free:
  1071. be_queue_free(adapter, q);
  1072. tx_cq_destroy:
  1073. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1074. tx_cq_free:
  1075. be_queue_free(adapter, cq);
  1076. tx_eq_destroy:
  1077. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1078. tx_eq_free:
  1079. be_queue_free(adapter, eq);
  1080. return -1;
  1081. }
  1082. static void be_rx_queues_destroy(struct be_adapter *adapter)
  1083. {
  1084. struct be_queue_info *q;
  1085. q = &adapter->rx_obj.q;
  1086. if (q->created) {
  1087. be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
  1088. /* After the rxq is invalidated, wait for a grace time
  1089. * of 1ms for all dma to end and the flush compl to arrive
  1090. */
  1091. mdelay(1);
  1092. be_rx_q_clean(adapter);
  1093. }
  1094. be_queue_free(adapter, q);
  1095. q = &adapter->rx_obj.cq;
  1096. if (q->created)
  1097. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1098. be_queue_free(adapter, q);
  1099. /* Clear any residual events */
  1100. be_eq_clean(adapter, &adapter->rx_eq);
  1101. q = &adapter->rx_eq.q;
  1102. if (q->created)
  1103. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1104. be_queue_free(adapter, q);
  1105. }
  1106. static int be_rx_queues_create(struct be_adapter *adapter)
  1107. {
  1108. struct be_queue_info *eq, *q, *cq;
  1109. int rc;
  1110. adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
  1111. adapter->rx_eq.max_eqd = BE_MAX_EQD;
  1112. adapter->rx_eq.min_eqd = 0;
  1113. adapter->rx_eq.cur_eqd = 0;
  1114. adapter->rx_eq.enable_aic = true;
  1115. /* Alloc Rx Event queue */
  1116. eq = &adapter->rx_eq.q;
  1117. rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
  1118. sizeof(struct be_eq_entry));
  1119. if (rc)
  1120. return rc;
  1121. /* Ask BE to create Rx Event queue */
  1122. rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
  1123. if (rc)
  1124. goto rx_eq_free;
  1125. /* Alloc RX eth compl queue */
  1126. cq = &adapter->rx_obj.cq;
  1127. rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
  1128. sizeof(struct be_eth_rx_compl));
  1129. if (rc)
  1130. goto rx_eq_destroy;
  1131. /* Ask BE to create Rx eth compl queue */
  1132. rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
  1133. if (rc)
  1134. goto rx_cq_free;
  1135. /* Alloc RX eth queue */
  1136. q = &adapter->rx_obj.q;
  1137. rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
  1138. if (rc)
  1139. goto rx_cq_destroy;
  1140. /* Ask BE to create Rx eth queue */
  1141. rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
  1142. BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
  1143. if (rc)
  1144. goto rx_q_free;
  1145. return 0;
  1146. rx_q_free:
  1147. be_queue_free(adapter, q);
  1148. rx_cq_destroy:
  1149. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1150. rx_cq_free:
  1151. be_queue_free(adapter, cq);
  1152. rx_eq_destroy:
  1153. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1154. rx_eq_free:
  1155. be_queue_free(adapter, eq);
  1156. return rc;
  1157. }
  1158. /* There are 8 evt ids per func. Retruns the evt id's bit number */
  1159. static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
  1160. {
  1161. return eq_id - 8 * be_pci_func(adapter);
  1162. }
  1163. static irqreturn_t be_intx(int irq, void *dev)
  1164. {
  1165. struct be_adapter *adapter = dev;
  1166. int isr;
  1167. isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
  1168. (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
  1169. if (!isr)
  1170. return IRQ_NONE;
  1171. event_handle(adapter, &adapter->tx_eq);
  1172. event_handle(adapter, &adapter->rx_eq);
  1173. return IRQ_HANDLED;
  1174. }
  1175. static irqreturn_t be_msix_rx(int irq, void *dev)
  1176. {
  1177. struct be_adapter *adapter = dev;
  1178. event_handle(adapter, &adapter->rx_eq);
  1179. return IRQ_HANDLED;
  1180. }
  1181. static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
  1182. {
  1183. struct be_adapter *adapter = dev;
  1184. event_handle(adapter, &adapter->tx_eq);
  1185. return IRQ_HANDLED;
  1186. }
  1187. static inline bool do_gro(struct be_adapter *adapter,
  1188. struct be_eth_rx_compl *rxcp)
  1189. {
  1190. int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
  1191. int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  1192. if (err)
  1193. drvr_stats(adapter)->be_rxcp_err++;
  1194. return (tcp_frame && !err) ? true : false;
  1195. }
  1196. int be_poll_rx(struct napi_struct *napi, int budget)
  1197. {
  1198. struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
  1199. struct be_adapter *adapter =
  1200. container_of(rx_eq, struct be_adapter, rx_eq);
  1201. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1202. struct be_eth_rx_compl *rxcp;
  1203. u32 work_done;
  1204. adapter->stats.drvr_stats.be_rx_polls++;
  1205. for (work_done = 0; work_done < budget; work_done++) {
  1206. rxcp = be_rx_compl_get(adapter);
  1207. if (!rxcp)
  1208. break;
  1209. if (do_gro(adapter, rxcp))
  1210. be_rx_compl_process_gro(adapter, rxcp);
  1211. else
  1212. be_rx_compl_process(adapter, rxcp);
  1213. be_rx_compl_reset(rxcp);
  1214. }
  1215. /* Refill the queue */
  1216. if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
  1217. be_post_rx_frags(adapter);
  1218. /* All consumed */
  1219. if (work_done < budget) {
  1220. napi_complete(napi);
  1221. be_cq_notify(adapter, rx_cq->id, true, work_done);
  1222. } else {
  1223. /* More to be consumed; continue with interrupts disabled */
  1224. be_cq_notify(adapter, rx_cq->id, false, work_done);
  1225. }
  1226. return work_done;
  1227. }
  1228. /* As TX and MCC share the same EQ check for both TX and MCC completions.
  1229. * For TX/MCC we don't honour budget; consume everything
  1230. */
  1231. static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
  1232. {
  1233. struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
  1234. struct be_adapter *adapter =
  1235. container_of(tx_eq, struct be_adapter, tx_eq);
  1236. struct be_queue_info *txq = &adapter->tx_obj.q;
  1237. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1238. struct be_eth_tx_compl *txcp;
  1239. int tx_compl = 0, mcc_compl, status = 0;
  1240. u16 end_idx;
  1241. while ((txcp = be_tx_compl_get(tx_cq))) {
  1242. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1243. wrb_index, txcp);
  1244. be_tx_compl_process(adapter, end_idx);
  1245. tx_compl++;
  1246. }
  1247. mcc_compl = be_process_mcc(adapter, &status);
  1248. napi_complete(napi);
  1249. if (mcc_compl) {
  1250. struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
  1251. be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
  1252. }
  1253. if (tx_compl) {
  1254. be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
  1255. /* As Tx wrbs have been freed up, wake up netdev queue if
  1256. * it was stopped due to lack of tx wrbs.
  1257. */
  1258. if (netif_queue_stopped(adapter->netdev) &&
  1259. atomic_read(&txq->used) < txq->len / 2) {
  1260. netif_wake_queue(adapter->netdev);
  1261. }
  1262. drvr_stats(adapter)->be_tx_events++;
  1263. drvr_stats(adapter)->be_tx_compl += tx_compl;
  1264. }
  1265. return 1;
  1266. }
  1267. static void be_worker(struct work_struct *work)
  1268. {
  1269. struct be_adapter *adapter =
  1270. container_of(work, struct be_adapter, work.work);
  1271. be_cmd_get_stats(adapter, &adapter->stats.cmd);
  1272. /* Set EQ delay */
  1273. be_rx_eqd_update(adapter);
  1274. be_tx_rate_update(adapter);
  1275. be_rx_rate_update(adapter);
  1276. if (adapter->rx_post_starved) {
  1277. adapter->rx_post_starved = false;
  1278. be_post_rx_frags(adapter);
  1279. }
  1280. schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
  1281. }
  1282. static void be_msix_disable(struct be_adapter *adapter)
  1283. {
  1284. if (adapter->msix_enabled) {
  1285. pci_disable_msix(adapter->pdev);
  1286. adapter->msix_enabled = false;
  1287. }
  1288. }
  1289. static void be_msix_enable(struct be_adapter *adapter)
  1290. {
  1291. int i, status;
  1292. for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
  1293. adapter->msix_entries[i].entry = i;
  1294. status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
  1295. BE_NUM_MSIX_VECTORS);
  1296. if (status == 0)
  1297. adapter->msix_enabled = true;
  1298. return;
  1299. }
  1300. static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
  1301. {
  1302. return adapter->msix_entries[
  1303. be_evt_bit_get(adapter, eq_id)].vector;
  1304. }
  1305. static int be_request_irq(struct be_adapter *adapter,
  1306. struct be_eq_obj *eq_obj,
  1307. void *handler, char *desc)
  1308. {
  1309. struct net_device *netdev = adapter->netdev;
  1310. int vec;
  1311. sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
  1312. vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1313. return request_irq(vec, handler, 0, eq_obj->desc, adapter);
  1314. }
  1315. static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
  1316. {
  1317. int vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1318. free_irq(vec, adapter);
  1319. }
  1320. static int be_msix_register(struct be_adapter *adapter)
  1321. {
  1322. int status;
  1323. status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
  1324. if (status)
  1325. goto err;
  1326. status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
  1327. if (status)
  1328. goto free_tx_irq;
  1329. return 0;
  1330. free_tx_irq:
  1331. be_free_irq(adapter, &adapter->tx_eq);
  1332. err:
  1333. dev_warn(&adapter->pdev->dev,
  1334. "MSIX Request IRQ failed - err %d\n", status);
  1335. pci_disable_msix(adapter->pdev);
  1336. adapter->msix_enabled = false;
  1337. return status;
  1338. }
  1339. static int be_irq_register(struct be_adapter *adapter)
  1340. {
  1341. struct net_device *netdev = adapter->netdev;
  1342. int status;
  1343. if (adapter->msix_enabled) {
  1344. status = be_msix_register(adapter);
  1345. if (status == 0)
  1346. goto done;
  1347. }
  1348. /* INTx */
  1349. netdev->irq = adapter->pdev->irq;
  1350. status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
  1351. adapter);
  1352. if (status) {
  1353. dev_err(&adapter->pdev->dev,
  1354. "INTx request IRQ failed - err %d\n", status);
  1355. return status;
  1356. }
  1357. done:
  1358. adapter->isr_registered = true;
  1359. return 0;
  1360. }
  1361. static void be_irq_unregister(struct be_adapter *adapter)
  1362. {
  1363. struct net_device *netdev = adapter->netdev;
  1364. if (!adapter->isr_registered)
  1365. return;
  1366. /* INTx */
  1367. if (!adapter->msix_enabled) {
  1368. free_irq(netdev->irq, adapter);
  1369. goto done;
  1370. }
  1371. /* MSIx */
  1372. be_free_irq(adapter, &adapter->tx_eq);
  1373. be_free_irq(adapter, &adapter->rx_eq);
  1374. done:
  1375. adapter->isr_registered = false;
  1376. return;
  1377. }
  1378. static int be_open(struct net_device *netdev)
  1379. {
  1380. struct be_adapter *adapter = netdev_priv(netdev);
  1381. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1382. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1383. bool link_up;
  1384. int status;
  1385. u8 mac_speed;
  1386. u16 link_speed;
  1387. /* First time posting */
  1388. be_post_rx_frags(adapter);
  1389. napi_enable(&rx_eq->napi);
  1390. napi_enable(&tx_eq->napi);
  1391. be_irq_register(adapter);
  1392. be_intr_set(adapter, true);
  1393. /* The evt queues are created in unarmed state; arm them */
  1394. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  1395. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  1396. /* Rx compl queue may be in unarmed state; rearm it */
  1397. be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
  1398. /* Now that interrupts are on we can process async mcc */
  1399. be_async_mcc_enable(adapter);
  1400. status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
  1401. &link_speed);
  1402. if (status)
  1403. goto ret_sts;
  1404. be_link_status_update(adapter, link_up);
  1405. status = be_vid_config(adapter);
  1406. if (status)
  1407. goto ret_sts;
  1408. status = be_cmd_set_flow_control(adapter,
  1409. adapter->tx_fc, adapter->rx_fc);
  1410. if (status)
  1411. goto ret_sts;
  1412. schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
  1413. ret_sts:
  1414. return status;
  1415. }
  1416. static int be_setup_wol(struct be_adapter *adapter, bool enable)
  1417. {
  1418. struct be_dma_mem cmd;
  1419. int status = 0;
  1420. u8 mac[ETH_ALEN];
  1421. memset(mac, 0, ETH_ALEN);
  1422. cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
  1423. cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
  1424. if (cmd.va == NULL)
  1425. return -1;
  1426. memset(cmd.va, 0, cmd.size);
  1427. if (enable) {
  1428. status = pci_write_config_dword(adapter->pdev,
  1429. PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
  1430. if (status) {
  1431. dev_err(&adapter->pdev->dev,
  1432. "Could not enable Wake-on-lan \n");
  1433. pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
  1434. cmd.dma);
  1435. return status;
  1436. }
  1437. status = be_cmd_enable_magic_wol(adapter,
  1438. adapter->netdev->dev_addr, &cmd);
  1439. pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
  1440. pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
  1441. } else {
  1442. status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
  1443. pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
  1444. pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
  1445. }
  1446. pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
  1447. return status;
  1448. }
  1449. static int be_setup(struct be_adapter *adapter)
  1450. {
  1451. struct net_device *netdev = adapter->netdev;
  1452. u32 cap_flags, en_flags;
  1453. int status;
  1454. cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
  1455. BE_IF_FLAGS_MCAST_PROMISCUOUS |
  1456. BE_IF_FLAGS_PROMISCUOUS |
  1457. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1458. en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
  1459. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1460. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1461. netdev->dev_addr, false/* pmac_invalid */,
  1462. &adapter->if_handle, &adapter->pmac_id);
  1463. if (status != 0)
  1464. goto do_none;
  1465. status = be_tx_queues_create(adapter);
  1466. if (status != 0)
  1467. goto if_destroy;
  1468. status = be_rx_queues_create(adapter);
  1469. if (status != 0)
  1470. goto tx_qs_destroy;
  1471. status = be_mcc_queues_create(adapter);
  1472. if (status != 0)
  1473. goto rx_qs_destroy;
  1474. adapter->link_speed = -1;
  1475. return 0;
  1476. rx_qs_destroy:
  1477. be_rx_queues_destroy(adapter);
  1478. tx_qs_destroy:
  1479. be_tx_queues_destroy(adapter);
  1480. if_destroy:
  1481. be_cmd_if_destroy(adapter, adapter->if_handle);
  1482. do_none:
  1483. return status;
  1484. }
  1485. static int be_clear(struct be_adapter *adapter)
  1486. {
  1487. be_mcc_queues_destroy(adapter);
  1488. be_rx_queues_destroy(adapter);
  1489. be_tx_queues_destroy(adapter);
  1490. be_cmd_if_destroy(adapter, adapter->if_handle);
  1491. /* tell fw we're done with firing cmds */
  1492. be_cmd_fw_clean(adapter);
  1493. return 0;
  1494. }
  1495. static int be_close(struct net_device *netdev)
  1496. {
  1497. struct be_adapter *adapter = netdev_priv(netdev);
  1498. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1499. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1500. int vec;
  1501. cancel_delayed_work_sync(&adapter->work);
  1502. be_async_mcc_disable(adapter);
  1503. netif_stop_queue(netdev);
  1504. netif_carrier_off(netdev);
  1505. adapter->link_up = false;
  1506. be_intr_set(adapter, false);
  1507. if (adapter->msix_enabled) {
  1508. vec = be_msix_vec_get(adapter, tx_eq->q.id);
  1509. synchronize_irq(vec);
  1510. vec = be_msix_vec_get(adapter, rx_eq->q.id);
  1511. synchronize_irq(vec);
  1512. } else {
  1513. synchronize_irq(netdev->irq);
  1514. }
  1515. be_irq_unregister(adapter);
  1516. napi_disable(&rx_eq->napi);
  1517. napi_disable(&tx_eq->napi);
  1518. /* Wait for all pending tx completions to arrive so that
  1519. * all tx skbs are freed.
  1520. */
  1521. be_tx_compl_clean(adapter);
  1522. return 0;
  1523. }
  1524. #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
  1525. char flash_cookie[2][16] = {"*** SE FLAS",
  1526. "H DIRECTORY *** "};
  1527. static bool be_flash_redboot(struct be_adapter *adapter,
  1528. const u8 *p, u32 img_start, int image_size,
  1529. int hdr_size)
  1530. {
  1531. u32 crc_offset;
  1532. u8 flashed_crc[4];
  1533. int status;
  1534. crc_offset = hdr_size + img_start + image_size - 4;
  1535. p += crc_offset;
  1536. status = be_cmd_get_flash_crc(adapter, flashed_crc,
  1537. (img_start + image_size - 4));
  1538. if (status) {
  1539. dev_err(&adapter->pdev->dev,
  1540. "could not get crc from flash, not flashing redboot\n");
  1541. return false;
  1542. }
  1543. /*update redboot only if crc does not match*/
  1544. if (!memcmp(flashed_crc, p, 4))
  1545. return false;
  1546. else
  1547. return true;
  1548. }
  1549. static int be_flash_data(struct be_adapter *adapter,
  1550. const struct firmware *fw,
  1551. struct be_dma_mem *flash_cmd, int num_of_images)
  1552. {
  1553. int status = 0, i, filehdr_size = 0;
  1554. u32 total_bytes = 0, flash_op;
  1555. int num_bytes;
  1556. const u8 *p = fw->data;
  1557. struct be_cmd_write_flashrom *req = flash_cmd->va;
  1558. struct flash_comp *pflashcomp;
  1559. struct flash_comp gen3_flash_types[8] = {
  1560. { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
  1561. FLASH_IMAGE_MAX_SIZE_g3},
  1562. { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
  1563. FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
  1564. { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
  1565. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1566. { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
  1567. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1568. { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
  1569. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1570. { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
  1571. FLASH_IMAGE_MAX_SIZE_g3},
  1572. { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
  1573. FLASH_IMAGE_MAX_SIZE_g3},
  1574. { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
  1575. FLASH_IMAGE_MAX_SIZE_g3}
  1576. };
  1577. struct flash_comp gen2_flash_types[8] = {
  1578. { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
  1579. FLASH_IMAGE_MAX_SIZE_g2},
  1580. { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
  1581. FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
  1582. { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
  1583. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1584. { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
  1585. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1586. { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
  1587. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1588. { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
  1589. FLASH_IMAGE_MAX_SIZE_g2},
  1590. { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
  1591. FLASH_IMAGE_MAX_SIZE_g2},
  1592. { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
  1593. FLASH_IMAGE_MAX_SIZE_g2}
  1594. };
  1595. if (adapter->generation == BE_GEN3) {
  1596. pflashcomp = gen3_flash_types;
  1597. filehdr_size = sizeof(struct flash_file_hdr_g3);
  1598. } else {
  1599. pflashcomp = gen2_flash_types;
  1600. filehdr_size = sizeof(struct flash_file_hdr_g2);
  1601. }
  1602. for (i = 0; i < 8; i++) {
  1603. if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
  1604. (!be_flash_redboot(adapter, fw->data,
  1605. pflashcomp[i].offset, pflashcomp[i].size,
  1606. filehdr_size)))
  1607. continue;
  1608. p = fw->data;
  1609. p += filehdr_size + pflashcomp[i].offset
  1610. + (num_of_images * sizeof(struct image_hdr));
  1611. if (p + pflashcomp[i].size > fw->data + fw->size)
  1612. return -1;
  1613. total_bytes = pflashcomp[i].size;
  1614. while (total_bytes) {
  1615. if (total_bytes > 32*1024)
  1616. num_bytes = 32*1024;
  1617. else
  1618. num_bytes = total_bytes;
  1619. total_bytes -= num_bytes;
  1620. if (!total_bytes)
  1621. flash_op = FLASHROM_OPER_FLASH;
  1622. else
  1623. flash_op = FLASHROM_OPER_SAVE;
  1624. memcpy(req->params.data_buf, p, num_bytes);
  1625. p += num_bytes;
  1626. status = be_cmd_write_flashrom(adapter, flash_cmd,
  1627. pflashcomp[i].optype, flash_op, num_bytes);
  1628. if (status) {
  1629. dev_err(&adapter->pdev->dev,
  1630. "cmd to write to flash rom failed.\n");
  1631. return -1;
  1632. }
  1633. yield();
  1634. }
  1635. }
  1636. return 0;
  1637. }
  1638. static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
  1639. {
  1640. if (fhdr == NULL)
  1641. return 0;
  1642. if (fhdr->build[0] == '3')
  1643. return BE_GEN3;
  1644. else if (fhdr->build[0] == '2')
  1645. return BE_GEN2;
  1646. else
  1647. return 0;
  1648. }
  1649. int be_load_fw(struct be_adapter *adapter, u8 *func)
  1650. {
  1651. char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
  1652. const struct firmware *fw;
  1653. struct flash_file_hdr_g2 *fhdr;
  1654. struct flash_file_hdr_g3 *fhdr3;
  1655. struct image_hdr *img_hdr_ptr = NULL;
  1656. struct be_dma_mem flash_cmd;
  1657. int status, i = 0;
  1658. const u8 *p;
  1659. char fw_ver[FW_VER_LEN];
  1660. char fw_cfg;
  1661. status = be_cmd_get_fw_ver(adapter, fw_ver);
  1662. if (status)
  1663. return status;
  1664. fw_cfg = *(fw_ver + 2);
  1665. if (fw_cfg == '0')
  1666. fw_cfg = '1';
  1667. strcpy(fw_file, func);
  1668. status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
  1669. if (status)
  1670. goto fw_exit;
  1671. p = fw->data;
  1672. fhdr = (struct flash_file_hdr_g2 *) p;
  1673. dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
  1674. flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
  1675. flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
  1676. &flash_cmd.dma);
  1677. if (!flash_cmd.va) {
  1678. status = -ENOMEM;
  1679. dev_err(&adapter->pdev->dev,
  1680. "Memory allocation failure while flashing\n");
  1681. goto fw_exit;
  1682. }
  1683. if ((adapter->generation == BE_GEN3) &&
  1684. (get_ufigen_type(fhdr) == BE_GEN3)) {
  1685. fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
  1686. for (i = 0; i < fhdr3->num_imgs; i++) {
  1687. img_hdr_ptr = (struct image_hdr *) (fw->data +
  1688. (sizeof(struct flash_file_hdr_g3) +
  1689. i * sizeof(struct image_hdr)));
  1690. if (img_hdr_ptr->imageid == 1) {
  1691. status = be_flash_data(adapter, fw,
  1692. &flash_cmd, fhdr3->num_imgs);
  1693. }
  1694. }
  1695. } else if ((adapter->generation == BE_GEN2) &&
  1696. (get_ufigen_type(fhdr) == BE_GEN2)) {
  1697. status = be_flash_data(adapter, fw, &flash_cmd, 0);
  1698. } else {
  1699. dev_err(&adapter->pdev->dev,
  1700. "UFI and Interface are not compatible for flashing\n");
  1701. status = -1;
  1702. }
  1703. pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
  1704. flash_cmd.dma);
  1705. if (status) {
  1706. dev_err(&adapter->pdev->dev, "Firmware load error\n");
  1707. goto fw_exit;
  1708. }
  1709. dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
  1710. fw_exit:
  1711. release_firmware(fw);
  1712. return status;
  1713. }
  1714. static struct net_device_ops be_netdev_ops = {
  1715. .ndo_open = be_open,
  1716. .ndo_stop = be_close,
  1717. .ndo_start_xmit = be_xmit,
  1718. .ndo_get_stats = be_get_stats,
  1719. .ndo_set_rx_mode = be_set_multicast_list,
  1720. .ndo_set_mac_address = be_mac_addr_set,
  1721. .ndo_change_mtu = be_change_mtu,
  1722. .ndo_validate_addr = eth_validate_addr,
  1723. .ndo_vlan_rx_register = be_vlan_register,
  1724. .ndo_vlan_rx_add_vid = be_vlan_add_vid,
  1725. .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
  1726. };
  1727. static void be_netdev_init(struct net_device *netdev)
  1728. {
  1729. struct be_adapter *adapter = netdev_priv(netdev);
  1730. netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
  1731. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
  1732. NETIF_F_GRO;
  1733. netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
  1734. netdev->flags |= IFF_MULTICAST;
  1735. adapter->rx_csum = true;
  1736. /* Default settings for Rx and Tx flow control */
  1737. adapter->rx_fc = true;
  1738. adapter->tx_fc = true;
  1739. netif_set_gso_max_size(netdev, 65535);
  1740. BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
  1741. SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
  1742. netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
  1743. BE_NAPI_WEIGHT);
  1744. netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
  1745. BE_NAPI_WEIGHT);
  1746. netif_carrier_off(netdev);
  1747. netif_stop_queue(netdev);
  1748. }
  1749. static void be_unmap_pci_bars(struct be_adapter *adapter)
  1750. {
  1751. if (adapter->csr)
  1752. iounmap(adapter->csr);
  1753. if (adapter->db)
  1754. iounmap(adapter->db);
  1755. if (adapter->pcicfg)
  1756. iounmap(adapter->pcicfg);
  1757. }
  1758. static int be_map_pci_bars(struct be_adapter *adapter)
  1759. {
  1760. u8 __iomem *addr;
  1761. int pcicfg_reg;
  1762. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
  1763. pci_resource_len(adapter->pdev, 2));
  1764. if (addr == NULL)
  1765. return -ENOMEM;
  1766. adapter->csr = addr;
  1767. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
  1768. 128 * 1024);
  1769. if (addr == NULL)
  1770. goto pci_map_err;
  1771. adapter->db = addr;
  1772. if (adapter->generation == BE_GEN2)
  1773. pcicfg_reg = 1;
  1774. else
  1775. pcicfg_reg = 0;
  1776. addr = ioremap_nocache(pci_resource_start(adapter->pdev, pcicfg_reg),
  1777. pci_resource_len(adapter->pdev, pcicfg_reg));
  1778. if (addr == NULL)
  1779. goto pci_map_err;
  1780. adapter->pcicfg = addr;
  1781. return 0;
  1782. pci_map_err:
  1783. be_unmap_pci_bars(adapter);
  1784. return -ENOMEM;
  1785. }
  1786. static void be_ctrl_cleanup(struct be_adapter *adapter)
  1787. {
  1788. struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
  1789. be_unmap_pci_bars(adapter);
  1790. if (mem->va)
  1791. pci_free_consistent(adapter->pdev, mem->size,
  1792. mem->va, mem->dma);
  1793. mem = &adapter->mc_cmd_mem;
  1794. if (mem->va)
  1795. pci_free_consistent(adapter->pdev, mem->size,
  1796. mem->va, mem->dma);
  1797. }
  1798. static int be_ctrl_init(struct be_adapter *adapter)
  1799. {
  1800. struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
  1801. struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
  1802. struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
  1803. int status;
  1804. status = be_map_pci_bars(adapter);
  1805. if (status)
  1806. goto done;
  1807. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  1808. mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
  1809. mbox_mem_alloc->size, &mbox_mem_alloc->dma);
  1810. if (!mbox_mem_alloc->va) {
  1811. status = -ENOMEM;
  1812. goto unmap_pci_bars;
  1813. }
  1814. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  1815. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  1816. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  1817. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  1818. mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
  1819. mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
  1820. &mc_cmd_mem->dma);
  1821. if (mc_cmd_mem->va == NULL) {
  1822. status = -ENOMEM;
  1823. goto free_mbox;
  1824. }
  1825. memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
  1826. spin_lock_init(&adapter->mbox_lock);
  1827. spin_lock_init(&adapter->mcc_lock);
  1828. spin_lock_init(&adapter->mcc_cq_lock);
  1829. pci_save_state(adapter->pdev);
  1830. return 0;
  1831. free_mbox:
  1832. pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
  1833. mbox_mem_alloc->va, mbox_mem_alloc->dma);
  1834. unmap_pci_bars:
  1835. be_unmap_pci_bars(adapter);
  1836. done:
  1837. return status;
  1838. }
  1839. static void be_stats_cleanup(struct be_adapter *adapter)
  1840. {
  1841. struct be_stats_obj *stats = &adapter->stats;
  1842. struct be_dma_mem *cmd = &stats->cmd;
  1843. if (cmd->va)
  1844. pci_free_consistent(adapter->pdev, cmd->size,
  1845. cmd->va, cmd->dma);
  1846. }
  1847. static int be_stats_init(struct be_adapter *adapter)
  1848. {
  1849. struct be_stats_obj *stats = &adapter->stats;
  1850. struct be_dma_mem *cmd = &stats->cmd;
  1851. cmd->size = sizeof(struct be_cmd_req_get_stats);
  1852. cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
  1853. if (cmd->va == NULL)
  1854. return -1;
  1855. memset(cmd->va, 0, cmd->size);
  1856. return 0;
  1857. }
  1858. static void __devexit be_remove(struct pci_dev *pdev)
  1859. {
  1860. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1861. if (!adapter)
  1862. return;
  1863. unregister_netdev(adapter->netdev);
  1864. be_clear(adapter);
  1865. be_stats_cleanup(adapter);
  1866. be_ctrl_cleanup(adapter);
  1867. be_msix_disable(adapter);
  1868. pci_set_drvdata(pdev, NULL);
  1869. pci_release_regions(pdev);
  1870. pci_disable_device(pdev);
  1871. free_netdev(adapter->netdev);
  1872. }
  1873. static int be_get_config(struct be_adapter *adapter)
  1874. {
  1875. int status;
  1876. u8 mac[ETH_ALEN];
  1877. status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
  1878. if (status)
  1879. return status;
  1880. status = be_cmd_query_fw_cfg(adapter,
  1881. &adapter->port_num, &adapter->cap);
  1882. if (status)
  1883. return status;
  1884. memset(mac, 0, ETH_ALEN);
  1885. status = be_cmd_mac_addr_query(adapter, mac,
  1886. MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
  1887. if (status)
  1888. return status;
  1889. if (!is_valid_ether_addr(mac))
  1890. return -EADDRNOTAVAIL;
  1891. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  1892. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  1893. if (adapter->cap & 0x400)
  1894. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
  1895. else
  1896. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
  1897. return 0;
  1898. }
  1899. static int __devinit be_probe(struct pci_dev *pdev,
  1900. const struct pci_device_id *pdev_id)
  1901. {
  1902. int status = 0;
  1903. struct be_adapter *adapter;
  1904. struct net_device *netdev;
  1905. status = pci_enable_device(pdev);
  1906. if (status)
  1907. goto do_none;
  1908. status = pci_request_regions(pdev, DRV_NAME);
  1909. if (status)
  1910. goto disable_dev;
  1911. pci_set_master(pdev);
  1912. netdev = alloc_etherdev(sizeof(struct be_adapter));
  1913. if (netdev == NULL) {
  1914. status = -ENOMEM;
  1915. goto rel_reg;
  1916. }
  1917. adapter = netdev_priv(netdev);
  1918. switch (pdev->device) {
  1919. case BE_DEVICE_ID1:
  1920. case OC_DEVICE_ID1:
  1921. adapter->generation = BE_GEN2;
  1922. break;
  1923. case BE_DEVICE_ID2:
  1924. case OC_DEVICE_ID2:
  1925. adapter->generation = BE_GEN3;
  1926. break;
  1927. default:
  1928. adapter->generation = 0;
  1929. }
  1930. adapter->pdev = pdev;
  1931. pci_set_drvdata(pdev, adapter);
  1932. adapter->netdev = netdev;
  1933. be_netdev_init(netdev);
  1934. SET_NETDEV_DEV(netdev, &pdev->dev);
  1935. be_msix_enable(adapter);
  1936. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  1937. if (!status) {
  1938. netdev->features |= NETIF_F_HIGHDMA;
  1939. } else {
  1940. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1941. if (status) {
  1942. dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
  1943. goto free_netdev;
  1944. }
  1945. }
  1946. status = be_ctrl_init(adapter);
  1947. if (status)
  1948. goto free_netdev;
  1949. /* sync up with fw's ready state */
  1950. status = be_cmd_POST(adapter);
  1951. if (status)
  1952. goto ctrl_clean;
  1953. /* tell fw we're ready to fire cmds */
  1954. status = be_cmd_fw_init(adapter);
  1955. if (status)
  1956. goto ctrl_clean;
  1957. status = be_cmd_reset_function(adapter);
  1958. if (status)
  1959. goto ctrl_clean;
  1960. status = be_stats_init(adapter);
  1961. if (status)
  1962. goto ctrl_clean;
  1963. status = be_get_config(adapter);
  1964. if (status)
  1965. goto stats_clean;
  1966. INIT_DELAYED_WORK(&adapter->work, be_worker);
  1967. status = be_setup(adapter);
  1968. if (status)
  1969. goto stats_clean;
  1970. status = register_netdev(netdev);
  1971. if (status != 0)
  1972. goto unsetup;
  1973. dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
  1974. return 0;
  1975. unsetup:
  1976. be_clear(adapter);
  1977. stats_clean:
  1978. be_stats_cleanup(adapter);
  1979. ctrl_clean:
  1980. be_ctrl_cleanup(adapter);
  1981. free_netdev:
  1982. be_msix_disable(adapter);
  1983. free_netdev(adapter->netdev);
  1984. pci_set_drvdata(pdev, NULL);
  1985. rel_reg:
  1986. pci_release_regions(pdev);
  1987. disable_dev:
  1988. pci_disable_device(pdev);
  1989. do_none:
  1990. dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
  1991. return status;
  1992. }
  1993. static int be_suspend(struct pci_dev *pdev, pm_message_t state)
  1994. {
  1995. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1996. struct net_device *netdev = adapter->netdev;
  1997. if (adapter->wol)
  1998. be_setup_wol(adapter, true);
  1999. netif_device_detach(netdev);
  2000. if (netif_running(netdev)) {
  2001. rtnl_lock();
  2002. be_close(netdev);
  2003. rtnl_unlock();
  2004. }
  2005. be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
  2006. be_clear(adapter);
  2007. pci_save_state(pdev);
  2008. pci_disable_device(pdev);
  2009. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2010. return 0;
  2011. }
  2012. static int be_resume(struct pci_dev *pdev)
  2013. {
  2014. int status = 0;
  2015. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2016. struct net_device *netdev = adapter->netdev;
  2017. netif_device_detach(netdev);
  2018. status = pci_enable_device(pdev);
  2019. if (status)
  2020. return status;
  2021. pci_set_power_state(pdev, 0);
  2022. pci_restore_state(pdev);
  2023. /* tell fw we're ready to fire cmds */
  2024. status = be_cmd_fw_init(adapter);
  2025. if (status)
  2026. return status;
  2027. be_setup(adapter);
  2028. if (netif_running(netdev)) {
  2029. rtnl_lock();
  2030. be_open(netdev);
  2031. rtnl_unlock();
  2032. }
  2033. netif_device_attach(netdev);
  2034. if (adapter->wol)
  2035. be_setup_wol(adapter, false);
  2036. return 0;
  2037. }
  2038. /*
  2039. * An FLR will stop BE from DMAing any data.
  2040. */
  2041. static void be_shutdown(struct pci_dev *pdev)
  2042. {
  2043. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2044. struct net_device *netdev = adapter->netdev;
  2045. netif_device_detach(netdev);
  2046. be_cmd_reset_function(adapter);
  2047. if (adapter->wol)
  2048. be_setup_wol(adapter, true);
  2049. pci_disable_device(pdev);
  2050. return;
  2051. }
  2052. static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
  2053. pci_channel_state_t state)
  2054. {
  2055. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2056. struct net_device *netdev = adapter->netdev;
  2057. dev_err(&adapter->pdev->dev, "EEH error detected\n");
  2058. adapter->eeh_err = true;
  2059. netif_device_detach(netdev);
  2060. if (netif_running(netdev)) {
  2061. rtnl_lock();
  2062. be_close(netdev);
  2063. rtnl_unlock();
  2064. }
  2065. be_clear(adapter);
  2066. if (state == pci_channel_io_perm_failure)
  2067. return PCI_ERS_RESULT_DISCONNECT;
  2068. pci_disable_device(pdev);
  2069. return PCI_ERS_RESULT_NEED_RESET;
  2070. }
  2071. static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
  2072. {
  2073. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2074. int status;
  2075. dev_info(&adapter->pdev->dev, "EEH reset\n");
  2076. adapter->eeh_err = false;
  2077. status = pci_enable_device(pdev);
  2078. if (status)
  2079. return PCI_ERS_RESULT_DISCONNECT;
  2080. pci_set_master(pdev);
  2081. pci_set_power_state(pdev, 0);
  2082. pci_restore_state(pdev);
  2083. /* Check if card is ok and fw is ready */
  2084. status = be_cmd_POST(adapter);
  2085. if (status)
  2086. return PCI_ERS_RESULT_DISCONNECT;
  2087. return PCI_ERS_RESULT_RECOVERED;
  2088. }
  2089. static void be_eeh_resume(struct pci_dev *pdev)
  2090. {
  2091. int status = 0;
  2092. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2093. struct net_device *netdev = adapter->netdev;
  2094. dev_info(&adapter->pdev->dev, "EEH resume\n");
  2095. pci_save_state(pdev);
  2096. /* tell fw we're ready to fire cmds */
  2097. status = be_cmd_fw_init(adapter);
  2098. if (status)
  2099. goto err;
  2100. status = be_setup(adapter);
  2101. if (status)
  2102. goto err;
  2103. if (netif_running(netdev)) {
  2104. status = be_open(netdev);
  2105. if (status)
  2106. goto err;
  2107. }
  2108. netif_device_attach(netdev);
  2109. return;
  2110. err:
  2111. dev_err(&adapter->pdev->dev, "EEH resume failed\n");
  2112. return;
  2113. }
  2114. static struct pci_error_handlers be_eeh_handlers = {
  2115. .error_detected = be_eeh_err_detected,
  2116. .slot_reset = be_eeh_reset,
  2117. .resume = be_eeh_resume,
  2118. };
  2119. static struct pci_driver be_driver = {
  2120. .name = DRV_NAME,
  2121. .id_table = be_dev_ids,
  2122. .probe = be_probe,
  2123. .remove = be_remove,
  2124. .suspend = be_suspend,
  2125. .resume = be_resume,
  2126. .shutdown = be_shutdown,
  2127. .err_handler = &be_eeh_handlers
  2128. };
  2129. static int __init be_init_module(void)
  2130. {
  2131. if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
  2132. rx_frag_size != 2048) {
  2133. printk(KERN_WARNING DRV_NAME
  2134. " : Module param rx_frag_size must be 2048/4096/8192."
  2135. " Using 2048\n");
  2136. rx_frag_size = 2048;
  2137. }
  2138. return pci_register_driver(&be_driver);
  2139. }
  2140. module_init(be_init_module);
  2141. static void __exit be_exit_module(void)
  2142. {
  2143. pci_unregister_driver(&be_driver);
  2144. }
  2145. module_exit(be_exit_module);