em28xx-core.c 31 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240
  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include <media/v4l2-common.h>
  25. #include "em28xx.h"
  26. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  27. static unsigned int core_debug;
  28. module_param(core_debug, int, 0644);
  29. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  30. #define em28xx_coredbg(fmt, arg...) do {\
  31. if (core_debug) \
  32. printk(KERN_INFO "%s %s :"fmt, \
  33. dev->name, __func__ , ##arg); } while (0)
  34. static unsigned int reg_debug;
  35. module_param(reg_debug, int, 0644);
  36. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  37. #define em28xx_regdbg(fmt, arg...) do {\
  38. if (reg_debug) \
  39. printk(KERN_INFO "%s %s :"fmt, \
  40. dev->name, __func__ , ##arg); } while (0)
  41. static int alt;
  42. module_param(alt, int, 0644);
  43. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  44. static unsigned int disable_vbi;
  45. module_param(disable_vbi, int, 0644);
  46. MODULE_PARM_DESC(disable_vbi, "disable vbi support");
  47. /* FIXME */
  48. #define em28xx_isocdbg(fmt, arg...) do {\
  49. if (core_debug) \
  50. printk(KERN_INFO "%s %s :"fmt, \
  51. dev->name, __func__ , ##arg); } while (0)
  52. /*
  53. * em28xx_read_reg_req()
  54. * reads data from the usb device specifying bRequest
  55. */
  56. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  57. char *buf, int len)
  58. {
  59. int ret;
  60. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  61. if (dev->state & DEV_DISCONNECTED)
  62. return -ENODEV;
  63. if (len > URB_MAX_CTRL_SIZE)
  64. return -EINVAL;
  65. if (reg_debug) {
  66. printk(KERN_DEBUG "(pipe 0x%08x): "
  67. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  68. pipe,
  69. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  70. req, 0, 0,
  71. reg & 0xff, reg >> 8,
  72. len & 0xff, len >> 8);
  73. }
  74. mutex_lock(&dev->ctrl_urb_lock);
  75. ret = usb_control_msg(dev->udev, pipe, req,
  76. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  77. 0x0000, reg, dev->urb_buf, len, HZ);
  78. if (ret < 0) {
  79. if (reg_debug)
  80. printk(" failed!\n");
  81. mutex_unlock(&dev->ctrl_urb_lock);
  82. return ret;
  83. }
  84. if (len)
  85. memcpy(buf, dev->urb_buf, len);
  86. mutex_unlock(&dev->ctrl_urb_lock);
  87. if (reg_debug) {
  88. int byte;
  89. printk("<<<");
  90. for (byte = 0; byte < len; byte++)
  91. printk(" %02x", (unsigned char)buf[byte]);
  92. printk("\n");
  93. }
  94. return ret;
  95. }
  96. /*
  97. * em28xx_read_reg_req()
  98. * reads data from the usb device specifying bRequest
  99. */
  100. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  101. {
  102. int ret;
  103. u8 val;
  104. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  105. if (ret < 0)
  106. return ret;
  107. return val;
  108. }
  109. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  110. {
  111. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  112. }
  113. /*
  114. * em28xx_write_regs_req()
  115. * sends data to the usb device, specifying bRequest
  116. */
  117. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  118. int len)
  119. {
  120. int ret;
  121. int pipe = usb_sndctrlpipe(dev->udev, 0);
  122. if (dev->state & DEV_DISCONNECTED)
  123. return -ENODEV;
  124. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  125. return -EINVAL;
  126. if (reg_debug) {
  127. int byte;
  128. printk(KERN_DEBUG "(pipe 0x%08x): "
  129. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  130. pipe,
  131. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  132. req, 0, 0,
  133. reg & 0xff, reg >> 8,
  134. len & 0xff, len >> 8);
  135. for (byte = 0; byte < len; byte++)
  136. printk(" %02x", (unsigned char)buf[byte]);
  137. printk("\n");
  138. }
  139. mutex_lock(&dev->ctrl_urb_lock);
  140. memcpy(dev->urb_buf, buf, len);
  141. ret = usb_control_msg(dev->udev, pipe, req,
  142. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  143. 0x0000, reg, dev->urb_buf, len, HZ);
  144. mutex_unlock(&dev->ctrl_urb_lock);
  145. if (dev->wait_after_write)
  146. msleep(dev->wait_after_write);
  147. return ret;
  148. }
  149. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  150. {
  151. int rc;
  152. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  153. /* Stores GPO/GPIO values at the cache, if changed
  154. Only write values should be stored, since input on a GPIO
  155. register will return the input bits.
  156. Not sure what happens on reading GPO register.
  157. */
  158. if (rc >= 0) {
  159. if (reg == dev->reg_gpo_num)
  160. dev->reg_gpo = buf[0];
  161. else if (reg == dev->reg_gpio_num)
  162. dev->reg_gpio = buf[0];
  163. }
  164. return rc;
  165. }
  166. /* Write a single register */
  167. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  168. {
  169. return em28xx_write_regs(dev, reg, &val, 1);
  170. }
  171. /*
  172. * em28xx_write_reg_bits()
  173. * sets only some bits (specified by bitmask) of a register, by first reading
  174. * the actual value
  175. */
  176. int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  177. u8 bitmask)
  178. {
  179. int oldval;
  180. u8 newval;
  181. /* Uses cache for gpo/gpio registers */
  182. if (reg == dev->reg_gpo_num)
  183. oldval = dev->reg_gpo;
  184. else if (reg == dev->reg_gpio_num)
  185. oldval = dev->reg_gpio;
  186. else
  187. oldval = em28xx_read_reg(dev, reg);
  188. if (oldval < 0)
  189. return oldval;
  190. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  191. return em28xx_write_regs(dev, reg, &newval, 1);
  192. }
  193. /*
  194. * em28xx_is_ac97_ready()
  195. * Checks if ac97 is ready
  196. */
  197. static int em28xx_is_ac97_ready(struct em28xx *dev)
  198. {
  199. int ret, i;
  200. /* Wait up to 50 ms for AC97 command to complete */
  201. for (i = 0; i < 10; i++, msleep(5)) {
  202. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  203. if (ret < 0)
  204. return ret;
  205. if (!(ret & 0x01))
  206. return 0;
  207. }
  208. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  209. return -EBUSY;
  210. }
  211. /*
  212. * em28xx_read_ac97()
  213. * write a 16 bit value to the specified AC97 address (LSB first!)
  214. */
  215. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  216. {
  217. int ret;
  218. u8 addr = (reg & 0x7f) | 0x80;
  219. u16 val;
  220. ret = em28xx_is_ac97_ready(dev);
  221. if (ret < 0)
  222. return ret;
  223. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  224. if (ret < 0)
  225. return ret;
  226. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  227. (u8 *)&val, sizeof(val));
  228. if (ret < 0)
  229. return ret;
  230. return le16_to_cpu(val);
  231. }
  232. /*
  233. * em28xx_write_ac97()
  234. * write a 16 bit value to the specified AC97 address (LSB first!)
  235. */
  236. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  237. {
  238. int ret;
  239. u8 addr = reg & 0x7f;
  240. __le16 value;
  241. value = cpu_to_le16(val);
  242. ret = em28xx_is_ac97_ready(dev);
  243. if (ret < 0)
  244. return ret;
  245. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  246. if (ret < 0)
  247. return ret;
  248. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  249. if (ret < 0)
  250. return ret;
  251. return 0;
  252. }
  253. struct em28xx_vol_table {
  254. enum em28xx_amux mux;
  255. u8 reg;
  256. };
  257. static struct em28xx_vol_table inputs[] = {
  258. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  259. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  260. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  261. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  262. { EM28XX_AMUX_CD, AC97_CD_VOL },
  263. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  264. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  265. };
  266. static int set_ac97_input(struct em28xx *dev)
  267. {
  268. int ret, i;
  269. enum em28xx_amux amux = dev->ctl_ainput;
  270. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  271. em28xx should point to LINE IN, while AC97 should use VIDEO
  272. */
  273. if (amux == EM28XX_AMUX_VIDEO2)
  274. amux = EM28XX_AMUX_VIDEO;
  275. /* Mute all entres but the one that were selected */
  276. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  277. if (amux == inputs[i].mux)
  278. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  279. else
  280. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  281. if (ret < 0)
  282. em28xx_warn("couldn't setup AC97 register %d\n",
  283. inputs[i].reg);
  284. }
  285. return 0;
  286. }
  287. static int em28xx_set_audio_source(struct em28xx *dev)
  288. {
  289. int ret;
  290. u8 input;
  291. if (dev->board.is_em2800) {
  292. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  293. input = EM2800_AUDIO_SRC_TUNER;
  294. else
  295. input = EM2800_AUDIO_SRC_LINE;
  296. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  297. if (ret < 0)
  298. return ret;
  299. }
  300. if (dev->board.has_msp34xx)
  301. input = EM28XX_AUDIO_SRC_TUNER;
  302. else {
  303. switch (dev->ctl_ainput) {
  304. case EM28XX_AMUX_VIDEO:
  305. input = EM28XX_AUDIO_SRC_TUNER;
  306. break;
  307. default:
  308. input = EM28XX_AUDIO_SRC_LINE;
  309. break;
  310. }
  311. }
  312. if (dev->board.mute_gpio && dev->mute)
  313. em28xx_gpio_set(dev, dev->board.mute_gpio);
  314. else
  315. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  316. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  317. if (ret < 0)
  318. return ret;
  319. msleep(5);
  320. switch (dev->audio_mode.ac97) {
  321. case EM28XX_NO_AC97:
  322. break;
  323. default:
  324. ret = set_ac97_input(dev);
  325. }
  326. return ret;
  327. }
  328. static const struct em28xx_vol_table outputs[] = {
  329. { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
  330. { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
  331. { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
  332. { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
  333. { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
  334. };
  335. int em28xx_audio_analog_set(struct em28xx *dev)
  336. {
  337. int ret, i;
  338. u8 xclk;
  339. if (!dev->audio_mode.has_audio)
  340. return 0;
  341. /* It is assumed that all devices use master volume for output.
  342. It would be possible to use also line output.
  343. */
  344. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  345. /* Mute all outputs */
  346. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  347. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  348. if (ret < 0)
  349. em28xx_warn("couldn't setup AC97 register %d\n",
  350. outputs[i].reg);
  351. }
  352. }
  353. xclk = dev->board.xclk & 0x7f;
  354. if (!dev->mute)
  355. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  356. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  357. if (ret < 0)
  358. return ret;
  359. msleep(10);
  360. /* Selects the proper audio input */
  361. ret = em28xx_set_audio_source(dev);
  362. /* Sets volume */
  363. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  364. int vol;
  365. em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
  366. em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
  367. em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
  368. /* LSB: left channel - both channels with the same level */
  369. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  370. /* Mute device, if needed */
  371. if (dev->mute)
  372. vol |= 0x8000;
  373. /* Sets volume */
  374. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  375. if (dev->ctl_aoutput & outputs[i].mux)
  376. ret = em28xx_write_ac97(dev, outputs[i].reg,
  377. vol);
  378. if (ret < 0)
  379. em28xx_warn("couldn't setup AC97 register %d\n",
  380. outputs[i].reg);
  381. }
  382. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  383. int sel = ac97_return_record_select(dev->ctl_aoutput);
  384. /* Use the same input for both left and right
  385. channels */
  386. sel |= (sel << 8);
  387. em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
  388. }
  389. }
  390. return ret;
  391. }
  392. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  393. int em28xx_audio_setup(struct em28xx *dev)
  394. {
  395. int vid1, vid2, feat, cfg;
  396. u32 vid;
  397. if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
  398. /* Digital only device - don't load any alsa module */
  399. dev->audio_mode.has_audio = 0;
  400. dev->has_audio_class = 0;
  401. dev->has_alsa_audio = 0;
  402. return 0;
  403. }
  404. /* If device doesn't support Usb Audio Class, use vendor class */
  405. if (!dev->has_audio_class)
  406. dev->has_alsa_audio = 1;
  407. dev->audio_mode.has_audio = 1;
  408. /* See how this device is configured */
  409. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  410. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  411. if (cfg < 0) {
  412. /* Register read error? */
  413. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  414. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  415. /* The device doesn't have vendor audio at all */
  416. dev->has_alsa_audio = 0;
  417. dev->audio_mode.has_audio = 0;
  418. return 0;
  419. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  420. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  421. em28xx_info("I2S Audio (3 sample rates)\n");
  422. dev->audio_mode.i2s_3rates = 1;
  423. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  424. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  425. em28xx_info("I2S Audio (5 sample rates)\n");
  426. dev->audio_mode.i2s_5rates = 1;
  427. }
  428. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  429. /* Skip the code that does AC97 vendor detection */
  430. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  431. goto init_audio;
  432. }
  433. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  434. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  435. if (vid1 < 0) {
  436. /*
  437. * Device likely doesn't support AC97
  438. * Note: (some) em2800 devices without eeprom reports 0x91 on
  439. * CHIPCFG register, even not having an AC97 chip
  440. */
  441. em28xx_warn("AC97 chip type couldn't be determined\n");
  442. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  443. dev->has_alsa_audio = 0;
  444. dev->audio_mode.has_audio = 0;
  445. goto init_audio;
  446. }
  447. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  448. if (vid2 < 0)
  449. goto init_audio;
  450. vid = vid1 << 16 | vid2;
  451. dev->audio_mode.ac97_vendor_id = vid;
  452. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  453. feat = em28xx_read_ac97(dev, AC97_RESET);
  454. if (feat < 0)
  455. goto init_audio;
  456. dev->audio_mode.ac97_feat = feat;
  457. em28xx_warn("AC97 features = 0x%04x\n", feat);
  458. /* Try to identify what audio processor we have */
  459. if ((vid == 0xffffffff) && (feat == 0x6a90))
  460. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  461. else if ((vid >> 8) == 0x838476)
  462. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  463. init_audio:
  464. /* Reports detected AC97 processor */
  465. switch (dev->audio_mode.ac97) {
  466. case EM28XX_NO_AC97:
  467. em28xx_info("No AC97 audio processor\n");
  468. break;
  469. case EM28XX_AC97_EM202:
  470. em28xx_info("Empia 202 AC97 audio processor detected\n");
  471. break;
  472. case EM28XX_AC97_SIGMATEL:
  473. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  474. dev->audio_mode.ac97_vendor_id & 0xff);
  475. break;
  476. case EM28XX_AC97_OTHER:
  477. em28xx_warn("Unknown AC97 audio processor detected!\n");
  478. break;
  479. default:
  480. break;
  481. }
  482. return em28xx_audio_analog_set(dev);
  483. }
  484. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  485. int em28xx_colorlevels_set_default(struct em28xx *dev)
  486. {
  487. em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
  488. em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
  489. em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
  490. em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
  491. em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
  492. em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
  493. em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
  494. em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
  495. em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
  496. em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
  497. em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
  498. em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
  499. return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
  500. }
  501. int em28xx_capture_start(struct em28xx *dev, int start)
  502. {
  503. int rc;
  504. if (dev->chip_id == CHIP_ID_EM2874) {
  505. /* The Transport Stream Enable Register moved in em2874 */
  506. if (!start) {
  507. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  508. 0x00,
  509. EM2874_TS1_CAPTURE_ENABLE);
  510. return rc;
  511. }
  512. /* Enable Transport Stream */
  513. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  514. EM2874_TS1_CAPTURE_ENABLE,
  515. EM2874_TS1_CAPTURE_ENABLE);
  516. return rc;
  517. }
  518. /* FIXME: which is the best order? */
  519. /* video registers are sampled by VREF */
  520. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  521. start ? 0x10 : 0x00, 0x10);
  522. if (rc < 0)
  523. return rc;
  524. if (!start) {
  525. /* disable video capture */
  526. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  527. return rc;
  528. }
  529. if (dev->board.is_webcam)
  530. rc = em28xx_write_reg(dev, 0x13, 0x0c);
  531. /* enable video capture */
  532. rc = em28xx_write_reg(dev, 0x48, 0x00);
  533. if (dev->mode == EM28XX_ANALOG_MODE)
  534. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  535. else
  536. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  537. msleep(6);
  538. return rc;
  539. }
  540. int em28xx_vbi_supported(struct em28xx *dev)
  541. {
  542. /* Modprobe option to manually disable */
  543. if (disable_vbi == 1)
  544. return 0;
  545. if (dev->chip_id == CHIP_ID_EM2860 ||
  546. dev->chip_id == CHIP_ID_EM2883)
  547. return 1;
  548. /* Version of em28xx that does not support VBI */
  549. return 0;
  550. }
  551. int em28xx_set_outfmt(struct em28xx *dev)
  552. {
  553. int ret;
  554. u8 vinctrl;
  555. ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
  556. dev->format->reg | 0x20, 0xff);
  557. if (ret < 0)
  558. return ret;
  559. ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
  560. if (ret < 0)
  561. return ret;
  562. vinctrl = dev->vinctl;
  563. if (em28xx_vbi_supported(dev) == 1) {
  564. vinctrl |= EM28XX_VINCTRL_VBI_RAW;
  565. em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
  566. em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
  567. em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
  568. if (dev->norm & V4L2_STD_525_60) {
  569. /* NTSC */
  570. em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
  571. } else if (dev->norm & V4L2_STD_625_50) {
  572. /* PAL */
  573. em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
  574. }
  575. }
  576. return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
  577. }
  578. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  579. u8 ymin, u8 ymax)
  580. {
  581. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  582. xmin, ymin, xmax, ymax);
  583. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  584. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  585. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  586. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  587. }
  588. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  589. u16 width, u16 height)
  590. {
  591. u8 cwidth = width;
  592. u8 cheight = height;
  593. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  594. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  595. (width | (overflow & 2) << 7),
  596. (height | (overflow & 1) << 8));
  597. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  598. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  599. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  600. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  601. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  602. }
  603. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  604. {
  605. u8 mode;
  606. /* the em2800 scaler only supports scaling down to 50% */
  607. if (dev->board.is_em2800) {
  608. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  609. } else {
  610. u8 buf[2];
  611. buf[0] = h;
  612. buf[1] = h >> 8;
  613. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  614. buf[0] = v;
  615. buf[1] = v >> 8;
  616. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  617. /* it seems that both H and V scalers must be active
  618. to work correctly */
  619. mode = (h || v) ? 0x30 : 0x00;
  620. }
  621. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  622. }
  623. /* FIXME: this only function read values from dev */
  624. int em28xx_resolution_set(struct em28xx *dev)
  625. {
  626. int width, height;
  627. width = norm_maxw(dev);
  628. height = norm_maxh(dev);
  629. /* Properly setup VBI */
  630. dev->vbi_width = 720;
  631. if (dev->norm & V4L2_STD_525_60)
  632. dev->vbi_height = 12;
  633. else
  634. dev->vbi_height = 18;
  635. if (!dev->progressive)
  636. height >>= norm_maxh(dev);
  637. em28xx_set_outfmt(dev);
  638. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  639. /* If we don't set the start position to 4 in VBI mode, we end up
  640. with line 21 being YUYV encoded instead of being in 8-bit
  641. greyscale */
  642. if (em28xx_vbi_supported(dev) == 1)
  643. em28xx_capture_area_set(dev, 0, 4, width >> 2, height >> 2);
  644. else
  645. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  646. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  647. }
  648. int em28xx_set_alternate(struct em28xx *dev)
  649. {
  650. int errCode, prev_alt = dev->alt;
  651. int i;
  652. unsigned int min_pkt_size = dev->width * 2 + 4;
  653. /*
  654. * alt = 0 is used only for control messages, so, only values
  655. * greater than 0 can be used for streaming.
  656. */
  657. if (alt && alt < dev->num_alt) {
  658. em28xx_coredbg("alternate forced to %d\n", dev->alt);
  659. dev->alt = alt;
  660. goto set_alt;
  661. }
  662. /* When image size is bigger than a certain value,
  663. the frame size should be increased, otherwise, only
  664. green screen will be received.
  665. */
  666. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  667. min_pkt_size *= 2;
  668. for (i = 0; i < dev->num_alt; i++) {
  669. /* stop when the selected alt setting offers enough bandwidth */
  670. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  671. dev->alt = i;
  672. break;
  673. /* otherwise make sure that we end up with the maximum bandwidth
  674. because the min_pkt_size equation might be wrong...
  675. */
  676. } else if (dev->alt_max_pkt_size[i] >
  677. dev->alt_max_pkt_size[dev->alt])
  678. dev->alt = i;
  679. }
  680. set_alt:
  681. if (dev->alt != prev_alt) {
  682. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  683. min_pkt_size, dev->alt);
  684. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  685. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  686. dev->alt, dev->max_pkt_size);
  687. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  688. if (errCode < 0) {
  689. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  690. dev->alt, errCode);
  691. return errCode;
  692. }
  693. }
  694. return 0;
  695. }
  696. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  697. {
  698. int rc = 0;
  699. if (!gpio)
  700. return rc;
  701. if (dev->mode != EM28XX_SUSPEND) {
  702. em28xx_write_reg(dev, 0x48, 0x00);
  703. if (dev->mode == EM28XX_ANALOG_MODE)
  704. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  705. else
  706. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  707. msleep(6);
  708. }
  709. /* Send GPIO reset sequences specified at board entry */
  710. while (gpio->sleep >= 0) {
  711. if (gpio->reg >= 0) {
  712. rc = em28xx_write_reg_bits(dev,
  713. gpio->reg,
  714. gpio->val,
  715. gpio->mask);
  716. if (rc < 0)
  717. return rc;
  718. }
  719. if (gpio->sleep > 0)
  720. msleep(gpio->sleep);
  721. gpio++;
  722. }
  723. return rc;
  724. }
  725. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  726. {
  727. if (dev->mode == set_mode)
  728. return 0;
  729. if (set_mode == EM28XX_SUSPEND) {
  730. dev->mode = set_mode;
  731. /* FIXME: add suspend support for ac97 */
  732. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  733. }
  734. dev->mode = set_mode;
  735. if (dev->mode == EM28XX_DIGITAL_MODE)
  736. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  737. else
  738. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  739. }
  740. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  741. /* ------------------------------------------------------------------
  742. URB control
  743. ------------------------------------------------------------------*/
  744. /*
  745. * IRQ callback, called by URB callback
  746. */
  747. static void em28xx_irq_callback(struct urb *urb)
  748. {
  749. struct em28xx *dev = urb->context;
  750. int rc, i;
  751. switch (urb->status) {
  752. case 0: /* success */
  753. case -ETIMEDOUT: /* NAK */
  754. break;
  755. case -ECONNRESET: /* kill */
  756. case -ENOENT:
  757. case -ESHUTDOWN:
  758. return;
  759. default: /* error */
  760. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  761. break;
  762. }
  763. /* Copy data from URB */
  764. spin_lock(&dev->slock);
  765. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  766. spin_unlock(&dev->slock);
  767. /* Reset urb buffers */
  768. for (i = 0; i < urb->number_of_packets; i++) {
  769. urb->iso_frame_desc[i].status = 0;
  770. urb->iso_frame_desc[i].actual_length = 0;
  771. }
  772. urb->status = 0;
  773. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  774. if (urb->status) {
  775. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  776. urb->status);
  777. }
  778. }
  779. /*
  780. * Stop and Deallocate URBs
  781. */
  782. void em28xx_uninit_isoc(struct em28xx *dev)
  783. {
  784. struct urb *urb;
  785. int i;
  786. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  787. dev->isoc_ctl.nfields = -1;
  788. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  789. urb = dev->isoc_ctl.urb[i];
  790. if (urb) {
  791. if (!irqs_disabled())
  792. usb_kill_urb(urb);
  793. else
  794. usb_unlink_urb(urb);
  795. if (dev->isoc_ctl.transfer_buffer[i]) {
  796. usb_buffer_free(dev->udev,
  797. urb->transfer_buffer_length,
  798. dev->isoc_ctl.transfer_buffer[i],
  799. urb->transfer_dma);
  800. }
  801. usb_free_urb(urb);
  802. dev->isoc_ctl.urb[i] = NULL;
  803. }
  804. dev->isoc_ctl.transfer_buffer[i] = NULL;
  805. }
  806. kfree(dev->isoc_ctl.urb);
  807. kfree(dev->isoc_ctl.transfer_buffer);
  808. dev->isoc_ctl.urb = NULL;
  809. dev->isoc_ctl.transfer_buffer = NULL;
  810. dev->isoc_ctl.num_bufs = 0;
  811. em28xx_capture_start(dev, 0);
  812. }
  813. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  814. /*
  815. * Allocate URBs and start IRQ
  816. */
  817. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  818. int num_bufs, int max_pkt_size,
  819. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  820. {
  821. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  822. struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
  823. int i;
  824. int sb_size, pipe;
  825. struct urb *urb;
  826. int j, k;
  827. int rc;
  828. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  829. /* De-allocates all pending stuff */
  830. em28xx_uninit_isoc(dev);
  831. dev->isoc_ctl.isoc_copy = isoc_copy;
  832. dev->isoc_ctl.num_bufs = num_bufs;
  833. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  834. if (!dev->isoc_ctl.urb) {
  835. em28xx_errdev("cannot alloc memory for usb buffers\n");
  836. return -ENOMEM;
  837. }
  838. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  839. GFP_KERNEL);
  840. if (!dev->isoc_ctl.transfer_buffer) {
  841. em28xx_errdev("cannot allocate memory for usb transfer\n");
  842. kfree(dev->isoc_ctl.urb);
  843. return -ENOMEM;
  844. }
  845. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  846. dev->isoc_ctl.vid_buf = NULL;
  847. dev->isoc_ctl.vbi_buf = NULL;
  848. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  849. /* allocate urbs and transfer buffers */
  850. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  851. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  852. if (!urb) {
  853. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  854. em28xx_uninit_isoc(dev);
  855. return -ENOMEM;
  856. }
  857. dev->isoc_ctl.urb[i] = urb;
  858. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  859. sb_size, GFP_KERNEL, &urb->transfer_dma);
  860. if (!dev->isoc_ctl.transfer_buffer[i]) {
  861. em28xx_err("unable to allocate %i bytes for transfer"
  862. " buffer %i%s\n",
  863. sb_size, i,
  864. in_interrupt() ? " while in int" : "");
  865. em28xx_uninit_isoc(dev);
  866. return -ENOMEM;
  867. }
  868. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  869. /* FIXME: this is a hack - should be
  870. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  871. should also be using 'desc.bInterval'
  872. */
  873. pipe = usb_rcvisocpipe(dev->udev,
  874. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  875. usb_fill_int_urb(urb, dev->udev, pipe,
  876. dev->isoc_ctl.transfer_buffer[i], sb_size,
  877. em28xx_irq_callback, dev, 1);
  878. urb->number_of_packets = max_packets;
  879. urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
  880. k = 0;
  881. for (j = 0; j < max_packets; j++) {
  882. urb->iso_frame_desc[j].offset = k;
  883. urb->iso_frame_desc[j].length =
  884. dev->isoc_ctl.max_pkt_size;
  885. k += dev->isoc_ctl.max_pkt_size;
  886. }
  887. }
  888. init_waitqueue_head(&dma_q->wq);
  889. init_waitqueue_head(&vbi_dma_q->wq);
  890. em28xx_capture_start(dev, 1);
  891. /* submit urbs and enables IRQ */
  892. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  893. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  894. if (rc) {
  895. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  896. rc);
  897. em28xx_uninit_isoc(dev);
  898. return rc;
  899. }
  900. }
  901. return 0;
  902. }
  903. EXPORT_SYMBOL_GPL(em28xx_init_isoc);
  904. /* Determine the packet size for the DVB stream for the given device
  905. (underlying value programmed into the eeprom) */
  906. int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
  907. {
  908. unsigned int chip_cfg2;
  909. unsigned int packet_size = 564;
  910. if (dev->chip_id == CHIP_ID_EM2874) {
  911. /* FIXME - for now assume 564 like it was before, but the
  912. em2874 code should be added to return the proper value... */
  913. packet_size = 564;
  914. } else {
  915. /* TS max packet size stored in bits 1-0 of R01 */
  916. chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
  917. switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
  918. case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
  919. packet_size = 188;
  920. break;
  921. case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
  922. packet_size = 376;
  923. break;
  924. case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
  925. packet_size = 564;
  926. break;
  927. case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
  928. packet_size = 752;
  929. break;
  930. }
  931. }
  932. em28xx_coredbg("dvb max packet size=%d\n", packet_size);
  933. return packet_size;
  934. }
  935. EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
  936. /*
  937. * em28xx_wake_i2c()
  938. * configure i2c attached devices
  939. */
  940. void em28xx_wake_i2c(struct em28xx *dev)
  941. {
  942. v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
  943. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
  944. INPUT(dev->ctl_input)->vmux, 0, 0);
  945. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
  946. }
  947. /*
  948. * Device control list
  949. */
  950. static LIST_HEAD(em28xx_devlist);
  951. static DEFINE_MUTEX(em28xx_devlist_mutex);
  952. /*
  953. * em28xx_realease_resources()
  954. * unregisters the v4l2,i2c and usb devices
  955. * called when the device gets disconected or at module unload
  956. */
  957. void em28xx_remove_from_devlist(struct em28xx *dev)
  958. {
  959. mutex_lock(&em28xx_devlist_mutex);
  960. list_del(&dev->devlist);
  961. mutex_unlock(&em28xx_devlist_mutex);
  962. };
  963. void em28xx_add_into_devlist(struct em28xx *dev)
  964. {
  965. mutex_lock(&em28xx_devlist_mutex);
  966. list_add_tail(&dev->devlist, &em28xx_devlist);
  967. mutex_unlock(&em28xx_devlist_mutex);
  968. };
  969. /*
  970. * Extension interface
  971. */
  972. static LIST_HEAD(em28xx_extension_devlist);
  973. static DEFINE_MUTEX(em28xx_extension_devlist_lock);
  974. int em28xx_register_extension(struct em28xx_ops *ops)
  975. {
  976. struct em28xx *dev = NULL;
  977. mutex_lock(&em28xx_devlist_mutex);
  978. mutex_lock(&em28xx_extension_devlist_lock);
  979. list_add_tail(&ops->next, &em28xx_extension_devlist);
  980. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  981. if (dev)
  982. ops->init(dev);
  983. }
  984. printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
  985. mutex_unlock(&em28xx_extension_devlist_lock);
  986. mutex_unlock(&em28xx_devlist_mutex);
  987. return 0;
  988. }
  989. EXPORT_SYMBOL(em28xx_register_extension);
  990. void em28xx_unregister_extension(struct em28xx_ops *ops)
  991. {
  992. struct em28xx *dev = NULL;
  993. mutex_lock(&em28xx_devlist_mutex);
  994. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  995. if (dev)
  996. ops->fini(dev);
  997. }
  998. mutex_lock(&em28xx_extension_devlist_lock);
  999. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  1000. list_del(&ops->next);
  1001. mutex_unlock(&em28xx_extension_devlist_lock);
  1002. mutex_unlock(&em28xx_devlist_mutex);
  1003. }
  1004. EXPORT_SYMBOL(em28xx_unregister_extension);
  1005. void em28xx_init_extension(struct em28xx *dev)
  1006. {
  1007. struct em28xx_ops *ops = NULL;
  1008. mutex_lock(&em28xx_extension_devlist_lock);
  1009. if (!list_empty(&em28xx_extension_devlist)) {
  1010. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1011. if (ops->init)
  1012. ops->init(dev);
  1013. }
  1014. }
  1015. mutex_unlock(&em28xx_extension_devlist_lock);
  1016. }
  1017. void em28xx_close_extension(struct em28xx *dev)
  1018. {
  1019. struct em28xx_ops *ops = NULL;
  1020. mutex_lock(&em28xx_extension_devlist_lock);
  1021. if (!list_empty(&em28xx_extension_devlist)) {
  1022. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1023. if (ops->fini)
  1024. ops->fini(dev);
  1025. }
  1026. }
  1027. mutex_unlock(&em28xx_extension_devlist_lock);
  1028. }