stv090x.c 124 KB

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  1. /*
  2. STV0900/0903 Multistandard Broadcast Frontend driver
  3. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  4. Copyright (C) ST Microelectronics
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/string.h>
  21. #include <linux/mutex.h>
  22. #include <linux/dvb/frontend.h>
  23. #include "dvb_frontend.h"
  24. #include "stv6110x.h" /* for demodulator internal modes */
  25. #include "stv090x_reg.h"
  26. #include "stv090x.h"
  27. #include "stv090x_priv.h"
  28. static unsigned int verbose;
  29. module_param(verbose, int, 0644);
  30. /* internal params node */
  31. struct stv090x_dev {
  32. /* pointer for internal params, one for each pair of demods */
  33. struct stv090x_internal *internal;
  34. struct stv090x_dev *next_dev;
  35. };
  36. /* first internal params */
  37. static struct stv090x_dev *stv090x_first_dev;
  38. /* find chip by i2c adapter and i2c address */
  39. static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
  40. u8 i2c_addr)
  41. {
  42. struct stv090x_dev *temp_dev = stv090x_first_dev;
  43. /*
  44. Search of the last stv0900 chip or
  45. find it by i2c adapter and i2c address */
  46. while ((temp_dev != NULL) &&
  47. ((temp_dev->internal->i2c_adap != i2c_adap) ||
  48. (temp_dev->internal->i2c_addr != i2c_addr))) {
  49. temp_dev = temp_dev->next_dev;
  50. }
  51. return temp_dev;
  52. }
  53. /* deallocating chip */
  54. static void remove_dev(struct stv090x_internal *internal)
  55. {
  56. struct stv090x_dev *prev_dev = stv090x_first_dev;
  57. struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
  58. internal->i2c_addr);
  59. if (del_dev != NULL) {
  60. if (del_dev == stv090x_first_dev) {
  61. stv090x_first_dev = del_dev->next_dev;
  62. } else {
  63. while (prev_dev->next_dev != del_dev)
  64. prev_dev = prev_dev->next_dev;
  65. prev_dev->next_dev = del_dev->next_dev;
  66. }
  67. kfree(del_dev);
  68. }
  69. }
  70. /* allocating new chip */
  71. static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
  72. {
  73. struct stv090x_dev *new_dev;
  74. struct stv090x_dev *temp_dev;
  75. new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
  76. if (new_dev != NULL) {
  77. new_dev->internal = internal;
  78. new_dev->next_dev = NULL;
  79. /* append to list */
  80. if (stv090x_first_dev == NULL) {
  81. stv090x_first_dev = new_dev;
  82. } else {
  83. temp_dev = stv090x_first_dev;
  84. while (temp_dev->next_dev != NULL)
  85. temp_dev = temp_dev->next_dev;
  86. temp_dev->next_dev = new_dev;
  87. }
  88. }
  89. return new_dev;
  90. }
  91. /* DVBS1 and DSS C/N Lookup table */
  92. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  93. { 0, 8917 }, /* 0.0dB */
  94. { 5, 8801 }, /* 0.5dB */
  95. { 10, 8667 }, /* 1.0dB */
  96. { 15, 8522 }, /* 1.5dB */
  97. { 20, 8355 }, /* 2.0dB */
  98. { 25, 8175 }, /* 2.5dB */
  99. { 30, 7979 }, /* 3.0dB */
  100. { 35, 7763 }, /* 3.5dB */
  101. { 40, 7530 }, /* 4.0dB */
  102. { 45, 7282 }, /* 4.5dB */
  103. { 50, 7026 }, /* 5.0dB */
  104. { 55, 6781 }, /* 5.5dB */
  105. { 60, 6514 }, /* 6.0dB */
  106. { 65, 6241 }, /* 6.5dB */
  107. { 70, 5965 }, /* 7.0dB */
  108. { 75, 5690 }, /* 7.5dB */
  109. { 80, 5424 }, /* 8.0dB */
  110. { 85, 5161 }, /* 8.5dB */
  111. { 90, 4902 }, /* 9.0dB */
  112. { 95, 4654 }, /* 9.5dB */
  113. { 100, 4417 }, /* 10.0dB */
  114. { 105, 4186 }, /* 10.5dB */
  115. { 110, 3968 }, /* 11.0dB */
  116. { 115, 3757 }, /* 11.5dB */
  117. { 120, 3558 }, /* 12.0dB */
  118. { 125, 3366 }, /* 12.5dB */
  119. { 130, 3185 }, /* 13.0dB */
  120. { 135, 3012 }, /* 13.5dB */
  121. { 140, 2850 }, /* 14.0dB */
  122. { 145, 2698 }, /* 14.5dB */
  123. { 150, 2550 }, /* 15.0dB */
  124. { 160, 2283 }, /* 16.0dB */
  125. { 170, 2042 }, /* 17.0dB */
  126. { 180, 1827 }, /* 18.0dB */
  127. { 190, 1636 }, /* 19.0dB */
  128. { 200, 1466 }, /* 20.0dB */
  129. { 210, 1315 }, /* 21.0dB */
  130. { 220, 1181 }, /* 22.0dB */
  131. { 230, 1064 }, /* 23.0dB */
  132. { 240, 960 }, /* 24.0dB */
  133. { 250, 869 }, /* 25.0dB */
  134. { 260, 792 }, /* 26.0dB */
  135. { 270, 724 }, /* 27.0dB */
  136. { 280, 665 }, /* 28.0dB */
  137. { 290, 616 }, /* 29.0dB */
  138. { 300, 573 }, /* 30.0dB */
  139. { 310, 537 }, /* 31.0dB */
  140. { 320, 507 }, /* 32.0dB */
  141. { 330, 483 }, /* 33.0dB */
  142. { 400, 398 }, /* 40.0dB */
  143. { 450, 381 }, /* 45.0dB */
  144. { 500, 377 } /* 50.0dB */
  145. };
  146. /* DVBS2 C/N Lookup table */
  147. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  148. { -30, 13348 }, /* -3.0dB */
  149. { -20, 12640 }, /* -2d.0B */
  150. { -10, 11883 }, /* -1.0dB */
  151. { 0, 11101 }, /* -0.0dB */
  152. { 5, 10718 }, /* 0.5dB */
  153. { 10, 10339 }, /* 1.0dB */
  154. { 15, 9947 }, /* 1.5dB */
  155. { 20, 9552 }, /* 2.0dB */
  156. { 25, 9183 }, /* 2.5dB */
  157. { 30, 8799 }, /* 3.0dB */
  158. { 35, 8422 }, /* 3.5dB */
  159. { 40, 8062 }, /* 4.0dB */
  160. { 45, 7707 }, /* 4.5dB */
  161. { 50, 7353 }, /* 5.0dB */
  162. { 55, 7025 }, /* 5.5dB */
  163. { 60, 6684 }, /* 6.0dB */
  164. { 65, 6331 }, /* 6.5dB */
  165. { 70, 6036 }, /* 7.0dB */
  166. { 75, 5727 }, /* 7.5dB */
  167. { 80, 5437 }, /* 8.0dB */
  168. { 85, 5164 }, /* 8.5dB */
  169. { 90, 4902 }, /* 9.0dB */
  170. { 95, 4653 }, /* 9.5dB */
  171. { 100, 4408 }, /* 10.0dB */
  172. { 105, 4187 }, /* 10.5dB */
  173. { 110, 3961 }, /* 11.0dB */
  174. { 115, 3751 }, /* 11.5dB */
  175. { 120, 3558 }, /* 12.0dB */
  176. { 125, 3368 }, /* 12.5dB */
  177. { 130, 3191 }, /* 13.0dB */
  178. { 135, 3017 }, /* 13.5dB */
  179. { 140, 2862 }, /* 14.0dB */
  180. { 145, 2710 }, /* 14.5dB */
  181. { 150, 2565 }, /* 15.0dB */
  182. { 160, 2300 }, /* 16.0dB */
  183. { 170, 2058 }, /* 17.0dB */
  184. { 180, 1849 }, /* 18.0dB */
  185. { 190, 1663 }, /* 19.0dB */
  186. { 200, 1495 }, /* 20.0dB */
  187. { 210, 1349 }, /* 21.0dB */
  188. { 220, 1222 }, /* 22.0dB */
  189. { 230, 1110 }, /* 23.0dB */
  190. { 240, 1011 }, /* 24.0dB */
  191. { 250, 925 }, /* 25.0dB */
  192. { 260, 853 }, /* 26.0dB */
  193. { 270, 789 }, /* 27.0dB */
  194. { 280, 734 }, /* 28.0dB */
  195. { 290, 690 }, /* 29.0dB */
  196. { 300, 650 }, /* 30.0dB */
  197. { 310, 619 }, /* 31.0dB */
  198. { 320, 593 }, /* 32.0dB */
  199. { 330, 571 }, /* 33.0dB */
  200. { 400, 498 }, /* 40.0dB */
  201. { 450, 484 }, /* 45.0dB */
  202. { 500, 481 } /* 50.0dB */
  203. };
  204. /* RF level C/N lookup table */
  205. static const struct stv090x_tab stv090x_rf_tab[] = {
  206. { -5, 0xcaa1 }, /* -5dBm */
  207. { -10, 0xc229 }, /* -10dBm */
  208. { -15, 0xbb08 }, /* -15dBm */
  209. { -20, 0xb4bc }, /* -20dBm */
  210. { -25, 0xad5a }, /* -25dBm */
  211. { -30, 0xa298 }, /* -30dBm */
  212. { -35, 0x98a8 }, /* -35dBm */
  213. { -40, 0x8389 }, /* -40dBm */
  214. { -45, 0x59be }, /* -45dBm */
  215. { -50, 0x3a14 }, /* -50dBm */
  216. { -55, 0x2d11 }, /* -55dBm */
  217. { -60, 0x210d }, /* -60dBm */
  218. { -65, 0xa14f }, /* -65dBm */
  219. { -70, 0x07aa } /* -70dBm */
  220. };
  221. static struct stv090x_reg stv0900_initval[] = {
  222. { STV090x_OUTCFG, 0x00 },
  223. { STV090x_MODECFG, 0xff },
  224. { STV090x_AGCRF1CFG, 0x11 },
  225. { STV090x_AGCRF2CFG, 0x13 },
  226. { STV090x_TSGENERAL1X, 0x14 },
  227. { STV090x_TSTTNR2, 0x21 },
  228. { STV090x_TSTTNR4, 0x21 },
  229. { STV090x_P2_DISTXCTL, 0x22 },
  230. { STV090x_P2_F22TX, 0xc0 },
  231. { STV090x_P2_F22RX, 0xc0 },
  232. { STV090x_P2_DISRXCTL, 0x00 },
  233. { STV090x_P2_DMDCFGMD, 0xF9 },
  234. { STV090x_P2_DEMOD, 0x08 },
  235. { STV090x_P2_DMDCFG3, 0xc4 },
  236. { STV090x_P2_CARFREQ, 0xed },
  237. { STV090x_P2_LDT, 0xd0 },
  238. { STV090x_P2_LDT2, 0xb8 },
  239. { STV090x_P2_TMGCFG, 0xd2 },
  240. { STV090x_P2_TMGTHRISE, 0x20 },
  241. { STV090x_P1_TMGCFG, 0xd2 },
  242. { STV090x_P2_TMGTHFALL, 0x00 },
  243. { STV090x_P2_FECSPY, 0x88 },
  244. { STV090x_P2_FSPYDATA, 0x3a },
  245. { STV090x_P2_FBERCPT4, 0x00 },
  246. { STV090x_P2_FSPYBER, 0x10 },
  247. { STV090x_P2_ERRCTRL1, 0x35 },
  248. { STV090x_P2_ERRCTRL2, 0xc1 },
  249. { STV090x_P2_CFRICFG, 0xf8 },
  250. { STV090x_P2_NOSCFG, 0x1c },
  251. { STV090x_P2_DMDTOM, 0x20 },
  252. { STV090x_P2_CORRELMANT, 0x70 },
  253. { STV090x_P2_CORRELABS, 0x88 },
  254. { STV090x_P2_AGC2O, 0x5b },
  255. { STV090x_P2_AGC2REF, 0x38 },
  256. { STV090x_P2_CARCFG, 0xe4 },
  257. { STV090x_P2_ACLC, 0x1A },
  258. { STV090x_P2_BCLC, 0x09 },
  259. { STV090x_P2_CARHDR, 0x08 },
  260. { STV090x_P2_KREFTMG, 0xc1 },
  261. { STV090x_P2_SFRUPRATIO, 0xf0 },
  262. { STV090x_P2_SFRLOWRATIO, 0x70 },
  263. { STV090x_P2_SFRSTEP, 0x58 },
  264. { STV090x_P2_TMGCFG2, 0x01 },
  265. { STV090x_P2_CAR2CFG, 0x26 },
  266. { STV090x_P2_BCLC2S2Q, 0x86 },
  267. { STV090x_P2_BCLC2S28, 0x86 },
  268. { STV090x_P2_SMAPCOEF7, 0x77 },
  269. { STV090x_P2_SMAPCOEF6, 0x85 },
  270. { STV090x_P2_SMAPCOEF5, 0x77 },
  271. { STV090x_P2_TSCFGL, 0x20 },
  272. { STV090x_P2_DMDCFG2, 0x3b },
  273. { STV090x_P2_MODCODLST0, 0xff },
  274. { STV090x_P2_MODCODLST1, 0xff },
  275. { STV090x_P2_MODCODLST2, 0xff },
  276. { STV090x_P2_MODCODLST3, 0xff },
  277. { STV090x_P2_MODCODLST4, 0xff },
  278. { STV090x_P2_MODCODLST5, 0xff },
  279. { STV090x_P2_MODCODLST6, 0xff },
  280. { STV090x_P2_MODCODLST7, 0xcc },
  281. { STV090x_P2_MODCODLST8, 0xcc },
  282. { STV090x_P2_MODCODLST9, 0xcc },
  283. { STV090x_P2_MODCODLSTA, 0xcc },
  284. { STV090x_P2_MODCODLSTB, 0xcc },
  285. { STV090x_P2_MODCODLSTC, 0xcc },
  286. { STV090x_P2_MODCODLSTD, 0xcc },
  287. { STV090x_P2_MODCODLSTE, 0xcc },
  288. { STV090x_P2_MODCODLSTF, 0xcf },
  289. { STV090x_P1_DISTXCTL, 0x22 },
  290. { STV090x_P1_F22TX, 0xc0 },
  291. { STV090x_P1_F22RX, 0xc0 },
  292. { STV090x_P1_DISRXCTL, 0x00 },
  293. { STV090x_P1_DMDCFGMD, 0xf9 },
  294. { STV090x_P1_DEMOD, 0x08 },
  295. { STV090x_P1_DMDCFG3, 0xc4 },
  296. { STV090x_P1_DMDTOM, 0x20 },
  297. { STV090x_P1_CARFREQ, 0xed },
  298. { STV090x_P1_LDT, 0xd0 },
  299. { STV090x_P1_LDT2, 0xb8 },
  300. { STV090x_P1_TMGCFG, 0xd2 },
  301. { STV090x_P1_TMGTHRISE, 0x20 },
  302. { STV090x_P1_TMGTHFALL, 0x00 },
  303. { STV090x_P1_SFRUPRATIO, 0xf0 },
  304. { STV090x_P1_SFRLOWRATIO, 0x70 },
  305. { STV090x_P1_TSCFGL, 0x20 },
  306. { STV090x_P1_FECSPY, 0x88 },
  307. { STV090x_P1_FSPYDATA, 0x3a },
  308. { STV090x_P1_FBERCPT4, 0x00 },
  309. { STV090x_P1_FSPYBER, 0x10 },
  310. { STV090x_P1_ERRCTRL1, 0x35 },
  311. { STV090x_P1_ERRCTRL2, 0xc1 },
  312. { STV090x_P1_CFRICFG, 0xf8 },
  313. { STV090x_P1_NOSCFG, 0x1c },
  314. { STV090x_P1_CORRELMANT, 0x70 },
  315. { STV090x_P1_CORRELABS, 0x88 },
  316. { STV090x_P1_AGC2O, 0x5b },
  317. { STV090x_P1_AGC2REF, 0x38 },
  318. { STV090x_P1_CARCFG, 0xe4 },
  319. { STV090x_P1_ACLC, 0x1A },
  320. { STV090x_P1_BCLC, 0x09 },
  321. { STV090x_P1_CARHDR, 0x08 },
  322. { STV090x_P1_KREFTMG, 0xc1 },
  323. { STV090x_P1_SFRSTEP, 0x58 },
  324. { STV090x_P1_TMGCFG2, 0x01 },
  325. { STV090x_P1_CAR2CFG, 0x26 },
  326. { STV090x_P1_BCLC2S2Q, 0x86 },
  327. { STV090x_P1_BCLC2S28, 0x86 },
  328. { STV090x_P1_SMAPCOEF7, 0x77 },
  329. { STV090x_P1_SMAPCOEF6, 0x85 },
  330. { STV090x_P1_SMAPCOEF5, 0x77 },
  331. { STV090x_P1_DMDCFG2, 0x3b },
  332. { STV090x_P1_MODCODLST0, 0xff },
  333. { STV090x_P1_MODCODLST1, 0xff },
  334. { STV090x_P1_MODCODLST2, 0xff },
  335. { STV090x_P1_MODCODLST3, 0xff },
  336. { STV090x_P1_MODCODLST4, 0xff },
  337. { STV090x_P1_MODCODLST5, 0xff },
  338. { STV090x_P1_MODCODLST6, 0xff },
  339. { STV090x_P1_MODCODLST7, 0xcc },
  340. { STV090x_P1_MODCODLST8, 0xcc },
  341. { STV090x_P1_MODCODLST9, 0xcc },
  342. { STV090x_P1_MODCODLSTA, 0xcc },
  343. { STV090x_P1_MODCODLSTB, 0xcc },
  344. { STV090x_P1_MODCODLSTC, 0xcc },
  345. { STV090x_P1_MODCODLSTD, 0xcc },
  346. { STV090x_P1_MODCODLSTE, 0xcc },
  347. { STV090x_P1_MODCODLSTF, 0xcf },
  348. { STV090x_GENCFG, 0x1d },
  349. { STV090x_NBITER_NF4, 0x37 },
  350. { STV090x_NBITER_NF5, 0x29 },
  351. { STV090x_NBITER_NF6, 0x37 },
  352. { STV090x_NBITER_NF7, 0x33 },
  353. { STV090x_NBITER_NF8, 0x31 },
  354. { STV090x_NBITER_NF9, 0x2f },
  355. { STV090x_NBITER_NF10, 0x39 },
  356. { STV090x_NBITER_NF11, 0x3a },
  357. { STV090x_NBITER_NF12, 0x29 },
  358. { STV090x_NBITER_NF13, 0x37 },
  359. { STV090x_NBITER_NF14, 0x33 },
  360. { STV090x_NBITER_NF15, 0x2f },
  361. { STV090x_NBITER_NF16, 0x39 },
  362. { STV090x_NBITER_NF17, 0x3a },
  363. { STV090x_NBITERNOERR, 0x04 },
  364. { STV090x_GAINLLR_NF4, 0x0C },
  365. { STV090x_GAINLLR_NF5, 0x0F },
  366. { STV090x_GAINLLR_NF6, 0x11 },
  367. { STV090x_GAINLLR_NF7, 0x14 },
  368. { STV090x_GAINLLR_NF8, 0x17 },
  369. { STV090x_GAINLLR_NF9, 0x19 },
  370. { STV090x_GAINLLR_NF10, 0x20 },
  371. { STV090x_GAINLLR_NF11, 0x21 },
  372. { STV090x_GAINLLR_NF12, 0x0D },
  373. { STV090x_GAINLLR_NF13, 0x0F },
  374. { STV090x_GAINLLR_NF14, 0x13 },
  375. { STV090x_GAINLLR_NF15, 0x1A },
  376. { STV090x_GAINLLR_NF16, 0x1F },
  377. { STV090x_GAINLLR_NF17, 0x21 },
  378. { STV090x_RCCFGH, 0x20 },
  379. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  380. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  381. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  382. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  383. };
  384. static struct stv090x_reg stv0903_initval[] = {
  385. { STV090x_OUTCFG, 0x00 },
  386. { STV090x_AGCRF1CFG, 0x11 },
  387. { STV090x_STOPCLK1, 0x48 },
  388. { STV090x_STOPCLK2, 0x14 },
  389. { STV090x_TSTTNR1, 0x27 },
  390. { STV090x_TSTTNR2, 0x21 },
  391. { STV090x_P1_DISTXCTL, 0x22 },
  392. { STV090x_P1_F22TX, 0xc0 },
  393. { STV090x_P1_F22RX, 0xc0 },
  394. { STV090x_P1_DISRXCTL, 0x00 },
  395. { STV090x_P1_DMDCFGMD, 0xF9 },
  396. { STV090x_P1_DEMOD, 0x08 },
  397. { STV090x_P1_DMDCFG3, 0xc4 },
  398. { STV090x_P1_CARFREQ, 0xed },
  399. { STV090x_P1_TNRCFG2, 0x82 },
  400. { STV090x_P1_LDT, 0xd0 },
  401. { STV090x_P1_LDT2, 0xb8 },
  402. { STV090x_P1_TMGCFG, 0xd2 },
  403. { STV090x_P1_TMGTHRISE, 0x20 },
  404. { STV090x_P1_TMGTHFALL, 0x00 },
  405. { STV090x_P1_SFRUPRATIO, 0xf0 },
  406. { STV090x_P1_SFRLOWRATIO, 0x70 },
  407. { STV090x_P1_TSCFGL, 0x20 },
  408. { STV090x_P1_FECSPY, 0x88 },
  409. { STV090x_P1_FSPYDATA, 0x3a },
  410. { STV090x_P1_FBERCPT4, 0x00 },
  411. { STV090x_P1_FSPYBER, 0x10 },
  412. { STV090x_P1_ERRCTRL1, 0x35 },
  413. { STV090x_P1_ERRCTRL2, 0xc1 },
  414. { STV090x_P1_CFRICFG, 0xf8 },
  415. { STV090x_P1_NOSCFG, 0x1c },
  416. { STV090x_P1_DMDTOM, 0x20 },
  417. { STV090x_P1_CORRELMANT, 0x70 },
  418. { STV090x_P1_CORRELABS, 0x88 },
  419. { STV090x_P1_AGC2O, 0x5b },
  420. { STV090x_P1_AGC2REF, 0x38 },
  421. { STV090x_P1_CARCFG, 0xe4 },
  422. { STV090x_P1_ACLC, 0x1A },
  423. { STV090x_P1_BCLC, 0x09 },
  424. { STV090x_P1_CARHDR, 0x08 },
  425. { STV090x_P1_KREFTMG, 0xc1 },
  426. { STV090x_P1_SFRSTEP, 0x58 },
  427. { STV090x_P1_TMGCFG2, 0x01 },
  428. { STV090x_P1_CAR2CFG, 0x26 },
  429. { STV090x_P1_BCLC2S2Q, 0x86 },
  430. { STV090x_P1_BCLC2S28, 0x86 },
  431. { STV090x_P1_SMAPCOEF7, 0x77 },
  432. { STV090x_P1_SMAPCOEF6, 0x85 },
  433. { STV090x_P1_SMAPCOEF5, 0x77 },
  434. { STV090x_P1_DMDCFG2, 0x3b },
  435. { STV090x_P1_MODCODLST0, 0xff },
  436. { STV090x_P1_MODCODLST1, 0xff },
  437. { STV090x_P1_MODCODLST2, 0xff },
  438. { STV090x_P1_MODCODLST3, 0xff },
  439. { STV090x_P1_MODCODLST4, 0xff },
  440. { STV090x_P1_MODCODLST5, 0xff },
  441. { STV090x_P1_MODCODLST6, 0xff },
  442. { STV090x_P1_MODCODLST7, 0xcc },
  443. { STV090x_P1_MODCODLST8, 0xcc },
  444. { STV090x_P1_MODCODLST9, 0xcc },
  445. { STV090x_P1_MODCODLSTA, 0xcc },
  446. { STV090x_P1_MODCODLSTB, 0xcc },
  447. { STV090x_P1_MODCODLSTC, 0xcc },
  448. { STV090x_P1_MODCODLSTD, 0xcc },
  449. { STV090x_P1_MODCODLSTE, 0xcc },
  450. { STV090x_P1_MODCODLSTF, 0xcf },
  451. { STV090x_GENCFG, 0x1c },
  452. { STV090x_NBITER_NF4, 0x37 },
  453. { STV090x_NBITER_NF5, 0x29 },
  454. { STV090x_NBITER_NF6, 0x37 },
  455. { STV090x_NBITER_NF7, 0x33 },
  456. { STV090x_NBITER_NF8, 0x31 },
  457. { STV090x_NBITER_NF9, 0x2f },
  458. { STV090x_NBITER_NF10, 0x39 },
  459. { STV090x_NBITER_NF11, 0x3a },
  460. { STV090x_NBITER_NF12, 0x29 },
  461. { STV090x_NBITER_NF13, 0x37 },
  462. { STV090x_NBITER_NF14, 0x33 },
  463. { STV090x_NBITER_NF15, 0x2f },
  464. { STV090x_NBITER_NF16, 0x39 },
  465. { STV090x_NBITER_NF17, 0x3a },
  466. { STV090x_NBITERNOERR, 0x04 },
  467. { STV090x_GAINLLR_NF4, 0x0C },
  468. { STV090x_GAINLLR_NF5, 0x0F },
  469. { STV090x_GAINLLR_NF6, 0x11 },
  470. { STV090x_GAINLLR_NF7, 0x14 },
  471. { STV090x_GAINLLR_NF8, 0x17 },
  472. { STV090x_GAINLLR_NF9, 0x19 },
  473. { STV090x_GAINLLR_NF10, 0x20 },
  474. { STV090x_GAINLLR_NF11, 0x21 },
  475. { STV090x_GAINLLR_NF12, 0x0D },
  476. { STV090x_GAINLLR_NF13, 0x0F },
  477. { STV090x_GAINLLR_NF14, 0x13 },
  478. { STV090x_GAINLLR_NF15, 0x1A },
  479. { STV090x_GAINLLR_NF16, 0x1F },
  480. { STV090x_GAINLLR_NF17, 0x21 },
  481. { STV090x_RCCFGH, 0x20 },
  482. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  483. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  484. };
  485. static struct stv090x_reg stv0900_cut20_val[] = {
  486. { STV090x_P2_DMDCFG3, 0xe8 },
  487. { STV090x_P2_DMDCFG4, 0x10 },
  488. { STV090x_P2_CARFREQ, 0x38 },
  489. { STV090x_P2_CARHDR, 0x20 },
  490. { STV090x_P2_KREFTMG, 0x5a },
  491. { STV090x_P2_SMAPCOEF7, 0x06 },
  492. { STV090x_P2_SMAPCOEF6, 0x00 },
  493. { STV090x_P2_SMAPCOEF5, 0x04 },
  494. { STV090x_P2_NOSCFG, 0x0c },
  495. { STV090x_P1_DMDCFG3, 0xe8 },
  496. { STV090x_P1_DMDCFG4, 0x10 },
  497. { STV090x_P1_CARFREQ, 0x38 },
  498. { STV090x_P1_CARHDR, 0x20 },
  499. { STV090x_P1_KREFTMG, 0x5a },
  500. { STV090x_P1_SMAPCOEF7, 0x06 },
  501. { STV090x_P1_SMAPCOEF6, 0x00 },
  502. { STV090x_P1_SMAPCOEF5, 0x04 },
  503. { STV090x_P1_NOSCFG, 0x0c },
  504. { STV090x_GAINLLR_NF4, 0x21 },
  505. { STV090x_GAINLLR_NF5, 0x21 },
  506. { STV090x_GAINLLR_NF6, 0x20 },
  507. { STV090x_GAINLLR_NF7, 0x1F },
  508. { STV090x_GAINLLR_NF8, 0x1E },
  509. { STV090x_GAINLLR_NF9, 0x1E },
  510. { STV090x_GAINLLR_NF10, 0x1D },
  511. { STV090x_GAINLLR_NF11, 0x1B },
  512. { STV090x_GAINLLR_NF12, 0x20 },
  513. { STV090x_GAINLLR_NF13, 0x20 },
  514. { STV090x_GAINLLR_NF14, 0x20 },
  515. { STV090x_GAINLLR_NF15, 0x20 },
  516. { STV090x_GAINLLR_NF16, 0x20 },
  517. { STV090x_GAINLLR_NF17, 0x21 },
  518. };
  519. static struct stv090x_reg stv0903_cut20_val[] = {
  520. { STV090x_P1_DMDCFG3, 0xe8 },
  521. { STV090x_P1_DMDCFG4, 0x10 },
  522. { STV090x_P1_CARFREQ, 0x38 },
  523. { STV090x_P1_CARHDR, 0x20 },
  524. { STV090x_P1_KREFTMG, 0x5a },
  525. { STV090x_P1_SMAPCOEF7, 0x06 },
  526. { STV090x_P1_SMAPCOEF6, 0x00 },
  527. { STV090x_P1_SMAPCOEF5, 0x04 },
  528. { STV090x_P1_NOSCFG, 0x0c },
  529. { STV090x_GAINLLR_NF4, 0x21 },
  530. { STV090x_GAINLLR_NF5, 0x21 },
  531. { STV090x_GAINLLR_NF6, 0x20 },
  532. { STV090x_GAINLLR_NF7, 0x1F },
  533. { STV090x_GAINLLR_NF8, 0x1E },
  534. { STV090x_GAINLLR_NF9, 0x1E },
  535. { STV090x_GAINLLR_NF10, 0x1D },
  536. { STV090x_GAINLLR_NF11, 0x1B },
  537. { STV090x_GAINLLR_NF12, 0x20 },
  538. { STV090x_GAINLLR_NF13, 0x20 },
  539. { STV090x_GAINLLR_NF14, 0x20 },
  540. { STV090x_GAINLLR_NF15, 0x20 },
  541. { STV090x_GAINLLR_NF16, 0x20 },
  542. { STV090x_GAINLLR_NF17, 0x21 }
  543. };
  544. /* Cut 2.0 Long Frame Tracking CR loop */
  545. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  546. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  547. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  548. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  549. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  550. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  551. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  552. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  553. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  554. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  555. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  556. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  557. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  558. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  559. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  560. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  561. };
  562. /* Cut 3.0 Long Frame Tracking CR loop */
  563. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
  564. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  565. { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
  566. { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  567. { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  568. { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  569. { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  570. { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  571. { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  572. { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  573. { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
  574. { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
  575. { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
  576. { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
  577. { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
  578. { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
  579. };
  580. /* Cut 2.0 Long Frame Tracking CR Loop */
  581. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  582. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  583. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  584. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  585. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  586. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  587. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  588. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  589. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  590. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  591. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  592. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  593. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  594. };
  595. /* Cut 3.0 Long Frame Tracking CR Loop */
  596. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
  597. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  598. { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
  599. { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
  600. { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  601. { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  602. { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  603. { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  604. { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  605. { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  606. { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  607. { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  608. { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
  609. };
  610. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  611. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  612. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  613. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  614. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  615. };
  616. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
  617. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  618. { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
  619. { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
  620. { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
  621. };
  622. /* Cut 2.0 Short Frame Tracking CR Loop */
  623. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
  624. /* MODCOD 2M 5M 10M 20M 30M */
  625. { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
  626. { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
  627. { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
  628. { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
  629. };
  630. /* Cut 3.0 Short Frame Tracking CR Loop */
  631. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
  632. /* MODCOD 2M 5M 10M 20M 30M */
  633. { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
  634. { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
  635. { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
  636. { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
  637. };
  638. static inline s32 comp2(s32 __x, s32 __width)
  639. {
  640. if (__width == 32)
  641. return __x;
  642. else
  643. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  644. }
  645. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  646. {
  647. const struct stv090x_config *config = state->config;
  648. int ret;
  649. u8 b0[] = { reg >> 8, reg & 0xff };
  650. u8 buf;
  651. struct i2c_msg msg[] = {
  652. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  653. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  654. };
  655. ret = i2c_transfer(state->i2c, msg, 2);
  656. if (ret != 2) {
  657. if (ret != -ERESTARTSYS)
  658. dprintk(FE_ERROR, 1,
  659. "Read error, Reg=[0x%02x], Status=%d",
  660. reg, ret);
  661. return ret < 0 ? ret : -EREMOTEIO;
  662. }
  663. if (unlikely(*state->verbose >= FE_DEBUGREG))
  664. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  665. reg, buf);
  666. return (unsigned int) buf;
  667. }
  668. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  669. {
  670. const struct stv090x_config *config = state->config;
  671. int ret;
  672. u8 buf[2 + count];
  673. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  674. buf[0] = reg >> 8;
  675. buf[1] = reg & 0xff;
  676. memcpy(&buf[2], data, count);
  677. if (unlikely(*state->verbose >= FE_DEBUGREG)) {
  678. int i;
  679. printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
  680. for (i = 0; i < count; i++)
  681. printk(" %02x", data[i]);
  682. printk("\n");
  683. }
  684. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  685. if (ret != 1) {
  686. if (ret != -ERESTARTSYS)
  687. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  688. reg, data[0], count, ret);
  689. return ret < 0 ? ret : -EREMOTEIO;
  690. }
  691. return 0;
  692. }
  693. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  694. {
  695. return stv090x_write_regs(state, reg, &data, 1);
  696. }
  697. static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  698. {
  699. struct stv090x_state *state = fe->demodulator_priv;
  700. u32 reg;
  701. if (enable)
  702. mutex_lock(&state->internal->tuner_lock);
  703. reg = STV090x_READ_DEMOD(state, I2CRPT);
  704. if (enable) {
  705. dprintk(FE_DEBUG, 1, "Enable Gate");
  706. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  707. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  708. goto err;
  709. } else {
  710. dprintk(FE_DEBUG, 1, "Disable Gate");
  711. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  712. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  713. goto err;
  714. }
  715. if (!enable)
  716. mutex_unlock(&state->internal->tuner_lock);
  717. return 0;
  718. err:
  719. dprintk(FE_ERROR, 1, "I/O error");
  720. mutex_unlock(&state->internal->tuner_lock);
  721. return -1;
  722. }
  723. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  724. {
  725. switch (state->algo) {
  726. case STV090x_BLIND_SEARCH:
  727. dprintk(FE_DEBUG, 1, "Blind Search");
  728. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  729. state->DemodTimeout = 1500;
  730. state->FecTimeout = 400;
  731. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  732. state->DemodTimeout = 1000;
  733. state->FecTimeout = 300;
  734. } else { /*SR >20Msps*/
  735. state->DemodTimeout = 700;
  736. state->FecTimeout = 100;
  737. }
  738. break;
  739. case STV090x_COLD_SEARCH:
  740. case STV090x_WARM_SEARCH:
  741. default:
  742. dprintk(FE_DEBUG, 1, "Normal Search");
  743. if (state->srate <= 1000000) { /*SR <=1Msps*/
  744. state->DemodTimeout = 4500;
  745. state->FecTimeout = 1700;
  746. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  747. state->DemodTimeout = 2500;
  748. state->FecTimeout = 1100;
  749. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  750. state->DemodTimeout = 1000;
  751. state->FecTimeout = 550;
  752. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  753. state->DemodTimeout = 700;
  754. state->FecTimeout = 250;
  755. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  756. state->DemodTimeout = 400;
  757. state->FecTimeout = 130;
  758. } else { /*SR >20Msps*/
  759. state->DemodTimeout = 300;
  760. state->FecTimeout = 100;
  761. }
  762. break;
  763. }
  764. if (state->algo == STV090x_WARM_SEARCH)
  765. state->DemodTimeout /= 2;
  766. }
  767. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  768. {
  769. u32 sym;
  770. if (srate > 60000000) {
  771. sym = (srate << 4); /* SR * 2^16 / master_clk */
  772. sym /= (state->internal->mclk >> 12);
  773. } else if (srate > 6000000) {
  774. sym = (srate << 6);
  775. sym /= (state->internal->mclk >> 10);
  776. } else {
  777. sym = (srate << 9);
  778. sym /= (state->internal->mclk >> 7);
  779. }
  780. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
  781. goto err;
  782. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  783. goto err;
  784. return 0;
  785. err:
  786. dprintk(FE_ERROR, 1, "I/O error");
  787. return -1;
  788. }
  789. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  790. {
  791. u32 sym;
  792. srate = 105 * (srate / 100);
  793. if (srate > 60000000) {
  794. sym = (srate << 4); /* SR * 2^16 / master_clk */
  795. sym /= (state->internal->mclk >> 12);
  796. } else if (srate > 6000000) {
  797. sym = (srate << 6);
  798. sym /= (state->internal->mclk >> 10);
  799. } else {
  800. sym = (srate << 9);
  801. sym /= (state->internal->mclk >> 7);
  802. }
  803. if (sym < 0x7fff) {
  804. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  805. goto err;
  806. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  807. goto err;
  808. } else {
  809. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
  810. goto err;
  811. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
  812. goto err;
  813. }
  814. return 0;
  815. err:
  816. dprintk(FE_ERROR, 1, "I/O error");
  817. return -1;
  818. }
  819. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  820. {
  821. u32 sym;
  822. srate = 95 * (srate / 100);
  823. if (srate > 60000000) {
  824. sym = (srate << 4); /* SR * 2^16 / master_clk */
  825. sym /= (state->internal->mclk >> 12);
  826. } else if (srate > 6000000) {
  827. sym = (srate << 6);
  828. sym /= (state->internal->mclk >> 10);
  829. } else {
  830. sym = (srate << 9);
  831. sym /= (state->internal->mclk >> 7);
  832. }
  833. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
  834. goto err;
  835. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  836. goto err;
  837. return 0;
  838. err:
  839. dprintk(FE_ERROR, 1, "I/O error");
  840. return -1;
  841. }
  842. static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
  843. {
  844. u32 ro;
  845. switch (rolloff) {
  846. case STV090x_RO_20:
  847. ro = 20;
  848. break;
  849. case STV090x_RO_25:
  850. ro = 25;
  851. break;
  852. case STV090x_RO_35:
  853. default:
  854. ro = 35;
  855. break;
  856. }
  857. return srate + (srate * ro) / 100;
  858. }
  859. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  860. {
  861. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  862. goto err;
  863. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  864. goto err;
  865. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  866. goto err;
  867. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  868. goto err;
  869. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  870. goto err;
  871. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  872. goto err;
  873. return 0;
  874. err:
  875. dprintk(FE_ERROR, 1, "I/O error");
  876. return -1;
  877. }
  878. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  879. {
  880. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  881. goto err;
  882. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  883. goto err;
  884. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  885. goto err;
  886. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  887. goto err;
  888. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  889. goto err;
  890. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  891. goto err;
  892. return 0;
  893. err:
  894. dprintk(FE_ERROR, 1, "I/O error");
  895. return -1;
  896. }
  897. static int stv090x_set_viterbi(struct stv090x_state *state)
  898. {
  899. switch (state->search_mode) {
  900. case STV090x_SEARCH_AUTO:
  901. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  902. goto err;
  903. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  904. goto err;
  905. break;
  906. case STV090x_SEARCH_DVBS1:
  907. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  908. goto err;
  909. switch (state->fec) {
  910. case STV090x_PR12:
  911. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  912. goto err;
  913. break;
  914. case STV090x_PR23:
  915. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  916. goto err;
  917. break;
  918. case STV090x_PR34:
  919. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  920. goto err;
  921. break;
  922. case STV090x_PR56:
  923. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  924. goto err;
  925. break;
  926. case STV090x_PR78:
  927. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  928. goto err;
  929. break;
  930. default:
  931. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  932. goto err;
  933. break;
  934. }
  935. break;
  936. case STV090x_SEARCH_DSS:
  937. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  938. goto err;
  939. switch (state->fec) {
  940. case STV090x_PR12:
  941. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  942. goto err;
  943. break;
  944. case STV090x_PR23:
  945. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  946. goto err;
  947. break;
  948. case STV090x_PR67:
  949. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  950. goto err;
  951. break;
  952. default:
  953. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  954. goto err;
  955. break;
  956. }
  957. break;
  958. default:
  959. break;
  960. }
  961. return 0;
  962. err:
  963. dprintk(FE_ERROR, 1, "I/O error");
  964. return -1;
  965. }
  966. static int stv090x_stop_modcod(struct stv090x_state *state)
  967. {
  968. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  969. goto err;
  970. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  971. goto err;
  972. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  973. goto err;
  974. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  975. goto err;
  976. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  977. goto err;
  978. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  979. goto err;
  980. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  981. goto err;
  982. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  983. goto err;
  984. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  985. goto err;
  986. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  987. goto err;
  988. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  989. goto err;
  990. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  991. goto err;
  992. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  993. goto err;
  994. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  995. goto err;
  996. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  997. goto err;
  998. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  999. goto err;
  1000. return 0;
  1001. err:
  1002. dprintk(FE_ERROR, 1, "I/O error");
  1003. return -1;
  1004. }
  1005. static int stv090x_activate_modcod(struct stv090x_state *state)
  1006. {
  1007. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1008. goto err;
  1009. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  1010. goto err;
  1011. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  1012. goto err;
  1013. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  1014. goto err;
  1015. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  1016. goto err;
  1017. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  1018. goto err;
  1019. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  1020. goto err;
  1021. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  1022. goto err;
  1023. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  1024. goto err;
  1025. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  1026. goto err;
  1027. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  1028. goto err;
  1029. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  1030. goto err;
  1031. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  1032. goto err;
  1033. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  1034. goto err;
  1035. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  1036. goto err;
  1037. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  1038. goto err;
  1039. return 0;
  1040. err:
  1041. dprintk(FE_ERROR, 1, "I/O error");
  1042. return -1;
  1043. }
  1044. static int stv090x_activate_modcod_single(struct stv090x_state *state)
  1045. {
  1046. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1047. goto err;
  1048. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
  1049. goto err;
  1050. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
  1051. goto err;
  1052. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
  1053. goto err;
  1054. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
  1055. goto err;
  1056. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
  1057. goto err;
  1058. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
  1059. goto err;
  1060. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
  1061. goto err;
  1062. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
  1063. goto err;
  1064. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
  1065. goto err;
  1066. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
  1067. goto err;
  1068. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
  1069. goto err;
  1070. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
  1071. goto err;
  1072. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
  1073. goto err;
  1074. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
  1075. goto err;
  1076. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
  1077. goto err;
  1078. return 0;
  1079. err:
  1080. dprintk(FE_ERROR, 1, "I/O error");
  1081. return -1;
  1082. }
  1083. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  1084. {
  1085. u32 reg;
  1086. switch (state->demod) {
  1087. case STV090x_DEMODULATOR_0:
  1088. mutex_lock(&state->internal->demod_lock);
  1089. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1090. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  1091. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1092. goto err;
  1093. mutex_unlock(&state->internal->demod_lock);
  1094. break;
  1095. case STV090x_DEMODULATOR_1:
  1096. mutex_lock(&state->internal->demod_lock);
  1097. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1098. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  1099. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1100. goto err;
  1101. mutex_unlock(&state->internal->demod_lock);
  1102. break;
  1103. default:
  1104. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  1105. break;
  1106. }
  1107. return 0;
  1108. err:
  1109. mutex_unlock(&state->internal->demod_lock);
  1110. dprintk(FE_ERROR, 1, "I/O error");
  1111. return -1;
  1112. }
  1113. static int stv090x_dvbs_track_crl(struct stv090x_state *state)
  1114. {
  1115. if (state->internal->dev_ver >= 0x30) {
  1116. /* Set ACLC BCLC optimised value vs SR */
  1117. if (state->srate >= 15000000) {
  1118. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
  1119. goto err;
  1120. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
  1121. goto err;
  1122. } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
  1123. if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
  1124. goto err;
  1125. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
  1126. goto err;
  1127. } else if (state->srate < 7000000) {
  1128. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
  1129. goto err;
  1130. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
  1131. goto err;
  1132. }
  1133. } else {
  1134. /* Cut 2.0 */
  1135. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1136. goto err;
  1137. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1138. goto err;
  1139. }
  1140. return 0;
  1141. err:
  1142. dprintk(FE_ERROR, 1, "I/O error");
  1143. return -1;
  1144. }
  1145. static int stv090x_delivery_search(struct stv090x_state *state)
  1146. {
  1147. u32 reg;
  1148. switch (state->search_mode) {
  1149. case STV090x_SEARCH_DVBS1:
  1150. case STV090x_SEARCH_DSS:
  1151. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1152. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1153. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1154. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1155. goto err;
  1156. /* Activate Viterbi decoder in legacy search,
  1157. * do not use FRESVIT1, might impact VITERBI2
  1158. */
  1159. if (stv090x_vitclk_ctl(state, 0) < 0)
  1160. goto err;
  1161. if (stv090x_dvbs_track_crl(state) < 0)
  1162. goto err;
  1163. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  1164. goto err;
  1165. if (stv090x_set_vit_thacq(state) < 0)
  1166. goto err;
  1167. if (stv090x_set_viterbi(state) < 0)
  1168. goto err;
  1169. break;
  1170. case STV090x_SEARCH_DVBS2:
  1171. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1172. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1173. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1174. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1175. goto err;
  1176. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1177. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1178. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1179. goto err;
  1180. if (stv090x_vitclk_ctl(state, 1) < 0)
  1181. goto err;
  1182. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1183. goto err;
  1184. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1185. goto err;
  1186. if (state->internal->dev_ver <= 0x20) {
  1187. /* enable S2 carrier loop */
  1188. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1189. goto err;
  1190. } else {
  1191. /* > Cut 3: Stop carrier 3 */
  1192. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1193. goto err;
  1194. }
  1195. if (state->demod_mode != STV090x_SINGLE) {
  1196. /* Cut 2: enable link during search */
  1197. if (stv090x_activate_modcod(state) < 0)
  1198. goto err;
  1199. } else {
  1200. /* Single demodulator
  1201. * Authorize SHORT and LONG frames,
  1202. * QPSK, 8PSK, 16APSK and 32APSK
  1203. */
  1204. if (stv090x_activate_modcod_single(state) < 0)
  1205. goto err;
  1206. }
  1207. if (stv090x_set_vit_thtracq(state) < 0)
  1208. goto err;
  1209. break;
  1210. case STV090x_SEARCH_AUTO:
  1211. default:
  1212. /* enable DVB-S2 and DVB-S2 in Auto MODE */
  1213. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1214. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1215. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1216. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1217. goto err;
  1218. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1219. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1220. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1221. goto err;
  1222. if (stv090x_vitclk_ctl(state, 0) < 0)
  1223. goto err;
  1224. if (stv090x_dvbs_track_crl(state) < 0)
  1225. goto err;
  1226. if (state->internal->dev_ver <= 0x20) {
  1227. /* enable S2 carrier loop */
  1228. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1229. goto err;
  1230. } else {
  1231. /* > Cut 3: Stop carrier 3 */
  1232. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1233. goto err;
  1234. }
  1235. if (state->demod_mode != STV090x_SINGLE) {
  1236. /* Cut 2: enable link during search */
  1237. if (stv090x_activate_modcod(state) < 0)
  1238. goto err;
  1239. } else {
  1240. /* Single demodulator
  1241. * Authorize SHORT and LONG frames,
  1242. * QPSK, 8PSK, 16APSK and 32APSK
  1243. */
  1244. if (stv090x_activate_modcod_single(state) < 0)
  1245. goto err;
  1246. }
  1247. if (stv090x_set_vit_thacq(state) < 0)
  1248. goto err;
  1249. if (stv090x_set_viterbi(state) < 0)
  1250. goto err;
  1251. break;
  1252. }
  1253. return 0;
  1254. err:
  1255. dprintk(FE_ERROR, 1, "I/O error");
  1256. return -1;
  1257. }
  1258. static int stv090x_start_search(struct stv090x_state *state)
  1259. {
  1260. u32 reg, freq_abs;
  1261. s16 freq;
  1262. /* Reset demodulator */
  1263. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1264. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1265. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1266. goto err;
  1267. if (state->internal->dev_ver <= 0x20) {
  1268. if (state->srate <= 5000000) {
  1269. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1270. goto err;
  1271. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1272. goto err;
  1273. if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
  1274. goto err;
  1275. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1276. goto err;
  1277. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1278. goto err;
  1279. /*enlarge the timing bandwith for Low SR*/
  1280. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1281. goto err;
  1282. } else {
  1283. /* If the symbol rate is >5 Msps
  1284. Set The carrier search up and low to auto mode */
  1285. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1286. goto err;
  1287. /*reduce the timing bandwith for high SR*/
  1288. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1289. goto err;
  1290. }
  1291. } else {
  1292. /* >= Cut 3 */
  1293. if (state->srate <= 5000000) {
  1294. /* enlarge the timing bandwith for Low SR */
  1295. STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
  1296. } else {
  1297. /* reduce timing bandwith for high SR */
  1298. STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
  1299. }
  1300. /* Set CFR min and max to manual mode */
  1301. STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
  1302. if (state->algo == STV090x_WARM_SEARCH) {
  1303. /* WARM Start
  1304. * CFR min = -1MHz,
  1305. * CFR max = +1MHz
  1306. */
  1307. freq_abs = 1000 << 16;
  1308. freq_abs /= (state->internal->mclk / 1000);
  1309. freq = (s16) freq_abs;
  1310. } else {
  1311. /* COLD Start
  1312. * CFR min =- (SearchRange / 2 + 600KHz)
  1313. * CFR max = +(SearchRange / 2 + 600KHz)
  1314. * (600KHz for the tuner step size)
  1315. */
  1316. freq_abs = (state->search_range / 2000) + 600;
  1317. freq_abs = freq_abs << 16;
  1318. freq_abs /= (state->internal->mclk / 1000);
  1319. freq = (s16) freq_abs;
  1320. }
  1321. if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
  1322. goto err;
  1323. if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
  1324. goto err;
  1325. freq *= -1;
  1326. if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
  1327. goto err;
  1328. if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
  1329. goto err;
  1330. }
  1331. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1332. goto err;
  1333. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1334. goto err;
  1335. if (state->internal->dev_ver >= 0x20) {
  1336. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1337. goto err;
  1338. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1339. goto err;
  1340. if ((state->search_mode == STV090x_DVBS1) ||
  1341. (state->search_mode == STV090x_DSS) ||
  1342. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1343. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1344. goto err;
  1345. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1346. goto err;
  1347. }
  1348. }
  1349. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1350. goto err;
  1351. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1352. goto err;
  1353. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1354. goto err;
  1355. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1356. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1357. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1358. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1359. goto err;
  1360. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1361. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1362. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1363. goto err;
  1364. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
  1365. goto err;
  1366. if (state->internal->dev_ver >= 0x20) {
  1367. /*Frequency offset detector setting*/
  1368. if (state->srate < 2000000) {
  1369. if (state->internal->dev_ver <= 0x20) {
  1370. /* Cut 2 */
  1371. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
  1372. goto err;
  1373. } else {
  1374. /* Cut 3 */
  1375. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
  1376. goto err;
  1377. }
  1378. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
  1379. goto err;
  1380. } else if (state->srate < 10000000) {
  1381. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1382. goto err;
  1383. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1384. goto err;
  1385. } else {
  1386. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1387. goto err;
  1388. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1389. goto err;
  1390. }
  1391. } else {
  1392. if (state->srate < 10000000) {
  1393. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1394. goto err;
  1395. } else {
  1396. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1397. goto err;
  1398. }
  1399. }
  1400. switch (state->algo) {
  1401. case STV090x_WARM_SEARCH:
  1402. /* The symbol rate and the exact
  1403. * carrier Frequency are known
  1404. */
  1405. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1406. goto err;
  1407. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1408. goto err;
  1409. break;
  1410. case STV090x_COLD_SEARCH:
  1411. /* The symbol rate is known */
  1412. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1413. goto err;
  1414. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1415. goto err;
  1416. break;
  1417. default:
  1418. break;
  1419. }
  1420. return 0;
  1421. err:
  1422. dprintk(FE_ERROR, 1, "I/O error");
  1423. return -1;
  1424. }
  1425. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1426. {
  1427. u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
  1428. s32 i, j, steps, dir;
  1429. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1430. goto err;
  1431. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1432. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1433. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1434. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1435. goto err;
  1436. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1437. goto err;
  1438. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1439. goto err;
  1440. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1441. goto err;
  1442. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1443. goto err;
  1444. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1445. goto err;
  1446. if (stv090x_set_srate(state, 1000000) < 0)
  1447. goto err;
  1448. steps = state->search_range / 1000000;
  1449. if (steps <= 0)
  1450. steps = 1;
  1451. dir = 1;
  1452. freq_step = (1000000 * 256) / (state->internal->mclk / 256);
  1453. freq_init = 0;
  1454. for (i = 0; i < steps; i++) {
  1455. if (dir > 0)
  1456. freq_init = freq_init + (freq_step * i);
  1457. else
  1458. freq_init = freq_init - (freq_step * i);
  1459. dir *= -1;
  1460. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1461. goto err;
  1462. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1463. goto err;
  1464. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1465. goto err;
  1466. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1467. goto err;
  1468. msleep(10);
  1469. agc2 = 0;
  1470. for (j = 0; j < 10; j++) {
  1471. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1472. STV090x_READ_DEMOD(state, AGC2I0);
  1473. }
  1474. agc2 /= 10;
  1475. if (agc2 < agc2_min)
  1476. agc2_min = agc2;
  1477. }
  1478. return agc2_min;
  1479. err:
  1480. dprintk(FE_ERROR, 1, "I/O error");
  1481. return -1;
  1482. }
  1483. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1484. {
  1485. u8 r3, r2, r1, r0;
  1486. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1487. r3 = STV090x_READ_DEMOD(state, SFR3);
  1488. r2 = STV090x_READ_DEMOD(state, SFR2);
  1489. r1 = STV090x_READ_DEMOD(state, SFR1);
  1490. r0 = STV090x_READ_DEMOD(state, SFR0);
  1491. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1492. int_1 = clk >> 16;
  1493. int_2 = srate >> 16;
  1494. tmp_1 = clk % 0x10000;
  1495. tmp_2 = srate % 0x10000;
  1496. srate = (int_1 * int_2) +
  1497. ((int_1 * tmp_2) >> 16) +
  1498. ((int_2 * tmp_1) >> 16);
  1499. return srate;
  1500. }
  1501. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1502. {
  1503. struct dvb_frontend *fe = &state->frontend;
  1504. int tmg_lock = 0, i;
  1505. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1506. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1507. u32 agc2th;
  1508. if (state->internal->dev_ver >= 0x30)
  1509. agc2th = 0x2e00;
  1510. else
  1511. agc2th = 0x1f00;
  1512. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1513. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1514. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1515. goto err;
  1516. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1517. goto err;
  1518. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
  1519. goto err;
  1520. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1521. goto err;
  1522. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1523. goto err;
  1524. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1525. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1526. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1527. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1528. goto err;
  1529. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1530. goto err;
  1531. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1532. goto err;
  1533. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1534. goto err;
  1535. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1536. goto err;
  1537. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1538. goto err;
  1539. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
  1540. goto err;
  1541. if (state->internal->dev_ver >= 0x30) {
  1542. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
  1543. goto err;
  1544. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
  1545. goto err;
  1546. } else if (state->internal->dev_ver >= 0x20) {
  1547. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1548. goto err;
  1549. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1550. goto err;
  1551. }
  1552. if (state->srate <= 2000000)
  1553. car_step = 1000;
  1554. else if (state->srate <= 5000000)
  1555. car_step = 2000;
  1556. else if (state->srate <= 12000000)
  1557. car_step = 3000;
  1558. else
  1559. car_step = 5000;
  1560. steps = -1 + ((state->search_range / 1000) / car_step);
  1561. steps /= 2;
  1562. steps = (2 * steps) + 1;
  1563. if (steps < 0)
  1564. steps = 1;
  1565. else if (steps > 10) {
  1566. steps = 11;
  1567. car_step = (state->search_range / 1000) / 10;
  1568. }
  1569. cur_step = 0;
  1570. dir = 1;
  1571. freq = state->frequency;
  1572. while ((!tmg_lock) && (cur_step < steps)) {
  1573. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1574. goto err;
  1575. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1576. goto err;
  1577. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1578. goto err;
  1579. if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
  1580. goto err;
  1581. if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
  1582. goto err;
  1583. /* trigger acquisition */
  1584. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
  1585. goto err;
  1586. msleep(50);
  1587. for (i = 0; i < 10; i++) {
  1588. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1589. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1590. tmg_cpt++;
  1591. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1592. STV090x_READ_DEMOD(state, AGC2I0);
  1593. }
  1594. agc2 /= 10;
  1595. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1596. cur_step++;
  1597. dir *= -1;
  1598. if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
  1599. (srate_coarse < 50000000) && (srate_coarse > 850000))
  1600. tmg_lock = 1;
  1601. else if (cur_step < steps) {
  1602. if (dir > 0)
  1603. freq += cur_step * car_step;
  1604. else
  1605. freq -= cur_step * car_step;
  1606. /* Setup tuner */
  1607. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1608. goto err;
  1609. if (state->config->tuner_set_frequency) {
  1610. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1611. goto err_gateoff;
  1612. }
  1613. if (state->config->tuner_set_bandwidth) {
  1614. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1615. goto err_gateoff;
  1616. }
  1617. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1618. goto err;
  1619. msleep(50);
  1620. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1621. goto err;
  1622. if (state->config->tuner_get_status) {
  1623. if (state->config->tuner_get_status(fe, &reg) < 0)
  1624. goto err_gateoff;
  1625. }
  1626. if (reg)
  1627. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1628. else
  1629. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1630. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1631. goto err;
  1632. }
  1633. }
  1634. if (!tmg_lock)
  1635. srate_coarse = 0;
  1636. else
  1637. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1638. return srate_coarse;
  1639. err_gateoff:
  1640. stv090x_i2c_gate_ctrl(fe, 0);
  1641. err:
  1642. dprintk(FE_ERROR, 1, "I/O error");
  1643. return -1;
  1644. }
  1645. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1646. {
  1647. u32 srate_coarse, freq_coarse, sym, reg;
  1648. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1649. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1650. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1651. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1652. if (sym < state->srate)
  1653. srate_coarse = 0;
  1654. else {
  1655. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1656. goto err;
  1657. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  1658. goto err;
  1659. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1660. goto err;
  1661. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1662. goto err;
  1663. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1664. goto err;
  1665. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1666. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1667. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1668. goto err;
  1669. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1670. goto err;
  1671. if (state->internal->dev_ver >= 0x30) {
  1672. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
  1673. goto err;
  1674. } else if (state->internal->dev_ver >= 0x20) {
  1675. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1676. goto err;
  1677. }
  1678. if (srate_coarse > 3000000) {
  1679. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1680. sym = (sym / 1000) * 65536;
  1681. sym /= (state->internal->mclk / 1000);
  1682. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1683. goto err;
  1684. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1685. goto err;
  1686. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1687. sym = (sym / 1000) * 65536;
  1688. sym /= (state->internal->mclk / 1000);
  1689. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1690. goto err;
  1691. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1692. goto err;
  1693. sym = (srate_coarse / 1000) * 65536;
  1694. sym /= (state->internal->mclk / 1000);
  1695. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1696. goto err;
  1697. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1698. goto err;
  1699. } else {
  1700. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1701. sym = (sym / 100) * 65536;
  1702. sym /= (state->internal->mclk / 100);
  1703. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1704. goto err;
  1705. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1706. goto err;
  1707. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1708. sym = (sym / 100) * 65536;
  1709. sym /= (state->internal->mclk / 100);
  1710. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1711. goto err;
  1712. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1713. goto err;
  1714. sym = (srate_coarse / 100) * 65536;
  1715. sym /= (state->internal->mclk / 100);
  1716. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1717. goto err;
  1718. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1719. goto err;
  1720. }
  1721. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1722. goto err;
  1723. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1724. goto err;
  1725. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1726. goto err;
  1727. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1728. goto err;
  1729. }
  1730. return srate_coarse;
  1731. err:
  1732. dprintk(FE_ERROR, 1, "I/O error");
  1733. return -1;
  1734. }
  1735. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1736. {
  1737. s32 timer = 0, lock = 0;
  1738. u32 reg;
  1739. u8 stat;
  1740. while ((timer < timeout) && (!lock)) {
  1741. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1742. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1743. switch (stat) {
  1744. case 0: /* searching */
  1745. case 1: /* first PLH detected */
  1746. default:
  1747. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1748. lock = 0;
  1749. break;
  1750. case 2: /* DVB-S2 mode */
  1751. case 3: /* DVB-S1/legacy mode */
  1752. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1753. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1754. break;
  1755. }
  1756. if (!lock)
  1757. msleep(10);
  1758. else
  1759. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1760. timer += 10;
  1761. }
  1762. return lock;
  1763. }
  1764. static int stv090x_blind_search(struct stv090x_state *state)
  1765. {
  1766. u32 agc2, reg, srate_coarse;
  1767. s32 cpt_fail, agc2_ovflw, i;
  1768. u8 k_ref, k_max, k_min;
  1769. int coarse_fail = 0;
  1770. int lock;
  1771. k_max = 110;
  1772. k_min = 10;
  1773. agc2 = stv090x_get_agc2_min_level(state);
  1774. if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
  1775. lock = 0;
  1776. } else {
  1777. if (state->internal->dev_ver <= 0x20) {
  1778. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1779. goto err;
  1780. } else {
  1781. /* > Cut 3 */
  1782. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
  1783. goto err;
  1784. }
  1785. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1786. goto err;
  1787. if (state->internal->dev_ver >= 0x20) {
  1788. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1789. goto err;
  1790. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1791. goto err;
  1792. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1793. goto err;
  1794. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1795. goto err;
  1796. }
  1797. k_ref = k_max;
  1798. do {
  1799. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1800. goto err;
  1801. if (stv090x_srate_srch_coarse(state) != 0) {
  1802. srate_coarse = stv090x_srate_srch_fine(state);
  1803. if (srate_coarse != 0) {
  1804. stv090x_get_lock_tmg(state);
  1805. lock = stv090x_get_dmdlock(state,
  1806. state->DemodTimeout);
  1807. } else {
  1808. lock = 0;
  1809. }
  1810. } else {
  1811. cpt_fail = 0;
  1812. agc2_ovflw = 0;
  1813. for (i = 0; i < 10; i++) {
  1814. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1815. STV090x_READ_DEMOD(state, AGC2I0);
  1816. if (agc2 >= 0xff00)
  1817. agc2_ovflw++;
  1818. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1819. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1820. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1821. cpt_fail++;
  1822. }
  1823. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1824. coarse_fail = 1;
  1825. lock = 0;
  1826. }
  1827. k_ref -= 20;
  1828. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1829. }
  1830. return lock;
  1831. err:
  1832. dprintk(FE_ERROR, 1, "I/O error");
  1833. return -1;
  1834. }
  1835. static int stv090x_chk_tmg(struct stv090x_state *state)
  1836. {
  1837. u32 reg;
  1838. s32 tmg_cpt = 0, i;
  1839. u8 freq, tmg_thh, tmg_thl;
  1840. int tmg_lock = 0;
  1841. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1842. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1843. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1844. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1845. goto err;
  1846. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1847. goto err;
  1848. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1849. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1850. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1851. goto err;
  1852. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1853. goto err;
  1854. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1855. goto err;
  1856. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1857. goto err;
  1858. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1859. goto err;
  1860. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1861. goto err;
  1862. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1863. goto err;
  1864. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1865. goto err;
  1866. msleep(10);
  1867. for (i = 0; i < 10; i++) {
  1868. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1869. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1870. tmg_cpt++;
  1871. msleep(1);
  1872. }
  1873. if (tmg_cpt >= 3)
  1874. tmg_lock = 1;
  1875. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1876. goto err;
  1877. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1878. goto err;
  1879. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1880. goto err;
  1881. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1882. goto err;
  1883. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1884. goto err;
  1885. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1886. goto err;
  1887. return tmg_lock;
  1888. err:
  1889. dprintk(FE_ERROR, 1, "I/O error");
  1890. return -1;
  1891. }
  1892. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1893. {
  1894. struct dvb_frontend *fe = &state->frontend;
  1895. u32 reg;
  1896. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1897. int lock = 0;
  1898. if (state->srate >= 10000000)
  1899. timeout_lock = timeout_dmd / 3;
  1900. else
  1901. timeout_lock = timeout_dmd / 2;
  1902. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1903. if (!lock) {
  1904. if (state->srate >= 10000000) {
  1905. if (stv090x_chk_tmg(state)) {
  1906. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1907. goto err;
  1908. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1909. goto err;
  1910. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1911. } else {
  1912. lock = 0;
  1913. }
  1914. } else {
  1915. if (state->srate <= 4000000)
  1916. car_step = 1000;
  1917. else if (state->srate <= 7000000)
  1918. car_step = 2000;
  1919. else if (state->srate <= 10000000)
  1920. car_step = 3000;
  1921. else
  1922. car_step = 5000;
  1923. steps = (state->search_range / 1000) / car_step;
  1924. steps /= 2;
  1925. steps = 2 * (steps + 1);
  1926. if (steps < 0)
  1927. steps = 2;
  1928. else if (steps > 12)
  1929. steps = 12;
  1930. cur_step = 1;
  1931. dir = 1;
  1932. if (!lock) {
  1933. freq = state->frequency;
  1934. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1935. while ((cur_step <= steps) && (!lock)) {
  1936. if (dir > 0)
  1937. freq += cur_step * car_step;
  1938. else
  1939. freq -= cur_step * car_step;
  1940. /* Setup tuner */
  1941. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1942. goto err;
  1943. if (state->config->tuner_set_frequency) {
  1944. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1945. goto err_gateoff;
  1946. }
  1947. if (state->config->tuner_set_bandwidth) {
  1948. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1949. goto err_gateoff;
  1950. }
  1951. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1952. goto err;
  1953. msleep(50);
  1954. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1955. goto err;
  1956. if (state->config->tuner_get_status) {
  1957. if (state->config->tuner_get_status(fe, &reg) < 0)
  1958. goto err_gateoff;
  1959. }
  1960. if (reg)
  1961. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1962. else
  1963. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1964. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1965. goto err;
  1966. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1967. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1968. goto err;
  1969. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1970. goto err;
  1971. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1972. goto err;
  1973. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1974. goto err;
  1975. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1976. dir *= -1;
  1977. cur_step++;
  1978. }
  1979. }
  1980. }
  1981. }
  1982. return lock;
  1983. err_gateoff:
  1984. stv090x_i2c_gate_ctrl(fe, 0);
  1985. err:
  1986. dprintk(FE_ERROR, 1, "I/O error");
  1987. return -1;
  1988. }
  1989. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  1990. {
  1991. s32 timeout, inc, steps_max, srate, car_max;
  1992. srate = state->srate;
  1993. car_max = state->search_range / 1000;
  1994. car_max += car_max / 10;
  1995. car_max = 65536 * (car_max / 2);
  1996. car_max /= (state->internal->mclk / 1000);
  1997. if (car_max > 0x4000)
  1998. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  1999. inc = srate;
  2000. inc /= state->internal->mclk / 1000;
  2001. inc *= 256;
  2002. inc *= 256;
  2003. inc /= 1000;
  2004. switch (state->search_mode) {
  2005. case STV090x_SEARCH_DVBS1:
  2006. case STV090x_SEARCH_DSS:
  2007. inc *= 3; /* freq step = 3% of srate */
  2008. timeout = 20;
  2009. break;
  2010. case STV090x_SEARCH_DVBS2:
  2011. inc *= 4;
  2012. timeout = 25;
  2013. break;
  2014. case STV090x_SEARCH_AUTO:
  2015. default:
  2016. inc *= 3;
  2017. timeout = 25;
  2018. break;
  2019. }
  2020. inc /= 100;
  2021. if ((inc > car_max) || (inc < 0))
  2022. inc = car_max / 2; /* increment <= 1/8 Mclk */
  2023. timeout *= 27500; /* 27.5 Msps reference */
  2024. if (srate > 0)
  2025. timeout /= (srate / 1000);
  2026. if ((timeout > 100) || (timeout < 0))
  2027. timeout = 100;
  2028. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  2029. if ((steps_max > 100) || (steps_max < 0)) {
  2030. steps_max = 100; /* max steps <= 100 */
  2031. inc = car_max / steps_max;
  2032. }
  2033. *freq_inc = inc;
  2034. *timeout_sw = timeout;
  2035. *steps = steps_max;
  2036. return 0;
  2037. }
  2038. static int stv090x_chk_signal(struct stv090x_state *state)
  2039. {
  2040. s32 offst_car, agc2, car_max;
  2041. int no_signal;
  2042. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  2043. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  2044. offst_car = comp2(offst_car, 16);
  2045. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  2046. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  2047. car_max = state->search_range / 1000;
  2048. car_max += (car_max / 10); /* 10% margin */
  2049. car_max = (65536 * car_max / 2);
  2050. car_max /= state->internal->mclk / 1000;
  2051. if (car_max > 0x4000)
  2052. car_max = 0x4000;
  2053. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  2054. no_signal = 1;
  2055. dprintk(FE_DEBUG, 1, "No Signal");
  2056. } else {
  2057. no_signal = 0;
  2058. dprintk(FE_DEBUG, 1, "Found Signal");
  2059. }
  2060. return no_signal;
  2061. }
  2062. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  2063. {
  2064. int no_signal, lock = 0;
  2065. s32 cpt_step = 0, offst_freq, car_max;
  2066. u32 reg;
  2067. car_max = state->search_range / 1000;
  2068. car_max += (car_max / 10);
  2069. car_max = (65536 * car_max / 2);
  2070. car_max /= (state->internal->mclk / 1000);
  2071. if (car_max > 0x4000)
  2072. car_max = 0x4000;
  2073. if (zigzag)
  2074. offst_freq = 0;
  2075. else
  2076. offst_freq = -car_max + inc;
  2077. do {
  2078. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2079. goto err;
  2080. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  2081. goto err;
  2082. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  2083. goto err;
  2084. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2085. goto err;
  2086. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2087. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  2088. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2089. goto err;
  2090. if (zigzag) {
  2091. if (offst_freq >= 0)
  2092. offst_freq = -offst_freq - 2 * inc;
  2093. else
  2094. offst_freq = -offst_freq;
  2095. } else {
  2096. offst_freq += 2 * inc;
  2097. }
  2098. cpt_step++;
  2099. lock = stv090x_get_dmdlock(state, timeout);
  2100. no_signal = stv090x_chk_signal(state);
  2101. } while ((!lock) &&
  2102. (!no_signal) &&
  2103. ((offst_freq - inc) < car_max) &&
  2104. ((offst_freq + inc) > -car_max) &&
  2105. (cpt_step < steps_max));
  2106. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2107. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  2108. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2109. goto err;
  2110. return lock;
  2111. err:
  2112. dprintk(FE_ERROR, 1, "I/O error");
  2113. return -1;
  2114. }
  2115. static int stv090x_sw_algo(struct stv090x_state *state)
  2116. {
  2117. int no_signal, zigzag, lock = 0;
  2118. u32 reg;
  2119. s32 dvbs2_fly_wheel;
  2120. s32 inc, timeout_step, trials, steps_max;
  2121. /* get params */
  2122. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
  2123. switch (state->search_mode) {
  2124. case STV090x_SEARCH_DVBS1:
  2125. case STV090x_SEARCH_DSS:
  2126. /* accelerate the frequency detector */
  2127. if (state->internal->dev_ver >= 0x20) {
  2128. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  2129. goto err;
  2130. }
  2131. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  2132. goto err;
  2133. zigzag = 0;
  2134. break;
  2135. case STV090x_SEARCH_DVBS2:
  2136. if (state->internal->dev_ver >= 0x20) {
  2137. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2138. goto err;
  2139. }
  2140. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2141. goto err;
  2142. zigzag = 1;
  2143. break;
  2144. case STV090x_SEARCH_AUTO:
  2145. default:
  2146. /* accelerate the frequency detector */
  2147. if (state->internal->dev_ver >= 0x20) {
  2148. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  2149. goto err;
  2150. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2151. goto err;
  2152. }
  2153. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
  2154. goto err;
  2155. zigzag = 0;
  2156. break;
  2157. }
  2158. trials = 0;
  2159. do {
  2160. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  2161. no_signal = stv090x_chk_signal(state);
  2162. trials++;
  2163. /*run the SW search 2 times maximum*/
  2164. if (lock || no_signal || (trials == 2)) {
  2165. /*Check if the demod is not losing lock in DVBS2*/
  2166. if (state->internal->dev_ver >= 0x20) {
  2167. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2168. goto err;
  2169. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2170. goto err;
  2171. }
  2172. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2173. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  2174. /*Check if the demod is not losing lock in DVBS2*/
  2175. msleep(timeout_step);
  2176. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2177. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2178. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  2179. msleep(timeout_step);
  2180. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2181. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2182. }
  2183. if (dvbs2_fly_wheel < 0xd) {
  2184. /*FALSE lock, The demod is loosing lock */
  2185. lock = 0;
  2186. if (trials < 2) {
  2187. if (state->internal->dev_ver >= 0x20) {
  2188. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2189. goto err;
  2190. }
  2191. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2192. goto err;
  2193. }
  2194. }
  2195. }
  2196. }
  2197. } while ((!lock) && (trials < 2) && (!no_signal));
  2198. return lock;
  2199. err:
  2200. dprintk(FE_ERROR, 1, "I/O error");
  2201. return -1;
  2202. }
  2203. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  2204. {
  2205. u32 reg;
  2206. enum stv090x_delsys delsys;
  2207. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2208. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  2209. delsys = STV090x_DVBS2;
  2210. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  2211. reg = STV090x_READ_DEMOD(state, FECM);
  2212. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  2213. delsys = STV090x_DSS;
  2214. else
  2215. delsys = STV090x_DVBS1;
  2216. } else {
  2217. delsys = STV090x_ERROR;
  2218. }
  2219. return delsys;
  2220. }
  2221. /* in Hz */
  2222. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  2223. {
  2224. s32 derot, int_1, int_2, tmp_1, tmp_2;
  2225. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  2226. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  2227. derot |= STV090x_READ_DEMOD(state, CFR0);
  2228. derot = comp2(derot, 24);
  2229. int_1 = mclk >> 12;
  2230. int_2 = derot >> 12;
  2231. /* carrier_frequency = MasterClock * Reg / 2^24 */
  2232. tmp_1 = mclk % 0x1000;
  2233. tmp_2 = derot % 0x1000;
  2234. derot = (int_1 * int_2) +
  2235. ((int_1 * tmp_2) >> 12) +
  2236. ((int_2 * tmp_1) >> 12);
  2237. return derot;
  2238. }
  2239. static int stv090x_get_viterbi(struct stv090x_state *state)
  2240. {
  2241. u32 reg, rate;
  2242. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  2243. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  2244. switch (rate) {
  2245. case 13:
  2246. state->fec = STV090x_PR12;
  2247. break;
  2248. case 18:
  2249. state->fec = STV090x_PR23;
  2250. break;
  2251. case 21:
  2252. state->fec = STV090x_PR34;
  2253. break;
  2254. case 24:
  2255. state->fec = STV090x_PR56;
  2256. break;
  2257. case 25:
  2258. state->fec = STV090x_PR67;
  2259. break;
  2260. case 26:
  2261. state->fec = STV090x_PR78;
  2262. break;
  2263. default:
  2264. state->fec = STV090x_PRERR;
  2265. break;
  2266. }
  2267. return 0;
  2268. }
  2269. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2270. {
  2271. struct dvb_frontend *fe = &state->frontend;
  2272. u8 tmg;
  2273. u32 reg;
  2274. s32 i = 0, offst_freq;
  2275. msleep(5);
  2276. if (state->algo == STV090x_BLIND_SEARCH) {
  2277. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2278. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2279. while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
  2280. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2281. msleep(5);
  2282. i += 5;
  2283. }
  2284. }
  2285. state->delsys = stv090x_get_std(state);
  2286. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2287. goto err;
  2288. if (state->config->tuner_get_frequency) {
  2289. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2290. goto err_gateoff;
  2291. }
  2292. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2293. goto err;
  2294. offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
  2295. state->frequency += offst_freq;
  2296. if (stv090x_get_viterbi(state) < 0)
  2297. goto err;
  2298. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2299. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2300. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2301. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2302. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2303. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2304. reg = STV090x_READ_DEMOD(state, FECM);
  2305. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2306. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2307. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2308. goto err;
  2309. if (state->config->tuner_get_frequency) {
  2310. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2311. goto err_gateoff;
  2312. }
  2313. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2314. goto err;
  2315. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2316. return STV090x_RANGEOK;
  2317. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2318. return STV090x_RANGEOK;
  2319. else
  2320. return STV090x_OUTOFRANGE; /* Out of Range */
  2321. } else {
  2322. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2323. return STV090x_RANGEOK;
  2324. else
  2325. return STV090x_OUTOFRANGE;
  2326. }
  2327. return STV090x_OUTOFRANGE;
  2328. err_gateoff:
  2329. stv090x_i2c_gate_ctrl(fe, 0);
  2330. err:
  2331. dprintk(FE_ERROR, 1, "I/O error");
  2332. return -1;
  2333. }
  2334. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2335. {
  2336. s32 offst_tmg;
  2337. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2338. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2339. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2340. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2341. if (!offst_tmg)
  2342. offst_tmg = 1;
  2343. offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
  2344. offst_tmg /= 320;
  2345. return offst_tmg;
  2346. }
  2347. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2348. {
  2349. u8 aclc = 0x29;
  2350. s32 i;
  2351. struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
  2352. if (state->internal->dev_ver == 0x20) {
  2353. car_loop = stv090x_s2_crl_cut20;
  2354. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
  2355. car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
  2356. } else {
  2357. /* >= Cut 3 */
  2358. car_loop = stv090x_s2_crl_cut30;
  2359. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
  2360. car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
  2361. }
  2362. if (modcod < STV090x_QPSK_12) {
  2363. i = 0;
  2364. while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
  2365. i++;
  2366. if (i >= 3)
  2367. i = 2;
  2368. } else {
  2369. i = 0;
  2370. while ((i < 14) && (modcod != car_loop[i].modcod))
  2371. i++;
  2372. if (i >= 14) {
  2373. i = 0;
  2374. while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
  2375. i++;
  2376. if (i >= 11)
  2377. i = 10;
  2378. }
  2379. }
  2380. if (modcod <= STV090x_QPSK_25) {
  2381. if (pilots) {
  2382. if (state->srate <= 3000000)
  2383. aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
  2384. else if (state->srate <= 7000000)
  2385. aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
  2386. else if (state->srate <= 15000000)
  2387. aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
  2388. else if (state->srate <= 25000000)
  2389. aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
  2390. else
  2391. aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
  2392. } else {
  2393. if (state->srate <= 3000000)
  2394. aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
  2395. else if (state->srate <= 7000000)
  2396. aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
  2397. else if (state->srate <= 15000000)
  2398. aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
  2399. else if (state->srate <= 25000000)
  2400. aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
  2401. else
  2402. aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
  2403. }
  2404. } else if (modcod <= STV090x_8PSK_910) {
  2405. if (pilots) {
  2406. if (state->srate <= 3000000)
  2407. aclc = car_loop[i].crl_pilots_on_2;
  2408. else if (state->srate <= 7000000)
  2409. aclc = car_loop[i].crl_pilots_on_5;
  2410. else if (state->srate <= 15000000)
  2411. aclc = car_loop[i].crl_pilots_on_10;
  2412. else if (state->srate <= 25000000)
  2413. aclc = car_loop[i].crl_pilots_on_20;
  2414. else
  2415. aclc = car_loop[i].crl_pilots_on_30;
  2416. } else {
  2417. if (state->srate <= 3000000)
  2418. aclc = car_loop[i].crl_pilots_off_2;
  2419. else if (state->srate <= 7000000)
  2420. aclc = car_loop[i].crl_pilots_off_5;
  2421. else if (state->srate <= 15000000)
  2422. aclc = car_loop[i].crl_pilots_off_10;
  2423. else if (state->srate <= 25000000)
  2424. aclc = car_loop[i].crl_pilots_off_20;
  2425. else
  2426. aclc = car_loop[i].crl_pilots_off_30;
  2427. }
  2428. } else { /* 16APSK and 32APSK */
  2429. if (state->srate <= 3000000)
  2430. aclc = car_loop_apsk_low[i].crl_pilots_on_2;
  2431. else if (state->srate <= 7000000)
  2432. aclc = car_loop_apsk_low[i].crl_pilots_on_5;
  2433. else if (state->srate <= 15000000)
  2434. aclc = car_loop_apsk_low[i].crl_pilots_on_10;
  2435. else if (state->srate <= 25000000)
  2436. aclc = car_loop_apsk_low[i].crl_pilots_on_20;
  2437. else
  2438. aclc = car_loop_apsk_low[i].crl_pilots_on_30;
  2439. }
  2440. return aclc;
  2441. }
  2442. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2443. {
  2444. struct stv090x_short_frame_crloop *short_crl = NULL;
  2445. s32 index = 0;
  2446. u8 aclc = 0x0b;
  2447. switch (state->modulation) {
  2448. case STV090x_QPSK:
  2449. default:
  2450. index = 0;
  2451. break;
  2452. case STV090x_8PSK:
  2453. index = 1;
  2454. break;
  2455. case STV090x_16APSK:
  2456. index = 2;
  2457. break;
  2458. case STV090x_32APSK:
  2459. index = 3;
  2460. break;
  2461. }
  2462. if (state->internal->dev_ver >= 0x30) {
  2463. /* Cut 3.0 and up */
  2464. short_crl = stv090x_s2_short_crl_cut30;
  2465. } else {
  2466. /* Cut 2.0 and up: we don't support cuts older than 2.0 */
  2467. short_crl = stv090x_s2_short_crl_cut20;
  2468. }
  2469. if (state->srate <= 3000000)
  2470. aclc = short_crl[index].crl_2;
  2471. else if (state->srate <= 7000000)
  2472. aclc = short_crl[index].crl_5;
  2473. else if (state->srate <= 15000000)
  2474. aclc = short_crl[index].crl_10;
  2475. else if (state->srate <= 25000000)
  2476. aclc = short_crl[index].crl_20;
  2477. else
  2478. aclc = short_crl[index].crl_30;
  2479. return aclc;
  2480. }
  2481. static int stv090x_optimize_track(struct stv090x_state *state)
  2482. {
  2483. struct dvb_frontend *fe = &state->frontend;
  2484. enum stv090x_rolloff rolloff;
  2485. enum stv090x_modcod modcod;
  2486. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2487. u32 reg;
  2488. srate = stv090x_get_srate(state, state->internal->mclk);
  2489. srate += stv090x_get_tmgoffst(state, srate);
  2490. switch (state->delsys) {
  2491. case STV090x_DVBS1:
  2492. case STV090x_DSS:
  2493. if (state->search_mode == STV090x_SEARCH_AUTO) {
  2494. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2495. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2496. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2497. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2498. goto err;
  2499. }
  2500. reg = STV090x_READ_DEMOD(state, DEMOD);
  2501. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2502. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
  2503. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2504. goto err;
  2505. if (state->internal->dev_ver >= 0x30) {
  2506. if (stv090x_get_viterbi(state) < 0)
  2507. goto err;
  2508. if (state->fec == STV090x_PR12) {
  2509. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
  2510. goto err;
  2511. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2512. goto err;
  2513. } else {
  2514. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
  2515. goto err;
  2516. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2517. goto err;
  2518. }
  2519. }
  2520. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2521. goto err;
  2522. break;
  2523. case STV090x_DVBS2:
  2524. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2525. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  2526. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2527. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2528. goto err;
  2529. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2530. goto err;
  2531. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2532. goto err;
  2533. if (state->frame_len == STV090x_LONG_FRAME) {
  2534. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2535. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2536. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2537. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2538. if (modcod <= STV090x_QPSK_910) {
  2539. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2540. } else if (modcod <= STV090x_8PSK_910) {
  2541. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2542. goto err;
  2543. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2544. goto err;
  2545. }
  2546. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2547. if (modcod <= STV090x_16APSK_910) {
  2548. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2549. goto err;
  2550. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2551. goto err;
  2552. } else {
  2553. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2554. goto err;
  2555. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2556. goto err;
  2557. }
  2558. }
  2559. } else {
  2560. /*Carrier loop setting for short frame*/
  2561. aclc = stv090x_optimize_carloop_short(state);
  2562. if (state->modulation == STV090x_QPSK) {
  2563. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2564. goto err;
  2565. } else if (state->modulation == STV090x_8PSK) {
  2566. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2567. goto err;
  2568. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2569. goto err;
  2570. } else if (state->modulation == STV090x_16APSK) {
  2571. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2572. goto err;
  2573. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2574. goto err;
  2575. } else if (state->modulation == STV090x_32APSK) {
  2576. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2577. goto err;
  2578. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2579. goto err;
  2580. }
  2581. }
  2582. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2583. break;
  2584. case STV090x_UNKNOWN:
  2585. default:
  2586. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2587. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2588. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2589. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2590. goto err;
  2591. break;
  2592. }
  2593. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2594. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2595. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2596. rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2597. if (state->algo == STV090x_BLIND_SEARCH) {
  2598. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2599. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2600. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2601. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2602. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2603. goto err;
  2604. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  2605. goto err;
  2606. if (stv090x_set_srate(state, srate) < 0)
  2607. goto err;
  2608. blind_tune = 1;
  2609. if (stv090x_dvbs_track_crl(state) < 0)
  2610. goto err;
  2611. }
  2612. if (state->internal->dev_ver >= 0x20) {
  2613. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2614. (state->search_mode == STV090x_SEARCH_DSS) ||
  2615. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2616. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2617. goto err;
  2618. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2619. goto err;
  2620. }
  2621. }
  2622. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2623. goto err;
  2624. /* AUTO tracking MODE */
  2625. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
  2626. goto err;
  2627. /* AUTO tracking MODE */
  2628. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
  2629. goto err;
  2630. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
  2631. (state->srate < 10000000)) {
  2632. /* update initial carrier freq with the found freq offset */
  2633. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2634. goto err;
  2635. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2636. goto err;
  2637. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2638. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
  2639. if (state->algo != STV090x_WARM_SEARCH) {
  2640. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2641. goto err;
  2642. if (state->config->tuner_set_bandwidth) {
  2643. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2644. goto err_gateoff;
  2645. }
  2646. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2647. goto err;
  2648. }
  2649. }
  2650. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2651. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2652. else
  2653. msleep(5);
  2654. stv090x_get_lock_tmg(state);
  2655. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2656. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2657. goto err;
  2658. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2659. goto err;
  2660. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2661. goto err;
  2662. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2663. goto err;
  2664. i = 0;
  2665. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2666. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2667. goto err;
  2668. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2669. goto err;
  2670. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2671. goto err;
  2672. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2673. goto err;
  2674. i++;
  2675. }
  2676. }
  2677. }
  2678. if (state->internal->dev_ver >= 0x20) {
  2679. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2680. goto err;
  2681. }
  2682. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2683. stv090x_set_vit_thtracq(state);
  2684. return 0;
  2685. err_gateoff:
  2686. stv090x_i2c_gate_ctrl(fe, 0);
  2687. err:
  2688. dprintk(FE_ERROR, 1, "I/O error");
  2689. return -1;
  2690. }
  2691. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2692. {
  2693. s32 timer = 0, lock = 0, stat;
  2694. u32 reg;
  2695. while ((timer < timeout) && (!lock)) {
  2696. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2697. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2698. switch (stat) {
  2699. case 0: /* searching */
  2700. case 1: /* first PLH detected */
  2701. default:
  2702. lock = 0;
  2703. break;
  2704. case 2: /* DVB-S2 mode */
  2705. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2706. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2707. break;
  2708. case 3: /* DVB-S1/legacy mode */
  2709. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2710. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2711. break;
  2712. }
  2713. if (!lock) {
  2714. msleep(10);
  2715. timer += 10;
  2716. }
  2717. }
  2718. return lock;
  2719. }
  2720. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2721. {
  2722. u32 reg;
  2723. s32 timer = 0;
  2724. int lock;
  2725. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2726. if (lock)
  2727. lock = stv090x_get_feclock(state, timeout_fec);
  2728. if (lock) {
  2729. lock = 0;
  2730. while ((timer < timeout_fec) && (!lock)) {
  2731. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2732. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2733. msleep(1);
  2734. timer++;
  2735. }
  2736. }
  2737. return lock;
  2738. }
  2739. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2740. {
  2741. u32 reg;
  2742. if (state->internal->dev_ver <= 0x20) {
  2743. /* rolloff to auto mode if DVBS2 */
  2744. reg = STV090x_READ_DEMOD(state, DEMOD);
  2745. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
  2746. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2747. goto err;
  2748. } else {
  2749. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2750. reg = STV090x_READ_DEMOD(state, DEMOD);
  2751. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
  2752. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2753. goto err;
  2754. }
  2755. return 0;
  2756. err:
  2757. dprintk(FE_ERROR, 1, "I/O error");
  2758. return -1;
  2759. }
  2760. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2761. {
  2762. struct dvb_frontend *fe = &state->frontend;
  2763. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2764. u32 reg;
  2765. s32 agc1_power, power_iq = 0, i;
  2766. int lock = 0, low_sr = 0, no_signal = 0;
  2767. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2768. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2769. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2770. goto err;
  2771. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2772. goto err;
  2773. if (state->internal->dev_ver >= 0x20) {
  2774. if (state->srate > 5000000) {
  2775. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2776. goto err;
  2777. } else {
  2778. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
  2779. goto err;
  2780. }
  2781. }
  2782. stv090x_get_lock_tmg(state);
  2783. if (state->algo == STV090x_BLIND_SEARCH) {
  2784. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2785. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
  2786. goto err;
  2787. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2788. goto err;
  2789. if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
  2790. goto err;
  2791. } else {
  2792. /* known srate */
  2793. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2794. goto err;
  2795. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2796. goto err;
  2797. if (state->srate < 2000000) {
  2798. /* SR < 2MSPS */
  2799. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
  2800. goto err;
  2801. } else {
  2802. /* SR >= 2Msps */
  2803. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2804. goto err;
  2805. }
  2806. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2807. goto err;
  2808. if (state->internal->dev_ver >= 0x20) {
  2809. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2810. goto err;
  2811. if (state->algo == STV090x_COLD_SEARCH)
  2812. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2813. else if (state->algo == STV090x_WARM_SEARCH)
  2814. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2815. }
  2816. /* if cold start or warm (Symbolrate is known)
  2817. * use a Narrow symbol rate scan range
  2818. */
  2819. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
  2820. goto err;
  2821. if (stv090x_set_srate(state, state->srate) < 0)
  2822. goto err;
  2823. if (stv090x_set_max_srate(state, state->internal->mclk,
  2824. state->srate) < 0)
  2825. goto err;
  2826. if (stv090x_set_min_srate(state, state->internal->mclk,
  2827. state->srate) < 0)
  2828. goto err;
  2829. if (state->srate >= 10000000)
  2830. low_sr = 0;
  2831. else
  2832. low_sr = 1;
  2833. }
  2834. /* Setup tuner */
  2835. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2836. goto err;
  2837. if (state->config->tuner_set_bbgain) {
  2838. reg = state->config->tuner_bbgain;
  2839. if (reg == 0)
  2840. reg = 10; /* default: 10dB */
  2841. if (state->config->tuner_set_bbgain(fe, reg) < 0)
  2842. goto err_gateoff;
  2843. }
  2844. if (state->config->tuner_set_frequency) {
  2845. if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
  2846. goto err_gateoff;
  2847. }
  2848. if (state->config->tuner_set_bandwidth) {
  2849. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2850. goto err_gateoff;
  2851. }
  2852. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2853. goto err;
  2854. msleep(50);
  2855. if (state->config->tuner_get_status) {
  2856. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2857. goto err;
  2858. if (state->config->tuner_get_status(fe, &reg) < 0)
  2859. goto err_gateoff;
  2860. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2861. goto err;
  2862. if (reg)
  2863. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2864. else {
  2865. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2866. return STV090x_NOCARRIER;
  2867. }
  2868. }
  2869. msleep(10);
  2870. agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
  2871. STV090x_READ_DEMOD(state, AGCIQIN0));
  2872. if (agc1_power == 0) {
  2873. /* If AGC1 integrator value is 0
  2874. * then read POWERI, POWERQ
  2875. */
  2876. for (i = 0; i < 5; i++) {
  2877. power_iq += (STV090x_READ_DEMOD(state, POWERI) +
  2878. STV090x_READ_DEMOD(state, POWERQ)) >> 1;
  2879. }
  2880. power_iq /= 5;
  2881. }
  2882. if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
  2883. dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
  2884. lock = 0;
  2885. signal_state = STV090x_NOAGC1;
  2886. } else {
  2887. reg = STV090x_READ_DEMOD(state, DEMOD);
  2888. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2889. if (state->internal->dev_ver <= 0x20) {
  2890. /* rolloff to auto mode if DVBS2 */
  2891. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
  2892. } else {
  2893. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2894. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
  2895. }
  2896. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2897. goto err;
  2898. if (stv090x_delivery_search(state) < 0)
  2899. goto err;
  2900. if (state->algo != STV090x_BLIND_SEARCH) {
  2901. if (stv090x_start_search(state) < 0)
  2902. goto err;
  2903. }
  2904. }
  2905. if (signal_state == STV090x_NOAGC1)
  2906. return signal_state;
  2907. if (state->algo == STV090x_BLIND_SEARCH)
  2908. lock = stv090x_blind_search(state);
  2909. else if (state->algo == STV090x_COLD_SEARCH)
  2910. lock = stv090x_get_coldlock(state, state->DemodTimeout);
  2911. else if (state->algo == STV090x_WARM_SEARCH)
  2912. lock = stv090x_get_dmdlock(state, state->DemodTimeout);
  2913. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2914. if (!low_sr) {
  2915. if (stv090x_chk_tmg(state))
  2916. lock = stv090x_sw_algo(state);
  2917. }
  2918. }
  2919. if (lock)
  2920. signal_state = stv090x_get_sig_params(state);
  2921. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2922. stv090x_optimize_track(state);
  2923. if (state->internal->dev_ver >= 0x20) {
  2924. /* >= Cut 2.0 :release TS reset after
  2925. * demod lock and optimized Tracking
  2926. */
  2927. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2928. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2929. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2930. goto err;
  2931. msleep(3);
  2932. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2933. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2934. goto err;
  2935. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2936. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2937. goto err;
  2938. }
  2939. lock = stv090x_get_lock(state, state->FecTimeout,
  2940. state->FecTimeout);
  2941. if (lock) {
  2942. if (state->delsys == STV090x_DVBS2) {
  2943. stv090x_set_s2rolloff(state);
  2944. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2945. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
  2946. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2947. goto err;
  2948. /* Reset DVBS2 packet delinator error counter */
  2949. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2950. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
  2951. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2952. goto err;
  2953. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2954. goto err;
  2955. } else {
  2956. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2957. goto err;
  2958. }
  2959. /* Reset the Total packet counter */
  2960. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2961. goto err;
  2962. /* Reset the packet Error counter2 */
  2963. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2964. goto err;
  2965. } else {
  2966. signal_state = STV090x_NODATA;
  2967. no_signal = stv090x_chk_signal(state);
  2968. }
  2969. }
  2970. return signal_state;
  2971. err_gateoff:
  2972. stv090x_i2c_gate_ctrl(fe, 0);
  2973. err:
  2974. dprintk(FE_ERROR, 1, "I/O error");
  2975. return -1;
  2976. }
  2977. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
  2978. {
  2979. struct stv090x_state *state = fe->demodulator_priv;
  2980. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  2981. if (p->frequency == 0)
  2982. return DVBFE_ALGO_SEARCH_INVALID;
  2983. state->delsys = props->delivery_system;
  2984. state->frequency = p->frequency;
  2985. state->srate = p->u.qpsk.symbol_rate;
  2986. state->search_mode = STV090x_SEARCH_AUTO;
  2987. state->algo = STV090x_COLD_SEARCH;
  2988. state->fec = STV090x_PRERR;
  2989. if (state->srate > 10000000) {
  2990. dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
  2991. state->search_range = 10000000;
  2992. } else {
  2993. dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
  2994. state->search_range = 5000000;
  2995. }
  2996. if (stv090x_algo(state) == STV090x_RANGEOK) {
  2997. dprintk(FE_DEBUG, 1, "Search success!");
  2998. return DVBFE_ALGO_SEARCH_SUCCESS;
  2999. } else {
  3000. dprintk(FE_DEBUG, 1, "Search failed!");
  3001. return DVBFE_ALGO_SEARCH_FAILED;
  3002. }
  3003. return DVBFE_ALGO_SEARCH_ERROR;
  3004. }
  3005. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  3006. {
  3007. struct stv090x_state *state = fe->demodulator_priv;
  3008. u32 reg;
  3009. u8 search_state;
  3010. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  3011. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  3012. switch (search_state) {
  3013. case 0: /* searching */
  3014. case 1: /* first PLH detected */
  3015. default:
  3016. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  3017. *status = 0;
  3018. break;
  3019. case 2: /* DVB-S2 mode */
  3020. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  3021. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3022. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  3023. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  3024. if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
  3025. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3026. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  3027. *status = FE_HAS_SIGNAL |
  3028. FE_HAS_CARRIER |
  3029. FE_HAS_VITERBI |
  3030. FE_HAS_SYNC |
  3031. FE_HAS_LOCK;
  3032. }
  3033. }
  3034. }
  3035. break;
  3036. case 3: /* DVB-S1/legacy mode */
  3037. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  3038. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3039. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  3040. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  3041. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  3042. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3043. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  3044. *status = FE_HAS_SIGNAL |
  3045. FE_HAS_CARRIER |
  3046. FE_HAS_VITERBI |
  3047. FE_HAS_SYNC |
  3048. FE_HAS_LOCK;
  3049. }
  3050. }
  3051. }
  3052. break;
  3053. }
  3054. return 0;
  3055. }
  3056. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  3057. {
  3058. struct stv090x_state *state = fe->demodulator_priv;
  3059. s32 count_4, count_3, count_2, count_1, count_0, count;
  3060. u32 reg, h, m, l;
  3061. enum fe_status status;
  3062. stv090x_read_status(fe, &status);
  3063. if (!(status & FE_HAS_LOCK)) {
  3064. *per = 1 << 23; /* Max PER */
  3065. } else {
  3066. /* Counter 2 */
  3067. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  3068. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  3069. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  3070. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  3071. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  3072. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  3073. *per = ((h << 16) | (m << 8) | l);
  3074. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  3075. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  3076. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  3077. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  3078. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  3079. if ((!count_4) && (!count_3)) {
  3080. count = (count_2 & 0xff) << 16;
  3081. count |= (count_1 & 0xff) << 8;
  3082. count |= count_0 & 0xff;
  3083. } else {
  3084. count = 1 << 24;
  3085. }
  3086. if (count == 0)
  3087. *per = 1;
  3088. }
  3089. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  3090. goto err;
  3091. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  3092. goto err;
  3093. return 0;
  3094. err:
  3095. dprintk(FE_ERROR, 1, "I/O error");
  3096. return -1;
  3097. }
  3098. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  3099. {
  3100. int res = 0;
  3101. int min = 0, med;
  3102. if ((val >= tab[min].read && val < tab[max].read) ||
  3103. (val >= tab[max].read && val < tab[min].read)) {
  3104. while ((max - min) > 1) {
  3105. med = (max + min) / 2;
  3106. if ((val >= tab[min].read && val < tab[med].read) ||
  3107. (val >= tab[med].read && val < tab[min].read))
  3108. max = med;
  3109. else
  3110. min = med;
  3111. }
  3112. res = ((val - tab[min].read) *
  3113. (tab[max].real - tab[min].real) /
  3114. (tab[max].read - tab[min].read)) +
  3115. tab[min].real;
  3116. } else {
  3117. if (tab[min].read < tab[max].read) {
  3118. if (val < tab[min].read)
  3119. res = tab[min].real;
  3120. else if (val >= tab[max].read)
  3121. res = tab[max].real;
  3122. } else {
  3123. if (val >= tab[min].read)
  3124. res = tab[min].real;
  3125. else if (val < tab[max].read)
  3126. res = tab[max].real;
  3127. }
  3128. }
  3129. return res;
  3130. }
  3131. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  3132. {
  3133. struct stv090x_state *state = fe->demodulator_priv;
  3134. u32 reg;
  3135. s32 agc_0, agc_1, agc;
  3136. s32 str;
  3137. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  3138. agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3139. reg = STV090x_READ_DEMOD(state, AGCIQIN0);
  3140. agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3141. agc = MAKEWORD16(agc_1, agc_0);
  3142. str = stv090x_table_lookup(stv090x_rf_tab,
  3143. ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  3144. if (agc > stv090x_rf_tab[0].read)
  3145. str = 0;
  3146. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  3147. str = -100;
  3148. *strength = (str + 100) * 0xFFFF / 100;
  3149. return 0;
  3150. }
  3151. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  3152. {
  3153. struct stv090x_state *state = fe->demodulator_priv;
  3154. u32 reg_0, reg_1, reg, i;
  3155. s32 val_0, val_1, val = 0;
  3156. u8 lock_f;
  3157. s32 div;
  3158. u32 last;
  3159. switch (state->delsys) {
  3160. case STV090x_DVBS2:
  3161. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3162. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3163. if (lock_f) {
  3164. msleep(5);
  3165. for (i = 0; i < 16; i++) {
  3166. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  3167. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  3168. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  3169. val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
  3170. val += MAKEWORD16(val_1, val_0);
  3171. msleep(1);
  3172. }
  3173. val /= 16;
  3174. last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
  3175. div = stv090x_s2cn_tab[0].read -
  3176. stv090x_s2cn_tab[last].read;
  3177. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3178. }
  3179. break;
  3180. case STV090x_DVBS1:
  3181. case STV090x_DSS:
  3182. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3183. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3184. if (lock_f) {
  3185. msleep(5);
  3186. for (i = 0; i < 16; i++) {
  3187. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  3188. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  3189. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  3190. val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
  3191. val += MAKEWORD16(val_1, val_0);
  3192. msleep(1);
  3193. }
  3194. val /= 16;
  3195. last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
  3196. div = stv090x_s1cn_tab[0].read -
  3197. stv090x_s1cn_tab[last].read;
  3198. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3199. }
  3200. break;
  3201. default:
  3202. break;
  3203. }
  3204. return 0;
  3205. }
  3206. static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  3207. {
  3208. struct stv090x_state *state = fe->demodulator_priv;
  3209. u32 reg;
  3210. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3211. switch (tone) {
  3212. case SEC_TONE_ON:
  3213. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3214. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3215. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3216. goto err;
  3217. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3218. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3219. goto err;
  3220. break;
  3221. case SEC_TONE_OFF:
  3222. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3223. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3224. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3225. goto err;
  3226. break;
  3227. default:
  3228. return -EINVAL;
  3229. }
  3230. return 0;
  3231. err:
  3232. dprintk(FE_ERROR, 1, "I/O error");
  3233. return -1;
  3234. }
  3235. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  3236. {
  3237. return DVBFE_ALGO_CUSTOM;
  3238. }
  3239. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  3240. {
  3241. struct stv090x_state *state = fe->demodulator_priv;
  3242. u32 reg, idle = 0, fifo_full = 1;
  3243. int i;
  3244. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3245. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
  3246. (state->config->diseqc_envelope_mode) ? 4 : 2);
  3247. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3248. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3249. goto err;
  3250. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3251. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3252. goto err;
  3253. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3254. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3255. goto err;
  3256. for (i = 0; i < cmd->msg_len; i++) {
  3257. while (fifo_full) {
  3258. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3259. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3260. }
  3261. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  3262. goto err;
  3263. }
  3264. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3265. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3266. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3267. goto err;
  3268. i = 0;
  3269. while ((!idle) && (i < 10)) {
  3270. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3271. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3272. msleep(10);
  3273. i++;
  3274. }
  3275. return 0;
  3276. err:
  3277. dprintk(FE_ERROR, 1, "I/O error");
  3278. return -1;
  3279. }
  3280. static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  3281. {
  3282. struct stv090x_state *state = fe->demodulator_priv;
  3283. u32 reg, idle = 0, fifo_full = 1;
  3284. u8 mode, value;
  3285. int i;
  3286. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3287. if (burst == SEC_MINI_A) {
  3288. mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
  3289. value = 0x00;
  3290. } else {
  3291. mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
  3292. value = 0xFF;
  3293. }
  3294. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
  3295. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3296. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3297. goto err;
  3298. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3299. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3300. goto err;
  3301. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3302. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3303. goto err;
  3304. while (fifo_full) {
  3305. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3306. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3307. }
  3308. if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
  3309. goto err;
  3310. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3311. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3312. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3313. goto err;
  3314. i = 0;
  3315. while ((!idle) && (i < 10)) {
  3316. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3317. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3318. msleep(10);
  3319. i++;
  3320. }
  3321. return 0;
  3322. err:
  3323. dprintk(FE_ERROR, 1, "I/O error");
  3324. return -1;
  3325. }
  3326. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  3327. {
  3328. struct stv090x_state *state = fe->demodulator_priv;
  3329. u32 reg = 0, i = 0, rx_end = 0;
  3330. while ((rx_end != 1) && (i < 10)) {
  3331. msleep(10);
  3332. i++;
  3333. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  3334. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  3335. }
  3336. if (rx_end) {
  3337. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  3338. for (i = 0; i < reply->msg_len; i++)
  3339. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  3340. }
  3341. return 0;
  3342. }
  3343. static int stv090x_sleep(struct dvb_frontend *fe)
  3344. {
  3345. struct stv090x_state *state = fe->demodulator_priv;
  3346. u32 reg;
  3347. dprintk(FE_DEBUG, 1, "Set %s to sleep",
  3348. state->device == STV0900 ? "STV0900" : "STV0903");
  3349. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3350. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3351. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3352. goto err;
  3353. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3354. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
  3355. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3356. goto err;
  3357. return 0;
  3358. err:
  3359. dprintk(FE_ERROR, 1, "I/O error");
  3360. return -1;
  3361. }
  3362. static int stv090x_wakeup(struct dvb_frontend *fe)
  3363. {
  3364. struct stv090x_state *state = fe->demodulator_priv;
  3365. u32 reg;
  3366. dprintk(FE_DEBUG, 1, "Wake %s from standby",
  3367. state->device == STV0900 ? "STV0900" : "STV0903");
  3368. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3369. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3370. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3371. goto err;
  3372. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3373. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
  3374. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3375. goto err;
  3376. return 0;
  3377. err:
  3378. dprintk(FE_ERROR, 1, "I/O error");
  3379. return -1;
  3380. }
  3381. static void stv090x_release(struct dvb_frontend *fe)
  3382. {
  3383. struct stv090x_state *state = fe->demodulator_priv;
  3384. state->internal->num_used--;
  3385. if (state->internal->num_used <= 0) {
  3386. dprintk(FE_ERROR, 1, "Actually removing");
  3387. remove_dev(state->internal);
  3388. kfree(state->internal);
  3389. }
  3390. kfree(state);
  3391. }
  3392. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3393. {
  3394. u32 reg = 0;
  3395. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3396. switch (ldpc_mode) {
  3397. case STV090x_DUAL:
  3398. default:
  3399. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3400. /* set LDPC to dual mode */
  3401. if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
  3402. goto err;
  3403. state->demod_mode = STV090x_DUAL;
  3404. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3405. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3406. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3407. goto err;
  3408. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3409. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3410. goto err;
  3411. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  3412. goto err;
  3413. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  3414. goto err;
  3415. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  3416. goto err;
  3417. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  3418. goto err;
  3419. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  3420. goto err;
  3421. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  3422. goto err;
  3423. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  3424. goto err;
  3425. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  3426. goto err;
  3427. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  3428. goto err;
  3429. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  3430. goto err;
  3431. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  3432. goto err;
  3433. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  3434. goto err;
  3435. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  3436. goto err;
  3437. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  3438. goto err;
  3439. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  3440. goto err;
  3441. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  3442. goto err;
  3443. }
  3444. break;
  3445. case STV090x_SINGLE:
  3446. if (stv090x_stop_modcod(state) < 0)
  3447. goto err;
  3448. if (stv090x_activate_modcod_single(state) < 0)
  3449. goto err;
  3450. if (state->demod == STV090x_DEMODULATOR_1) {
  3451. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3452. goto err;
  3453. } else {
  3454. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3455. goto err;
  3456. }
  3457. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3458. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3459. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3460. goto err;
  3461. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3462. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3463. goto err;
  3464. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3465. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3466. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3467. goto err;
  3468. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3469. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3470. goto err;
  3471. break;
  3472. }
  3473. return 0;
  3474. err:
  3475. dprintk(FE_ERROR, 1, "I/O error");
  3476. return -1;
  3477. }
  3478. /* return (Hz), clk in Hz*/
  3479. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3480. {
  3481. const struct stv090x_config *config = state->config;
  3482. u32 div, reg;
  3483. u8 ratio;
  3484. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3485. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3486. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3487. return (div + 1) * config->xtal / ratio; /* kHz */
  3488. }
  3489. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3490. {
  3491. const struct stv090x_config *config = state->config;
  3492. u32 reg, div, clk_sel;
  3493. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3494. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3495. div = ((clk_sel * mclk) / config->xtal) - 1;
  3496. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3497. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3498. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3499. goto err;
  3500. state->internal->mclk = stv090x_get_mclk(state);
  3501. /*Set the DiseqC frequency to 22KHz */
  3502. div = state->internal->mclk / 704000;
  3503. if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
  3504. goto err;
  3505. if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
  3506. goto err;
  3507. return 0;
  3508. err:
  3509. dprintk(FE_ERROR, 1, "I/O error");
  3510. return -1;
  3511. }
  3512. static int stv090x_set_tspath(struct stv090x_state *state)
  3513. {
  3514. u32 reg;
  3515. if (state->internal->dev_ver >= 0x20) {
  3516. switch (state->config->ts1_mode) {
  3517. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3518. case STV090x_TSMODE_DVBCI:
  3519. switch (state->config->ts2_mode) {
  3520. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3521. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3522. default:
  3523. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3524. break;
  3525. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3526. case STV090x_TSMODE_DVBCI:
  3527. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3528. goto err;
  3529. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3530. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3531. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3532. goto err;
  3533. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3534. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3535. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3536. goto err;
  3537. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3538. goto err;
  3539. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3540. goto err;
  3541. break;
  3542. }
  3543. break;
  3544. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3545. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3546. default:
  3547. switch (state->config->ts2_mode) {
  3548. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3549. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3550. default:
  3551. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3552. goto err;
  3553. break;
  3554. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3555. case STV090x_TSMODE_DVBCI:
  3556. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3557. goto err;
  3558. break;
  3559. }
  3560. break;
  3561. }
  3562. } else {
  3563. switch (state->config->ts1_mode) {
  3564. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3565. case STV090x_TSMODE_DVBCI:
  3566. switch (state->config->ts2_mode) {
  3567. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3568. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3569. default:
  3570. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  3571. break;
  3572. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3573. case STV090x_TSMODE_DVBCI:
  3574. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
  3575. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3576. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3577. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3578. goto err;
  3579. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3580. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3581. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3582. goto err;
  3583. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3584. goto err;
  3585. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3586. goto err;
  3587. break;
  3588. }
  3589. break;
  3590. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3591. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3592. default:
  3593. switch (state->config->ts2_mode) {
  3594. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3595. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3596. default:
  3597. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  3598. break;
  3599. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3600. case STV090x_TSMODE_DVBCI:
  3601. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
  3602. break;
  3603. }
  3604. break;
  3605. }
  3606. }
  3607. switch (state->config->ts1_mode) {
  3608. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3609. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3610. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3611. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3612. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3613. goto err;
  3614. break;
  3615. case STV090x_TSMODE_DVBCI:
  3616. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3617. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3618. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3619. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3620. goto err;
  3621. break;
  3622. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3623. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3624. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3625. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3626. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3627. goto err;
  3628. break;
  3629. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3630. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3631. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3632. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3633. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3634. goto err;
  3635. break;
  3636. default:
  3637. break;
  3638. }
  3639. switch (state->config->ts2_mode) {
  3640. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3641. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3642. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3643. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3644. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3645. goto err;
  3646. break;
  3647. case STV090x_TSMODE_DVBCI:
  3648. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3649. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3650. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3651. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3652. goto err;
  3653. break;
  3654. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3655. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3656. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3657. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3658. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3659. goto err;
  3660. break;
  3661. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3662. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3663. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3664. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3665. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3666. goto err;
  3667. break;
  3668. default:
  3669. break;
  3670. }
  3671. if (state->config->ts1_clk > 0) {
  3672. u32 speed;
  3673. switch (state->config->ts1_mode) {
  3674. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3675. case STV090x_TSMODE_DVBCI:
  3676. default:
  3677. speed = state->internal->mclk /
  3678. (state->config->ts1_clk / 4);
  3679. if (speed < 0x08)
  3680. speed = 0x08;
  3681. if (speed > 0xFF)
  3682. speed = 0xFF;
  3683. break;
  3684. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3685. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3686. speed = state->internal->mclk /
  3687. (state->config->ts1_clk / 32);
  3688. if (speed < 0x20)
  3689. speed = 0x20;
  3690. if (speed > 0xFF)
  3691. speed = 0xFF;
  3692. break;
  3693. }
  3694. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3695. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3696. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3697. goto err;
  3698. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
  3699. goto err;
  3700. }
  3701. if (state->config->ts2_clk > 0) {
  3702. u32 speed;
  3703. switch (state->config->ts2_mode) {
  3704. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3705. case STV090x_TSMODE_DVBCI:
  3706. default:
  3707. speed = state->internal->mclk /
  3708. (state->config->ts2_clk / 4);
  3709. if (speed < 0x08)
  3710. speed = 0x08;
  3711. if (speed > 0xFF)
  3712. speed = 0xFF;
  3713. break;
  3714. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3715. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3716. speed = state->internal->mclk /
  3717. (state->config->ts2_clk / 32);
  3718. if (speed < 0x20)
  3719. speed = 0x20;
  3720. if (speed > 0xFF)
  3721. speed = 0xFF;
  3722. break;
  3723. }
  3724. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3725. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3726. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3727. goto err;
  3728. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
  3729. goto err;
  3730. }
  3731. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3732. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3733. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3734. goto err;
  3735. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3736. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3737. goto err;
  3738. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3739. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3740. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3741. goto err;
  3742. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3743. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3744. goto err;
  3745. return 0;
  3746. err:
  3747. dprintk(FE_ERROR, 1, "I/O error");
  3748. return -1;
  3749. }
  3750. static int stv090x_init(struct dvb_frontend *fe)
  3751. {
  3752. struct stv090x_state *state = fe->demodulator_priv;
  3753. const struct stv090x_config *config = state->config;
  3754. u32 reg;
  3755. if (state->internal->mclk == 0) {
  3756. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  3757. msleep(5);
  3758. if (stv090x_write_reg(state, STV090x_SYNTCTRL,
  3759. 0x20 | config->clk_mode) < 0)
  3760. goto err;
  3761. stv090x_get_mclk(state);
  3762. }
  3763. if (stv090x_wakeup(fe) < 0) {
  3764. dprintk(FE_ERROR, 1, "Error waking device");
  3765. goto err;
  3766. }
  3767. if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
  3768. goto err;
  3769. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  3770. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  3771. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  3772. goto err;
  3773. reg = STV090x_READ_DEMOD(state, DEMOD);
  3774. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  3775. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  3776. goto err;
  3777. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  3778. goto err;
  3779. if (config->tuner_set_mode) {
  3780. if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
  3781. goto err_gateoff;
  3782. }
  3783. if (config->tuner_init) {
  3784. if (config->tuner_init(fe) < 0)
  3785. goto err_gateoff;
  3786. }
  3787. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  3788. goto err;
  3789. if (stv090x_set_tspath(state) < 0)
  3790. goto err;
  3791. return 0;
  3792. err_gateoff:
  3793. stv090x_i2c_gate_ctrl(fe, 0);
  3794. err:
  3795. dprintk(FE_ERROR, 1, "I/O error");
  3796. return -1;
  3797. }
  3798. static int stv090x_setup(struct dvb_frontend *fe)
  3799. {
  3800. struct stv090x_state *state = fe->demodulator_priv;
  3801. const struct stv090x_config *config = state->config;
  3802. const struct stv090x_reg *stv090x_initval = NULL;
  3803. const struct stv090x_reg *stv090x_cut20_val = NULL;
  3804. unsigned long t1_size = 0, t2_size = 0;
  3805. u32 reg = 0;
  3806. int i;
  3807. if (state->device == STV0900) {
  3808. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  3809. stv090x_initval = stv0900_initval;
  3810. t1_size = ARRAY_SIZE(stv0900_initval);
  3811. stv090x_cut20_val = stv0900_cut20_val;
  3812. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  3813. } else if (state->device == STV0903) {
  3814. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  3815. stv090x_initval = stv0903_initval;
  3816. t1_size = ARRAY_SIZE(stv0903_initval);
  3817. stv090x_cut20_val = stv0903_cut20_val;
  3818. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  3819. }
  3820. /* STV090x init */
  3821. /* Stop Demod */
  3822. if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
  3823. goto err;
  3824. if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
  3825. goto err;
  3826. msleep(5);
  3827. /* Set No Tuner Mode */
  3828. if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
  3829. goto err;
  3830. if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
  3831. goto err;
  3832. /* I2C repeater OFF */
  3833. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  3834. if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
  3835. goto err;
  3836. if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
  3837. goto err;
  3838. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  3839. goto err;
  3840. msleep(5);
  3841. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  3842. goto err;
  3843. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  3844. goto err;
  3845. msleep(5);
  3846. /* write initval */
  3847. dprintk(FE_DEBUG, 1, "Setting up initial values");
  3848. for (i = 0; i < t1_size; i++) {
  3849. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  3850. goto err;
  3851. }
  3852. state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
  3853. if (state->internal->dev_ver >= 0x20) {
  3854. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3855. goto err;
  3856. /* write cut20_val*/
  3857. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  3858. for (i = 0; i < t2_size; i++) {
  3859. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  3860. goto err;
  3861. }
  3862. } else if (state->internal->dev_ver < 0x20) {
  3863. dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
  3864. state->internal->dev_ver);
  3865. goto err;
  3866. } else if (state->internal->dev_ver > 0x30) {
  3867. /* we shouldn't bail out from here */
  3868. dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
  3869. state->internal->dev_ver);
  3870. }
  3871. /* ADC1 range */
  3872. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3873. STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
  3874. (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
  3875. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3876. goto err;
  3877. /* ADC2 range */
  3878. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  3879. STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
  3880. (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
  3881. if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
  3882. goto err;
  3883. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  3884. goto err;
  3885. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  3886. goto err;
  3887. return 0;
  3888. err:
  3889. dprintk(FE_ERROR, 1, "I/O error");
  3890. return -1;
  3891. }
  3892. static struct dvb_frontend_ops stv090x_ops = {
  3893. .info = {
  3894. .name = "STV090x Multistandard",
  3895. .type = FE_QPSK,
  3896. .frequency_min = 950000,
  3897. .frequency_max = 2150000,
  3898. .frequency_stepsize = 0,
  3899. .frequency_tolerance = 0,
  3900. .symbol_rate_min = 1000000,
  3901. .symbol_rate_max = 45000000,
  3902. .caps = FE_CAN_INVERSION_AUTO |
  3903. FE_CAN_FEC_AUTO |
  3904. FE_CAN_QPSK |
  3905. FE_CAN_2G_MODULATION
  3906. },
  3907. .release = stv090x_release,
  3908. .init = stv090x_init,
  3909. .sleep = stv090x_sleep,
  3910. .get_frontend_algo = stv090x_frontend_algo,
  3911. .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
  3912. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  3913. .diseqc_send_burst = stv090x_send_diseqc_burst,
  3914. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  3915. .set_tone = stv090x_set_tone,
  3916. .search = stv090x_search,
  3917. .read_status = stv090x_read_status,
  3918. .read_ber = stv090x_read_per,
  3919. .read_signal_strength = stv090x_read_signal_strength,
  3920. .read_snr = stv090x_read_cnr
  3921. };
  3922. struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
  3923. struct i2c_adapter *i2c,
  3924. enum stv090x_demodulator demod)
  3925. {
  3926. struct stv090x_state *state = NULL;
  3927. struct stv090x_dev *temp_int;
  3928. state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
  3929. if (state == NULL)
  3930. goto error;
  3931. state->verbose = &verbose;
  3932. state->config = config;
  3933. state->i2c = i2c;
  3934. state->frontend.ops = stv090x_ops;
  3935. state->frontend.demodulator_priv = state;
  3936. state->demod = demod;
  3937. state->demod_mode = config->demod_mode; /* Single or Dual mode */
  3938. state->device = config->device;
  3939. state->rolloff = STV090x_RO_35; /* default */
  3940. temp_int = find_dev(state->i2c,
  3941. state->config->address);
  3942. if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
  3943. state->internal = temp_int->internal;
  3944. state->internal->num_used++;
  3945. dprintk(FE_INFO, 1, "Found Internal Structure!");
  3946. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
  3947. state->device == STV0900 ? "STV0900" : "STV0903",
  3948. demod,
  3949. state->internal->dev_ver);
  3950. return &state->frontend;
  3951. } else {
  3952. state->internal = kmalloc(sizeof(struct stv090x_internal),
  3953. GFP_KERNEL);
  3954. temp_int = append_internal(state->internal);
  3955. state->internal->num_used = 1;
  3956. state->internal->mclk = 0;
  3957. state->internal->dev_ver = 0;
  3958. state->internal->i2c_adap = state->i2c;
  3959. state->internal->i2c_addr = state->config->address;
  3960. dprintk(FE_INFO, 1, "Create New Internal Structure!");
  3961. }
  3962. mutex_init(&state->internal->demod_lock);
  3963. mutex_init(&state->internal->tuner_lock);
  3964. if (stv090x_sleep(&state->frontend) < 0) {
  3965. dprintk(FE_ERROR, 1, "Error putting device to sleep");
  3966. goto error;
  3967. }
  3968. if (stv090x_setup(&state->frontend) < 0) {
  3969. dprintk(FE_ERROR, 1, "Error setting up device");
  3970. goto error;
  3971. }
  3972. if (stv090x_wakeup(&state->frontend) < 0) {
  3973. dprintk(FE_ERROR, 1, "Error waking device");
  3974. goto error;
  3975. }
  3976. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
  3977. state->device == STV0900 ? "STV0900" : "STV0903",
  3978. demod,
  3979. state->internal->dev_ver);
  3980. return &state->frontend;
  3981. error:
  3982. kfree(state);
  3983. return NULL;
  3984. }
  3985. EXPORT_SYMBOL(stv090x_attach);
  3986. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  3987. MODULE_AUTHOR("Manu Abraham");
  3988. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  3989. MODULE_LICENSE("GPL");