mb86a16.c 46 KB

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  1. /*
  2. Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
  3. Copyright (C) Manu Abraham (abraham.manu@gmail.com)
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include "dvb_frontend.h"
  21. #include "mb86a16.h"
  22. #include "mb86a16_priv.h"
  23. unsigned int verbose = 5;
  24. module_param(verbose, int, 0644);
  25. #define ABS(x) ((x) < 0 ? (-x) : (x))
  26. struct mb86a16_state {
  27. struct i2c_adapter *i2c_adap;
  28. const struct mb86a16_config *config;
  29. struct dvb_frontend frontend;
  30. /* tuning parameters */
  31. int frequency;
  32. int srate;
  33. /* Internal stuff */
  34. int master_clk;
  35. int deci;
  36. int csel;
  37. int rsel;
  38. };
  39. #define MB86A16_ERROR 0
  40. #define MB86A16_NOTICE 1
  41. #define MB86A16_INFO 2
  42. #define MB86A16_DEBUG 3
  43. #define dprintk(x, y, z, format, arg...) do { \
  44. if (z) { \
  45. if ((x > MB86A16_ERROR) && (x > y)) \
  46. printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
  47. else if ((x > MB86A16_NOTICE) && (x > y)) \
  48. printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
  49. else if ((x > MB86A16_INFO) && (x > y)) \
  50. printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
  51. else if ((x > MB86A16_DEBUG) && (x > y)) \
  52. printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
  53. } else { \
  54. if (x > y) \
  55. printk(format, ##arg); \
  56. } \
  57. } while (0)
  58. #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
  59. #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
  60. static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
  61. {
  62. int ret;
  63. u8 buf[] = { reg, val };
  64. struct i2c_msg msg = {
  65. .addr = state->config->demod_address,
  66. .flags = 0,
  67. .buf = buf,
  68. .len = 2
  69. };
  70. dprintk(verbose, MB86A16_DEBUG, 1,
  71. "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
  72. state->config->demod_address, buf[0], buf[1]);
  73. ret = i2c_transfer(state->i2c_adap, &msg, 1);
  74. return (ret != 1) ? -EREMOTEIO : 0;
  75. }
  76. static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
  77. {
  78. int ret;
  79. u8 b0[] = { reg };
  80. u8 b1[] = { 0 };
  81. struct i2c_msg msg[] = {
  82. {
  83. .addr = state->config->demod_address,
  84. .flags = 0,
  85. .buf = b0,
  86. .len = 1
  87. }, {
  88. .addr = state->config->demod_address,
  89. .flags = I2C_M_RD,
  90. .buf = b1,
  91. .len = 1
  92. }
  93. };
  94. ret = i2c_transfer(state->i2c_adap, msg, 2);
  95. if (ret != 2) {
  96. dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
  97. reg, ret);
  98. return -EREMOTEIO;
  99. }
  100. *val = b1[0];
  101. return ret;
  102. }
  103. static int CNTM_set(struct mb86a16_state *state,
  104. unsigned char timint1,
  105. unsigned char timint2,
  106. unsigned char cnext)
  107. {
  108. unsigned char val;
  109. val = (timint1 << 4) | (timint2 << 2) | cnext;
  110. if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
  111. goto err;
  112. return 0;
  113. err:
  114. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  115. return -EREMOTEIO;
  116. }
  117. static int smrt_set(struct mb86a16_state *state, int rate)
  118. {
  119. int tmp ;
  120. int m ;
  121. unsigned char STOFS0, STOFS1;
  122. m = 1 << state->deci;
  123. tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
  124. STOFS0 = tmp & 0x0ff;
  125. STOFS1 = (tmp & 0xf00) >> 8;
  126. if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
  127. (state->csel << 1) |
  128. state->rsel) < 0)
  129. goto err;
  130. if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
  131. goto err;
  132. if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
  133. goto err;
  134. return 0;
  135. err:
  136. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  137. return -1;
  138. }
  139. static int srst(struct mb86a16_state *state)
  140. {
  141. if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
  142. goto err;
  143. return 0;
  144. err:
  145. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  146. return -EREMOTEIO;
  147. }
  148. static int afcex_data_set(struct mb86a16_state *state,
  149. unsigned char AFCEX_L,
  150. unsigned char AFCEX_H)
  151. {
  152. if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
  153. goto err;
  154. if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
  155. goto err;
  156. return 0;
  157. err:
  158. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  159. return -1;
  160. }
  161. static int afcofs_data_set(struct mb86a16_state *state,
  162. unsigned char AFCEX_L,
  163. unsigned char AFCEX_H)
  164. {
  165. if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
  166. goto err;
  167. if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
  168. goto err;
  169. return 0;
  170. err:
  171. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  172. return -EREMOTEIO;
  173. }
  174. static int stlp_set(struct mb86a16_state *state,
  175. unsigned char STRAS,
  176. unsigned char STRBS)
  177. {
  178. if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
  179. goto err;
  180. return 0;
  181. err:
  182. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  183. return -EREMOTEIO;
  184. }
  185. static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
  186. {
  187. if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
  188. goto err;
  189. if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
  190. goto err;
  191. return 0;
  192. err:
  193. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  194. return -EREMOTEIO;
  195. }
  196. static int initial_set(struct mb86a16_state *state)
  197. {
  198. if (stlp_set(state, 5, 7))
  199. goto err;
  200. udelay(100);
  201. if (afcex_data_set(state, 0, 0))
  202. goto err;
  203. udelay(100);
  204. if (afcofs_data_set(state, 0, 0))
  205. goto err;
  206. udelay(100);
  207. if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
  208. goto err;
  209. if (mb86a16_write(state, 0x2f, 0x21) < 0)
  210. goto err;
  211. if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
  212. goto err;
  213. if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
  214. goto err;
  215. if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
  216. goto err;
  217. if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
  218. goto err;
  219. if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
  220. goto err;
  221. if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
  222. goto err;
  223. if (mb86a16_write(state, 0x54, 0xff) < 0)
  224. goto err;
  225. if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
  226. goto err;
  227. return 0;
  228. err:
  229. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  230. return -EREMOTEIO;
  231. }
  232. static int S01T_set(struct mb86a16_state *state,
  233. unsigned char s1t,
  234. unsigned s0t)
  235. {
  236. if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
  237. goto err;
  238. return 0;
  239. err:
  240. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  241. return -EREMOTEIO;
  242. }
  243. static int EN_set(struct mb86a16_state *state,
  244. int cren,
  245. int afcen)
  246. {
  247. unsigned char val;
  248. val = 0x7a | (cren << 7) | (afcen << 2);
  249. if (mb86a16_write(state, 0x49, val) < 0)
  250. goto err;
  251. return 0;
  252. err:
  253. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  254. return -EREMOTEIO;
  255. }
  256. static int AFCEXEN_set(struct mb86a16_state *state,
  257. int afcexen,
  258. int smrt)
  259. {
  260. unsigned char AFCA ;
  261. if (smrt > 18875)
  262. AFCA = 4;
  263. else if (smrt > 9375)
  264. AFCA = 3;
  265. else if (smrt > 2250)
  266. AFCA = 2;
  267. else
  268. AFCA = 1;
  269. if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
  270. goto err;
  271. return 0;
  272. err:
  273. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  274. return -EREMOTEIO;
  275. }
  276. static int DAGC_data_set(struct mb86a16_state *state,
  277. unsigned char DAGCA,
  278. unsigned char DAGCW)
  279. {
  280. if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
  281. goto err;
  282. return 0;
  283. err:
  284. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  285. return -EREMOTEIO;
  286. }
  287. static void smrt_info_get(struct mb86a16_state *state, int rate)
  288. {
  289. if (rate >= 37501) {
  290. state->deci = 0; state->csel = 0; state->rsel = 0;
  291. } else if (rate >= 30001) {
  292. state->deci = 0; state->csel = 0; state->rsel = 1;
  293. } else if (rate >= 26251) {
  294. state->deci = 0; state->csel = 1; state->rsel = 0;
  295. } else if (rate >= 22501) {
  296. state->deci = 0; state->csel = 1; state->rsel = 1;
  297. } else if (rate >= 18751) {
  298. state->deci = 1; state->csel = 0; state->rsel = 0;
  299. } else if (rate >= 15001) {
  300. state->deci = 1; state->csel = 0; state->rsel = 1;
  301. } else if (rate >= 13126) {
  302. state->deci = 1; state->csel = 1; state->rsel = 0;
  303. } else if (rate >= 11251) {
  304. state->deci = 1; state->csel = 1; state->rsel = 1;
  305. } else if (rate >= 9376) {
  306. state->deci = 2; state->csel = 0; state->rsel = 0;
  307. } else if (rate >= 7501) {
  308. state->deci = 2; state->csel = 0; state->rsel = 1;
  309. } else if (rate >= 6563) {
  310. state->deci = 2; state->csel = 1; state->rsel = 0;
  311. } else if (rate >= 5626) {
  312. state->deci = 2; state->csel = 1; state->rsel = 1;
  313. } else if (rate >= 4688) {
  314. state->deci = 3; state->csel = 0; state->rsel = 0;
  315. } else if (rate >= 3751) {
  316. state->deci = 3; state->csel = 0; state->rsel = 1;
  317. } else if (rate >= 3282) {
  318. state->deci = 3; state->csel = 1; state->rsel = 0;
  319. } else if (rate >= 2814) {
  320. state->deci = 3; state->csel = 1; state->rsel = 1;
  321. } else if (rate >= 2344) {
  322. state->deci = 4; state->csel = 0; state->rsel = 0;
  323. } else if (rate >= 1876) {
  324. state->deci = 4; state->csel = 0; state->rsel = 1;
  325. } else if (rate >= 1641) {
  326. state->deci = 4; state->csel = 1; state->rsel = 0;
  327. } else if (rate >= 1407) {
  328. state->deci = 4; state->csel = 1; state->rsel = 1;
  329. } else if (rate >= 1172) {
  330. state->deci = 5; state->csel = 0; state->rsel = 0;
  331. } else if (rate >= 939) {
  332. state->deci = 5; state->csel = 0; state->rsel = 1;
  333. } else if (rate >= 821) {
  334. state->deci = 5; state->csel = 1; state->rsel = 0;
  335. } else {
  336. state->deci = 5; state->csel = 1; state->rsel = 1;
  337. }
  338. if (state->csel == 0)
  339. state->master_clk = 92000;
  340. else
  341. state->master_clk = 61333;
  342. }
  343. static int signal_det(struct mb86a16_state *state,
  344. int smrt,
  345. unsigned char *SIG)
  346. {
  347. int ret ;
  348. int smrtd ;
  349. int wait_sym ;
  350. u32 wait_t;
  351. unsigned char S[3] ;
  352. int i ;
  353. if (*SIG > 45) {
  354. if (CNTM_set(state, 2, 1, 2) < 0) {
  355. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  356. return -1;
  357. }
  358. wait_sym = 40000;
  359. } else {
  360. if (CNTM_set(state, 3, 1, 2) < 0) {
  361. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  362. return -1;
  363. }
  364. wait_sym = 80000;
  365. }
  366. for (i = 0; i < 3; i++) {
  367. if (i == 0)
  368. smrtd = smrt * 98 / 100;
  369. else if (i == 1)
  370. smrtd = smrt;
  371. else
  372. smrtd = smrt * 102 / 100;
  373. smrt_info_get(state, smrtd);
  374. smrt_set(state, smrtd);
  375. srst(state);
  376. wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
  377. if (wait_t == 0)
  378. wait_t = 1;
  379. msleep_interruptible(10);
  380. if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
  381. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  382. return -EREMOTEIO;
  383. }
  384. }
  385. if ((S[1] > S[0] * 112 / 100) &&
  386. (S[1] > S[2] * 112 / 100)) {
  387. ret = 1;
  388. } else {
  389. ret = 0;
  390. }
  391. *SIG = S[1];
  392. if (CNTM_set(state, 0, 1, 2) < 0) {
  393. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  394. return -1;
  395. }
  396. return ret;
  397. }
  398. static int rf_val_set(struct mb86a16_state *state,
  399. int f,
  400. int smrt,
  401. unsigned char R)
  402. {
  403. unsigned char C, F, B;
  404. int M;
  405. unsigned char rf_val[5];
  406. int ack = -1;
  407. if (smrt > 37750)
  408. C = 1;
  409. else if (smrt > 18875)
  410. C = 2;
  411. else if (smrt > 5500)
  412. C = 3;
  413. else
  414. C = 4;
  415. if (smrt > 30500)
  416. F = 3;
  417. else if (smrt > 9375)
  418. F = 1;
  419. else if (smrt > 4625)
  420. F = 0;
  421. else
  422. F = 2;
  423. if (f < 1060)
  424. B = 0;
  425. else if (f < 1175)
  426. B = 1;
  427. else if (f < 1305)
  428. B = 2;
  429. else if (f < 1435)
  430. B = 3;
  431. else if (f < 1570)
  432. B = 4;
  433. else if (f < 1715)
  434. B = 5;
  435. else if (f < 1845)
  436. B = 6;
  437. else if (f < 1980)
  438. B = 7;
  439. else if (f < 2080)
  440. B = 8;
  441. else
  442. B = 9;
  443. M = f * (1 << R) / 2;
  444. rf_val[0] = 0x01 | (C << 3) | (F << 1);
  445. rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
  446. rf_val[2] = (M & 0x00ff0) >> 4;
  447. rf_val[3] = ((M & 0x0000f) << 4) | B;
  448. /* Frequency Set */
  449. if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
  450. ack = 0;
  451. if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
  452. ack = 0;
  453. if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
  454. ack = 0;
  455. if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
  456. ack = 0;
  457. if (mb86a16_write(state, 0x25, 0x01) < 0)
  458. ack = 0;
  459. if (ack == 0) {
  460. dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
  461. return -EREMOTEIO;
  462. }
  463. return 0;
  464. }
  465. static int afcerr_chk(struct mb86a16_state *state)
  466. {
  467. unsigned char AFCM_L, AFCM_H ;
  468. int AFCM ;
  469. int afcm, afcerr ;
  470. if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
  471. goto err;
  472. if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
  473. goto err;
  474. AFCM = (AFCM_H << 8) + AFCM_L;
  475. if (AFCM > 2048)
  476. afcm = AFCM - 4096;
  477. else
  478. afcm = AFCM;
  479. afcerr = afcm * state->master_clk / 8192;
  480. return afcerr;
  481. err:
  482. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  483. return -EREMOTEIO;
  484. }
  485. static int dagcm_val_get(struct mb86a16_state *state)
  486. {
  487. int DAGCM;
  488. unsigned char DAGCM_H, DAGCM_L;
  489. if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
  490. goto err;
  491. if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
  492. goto err;
  493. DAGCM = (DAGCM_H << 8) + DAGCM_L;
  494. return DAGCM;
  495. err:
  496. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  497. return -EREMOTEIO;
  498. }
  499. static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
  500. {
  501. u8 stat, stat2;
  502. struct mb86a16_state *state = fe->demodulator_priv;
  503. *status = 0;
  504. if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
  505. goto err;
  506. if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
  507. goto err;
  508. if ((stat > 25) && (stat2 > 25))
  509. *status |= FE_HAS_SIGNAL;
  510. if ((stat > 45) && (stat2 > 45))
  511. *status |= FE_HAS_CARRIER;
  512. if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
  513. goto err;
  514. if (stat & 0x01)
  515. *status |= FE_HAS_SYNC;
  516. if (stat & 0x01)
  517. *status |= FE_HAS_VITERBI;
  518. if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
  519. goto err;
  520. if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
  521. *status |= FE_HAS_LOCK;
  522. return 0;
  523. err:
  524. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  525. return -EREMOTEIO;
  526. }
  527. static int sync_chk(struct mb86a16_state *state,
  528. unsigned char *VIRM)
  529. {
  530. unsigned char val;
  531. int sync;
  532. if (mb86a16_read(state, 0x0d, &val) != 2)
  533. goto err;
  534. dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
  535. sync = val & 0x01;
  536. *VIRM = (val & 0x1c) >> 2;
  537. return sync;
  538. err:
  539. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  540. return -EREMOTEIO;
  541. }
  542. static int freqerr_chk(struct mb86a16_state *state,
  543. int fTP,
  544. int smrt,
  545. int unit)
  546. {
  547. unsigned char CRM, AFCML, AFCMH;
  548. unsigned char temp1, temp2, temp3;
  549. int crm, afcm, AFCM;
  550. int crrerr, afcerr; /* kHz */
  551. int frqerr; /* MHz */
  552. int afcen, afcexen = 0;
  553. int R, M, fOSC, fOSC_OFS;
  554. if (mb86a16_read(state, 0x43, &CRM) != 2)
  555. goto err;
  556. if (CRM > 127)
  557. crm = CRM - 256;
  558. else
  559. crm = CRM;
  560. crrerr = smrt * crm / 256;
  561. if (mb86a16_read(state, 0x49, &temp1) != 2)
  562. goto err;
  563. afcen = (temp1 & 0x04) >> 2;
  564. if (afcen == 0) {
  565. if (mb86a16_read(state, 0x2a, &temp1) != 2)
  566. goto err;
  567. afcexen = (temp1 & 0x20) >> 5;
  568. }
  569. if (afcen == 1) {
  570. if (mb86a16_read(state, 0x0e, &AFCML) != 2)
  571. goto err;
  572. if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
  573. goto err;
  574. } else if (afcexen == 1) {
  575. if (mb86a16_read(state, 0x2b, &AFCML) != 2)
  576. goto err;
  577. if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
  578. goto err;
  579. }
  580. if ((afcen == 1) || (afcexen == 1)) {
  581. smrt_info_get(state, smrt);
  582. AFCM = ((AFCMH & 0x01) << 8) + AFCML;
  583. if (AFCM > 255)
  584. afcm = AFCM - 512;
  585. else
  586. afcm = AFCM;
  587. afcerr = afcm * state->master_clk / 8192;
  588. } else
  589. afcerr = 0;
  590. if (mb86a16_read(state, 0x22, &temp1) != 2)
  591. goto err;
  592. if (mb86a16_read(state, 0x23, &temp2) != 2)
  593. goto err;
  594. if (mb86a16_read(state, 0x24, &temp3) != 2)
  595. goto err;
  596. R = (temp1 & 0xe0) >> 5;
  597. M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
  598. if (R == 0)
  599. fOSC = 2 * M;
  600. else
  601. fOSC = M;
  602. fOSC_OFS = fOSC - fTP;
  603. if (unit == 0) { /* MHz */
  604. if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
  605. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
  606. else
  607. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
  608. } else { /* kHz */
  609. frqerr = crrerr + afcerr + fOSC_OFS * 1000;
  610. }
  611. return frqerr;
  612. err:
  613. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  614. return -EREMOTEIO;
  615. }
  616. static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
  617. {
  618. unsigned char R;
  619. if (smrt > 9375)
  620. R = 0;
  621. else
  622. R = 1;
  623. return R;
  624. }
  625. static void swp_info_get(struct mb86a16_state *state,
  626. int fOSC_start,
  627. int smrt,
  628. int v, int R,
  629. int swp_ofs,
  630. int *fOSC,
  631. int *afcex_freq,
  632. unsigned char *AFCEX_L,
  633. unsigned char *AFCEX_H)
  634. {
  635. int AFCEX ;
  636. int crnt_swp_freq ;
  637. crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
  638. if (R == 0)
  639. *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
  640. else
  641. *fOSC = (crnt_swp_freq + 500) / 1000;
  642. if (*fOSC >= crnt_swp_freq)
  643. *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
  644. else
  645. *afcex_freq = crnt_swp_freq - *fOSC * 1000;
  646. AFCEX = *afcex_freq * 8192 / state->master_clk;
  647. *AFCEX_L = AFCEX & 0x00ff;
  648. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  649. }
  650. static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
  651. int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
  652. {
  653. int swp_freq ;
  654. if ((i % 2 == 1) && (v <= vmax)) {
  655. /* positive v (case 1) */
  656. if ((v - 1 == vmin) &&
  657. (*(V + 30 + v) >= 0) &&
  658. (*(V + 30 + v - 1) >= 0) &&
  659. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  660. (*(V + 30 + v - 1) > SIGMIN)) {
  661. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  662. *SIG1 = *(V + 30 + v - 1);
  663. } else if ((v == vmax) &&
  664. (*(V + 30 + v) >= 0) &&
  665. (*(V + 30 + v - 1) >= 0) &&
  666. (*(V + 30 + v) > *(V + 30 + v - 1)) &&
  667. (*(V + 30 + v) > SIGMIN)) {
  668. /* (case 2) */
  669. swp_freq = fOSC * 1000 + afcex_freq;
  670. *SIG1 = *(V + 30 + v);
  671. } else if ((*(V + 30 + v) > 0) &&
  672. (*(V + 30 + v - 1) > 0) &&
  673. (*(V + 30 + v - 2) > 0) &&
  674. (*(V + 30 + v - 3) > 0) &&
  675. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  676. (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
  677. ((*(V + 30 + v - 1) > SIGMIN) ||
  678. (*(V + 30 + v - 2) > SIGMIN))) {
  679. /* (case 3) */
  680. if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
  681. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  682. *SIG1 = *(V + 30 + v - 1);
  683. } else {
  684. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
  685. *SIG1 = *(V + 30 + v - 2);
  686. }
  687. } else if ((v == vmax) &&
  688. (*(V + 30 + v) >= 0) &&
  689. (*(V + 30 + v - 1) >= 0) &&
  690. (*(V + 30 + v - 2) >= 0) &&
  691. (*(V + 30 + v) > *(V + 30 + v - 2)) &&
  692. (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
  693. ((*(V + 30 + v) > SIGMIN) ||
  694. (*(V + 30 + v - 1) > SIGMIN))) {
  695. /* (case 4) */
  696. if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
  697. swp_freq = fOSC * 1000 + afcex_freq;
  698. *SIG1 = *(V + 30 + v);
  699. } else {
  700. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  701. *SIG1 = *(V + 30 + v - 1);
  702. }
  703. } else {
  704. swp_freq = -1 ;
  705. }
  706. } else if ((i % 2 == 0) && (v >= vmin)) {
  707. /* Negative v (case 1) */
  708. if ((*(V + 30 + v) > 0) &&
  709. (*(V + 30 + v + 1) > 0) &&
  710. (*(V + 30 + v + 2) > 0) &&
  711. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  712. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  713. (*(V + 30 + v + 1) > SIGMIN)) {
  714. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  715. *SIG1 = *(V + 30 + v + 1);
  716. } else if ((v + 1 == vmax) &&
  717. (*(V + 30 + v) >= 0) &&
  718. (*(V + 30 + v + 1) >= 0) &&
  719. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  720. (*(V + 30 + v + 1) > SIGMIN)) {
  721. /* (case 2) */
  722. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  723. *SIG1 = *(V + 30 + v);
  724. } else if ((v == vmin) &&
  725. (*(V + 30 + v) > 0) &&
  726. (*(V + 30 + v + 1) > 0) &&
  727. (*(V + 30 + v + 2) > 0) &&
  728. (*(V + 30 + v) > *(V + 30 + v + 1)) &&
  729. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  730. (*(V + 30 + v) > SIGMIN)) {
  731. /* (case 3) */
  732. swp_freq = fOSC * 1000 + afcex_freq;
  733. *SIG1 = *(V + 30 + v);
  734. } else if ((*(V + 30 + v) >= 0) &&
  735. (*(V + 30 + v + 1) >= 0) &&
  736. (*(V + 30 + v + 2) >= 0) &&
  737. (*(V + 30 + v + 3) >= 0) &&
  738. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  739. (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
  740. ((*(V + 30 + v + 1) > SIGMIN) ||
  741. (*(V + 30 + v + 2) > SIGMIN))) {
  742. /* (case 4) */
  743. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  744. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  745. *SIG1 = *(V + 30 + v + 1);
  746. } else {
  747. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  748. *SIG1 = *(V + 30 + v + 2);
  749. }
  750. } else if ((*(V + 30 + v) >= 0) &&
  751. (*(V + 30 + v + 1) >= 0) &&
  752. (*(V + 30 + v + 2) >= 0) &&
  753. (*(V + 30 + v + 3) >= 0) &&
  754. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  755. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  756. (*(V + 30 + v) > *(V + 30 + v + 3)) &&
  757. (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
  758. ((*(V + 30 + v) > SIGMIN) ||
  759. (*(V + 30 + v + 1) > SIGMIN))) {
  760. /* (case 5) */
  761. if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
  762. swp_freq = fOSC * 1000 + afcex_freq;
  763. *SIG1 = *(V + 30 + v);
  764. } else {
  765. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  766. *SIG1 = *(V + 30 + v + 1);
  767. }
  768. } else if ((v + 2 == vmin) &&
  769. (*(V + 30 + v) >= 0) &&
  770. (*(V + 30 + v + 1) >= 0) &&
  771. (*(V + 30 + v + 2) >= 0) &&
  772. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  773. (*(V + 30 + v + 2) > *(V + 30 + v)) &&
  774. ((*(V + 30 + v + 1) > SIGMIN) ||
  775. (*(V + 30 + v + 2) > SIGMIN))) {
  776. /* (case 6) */
  777. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  778. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  779. *SIG1 = *(V + 30 + v + 1);
  780. } else {
  781. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  782. *SIG1 = *(V + 30 + v + 2);
  783. }
  784. } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
  785. swp_freq = fOSC * 1000;
  786. *SIG1 = *(V + 30 + v);
  787. } else
  788. swp_freq = -1;
  789. } else
  790. swp_freq = -1;
  791. return swp_freq;
  792. }
  793. static void swp_info_get2(struct mb86a16_state *state,
  794. int smrt,
  795. int R,
  796. int swp_freq,
  797. int *afcex_freq,
  798. int *fOSC,
  799. unsigned char *AFCEX_L,
  800. unsigned char *AFCEX_H)
  801. {
  802. int AFCEX ;
  803. if (R == 0)
  804. *fOSC = (swp_freq + 1000) / 2000 * 2;
  805. else
  806. *fOSC = (swp_freq + 500) / 1000;
  807. if (*fOSC >= swp_freq)
  808. *afcex_freq = *fOSC * 1000 - swp_freq;
  809. else
  810. *afcex_freq = swp_freq - *fOSC * 1000;
  811. AFCEX = *afcex_freq * 8192 / state->master_clk;
  812. *AFCEX_L = AFCEX & 0x00ff;
  813. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  814. }
  815. static void afcex_info_get(struct mb86a16_state *state,
  816. int afcex_freq,
  817. unsigned char *AFCEX_L,
  818. unsigned char *AFCEX_H)
  819. {
  820. int AFCEX ;
  821. AFCEX = afcex_freq * 8192 / state->master_clk;
  822. *AFCEX_L = AFCEX & 0x00ff;
  823. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  824. }
  825. static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
  826. {
  827. /* SLOCK0 = 0 */
  828. if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
  829. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  830. return -EREMOTEIO;
  831. }
  832. return 0;
  833. }
  834. static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
  835. {
  836. /* Viterbi Rate, IQ Settings */
  837. if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
  838. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  839. return -EREMOTEIO;
  840. }
  841. return 0;
  842. }
  843. static int FEC_srst(struct mb86a16_state *state)
  844. {
  845. if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
  846. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  847. return -EREMOTEIO;
  848. }
  849. return 0;
  850. }
  851. static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
  852. {
  853. if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
  854. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  855. return -EREMOTEIO;
  856. }
  857. return 0;
  858. }
  859. static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
  860. {
  861. if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
  862. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  863. return -EREMOTEIO;
  864. }
  865. return 0;
  866. }
  867. static int mb86a16_set_fe(struct mb86a16_state *state)
  868. {
  869. u8 agcval, cnmval;
  870. int i, j;
  871. int fOSC = 0;
  872. int fOSC_start = 0;
  873. int wait_t;
  874. int fcp;
  875. int swp_ofs;
  876. int V[60];
  877. u8 SIG1MIN;
  878. unsigned char CREN, AFCEN, AFCEXEN;
  879. unsigned char SIG1;
  880. unsigned char TIMINT1, TIMINT2, TIMEXT;
  881. unsigned char S0T, S1T;
  882. unsigned char S2T;
  883. /* unsigned char S2T, S3T; */
  884. unsigned char S4T, S5T;
  885. unsigned char AFCEX_L, AFCEX_H;
  886. unsigned char R;
  887. unsigned char VIRM;
  888. unsigned char ETH, VIA;
  889. unsigned char junk;
  890. int loop;
  891. int ftemp;
  892. int v, vmax, vmin;
  893. int vmax_his, vmin_his;
  894. int swp_freq, prev_swp_freq[20];
  895. int prev_freq_num;
  896. int signal_dupl;
  897. int afcex_freq;
  898. int signal;
  899. int afcerr;
  900. int temp_freq, delta_freq;
  901. int dagcm[4];
  902. int smrt_d;
  903. /* int freq_err; */
  904. int n;
  905. int ret = -1;
  906. int sync;
  907. dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
  908. fcp = 3000;
  909. swp_ofs = state->srate / 4;
  910. for (i = 0; i < 60; i++)
  911. V[i] = -1;
  912. for (i = 0; i < 20; i++)
  913. prev_swp_freq[i] = 0;
  914. SIG1MIN = 25;
  915. for (n = 0; ((n < 3) && (ret == -1)); n++) {
  916. SEQ_set(state, 0);
  917. iq_vt_set(state, 0);
  918. CREN = 0;
  919. AFCEN = 0;
  920. AFCEXEN = 1;
  921. TIMINT1 = 0;
  922. TIMINT2 = 1;
  923. TIMEXT = 2;
  924. S1T = 0;
  925. S0T = 0;
  926. if (initial_set(state) < 0) {
  927. dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
  928. return -1;
  929. }
  930. if (DAGC_data_set(state, 3, 2) < 0) {
  931. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  932. return -1;
  933. }
  934. if (EN_set(state, CREN, AFCEN) < 0) {
  935. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  936. return -1; /* (0, 0) */
  937. }
  938. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  939. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  940. return -1; /* (1, smrt) = (1, symbolrate) */
  941. }
  942. if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
  943. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
  944. return -1; /* (0, 1, 2) */
  945. }
  946. if (S01T_set(state, S1T, S0T) < 0) {
  947. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  948. return -1; /* (0, 0) */
  949. }
  950. smrt_info_get(state, state->srate);
  951. if (smrt_set(state, state->srate) < 0) {
  952. dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
  953. return -1;
  954. }
  955. R = vco_dev_get(state, state->srate);
  956. if (R == 1)
  957. fOSC_start = state->frequency;
  958. else if (R == 0) {
  959. if (state->frequency % 2 == 0) {
  960. fOSC_start = state->frequency;
  961. } else {
  962. fOSC_start = state->frequency + 1;
  963. if (fOSC_start > 2150)
  964. fOSC_start = state->frequency - 1;
  965. }
  966. }
  967. loop = 1;
  968. ftemp = fOSC_start * 1000;
  969. vmax = 0 ;
  970. while (loop == 1) {
  971. ftemp = ftemp + swp_ofs;
  972. vmax++;
  973. /* Upper bound */
  974. if (ftemp > 2150000) {
  975. loop = 0;
  976. vmax--;
  977. } else {
  978. if ((ftemp == 2150000) ||
  979. (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
  980. loop = 0;
  981. }
  982. }
  983. loop = 1;
  984. ftemp = fOSC_start * 1000;
  985. vmin = 0 ;
  986. while (loop == 1) {
  987. ftemp = ftemp - swp_ofs;
  988. vmin--;
  989. /* Lower bound */
  990. if (ftemp < 950000) {
  991. loop = 0;
  992. vmin++;
  993. } else {
  994. if ((ftemp == 950000) ||
  995. (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
  996. loop = 0;
  997. }
  998. }
  999. wait_t = (8000 + state->srate / 2) / state->srate;
  1000. if (wait_t == 0)
  1001. wait_t = 1;
  1002. i = 0;
  1003. j = 0;
  1004. prev_freq_num = 0;
  1005. loop = 1;
  1006. signal = 0;
  1007. vmax_his = 0;
  1008. vmin_his = 0;
  1009. v = 0;
  1010. while (loop == 1) {
  1011. swp_info_get(state, fOSC_start, state->srate,
  1012. v, R, swp_ofs, &fOSC,
  1013. &afcex_freq, &AFCEX_L, &AFCEX_H);
  1014. udelay(100);
  1015. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1016. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1017. return -1;
  1018. }
  1019. udelay(100);
  1020. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1021. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1022. return -1;
  1023. }
  1024. if (srst(state) < 0) {
  1025. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1026. return -1;
  1027. }
  1028. msleep_interruptible(wait_t);
  1029. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1030. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1031. return -1;
  1032. }
  1033. V[30 + v] = SIG1 ;
  1034. swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
  1035. SIG1MIN, fOSC, afcex_freq,
  1036. swp_ofs, &SIG1); /* changed */
  1037. signal_dupl = 0;
  1038. for (j = 0; j < prev_freq_num; j++) {
  1039. if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
  1040. signal_dupl = 1;
  1041. dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
  1042. }
  1043. }
  1044. if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
  1045. dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
  1046. prev_swp_freq[prev_freq_num] = swp_freq;
  1047. prev_freq_num++;
  1048. swp_info_get2(state, state->srate, R, swp_freq,
  1049. &afcex_freq, &fOSC,
  1050. &AFCEX_L, &AFCEX_H);
  1051. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1052. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1053. return -1;
  1054. }
  1055. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1056. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1057. return -1;
  1058. }
  1059. signal = signal_det(state, state->srate, &SIG1);
  1060. if (signal == 1) {
  1061. dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
  1062. loop = 0;
  1063. } else {
  1064. dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
  1065. smrt_info_get(state, state->srate);
  1066. if (smrt_set(state, state->srate) < 0) {
  1067. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1068. return -1;
  1069. }
  1070. }
  1071. }
  1072. if (v > vmax)
  1073. vmax_his = 1 ;
  1074. if (v < vmin)
  1075. vmin_his = 1 ;
  1076. i++;
  1077. if ((i % 2 == 1) && (vmax_his == 1))
  1078. i++;
  1079. if ((i % 2 == 0) && (vmin_his == 1))
  1080. i++;
  1081. if (i % 2 == 1)
  1082. v = (i + 1) / 2;
  1083. else
  1084. v = -i / 2;
  1085. if ((vmax_his == 1) && (vmin_his == 1))
  1086. loop = 0 ;
  1087. }
  1088. if (signal == 1) {
  1089. dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
  1090. S1T = 7 ;
  1091. S0T = 1 ;
  1092. CREN = 0 ;
  1093. AFCEN = 1 ;
  1094. AFCEXEN = 0 ;
  1095. if (S01T_set(state, S1T, S0T) < 0) {
  1096. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1097. return -1;
  1098. }
  1099. smrt_info_get(state, state->srate);
  1100. if (smrt_set(state, state->srate) < 0) {
  1101. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1102. return -1;
  1103. }
  1104. if (EN_set(state, CREN, AFCEN) < 0) {
  1105. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1106. return -1;
  1107. }
  1108. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1109. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1110. return -1;
  1111. }
  1112. afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
  1113. if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1114. dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
  1115. return -1;
  1116. }
  1117. if (srst(state) < 0) {
  1118. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1119. return -1;
  1120. }
  1121. /* delay 4~200 */
  1122. wait_t = 200000 / state->master_clk + 200000 / state->srate;
  1123. msleep(wait_t);
  1124. afcerr = afcerr_chk(state);
  1125. if (afcerr == -1)
  1126. return -1;
  1127. swp_freq = fOSC * 1000 + afcerr ;
  1128. AFCEXEN = 1 ;
  1129. if (state->srate >= 1500)
  1130. smrt_d = state->srate / 3;
  1131. else
  1132. smrt_d = state->srate / 2;
  1133. smrt_info_get(state, smrt_d);
  1134. if (smrt_set(state, smrt_d) < 0) {
  1135. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1136. return -1;
  1137. }
  1138. if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
  1139. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1140. return -1;
  1141. }
  1142. R = vco_dev_get(state, smrt_d);
  1143. if (DAGC_data_set(state, 2, 0) < 0) {
  1144. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1145. return -1;
  1146. }
  1147. for (i = 0; i < 3; i++) {
  1148. temp_freq = swp_freq + (i - 1) * state->srate / 8;
  1149. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1150. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1151. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1152. return -1;
  1153. }
  1154. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1155. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1156. return -1;
  1157. }
  1158. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1159. msleep(wait_t);
  1160. dagcm[i] = dagcm_val_get(state);
  1161. }
  1162. if ((dagcm[0] > dagcm[1]) &&
  1163. (dagcm[0] > dagcm[2]) &&
  1164. (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
  1165. temp_freq = swp_freq - 2 * state->srate / 8;
  1166. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1167. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1168. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1169. return -1;
  1170. }
  1171. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1172. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1173. return -1;
  1174. }
  1175. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1176. msleep(wait_t);
  1177. dagcm[3] = dagcm_val_get(state);
  1178. if (dagcm[3] > dagcm[1])
  1179. delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
  1180. else
  1181. delta_freq = 0;
  1182. } else if ((dagcm[2] > dagcm[1]) &&
  1183. (dagcm[2] > dagcm[0]) &&
  1184. (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
  1185. temp_freq = swp_freq + 2 * state->srate / 8;
  1186. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1187. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1188. dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
  1189. return -1;
  1190. }
  1191. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1192. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1193. return -1;
  1194. }
  1195. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1196. msleep(wait_t);
  1197. dagcm[3] = dagcm_val_get(state);
  1198. if (dagcm[3] > dagcm[1])
  1199. delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
  1200. else
  1201. delta_freq = 0 ;
  1202. } else {
  1203. delta_freq = 0 ;
  1204. }
  1205. dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
  1206. swp_freq += delta_freq;
  1207. dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
  1208. if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
  1209. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
  1210. } else {
  1211. S1T = 0;
  1212. S0T = 3;
  1213. CREN = 1;
  1214. AFCEN = 0;
  1215. AFCEXEN = 1;
  1216. if (S01T_set(state, S1T, S0T) < 0) {
  1217. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1218. return -1;
  1219. }
  1220. if (DAGC_data_set(state, 0, 0) < 0) {
  1221. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1222. return -1;
  1223. }
  1224. R = vco_dev_get(state, state->srate);
  1225. smrt_info_get(state, state->srate);
  1226. if (smrt_set(state, state->srate) < 0) {
  1227. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1228. return -1;
  1229. }
  1230. if (EN_set(state, CREN, AFCEN) < 0) {
  1231. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1232. return -1;
  1233. }
  1234. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1235. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1236. return -1;
  1237. }
  1238. swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1239. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1240. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1241. return -1;
  1242. }
  1243. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1244. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1245. return -1;
  1246. }
  1247. if (srst(state) < 0) {
  1248. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1249. return -1;
  1250. }
  1251. wait_t = 7 + (10000 + state->srate / 2) / state->srate;
  1252. if (wait_t == 0)
  1253. wait_t = 1;
  1254. msleep_interruptible(wait_t);
  1255. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1256. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1257. return -EREMOTEIO;
  1258. }
  1259. if (SIG1 > 110) {
  1260. S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
  1261. wait_t = 7 + (917504 + state->srate / 2) / state->srate;
  1262. } else if (SIG1 > 105) {
  1263. S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1264. wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
  1265. } else if (SIG1 > 85) {
  1266. S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1267. wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
  1268. } else if (SIG1 > 65) {
  1269. S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1270. wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
  1271. } else {
  1272. S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1273. wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
  1274. }
  1275. wait_t *= 2; /* FOS */
  1276. S2T_set(state, S2T);
  1277. S45T_set(state, S4T, S5T);
  1278. Vi_set(state, ETH, VIA);
  1279. srst(state);
  1280. msleep_interruptible(wait_t);
  1281. sync = sync_chk(state, &VIRM);
  1282. dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
  1283. if (VIRM) {
  1284. if (VIRM == 4) {
  1285. /* 5/6 */
  1286. if (SIG1 > 110)
  1287. wait_t = (786432 + state->srate / 2) / state->srate;
  1288. else
  1289. wait_t = (1572864 + state->srate / 2) / state->srate;
  1290. if (state->srate < 5000)
  1291. /* FIXME ! , should be a long wait ! */
  1292. msleep_interruptible(wait_t);
  1293. else
  1294. msleep_interruptible(wait_t);
  1295. if (sync_chk(state, &junk) == 0) {
  1296. iq_vt_set(state, 1);
  1297. FEC_srst(state);
  1298. }
  1299. }
  1300. /* 1/2, 2/3, 3/4, 7/8 */
  1301. if (SIG1 > 110)
  1302. wait_t = (786432 + state->srate / 2) / state->srate;
  1303. else
  1304. wait_t = (1572864 + state->srate / 2) / state->srate;
  1305. msleep_interruptible(wait_t);
  1306. SEQ_set(state, 1);
  1307. } else {
  1308. dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
  1309. SEQ_set(state, 1);
  1310. ret = -1;
  1311. }
  1312. }
  1313. } else {
  1314. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
  1315. ret = -1;
  1316. }
  1317. sync = sync_chk(state, &junk);
  1318. if (sync) {
  1319. dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
  1320. freqerr_chk(state, state->frequency, state->srate, 1);
  1321. ret = 0;
  1322. break;
  1323. }
  1324. }
  1325. mb86a16_read(state, 0x15, &agcval);
  1326. mb86a16_read(state, 0x26, &cnmval);
  1327. dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
  1328. return ret;
  1329. }
  1330. static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
  1331. struct dvb_diseqc_master_cmd *cmd)
  1332. {
  1333. struct mb86a16_state *state = fe->demodulator_priv;
  1334. int i;
  1335. u8 regs;
  1336. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1337. goto err;
  1338. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1339. goto err;
  1340. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1341. goto err;
  1342. regs = 0x18;
  1343. if (cmd->msg_len > 5 || cmd->msg_len < 4)
  1344. return -EINVAL;
  1345. for (i = 0; i < cmd->msg_len; i++) {
  1346. if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
  1347. goto err;
  1348. regs++;
  1349. }
  1350. i += 0x90;
  1351. msleep_interruptible(10);
  1352. if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
  1353. goto err;
  1354. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1355. goto err;
  1356. return 0;
  1357. err:
  1358. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1359. return -EREMOTEIO;
  1360. }
  1361. static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  1362. {
  1363. struct mb86a16_state *state = fe->demodulator_priv;
  1364. switch (burst) {
  1365. case SEC_MINI_A:
  1366. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1367. MB86A16_DCC1_TBEN |
  1368. MB86A16_DCC1_TBO) < 0)
  1369. goto err;
  1370. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1371. goto err;
  1372. break;
  1373. case SEC_MINI_B:
  1374. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1375. MB86A16_DCC1_TBEN) < 0)
  1376. goto err;
  1377. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1378. goto err;
  1379. break;
  1380. }
  1381. return 0;
  1382. err:
  1383. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1384. return -EREMOTEIO;
  1385. }
  1386. static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  1387. {
  1388. struct mb86a16_state *state = fe->demodulator_priv;
  1389. switch (tone) {
  1390. case SEC_TONE_ON:
  1391. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
  1392. goto err;
  1393. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1394. MB86A16_DCC1_CTOE) < 0)
  1395. goto err;
  1396. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1397. goto err;
  1398. break;
  1399. case SEC_TONE_OFF:
  1400. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1401. goto err;
  1402. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1403. goto err;
  1404. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1405. goto err;
  1406. break;
  1407. default:
  1408. return -EINVAL;
  1409. }
  1410. return 0;
  1411. err:
  1412. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1413. return -EREMOTEIO;
  1414. }
  1415. static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe,
  1416. struct dvb_frontend_parameters *p)
  1417. {
  1418. struct mb86a16_state *state = fe->demodulator_priv;
  1419. state->frequency = p->frequency / 1000;
  1420. state->srate = p->u.qpsk.symbol_rate / 1000;
  1421. if (!mb86a16_set_fe(state)) {
  1422. dprintk(verbose, MB86A16_ERROR, 1, "Succesfully acquired LOCK");
  1423. return DVBFE_ALGO_SEARCH_SUCCESS;
  1424. }
  1425. dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
  1426. return DVBFE_ALGO_SEARCH_FAILED;
  1427. }
  1428. static void mb86a16_release(struct dvb_frontend *fe)
  1429. {
  1430. struct mb86a16_state *state = fe->demodulator_priv;
  1431. kfree(state);
  1432. }
  1433. static int mb86a16_init(struct dvb_frontend *fe)
  1434. {
  1435. return 0;
  1436. }
  1437. static int mb86a16_sleep(struct dvb_frontend *fe)
  1438. {
  1439. return 0;
  1440. }
  1441. static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
  1442. {
  1443. u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
  1444. u32 timer;
  1445. struct mb86a16_state *state = fe->demodulator_priv;
  1446. *ber = 0;
  1447. if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
  1448. goto err;
  1449. if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
  1450. goto err;
  1451. if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
  1452. goto err;
  1453. if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
  1454. goto err;
  1455. if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
  1456. goto err;
  1457. /* BER monitor invalid when BER_EN = 0 */
  1458. if (ber_mon & 0x04) {
  1459. /* coarse, fast calculation */
  1460. *ber = ber_tab & 0x1f;
  1461. dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
  1462. if (ber_mon & 0x01) {
  1463. /*
  1464. * BER_SEL = 1, The monitored BER is the estimated
  1465. * value with a Reed-Solomon decoder error amount at
  1466. * the deinterleaver output.
  1467. * monitored BER is expressed as a 20 bit output in total
  1468. */
  1469. ber_rst = ber_mon >> 3;
  1470. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1471. if (ber_rst == 0)
  1472. timer = 12500000;
  1473. if (ber_rst == 1)
  1474. timer = 25000000;
  1475. if (ber_rst == 2)
  1476. timer = 50000000;
  1477. if (ber_rst == 3)
  1478. timer = 100000000;
  1479. *ber /= timer;
  1480. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1481. } else {
  1482. /*
  1483. * BER_SEL = 0, The monitored BER is the estimated
  1484. * value with a Viterbi decoder error amount at the
  1485. * QPSK demodulator output.
  1486. * monitored BER is expressed as a 24 bit output in total
  1487. */
  1488. ber_tim = ber_mon >> 1;
  1489. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1490. if (ber_tim == 0)
  1491. timer = 16;
  1492. if (ber_tim == 1)
  1493. timer = 24;
  1494. *ber /= 2 ^ timer;
  1495. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1496. }
  1497. }
  1498. return 0;
  1499. err:
  1500. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1501. return -EREMOTEIO;
  1502. }
  1503. static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  1504. {
  1505. u8 agcm = 0;
  1506. struct mb86a16_state *state = fe->demodulator_priv;
  1507. *strength = 0;
  1508. if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
  1509. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1510. return -EREMOTEIO;
  1511. }
  1512. *strength = ((0xff - agcm) * 100) / 256;
  1513. dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
  1514. *strength = (0xffff - 0xff) + agcm;
  1515. return 0;
  1516. }
  1517. struct cnr {
  1518. u8 cn_reg;
  1519. u8 cn_val;
  1520. };
  1521. static const struct cnr cnr_tab[] = {
  1522. { 35, 2 },
  1523. { 40, 3 },
  1524. { 50, 4 },
  1525. { 60, 5 },
  1526. { 70, 6 },
  1527. { 80, 7 },
  1528. { 92, 8 },
  1529. { 103, 9 },
  1530. { 115, 10 },
  1531. { 138, 12 },
  1532. { 162, 15 },
  1533. { 180, 18 },
  1534. { 185, 19 },
  1535. { 189, 20 },
  1536. { 195, 22 },
  1537. { 199, 24 },
  1538. { 201, 25 },
  1539. { 202, 26 },
  1540. { 203, 27 },
  1541. { 205, 28 },
  1542. { 208, 30 }
  1543. };
  1544. static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
  1545. {
  1546. struct mb86a16_state *state = fe->demodulator_priv;
  1547. int i = 0;
  1548. int low_tide = 2, high_tide = 30, q_level;
  1549. u8 cn;
  1550. *snr = 0;
  1551. if (mb86a16_read(state, 0x26, &cn) != 2) {
  1552. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1553. return -EREMOTEIO;
  1554. }
  1555. for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
  1556. if (cn < cnr_tab[i].cn_reg) {
  1557. *snr = cnr_tab[i].cn_val;
  1558. break;
  1559. }
  1560. }
  1561. q_level = (*snr * 100) / (high_tide - low_tide);
  1562. dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
  1563. *snr = (0xffff - 0xff) + *snr;
  1564. return 0;
  1565. }
  1566. static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  1567. {
  1568. u8 dist;
  1569. struct mb86a16_state *state = fe->demodulator_priv;
  1570. if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
  1571. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1572. return -EREMOTEIO;
  1573. }
  1574. *ucblocks = dist;
  1575. return 0;
  1576. }
  1577. static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
  1578. {
  1579. return DVBFE_ALGO_CUSTOM;
  1580. }
  1581. static struct dvb_frontend_ops mb86a16_ops = {
  1582. .info = {
  1583. .name = "Fujitsu MB86A16 DVB-S",
  1584. .type = FE_QPSK,
  1585. .frequency_min = 950000,
  1586. .frequency_max = 2150000,
  1587. .frequency_stepsize = 3000,
  1588. .frequency_tolerance = 0,
  1589. .symbol_rate_min = 1000000,
  1590. .symbol_rate_max = 45000000,
  1591. .symbol_rate_tolerance = 500,
  1592. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  1593. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
  1594. FE_CAN_FEC_7_8 | FE_CAN_QPSK |
  1595. FE_CAN_FEC_AUTO
  1596. },
  1597. .release = mb86a16_release,
  1598. .get_frontend_algo = mb86a16_frontend_algo,
  1599. .search = mb86a16_search,
  1600. .read_status = mb86a16_read_status,
  1601. .init = mb86a16_init,
  1602. .sleep = mb86a16_sleep,
  1603. .read_status = mb86a16_read_status,
  1604. .read_ber = mb86a16_read_ber,
  1605. .read_signal_strength = mb86a16_read_signal_strength,
  1606. .read_snr = mb86a16_read_snr,
  1607. .read_ucblocks = mb86a16_read_ucblocks,
  1608. .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
  1609. .diseqc_send_burst = mb86a16_send_diseqc_burst,
  1610. .set_tone = mb86a16_set_tone,
  1611. };
  1612. struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
  1613. struct i2c_adapter *i2c_adap)
  1614. {
  1615. u8 dev_id = 0;
  1616. struct mb86a16_state *state = NULL;
  1617. state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
  1618. if (state == NULL)
  1619. goto error;
  1620. state->config = config;
  1621. state->i2c_adap = i2c_adap;
  1622. mb86a16_read(state, 0x7f, &dev_id);
  1623. if (dev_id != 0xfe)
  1624. goto error;
  1625. memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
  1626. state->frontend.demodulator_priv = state;
  1627. state->frontend.ops.set_voltage = state->config->set_voltage;
  1628. return &state->frontend;
  1629. error:
  1630. kfree(state);
  1631. return NULL;
  1632. }
  1633. EXPORT_SYMBOL(mb86a16_attach);
  1634. MODULE_LICENSE("GPL");
  1635. MODULE_AUTHOR("Manu Abraham");