radeon_ring.c 12 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include "drmP.h"
  30. #include "radeon_drm.h"
  31. #include "radeon_reg.h"
  32. #include "radeon.h"
  33. #include "atom.h"
  34. int radeon_debugfs_ib_init(struct radeon_device *rdev);
  35. void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
  36. {
  37. struct radeon_ib *ib, *n;
  38. list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
  39. list_del(&ib->list);
  40. vfree(ib->ptr);
  41. kfree(ib);
  42. }
  43. }
  44. void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
  45. {
  46. struct radeon_ib *bib;
  47. bib = kmalloc(sizeof(*bib), GFP_KERNEL);
  48. if (bib == NULL)
  49. return;
  50. bib->ptr = vmalloc(ib->length_dw * 4);
  51. if (bib->ptr == NULL) {
  52. kfree(bib);
  53. return;
  54. }
  55. memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
  56. bib->length_dw = ib->length_dw;
  57. mutex_lock(&rdev->ib_pool.mutex);
  58. list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
  59. mutex_unlock(&rdev->ib_pool.mutex);
  60. }
  61. /*
  62. * IB.
  63. */
  64. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
  65. {
  66. struct radeon_fence *fence;
  67. struct radeon_ib *nib;
  68. int r = 0, i, c;
  69. *ib = NULL;
  70. r = radeon_fence_create(rdev, &fence);
  71. if (r) {
  72. dev_err(rdev->dev, "failed to create fence for new IB\n");
  73. return r;
  74. }
  75. mutex_lock(&rdev->ib_pool.mutex);
  76. for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
  77. i &= (RADEON_IB_POOL_SIZE - 1);
  78. if (rdev->ib_pool.ibs[i].free) {
  79. nib = &rdev->ib_pool.ibs[i];
  80. break;
  81. }
  82. }
  83. if (nib == NULL) {
  84. /* This should never happen, it means we allocated all
  85. * IB and haven't scheduled one yet, return EBUSY to
  86. * userspace hoping that on ioctl recall we get better
  87. * luck
  88. */
  89. dev_err(rdev->dev, "no free indirect buffer !\n");
  90. mutex_unlock(&rdev->ib_pool.mutex);
  91. radeon_fence_unref(&fence);
  92. return -EBUSY;
  93. }
  94. rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
  95. nib->free = false;
  96. if (nib->fence) {
  97. mutex_unlock(&rdev->ib_pool.mutex);
  98. r = radeon_fence_wait(nib->fence, false);
  99. if (r) {
  100. dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
  101. nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
  102. mutex_lock(&rdev->ib_pool.mutex);
  103. nib->free = true;
  104. mutex_unlock(&rdev->ib_pool.mutex);
  105. radeon_fence_unref(&fence);
  106. return r;
  107. }
  108. mutex_lock(&rdev->ib_pool.mutex);
  109. }
  110. radeon_fence_unref(&nib->fence);
  111. nib->fence = fence;
  112. nib->length_dw = 0;
  113. mutex_unlock(&rdev->ib_pool.mutex);
  114. *ib = nib;
  115. return 0;
  116. }
  117. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
  118. {
  119. struct radeon_ib *tmp = *ib;
  120. *ib = NULL;
  121. if (tmp == NULL) {
  122. return;
  123. }
  124. if (!tmp->fence->emited)
  125. radeon_fence_unref(&tmp->fence);
  126. mutex_lock(&rdev->ib_pool.mutex);
  127. tmp->free = true;
  128. mutex_unlock(&rdev->ib_pool.mutex);
  129. }
  130. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
  131. {
  132. int r = 0;
  133. if (!ib->length_dw || !rdev->cp.ready) {
  134. /* TODO: Nothings in the ib we should report. */
  135. DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
  136. return -EINVAL;
  137. }
  138. /* 64 dwords should be enough for fence too */
  139. r = radeon_ring_lock(rdev, 64);
  140. if (r) {
  141. DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
  142. return r;
  143. }
  144. radeon_ring_ib_execute(rdev, ib);
  145. radeon_fence_emit(rdev, ib->fence);
  146. mutex_lock(&rdev->ib_pool.mutex);
  147. /* once scheduled IB is considered free and protected by the fence */
  148. ib->free = true;
  149. mutex_unlock(&rdev->ib_pool.mutex);
  150. radeon_ring_unlock_commit(rdev);
  151. return 0;
  152. }
  153. int radeon_ib_pool_init(struct radeon_device *rdev)
  154. {
  155. void *ptr;
  156. uint64_t gpu_addr;
  157. int i;
  158. int r = 0;
  159. if (rdev->ib_pool.robj)
  160. return 0;
  161. INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
  162. /* Allocate 1M object buffer */
  163. r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
  164. true, RADEON_GEM_DOMAIN_GTT,
  165. &rdev->ib_pool.robj);
  166. if (r) {
  167. DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
  168. return r;
  169. }
  170. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  171. if (unlikely(r != 0))
  172. return r;
  173. r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
  174. if (r) {
  175. radeon_bo_unreserve(rdev->ib_pool.robj);
  176. DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
  177. return r;
  178. }
  179. r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
  180. radeon_bo_unreserve(rdev->ib_pool.robj);
  181. if (r) {
  182. DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
  183. return r;
  184. }
  185. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  186. unsigned offset;
  187. offset = i * 64 * 1024;
  188. rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
  189. rdev->ib_pool.ibs[i].ptr = ptr + offset;
  190. rdev->ib_pool.ibs[i].idx = i;
  191. rdev->ib_pool.ibs[i].length_dw = 0;
  192. rdev->ib_pool.ibs[i].free = true;
  193. }
  194. rdev->ib_pool.head_id = 0;
  195. rdev->ib_pool.ready = true;
  196. DRM_INFO("radeon: ib pool ready.\n");
  197. if (radeon_debugfs_ib_init(rdev)) {
  198. DRM_ERROR("Failed to register debugfs file for IB !\n");
  199. }
  200. return r;
  201. }
  202. void radeon_ib_pool_fini(struct radeon_device *rdev)
  203. {
  204. int r;
  205. if (!rdev->ib_pool.ready) {
  206. return;
  207. }
  208. mutex_lock(&rdev->ib_pool.mutex);
  209. radeon_ib_bogus_cleanup(rdev);
  210. if (rdev->ib_pool.robj) {
  211. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  212. if (likely(r == 0)) {
  213. radeon_bo_kunmap(rdev->ib_pool.robj);
  214. radeon_bo_unpin(rdev->ib_pool.robj);
  215. radeon_bo_unreserve(rdev->ib_pool.robj);
  216. }
  217. radeon_bo_unref(&rdev->ib_pool.robj);
  218. rdev->ib_pool.robj = NULL;
  219. }
  220. mutex_unlock(&rdev->ib_pool.mutex);
  221. }
  222. /*
  223. * Ring.
  224. */
  225. void radeon_ring_free_size(struct radeon_device *rdev)
  226. {
  227. if (rdev->family >= CHIP_R600)
  228. rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
  229. else
  230. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  231. /* This works because ring_size is a power of 2 */
  232. rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
  233. rdev->cp.ring_free_dw -= rdev->cp.wptr;
  234. rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
  235. if (!rdev->cp.ring_free_dw) {
  236. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  237. }
  238. }
  239. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
  240. {
  241. int r;
  242. /* Align requested size with padding so unlock_commit can
  243. * pad safely */
  244. ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
  245. mutex_lock(&rdev->cp.mutex);
  246. while (ndw > (rdev->cp.ring_free_dw - 1)) {
  247. radeon_ring_free_size(rdev);
  248. if (ndw < rdev->cp.ring_free_dw) {
  249. break;
  250. }
  251. r = radeon_fence_wait_next(rdev);
  252. if (r) {
  253. mutex_unlock(&rdev->cp.mutex);
  254. return r;
  255. }
  256. }
  257. rdev->cp.count_dw = ndw;
  258. rdev->cp.wptr_old = rdev->cp.wptr;
  259. return 0;
  260. }
  261. void radeon_ring_unlock_commit(struct radeon_device *rdev)
  262. {
  263. unsigned count_dw_pad;
  264. unsigned i;
  265. /* We pad to match fetch size */
  266. count_dw_pad = (rdev->cp.align_mask + 1) -
  267. (rdev->cp.wptr & rdev->cp.align_mask);
  268. for (i = 0; i < count_dw_pad; i++) {
  269. radeon_ring_write(rdev, 2 << 30);
  270. }
  271. DRM_MEMORYBARRIER();
  272. radeon_cp_commit(rdev);
  273. mutex_unlock(&rdev->cp.mutex);
  274. }
  275. void radeon_ring_unlock_undo(struct radeon_device *rdev)
  276. {
  277. rdev->cp.wptr = rdev->cp.wptr_old;
  278. mutex_unlock(&rdev->cp.mutex);
  279. }
  280. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
  281. {
  282. int r;
  283. rdev->cp.ring_size = ring_size;
  284. /* Allocate ring buffer */
  285. if (rdev->cp.ring_obj == NULL) {
  286. r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
  287. RADEON_GEM_DOMAIN_GTT,
  288. &rdev->cp.ring_obj);
  289. if (r) {
  290. dev_err(rdev->dev, "(%d) ring create failed\n", r);
  291. return r;
  292. }
  293. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  294. if (unlikely(r != 0))
  295. return r;
  296. r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
  297. &rdev->cp.gpu_addr);
  298. if (r) {
  299. radeon_bo_unreserve(rdev->cp.ring_obj);
  300. dev_err(rdev->dev, "(%d) ring pin failed\n", r);
  301. return r;
  302. }
  303. r = radeon_bo_kmap(rdev->cp.ring_obj,
  304. (void **)&rdev->cp.ring);
  305. radeon_bo_unreserve(rdev->cp.ring_obj);
  306. if (r) {
  307. dev_err(rdev->dev, "(%d) ring map failed\n", r);
  308. return r;
  309. }
  310. }
  311. rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
  312. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  313. return 0;
  314. }
  315. void radeon_ring_fini(struct radeon_device *rdev)
  316. {
  317. int r;
  318. mutex_lock(&rdev->cp.mutex);
  319. if (rdev->cp.ring_obj) {
  320. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  321. if (likely(r == 0)) {
  322. radeon_bo_kunmap(rdev->cp.ring_obj);
  323. radeon_bo_unpin(rdev->cp.ring_obj);
  324. radeon_bo_unreserve(rdev->cp.ring_obj);
  325. }
  326. radeon_bo_unref(&rdev->cp.ring_obj);
  327. rdev->cp.ring = NULL;
  328. rdev->cp.ring_obj = NULL;
  329. }
  330. mutex_unlock(&rdev->cp.mutex);
  331. }
  332. /*
  333. * Debugfs info
  334. */
  335. #if defined(CONFIG_DEBUG_FS)
  336. static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
  337. {
  338. struct drm_info_node *node = (struct drm_info_node *) m->private;
  339. struct radeon_ib *ib = node->info_ent->data;
  340. unsigned i;
  341. if (ib == NULL) {
  342. return 0;
  343. }
  344. seq_printf(m, "IB %04u\n", ib->idx);
  345. seq_printf(m, "IB fence %p\n", ib->fence);
  346. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  347. for (i = 0; i < ib->length_dw; i++) {
  348. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  349. }
  350. return 0;
  351. }
  352. static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
  353. {
  354. struct drm_info_node *node = (struct drm_info_node *) m->private;
  355. struct radeon_device *rdev = node->info_ent->data;
  356. struct radeon_ib *ib;
  357. unsigned i;
  358. mutex_lock(&rdev->ib_pool.mutex);
  359. if (list_empty(&rdev->ib_pool.bogus_ib)) {
  360. mutex_unlock(&rdev->ib_pool.mutex);
  361. seq_printf(m, "no bogus IB recorded\n");
  362. return 0;
  363. }
  364. ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
  365. list_del_init(&ib->list);
  366. mutex_unlock(&rdev->ib_pool.mutex);
  367. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  368. for (i = 0; i < ib->length_dw; i++) {
  369. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  370. }
  371. vfree(ib->ptr);
  372. kfree(ib);
  373. return 0;
  374. }
  375. static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
  376. static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
  377. static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
  378. {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
  379. };
  380. #endif
  381. int radeon_debugfs_ib_init(struct radeon_device *rdev)
  382. {
  383. #if defined(CONFIG_DEBUG_FS)
  384. unsigned i;
  385. int r;
  386. radeon_debugfs_ib_bogus_info_list[0].data = rdev;
  387. r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
  388. if (r)
  389. return r;
  390. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  391. sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
  392. radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
  393. radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
  394. radeon_debugfs_ib_list[i].driver_features = 0;
  395. radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
  396. }
  397. return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
  398. RADEON_IB_POOL_SIZE);
  399. #else
  400. return 0;
  401. #endif
  402. }