nouveau_drv.c 11 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include "drmP.h"
  26. #include "drm.h"
  27. #include "drm_crtc_helper.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_hw.h"
  30. #include "nouveau_fb.h"
  31. #include "nouveau_fbcon.h"
  32. #include "nv50_display.h"
  33. #include "drm_pciids.h"
  34. MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
  35. int nouveau_ctxfw = 0;
  36. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  37. MODULE_PARM_DESC(noagp, "Disable AGP");
  38. int nouveau_noagp;
  39. module_param_named(noagp, nouveau_noagp, int, 0400);
  40. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  41. static int nouveau_modeset = -1; /* kms */
  42. module_param_named(modeset, nouveau_modeset, int, 0400);
  43. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  44. char *nouveau_vbios;
  45. module_param_named(vbios, nouveau_vbios, charp, 0400);
  46. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  47. int nouveau_vram_pushbuf;
  48. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  49. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  50. int nouveau_vram_notify = 1;
  51. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  52. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  53. int nouveau_duallink = 1;
  54. module_param_named(duallink, nouveau_duallink, int, 0400);
  55. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  56. int nouveau_uscript_lvds = -1;
  57. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  58. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  59. int nouveau_uscript_tmds = -1;
  60. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  61. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  62. int nouveau_ignorelid = 0;
  63. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  64. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  65. int nouveau_noaccel = 0;
  66. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  67. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  68. int nouveau_nofbaccel = 0;
  69. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  70. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  71. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  72. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  73. "\t\tDefault: PAL\n"
  74. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  75. char *nouveau_tv_norm;
  76. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  77. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  78. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  79. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  80. "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
  81. int nouveau_reg_debug;
  82. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  83. int nouveau_fbpercrtc;
  84. #if 0
  85. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  86. #endif
  87. static struct pci_device_id pciidlist[] = {
  88. {
  89. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  90. .class = PCI_BASE_CLASS_DISPLAY << 16,
  91. .class_mask = 0xff << 16,
  92. },
  93. {
  94. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  95. .class = PCI_BASE_CLASS_DISPLAY << 16,
  96. .class_mask = 0xff << 16,
  97. },
  98. {}
  99. };
  100. MODULE_DEVICE_TABLE(pci, pciidlist);
  101. static struct drm_driver driver;
  102. static int __devinit
  103. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  104. {
  105. return drm_get_dev(pdev, ent, &driver);
  106. }
  107. static void
  108. nouveau_pci_remove(struct pci_dev *pdev)
  109. {
  110. struct drm_device *dev = pci_get_drvdata(pdev);
  111. drm_put_dev(dev);
  112. }
  113. int
  114. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  115. {
  116. struct drm_device *dev = pci_get_drvdata(pdev);
  117. struct drm_nouveau_private *dev_priv = dev->dev_private;
  118. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  119. struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  120. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  121. struct nouveau_channel *chan;
  122. struct drm_crtc *crtc;
  123. uint32_t fbdev_flags;
  124. int ret, i;
  125. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  126. return -ENODEV;
  127. if (pm_state.event == PM_EVENT_PRETHAW)
  128. return 0;
  129. fbdev_flags = dev_priv->fbdev_info->flags;
  130. dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
  131. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  132. struct nouveau_framebuffer *nouveau_fb;
  133. nouveau_fb = nouveau_framebuffer(crtc->fb);
  134. if (!nouveau_fb || !nouveau_fb->nvbo)
  135. continue;
  136. nouveau_bo_unpin(nouveau_fb->nvbo);
  137. }
  138. NV_INFO(dev, "Evicting buffers...\n");
  139. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  140. NV_INFO(dev, "Idling channels...\n");
  141. for (i = 0; i < pfifo->channels; i++) {
  142. struct nouveau_fence *fence = NULL;
  143. chan = dev_priv->fifos[i];
  144. if (!chan || (dev_priv->card_type >= NV_50 &&
  145. chan == dev_priv->fifos[0]))
  146. continue;
  147. ret = nouveau_fence_new(chan, &fence, true);
  148. if (ret == 0) {
  149. ret = nouveau_fence_wait(fence, NULL, false, false);
  150. nouveau_fence_unref((void *)&fence);
  151. }
  152. if (ret) {
  153. NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
  154. chan->id);
  155. }
  156. }
  157. pgraph->fifo_access(dev, false);
  158. nouveau_wait_for_idle(dev);
  159. pfifo->reassign(dev, false);
  160. pfifo->disable(dev);
  161. pfifo->unload_context(dev);
  162. pgraph->unload_context(dev);
  163. NV_INFO(dev, "Suspending GPU objects...\n");
  164. ret = nouveau_gpuobj_suspend(dev);
  165. if (ret) {
  166. NV_ERROR(dev, "... failed: %d\n", ret);
  167. goto out_abort;
  168. }
  169. ret = pinstmem->suspend(dev);
  170. if (ret) {
  171. NV_ERROR(dev, "... failed: %d\n", ret);
  172. nouveau_gpuobj_suspend_cleanup(dev);
  173. goto out_abort;
  174. }
  175. NV_INFO(dev, "And we're gone!\n");
  176. pci_save_state(pdev);
  177. if (pm_state.event == PM_EVENT_SUSPEND) {
  178. pci_disable_device(pdev);
  179. pci_set_power_state(pdev, PCI_D3hot);
  180. }
  181. acquire_console_sem();
  182. fb_set_suspend(dev_priv->fbdev_info, 1);
  183. release_console_sem();
  184. dev_priv->fbdev_info->flags = fbdev_flags;
  185. return 0;
  186. out_abort:
  187. NV_INFO(dev, "Re-enabling acceleration..\n");
  188. pfifo->enable(dev);
  189. pfifo->reassign(dev, true);
  190. pgraph->fifo_access(dev, true);
  191. return ret;
  192. }
  193. int
  194. nouveau_pci_resume(struct pci_dev *pdev)
  195. {
  196. struct drm_device *dev = pci_get_drvdata(pdev);
  197. struct drm_nouveau_private *dev_priv = dev->dev_private;
  198. struct nouveau_engine *engine = &dev_priv->engine;
  199. struct drm_crtc *crtc;
  200. uint32_t fbdev_flags;
  201. int ret, i;
  202. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  203. return -ENODEV;
  204. fbdev_flags = dev_priv->fbdev_info->flags;
  205. dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
  206. NV_INFO(dev, "We're back, enabling device...\n");
  207. pci_set_power_state(pdev, PCI_D0);
  208. pci_restore_state(pdev);
  209. if (pci_enable_device(pdev))
  210. return -1;
  211. pci_set_master(dev->pdev);
  212. NV_INFO(dev, "POSTing device...\n");
  213. ret = nouveau_run_vbios_init(dev);
  214. if (ret)
  215. return ret;
  216. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  217. ret = nouveau_mem_init_agp(dev);
  218. if (ret) {
  219. NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
  220. return ret;
  221. }
  222. }
  223. NV_INFO(dev, "Reinitialising engines...\n");
  224. engine->instmem.resume(dev);
  225. engine->mc.init(dev);
  226. engine->timer.init(dev);
  227. engine->fb.init(dev);
  228. engine->graph.init(dev);
  229. engine->fifo.init(dev);
  230. NV_INFO(dev, "Restoring GPU objects...\n");
  231. nouveau_gpuobj_resume(dev);
  232. nouveau_irq_postinstall(dev);
  233. /* Re-write SKIPS, they'll have been lost over the suspend */
  234. if (nouveau_vram_pushbuf) {
  235. struct nouveau_channel *chan;
  236. int j;
  237. for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  238. chan = dev_priv->fifos[i];
  239. if (!chan || !chan->pushbuf_bo)
  240. continue;
  241. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  242. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  243. }
  244. }
  245. NV_INFO(dev, "Restoring mode...\n");
  246. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  247. struct nouveau_framebuffer *nouveau_fb;
  248. nouveau_fb = nouveau_framebuffer(crtc->fb);
  249. if (!nouveau_fb || !nouveau_fb->nvbo)
  250. continue;
  251. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  252. }
  253. if (dev_priv->card_type < NV_50) {
  254. nv04_display_restore(dev);
  255. NVLockVgaCrtcs(dev, false);
  256. } else
  257. nv50_display_init(dev);
  258. /* Force CLUT to get re-loaded during modeset */
  259. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  260. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  261. nv_crtc->lut.depth = 0;
  262. }
  263. acquire_console_sem();
  264. fb_set_suspend(dev_priv->fbdev_info, 0);
  265. release_console_sem();
  266. nouveau_fbcon_zfill(dev);
  267. drm_helper_resume_force_mode(dev);
  268. dev_priv->fbdev_info->flags = fbdev_flags;
  269. return 0;
  270. }
  271. static struct drm_driver driver = {
  272. .driver_features =
  273. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  274. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  275. .load = nouveau_load,
  276. .firstopen = nouveau_firstopen,
  277. .lastclose = nouveau_lastclose,
  278. .unload = nouveau_unload,
  279. .preclose = nouveau_preclose,
  280. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  281. .debugfs_init = nouveau_debugfs_init,
  282. .debugfs_cleanup = nouveau_debugfs_takedown,
  283. #endif
  284. .irq_preinstall = nouveau_irq_preinstall,
  285. .irq_postinstall = nouveau_irq_postinstall,
  286. .irq_uninstall = nouveau_irq_uninstall,
  287. .irq_handler = nouveau_irq_handler,
  288. .reclaim_buffers = drm_core_reclaim_buffers,
  289. .get_map_ofs = drm_core_get_map_ofs,
  290. .get_reg_ofs = drm_core_get_reg_ofs,
  291. .ioctls = nouveau_ioctls,
  292. .fops = {
  293. .owner = THIS_MODULE,
  294. .open = drm_open,
  295. .release = drm_release,
  296. .unlocked_ioctl = drm_ioctl,
  297. .mmap = nouveau_ttm_mmap,
  298. .poll = drm_poll,
  299. .fasync = drm_fasync,
  300. #if defined(CONFIG_COMPAT)
  301. .compat_ioctl = nouveau_compat_ioctl,
  302. #endif
  303. },
  304. .pci_driver = {
  305. .name = DRIVER_NAME,
  306. .id_table = pciidlist,
  307. .probe = nouveau_pci_probe,
  308. .remove = nouveau_pci_remove,
  309. .suspend = nouveau_pci_suspend,
  310. .resume = nouveau_pci_resume
  311. },
  312. .gem_init_object = nouveau_gem_object_new,
  313. .gem_free_object = nouveau_gem_object_del,
  314. .name = DRIVER_NAME,
  315. .desc = DRIVER_DESC,
  316. #ifdef GIT_REVISION
  317. .date = GIT_REVISION,
  318. #else
  319. .date = DRIVER_DATE,
  320. #endif
  321. .major = DRIVER_MAJOR,
  322. .minor = DRIVER_MINOR,
  323. .patchlevel = DRIVER_PATCHLEVEL,
  324. };
  325. static int __init nouveau_init(void)
  326. {
  327. driver.num_ioctls = nouveau_max_ioctl;
  328. if (nouveau_modeset == -1) {
  329. #ifdef CONFIG_VGA_CONSOLE
  330. if (vgacon_text_force())
  331. nouveau_modeset = 0;
  332. else
  333. #endif
  334. nouveau_modeset = 1;
  335. }
  336. if (nouveau_modeset == 1) {
  337. driver.driver_features |= DRIVER_MODESET;
  338. nouveau_register_dsm_handler();
  339. }
  340. return drm_init(&driver);
  341. }
  342. static void __exit nouveau_exit(void)
  343. {
  344. drm_exit(&driver);
  345. nouveau_unregister_dsm_handler();
  346. }
  347. module_init(nouveau_init);
  348. module_exit(nouveau_exit);
  349. MODULE_AUTHOR(DRIVER_AUTHOR);
  350. MODULE_DESCRIPTION(DRIVER_DESC);
  351. MODULE_LICENSE("GPL and additional rights");