solos-pci.c 34 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 2048
  58. #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
  59. #define FPGA_PAGE 528 /* FPGA flash page size*/
  60. #define SOLOS_PAGE 512 /* Solos flash page size*/
  61. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  62. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  63. #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
  64. #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
  65. #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
  66. #define RX_DMA_SIZE 2048
  67. #define FPGA_VERSION(a,b) (((a) << 8) + (b))
  68. #define LEGACY_BUFFERS 2
  69. #define DMA_SUPPORTED 4
  70. static int reset = 0;
  71. static int atmdebug = 0;
  72. static int firmware_upgrade = 0;
  73. static int fpga_upgrade = 0;
  74. static int db_firmware_upgrade = 0;
  75. static int db_fpga_upgrade = 0;
  76. struct pkt_hdr {
  77. __le16 size;
  78. __le16 vpi;
  79. __le16 vci;
  80. __le16 type;
  81. };
  82. struct solos_skb_cb {
  83. struct atm_vcc *vcc;
  84. uint32_t dma_addr;
  85. };
  86. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  87. #define PKT_DATA 0
  88. #define PKT_COMMAND 1
  89. #define PKT_POPEN 3
  90. #define PKT_PCLOSE 4
  91. #define PKT_STATUS 5
  92. struct solos_card {
  93. void __iomem *config_regs;
  94. void __iomem *buffers;
  95. int nr_ports;
  96. int tx_mask;
  97. struct pci_dev *dev;
  98. struct atm_dev *atmdev[4];
  99. struct tasklet_struct tlet;
  100. spinlock_t tx_lock;
  101. spinlock_t tx_queue_lock;
  102. spinlock_t cli_queue_lock;
  103. spinlock_t param_queue_lock;
  104. struct list_head param_queue;
  105. struct sk_buff_head tx_queue[4];
  106. struct sk_buff_head cli_queue[4];
  107. struct sk_buff *tx_skb[4];
  108. struct sk_buff *rx_skb[4];
  109. wait_queue_head_t param_wq;
  110. wait_queue_head_t fw_wq;
  111. int using_dma;
  112. int fpga_version;
  113. int buffer_size;
  114. };
  115. struct solos_param {
  116. struct list_head list;
  117. pid_t pid;
  118. int port;
  119. struct sk_buff *response;
  120. };
  121. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  122. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  123. MODULE_DESCRIPTION("Solos PCI driver");
  124. MODULE_VERSION(VERSION);
  125. MODULE_LICENSE("GPL");
  126. MODULE_FIRMWARE("solos-FPGA.bin");
  127. MODULE_FIRMWARE("solos-Firmware.bin");
  128. MODULE_FIRMWARE("solos-db-FPGA.bin");
  129. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  130. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  131. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  132. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  133. MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
  134. MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
  135. module_param(reset, int, 0444);
  136. module_param(atmdebug, int, 0644);
  137. module_param(firmware_upgrade, int, 0444);
  138. module_param(fpga_upgrade, int, 0444);
  139. module_param(db_firmware_upgrade, int, 0444);
  140. module_param(db_fpga_upgrade, int, 0444);
  141. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  142. struct atm_vcc *vcc);
  143. static uint32_t fpga_tx(struct solos_card *);
  144. static irqreturn_t solos_irq(int irq, void *dev_id);
  145. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  146. static int list_vccs(int vci);
  147. static void release_vccs(struct atm_dev *dev);
  148. static int atm_init(struct solos_card *);
  149. static void atm_remove(struct solos_card *);
  150. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  151. static void solos_bh(unsigned long);
  152. static int print_buffer(struct sk_buff *buf);
  153. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  154. {
  155. if (vcc->pop)
  156. vcc->pop(vcc, skb);
  157. else
  158. dev_kfree_skb_any(skb);
  159. }
  160. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  161. char *buf)
  162. {
  163. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  164. struct solos_card *card = atmdev->dev_data;
  165. struct solos_param prm;
  166. struct sk_buff *skb;
  167. struct pkt_hdr *header;
  168. int buflen;
  169. buflen = strlen(attr->attr.name) + 10;
  170. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  171. if (!skb) {
  172. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  173. return -ENOMEM;
  174. }
  175. header = (void *)skb_put(skb, sizeof(*header));
  176. buflen = snprintf((void *)&header[1], buflen - 1,
  177. "L%05d\n%s\n", current->pid, attr->attr.name);
  178. skb_put(skb, buflen);
  179. header->size = cpu_to_le16(buflen);
  180. header->vpi = cpu_to_le16(0);
  181. header->vci = cpu_to_le16(0);
  182. header->type = cpu_to_le16(PKT_COMMAND);
  183. prm.pid = current->pid;
  184. prm.response = NULL;
  185. prm.port = SOLOS_CHAN(atmdev);
  186. spin_lock_irq(&card->param_queue_lock);
  187. list_add(&prm.list, &card->param_queue);
  188. spin_unlock_irq(&card->param_queue_lock);
  189. fpga_queue(card, prm.port, skb, NULL);
  190. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  191. spin_lock_irq(&card->param_queue_lock);
  192. list_del(&prm.list);
  193. spin_unlock_irq(&card->param_queue_lock);
  194. if (!prm.response)
  195. return -EIO;
  196. buflen = prm.response->len;
  197. memcpy(buf, prm.response->data, buflen);
  198. kfree_skb(prm.response);
  199. return buflen;
  200. }
  201. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  202. const char *buf, size_t count)
  203. {
  204. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  205. struct solos_card *card = atmdev->dev_data;
  206. struct solos_param prm;
  207. struct sk_buff *skb;
  208. struct pkt_hdr *header;
  209. int buflen;
  210. ssize_t ret;
  211. buflen = strlen(attr->attr.name) + 11 + count;
  212. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  213. if (!skb) {
  214. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  215. return -ENOMEM;
  216. }
  217. header = (void *)skb_put(skb, sizeof(*header));
  218. buflen = snprintf((void *)&header[1], buflen - 1,
  219. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  220. skb_put(skb, buflen);
  221. header->size = cpu_to_le16(buflen);
  222. header->vpi = cpu_to_le16(0);
  223. header->vci = cpu_to_le16(0);
  224. header->type = cpu_to_le16(PKT_COMMAND);
  225. prm.pid = current->pid;
  226. prm.response = NULL;
  227. prm.port = SOLOS_CHAN(atmdev);
  228. spin_lock_irq(&card->param_queue_lock);
  229. list_add(&prm.list, &card->param_queue);
  230. spin_unlock_irq(&card->param_queue_lock);
  231. fpga_queue(card, prm.port, skb, NULL);
  232. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  233. spin_lock_irq(&card->param_queue_lock);
  234. list_del(&prm.list);
  235. spin_unlock_irq(&card->param_queue_lock);
  236. skb = prm.response;
  237. if (!skb)
  238. return -EIO;
  239. buflen = skb->len;
  240. /* Sometimes it has a newline, sometimes it doesn't. */
  241. if (skb->data[buflen - 1] == '\n')
  242. buflen--;
  243. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  244. ret = count;
  245. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  246. ret = -EIO;
  247. else {
  248. /* We know we have enough space allocated for this; we allocated
  249. it ourselves */
  250. skb->data[buflen] = 0;
  251. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  252. skb->data);
  253. ret = -EIO;
  254. }
  255. kfree_skb(skb);
  256. return ret;
  257. }
  258. static char *next_string(struct sk_buff *skb)
  259. {
  260. int i = 0;
  261. char *this = skb->data;
  262. for (i = 0; i < skb->len; i++) {
  263. if (this[i] == '\n') {
  264. this[i] = 0;
  265. skb_pull(skb, i + 1);
  266. return this;
  267. }
  268. if (!isprint(this[i]))
  269. return NULL;
  270. }
  271. return NULL;
  272. }
  273. /*
  274. * Status packet has fields separated by \n, starting with a version number
  275. * for the information therein. Fields are....
  276. *
  277. * packet version
  278. * RxBitRate (version >= 1)
  279. * TxBitRate (version >= 1)
  280. * State (version >= 1)
  281. * LocalSNRMargin (version >= 1)
  282. * LocalLineAttn (version >= 1)
  283. */
  284. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  285. {
  286. char *str, *end, *state_str, *snr, *attn;
  287. int ver, rate_up, rate_down;
  288. if (!card->atmdev[port])
  289. return -ENODEV;
  290. str = next_string(skb);
  291. if (!str)
  292. return -EIO;
  293. ver = simple_strtol(str, NULL, 10);
  294. if (ver < 1) {
  295. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  296. ver);
  297. return -EIO;
  298. }
  299. str = next_string(skb);
  300. if (!str)
  301. return -EIO;
  302. if (!strcmp(str, "ERROR")) {
  303. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  304. port);
  305. return 0;
  306. }
  307. rate_down = simple_strtol(str, &end, 10);
  308. if (*end)
  309. return -EIO;
  310. str = next_string(skb);
  311. if (!str)
  312. return -EIO;
  313. rate_up = simple_strtol(str, &end, 10);
  314. if (*end)
  315. return -EIO;
  316. state_str = next_string(skb);
  317. if (!state_str)
  318. return -EIO;
  319. /* Anything but 'Showtime' is down */
  320. if (strcmp(state_str, "Showtime")) {
  321. card->atmdev[port]->signal = ATM_PHY_SIG_LOST;
  322. release_vccs(card->atmdev[port]);
  323. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  324. return 0;
  325. }
  326. snr = next_string(skb);
  327. if (!snr)
  328. return -EIO;
  329. attn = next_string(skb);
  330. if (!attn)
  331. return -EIO;
  332. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  333. port, state_str, rate_down/1000, rate_up/1000,
  334. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  335. card->atmdev[port]->link_rate = rate_down / 424;
  336. card->atmdev[port]->signal = ATM_PHY_SIG_FOUND;
  337. return 0;
  338. }
  339. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  340. {
  341. struct solos_param *prm;
  342. unsigned long flags;
  343. int cmdpid;
  344. int found = 0;
  345. if (skb->len < 7)
  346. return 0;
  347. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  348. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  349. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  350. skb->data[6] != '\n')
  351. return 0;
  352. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  353. spin_lock_irqsave(&card->param_queue_lock, flags);
  354. list_for_each_entry(prm, &card->param_queue, list) {
  355. if (prm->port == port && prm->pid == cmdpid) {
  356. prm->response = skb;
  357. skb_pull(skb, 7);
  358. wake_up(&card->param_wq);
  359. found = 1;
  360. break;
  361. }
  362. }
  363. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  364. return found;
  365. }
  366. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  367. char *buf)
  368. {
  369. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  370. struct solos_card *card = atmdev->dev_data;
  371. struct sk_buff *skb;
  372. spin_lock(&card->cli_queue_lock);
  373. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  374. spin_unlock(&card->cli_queue_lock);
  375. if(skb == NULL)
  376. return sprintf(buf, "No data.\n");
  377. memcpy(buf, skb->data, skb->len);
  378. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  379. kfree_skb(skb);
  380. return skb->len;
  381. }
  382. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  383. {
  384. struct sk_buff *skb;
  385. struct pkt_hdr *header;
  386. if (size > (BUF_SIZE - sizeof(*header))) {
  387. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  388. return 0;
  389. }
  390. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  391. if (!skb) {
  392. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  393. return 0;
  394. }
  395. header = (void *)skb_put(skb, sizeof(*header));
  396. header->size = cpu_to_le16(size);
  397. header->vpi = cpu_to_le16(0);
  398. header->vci = cpu_to_le16(0);
  399. header->type = cpu_to_le16(PKT_COMMAND);
  400. memcpy(skb_put(skb, size), buf, size);
  401. fpga_queue(card, dev, skb, NULL);
  402. return 0;
  403. }
  404. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  405. const char *buf, size_t count)
  406. {
  407. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  408. struct solos_card *card = atmdev->dev_data;
  409. int err;
  410. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  411. return err?:count;
  412. }
  413. static DEVICE_ATTR(console, 0644, console_show, console_store);
  414. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  415. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  416. #include "solos-attrlist.c"
  417. #undef SOLOS_ATTR_RO
  418. #undef SOLOS_ATTR_RW
  419. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  420. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  421. static struct attribute *solos_attrs[] = {
  422. #include "solos-attrlist.c"
  423. NULL
  424. };
  425. static struct attribute_group solos_attr_group = {
  426. .attrs = solos_attrs,
  427. .name = "parameters",
  428. };
  429. static int flash_upgrade(struct solos_card *card, int chip)
  430. {
  431. const struct firmware *fw;
  432. const char *fw_name;
  433. uint32_t data32 = 0;
  434. int blocksize = 0;
  435. int numblocks = 0;
  436. int offset;
  437. switch (chip) {
  438. case 0:
  439. fw_name = "solos-FPGA.bin";
  440. blocksize = FPGA_BLOCK;
  441. break;
  442. case 1:
  443. fw_name = "solos-Firmware.bin";
  444. blocksize = SOLOS_BLOCK;
  445. break;
  446. case 2:
  447. if (card->fpga_version > LEGACY_BUFFERS){
  448. fw_name = "solos-db-FPGA.bin";
  449. blocksize = FPGA_BLOCK;
  450. } else {
  451. dev_info(&card->dev->dev, "FPGA version doesn't support"
  452. " daughter board upgrades\n");
  453. return -EPERM;
  454. }
  455. break;
  456. case 3:
  457. if (card->fpga_version > LEGACY_BUFFERS){
  458. fw_name = "solos-Firmware.bin";
  459. blocksize = SOLOS_BLOCK;
  460. } else {
  461. dev_info(&card->dev->dev, "FPGA version doesn't support"
  462. " daughter board upgrades\n");
  463. return -EPERM;
  464. }
  465. break;
  466. default:
  467. return -ENODEV;
  468. }
  469. if (request_firmware(&fw, fw_name, &card->dev->dev))
  470. return -ENOENT;
  471. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  472. numblocks = fw->size / blocksize;
  473. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  474. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  475. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  476. iowrite32(1, card->config_regs + FPGA_MODE);
  477. data32 = ioread32(card->config_regs + FPGA_MODE);
  478. /* Set mode to Chip Erase */
  479. if(chip == 0 || chip == 2)
  480. dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
  481. if(chip == 1 || chip == 3)
  482. dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
  483. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  484. iowrite32(1, card->config_regs + WRITE_FLASH);
  485. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  486. for (offset = 0; offset < fw->size; offset += blocksize) {
  487. int i;
  488. /* Clear write flag */
  489. iowrite32(0, card->config_regs + WRITE_FLASH);
  490. /* Set mode to Block Write */
  491. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  492. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  493. /* Copy block to buffer, swapping each 16 bits */
  494. for(i = 0; i < blocksize; i += 4) {
  495. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  496. if(card->fpga_version > LEGACY_BUFFERS)
  497. iowrite32(word, FLASH_BUF + i);
  498. else
  499. iowrite32(word, RX_BUF(card, 3) + i);
  500. }
  501. /* Specify block number and then trigger flash write */
  502. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  503. iowrite32(1, card->config_regs + WRITE_FLASH);
  504. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  505. }
  506. release_firmware(fw);
  507. iowrite32(0, card->config_regs + WRITE_FLASH);
  508. iowrite32(0, card->config_regs + FPGA_MODE);
  509. iowrite32(0, card->config_regs + FLASH_MODE);
  510. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  511. return 0;
  512. }
  513. static irqreturn_t solos_irq(int irq, void *dev_id)
  514. {
  515. struct solos_card *card = dev_id;
  516. int handled = 1;
  517. iowrite32(0, card->config_regs + IRQ_CLEAR);
  518. /* If we're up and running, just kick the tasklet to process TX/RX */
  519. if (card->atmdev[0])
  520. tasklet_schedule(&card->tlet);
  521. else
  522. wake_up(&card->fw_wq);
  523. return IRQ_RETVAL(handled);
  524. }
  525. void solos_bh(unsigned long card_arg)
  526. {
  527. struct solos_card *card = (void *)card_arg;
  528. uint32_t card_flags;
  529. uint32_t rx_done = 0;
  530. int port;
  531. /*
  532. * Since fpga_tx() is going to need to read the flags under its lock,
  533. * it can return them to us so that we don't have to hit PCI MMIO
  534. * again for the same information
  535. */
  536. card_flags = fpga_tx(card);
  537. for (port = 0; port < card->nr_ports; port++) {
  538. if (card_flags & (0x10 << port)) {
  539. struct pkt_hdr _hdr, *header;
  540. struct sk_buff *skb;
  541. struct atm_vcc *vcc;
  542. int size;
  543. if (card->using_dma) {
  544. skb = card->rx_skb[port];
  545. card->rx_skb[port] = NULL;
  546. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  547. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  548. header = (void *)skb->data;
  549. size = le16_to_cpu(header->size);
  550. skb_put(skb, size + sizeof(*header));
  551. skb_pull(skb, sizeof(*header));
  552. } else {
  553. header = &_hdr;
  554. rx_done |= 0x10 << port;
  555. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  556. size = le16_to_cpu(header->size);
  557. if (size > (card->buffer_size - sizeof(*header))){
  558. dev_warn(&card->dev->dev, "Invalid buffer size\n");
  559. continue;
  560. }
  561. skb = alloc_skb(size + 1, GFP_ATOMIC);
  562. if (!skb) {
  563. if (net_ratelimit())
  564. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  565. continue;
  566. }
  567. memcpy_fromio(skb_put(skb, size),
  568. RX_BUF(card, port) + sizeof(*header),
  569. size);
  570. }
  571. if (atmdebug) {
  572. dev_info(&card->dev->dev, "Received: device %d\n", port);
  573. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  574. size, le16_to_cpu(header->vpi),
  575. le16_to_cpu(header->vci));
  576. print_buffer(skb);
  577. }
  578. switch (le16_to_cpu(header->type)) {
  579. case PKT_DATA:
  580. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  581. le16_to_cpu(header->vci));
  582. if (!vcc) {
  583. if (net_ratelimit())
  584. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  585. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  586. port);
  587. continue;
  588. }
  589. atm_charge(vcc, skb->truesize);
  590. vcc->push(vcc, skb);
  591. atomic_inc(&vcc->stats->rx);
  592. break;
  593. case PKT_STATUS:
  594. if (process_status(card, port, skb) &&
  595. net_ratelimit()) {
  596. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  597. print_buffer(skb);
  598. }
  599. dev_kfree_skb_any(skb);
  600. break;
  601. case PKT_COMMAND:
  602. default: /* FIXME: Not really, surely? */
  603. if (process_command(card, port, skb))
  604. break;
  605. spin_lock(&card->cli_queue_lock);
  606. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  607. if (net_ratelimit())
  608. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  609. port);
  610. dev_kfree_skb_any(skb);
  611. } else
  612. skb_queue_tail(&card->cli_queue[port], skb);
  613. spin_unlock(&card->cli_queue_lock);
  614. break;
  615. }
  616. }
  617. /* Allocate RX skbs for any ports which need them */
  618. if (card->using_dma && card->atmdev[port] &&
  619. !card->rx_skb[port]) {
  620. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  621. if (skb) {
  622. SKB_CB(skb)->dma_addr =
  623. pci_map_single(card->dev, skb->data,
  624. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  625. iowrite32(SKB_CB(skb)->dma_addr,
  626. card->config_regs + RX_DMA_ADDR(port));
  627. card->rx_skb[port] = skb;
  628. } else {
  629. if (net_ratelimit())
  630. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  631. /* We'll have to try again later */
  632. tasklet_schedule(&card->tlet);
  633. }
  634. }
  635. }
  636. if (rx_done)
  637. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  638. return;
  639. }
  640. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  641. {
  642. struct hlist_head *head;
  643. struct atm_vcc *vcc = NULL;
  644. struct hlist_node *node;
  645. struct sock *s;
  646. read_lock(&vcc_sklist_lock);
  647. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  648. sk_for_each(s, node, head) {
  649. vcc = atm_sk(s);
  650. if (vcc->dev == dev && vcc->vci == vci &&
  651. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  652. goto out;
  653. }
  654. vcc = NULL;
  655. out:
  656. read_unlock(&vcc_sklist_lock);
  657. return vcc;
  658. }
  659. static int list_vccs(int vci)
  660. {
  661. struct hlist_head *head;
  662. struct atm_vcc *vcc;
  663. struct hlist_node *node;
  664. struct sock *s;
  665. int num_found = 0;
  666. int i;
  667. read_lock(&vcc_sklist_lock);
  668. if (vci != 0){
  669. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  670. sk_for_each(s, node, head) {
  671. num_found ++;
  672. vcc = atm_sk(s);
  673. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  674. vcc->dev->number,
  675. vcc->vpi,
  676. vcc->vci);
  677. }
  678. } else {
  679. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  680. head = &vcc_hash[i];
  681. sk_for_each(s, node, head) {
  682. num_found ++;
  683. vcc = atm_sk(s);
  684. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  685. vcc->dev->number,
  686. vcc->vpi,
  687. vcc->vci);
  688. }
  689. }
  690. }
  691. read_unlock(&vcc_sklist_lock);
  692. return num_found;
  693. }
  694. static void release_vccs(struct atm_dev *dev)
  695. {
  696. int i;
  697. write_lock_irq(&vcc_sklist_lock);
  698. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  699. struct hlist_head *head = &vcc_hash[i];
  700. struct hlist_node *node, *tmp;
  701. struct sock *s;
  702. struct atm_vcc *vcc;
  703. sk_for_each_safe(s, node, tmp, head) {
  704. vcc = atm_sk(s);
  705. if (vcc->dev == dev) {
  706. vcc_release_async(vcc, -EPIPE);
  707. sk_del_node_init(s);
  708. }
  709. }
  710. }
  711. write_unlock_irq(&vcc_sklist_lock);
  712. }
  713. static int popen(struct atm_vcc *vcc)
  714. {
  715. struct solos_card *card = vcc->dev->dev_data;
  716. struct sk_buff *skb;
  717. struct pkt_hdr *header;
  718. if (vcc->qos.aal != ATM_AAL5) {
  719. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  720. vcc->qos.aal);
  721. return -EINVAL;
  722. }
  723. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  724. if (!skb && net_ratelimit()) {
  725. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  726. return -ENOMEM;
  727. }
  728. header = (void *)skb_put(skb, sizeof(*header));
  729. header->size = cpu_to_le16(0);
  730. header->vpi = cpu_to_le16(vcc->vpi);
  731. header->vci = cpu_to_le16(vcc->vci);
  732. header->type = cpu_to_le16(PKT_POPEN);
  733. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  734. set_bit(ATM_VF_ADDR, &vcc->flags);
  735. set_bit(ATM_VF_READY, &vcc->flags);
  736. list_vccs(0);
  737. return 0;
  738. }
  739. static void pclose(struct atm_vcc *vcc)
  740. {
  741. struct solos_card *card = vcc->dev->dev_data;
  742. struct sk_buff *skb;
  743. struct pkt_hdr *header;
  744. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  745. if (!skb) {
  746. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  747. return;
  748. }
  749. header = (void *)skb_put(skb, sizeof(*header));
  750. header->size = cpu_to_le16(0);
  751. header->vpi = cpu_to_le16(vcc->vpi);
  752. header->vci = cpu_to_le16(vcc->vci);
  753. header->type = cpu_to_le16(PKT_PCLOSE);
  754. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  755. clear_bit(ATM_VF_ADDR, &vcc->flags);
  756. clear_bit(ATM_VF_READY, &vcc->flags);
  757. return;
  758. }
  759. static int print_buffer(struct sk_buff *buf)
  760. {
  761. int len,i;
  762. char msg[500];
  763. char item[10];
  764. len = buf->len;
  765. for (i = 0; i < len; i++){
  766. if(i % 8 == 0)
  767. sprintf(msg, "%02X: ", i);
  768. sprintf(item,"%02X ",*(buf->data + i));
  769. strcat(msg, item);
  770. if(i % 8 == 7) {
  771. sprintf(item, "\n");
  772. strcat(msg, item);
  773. printk(KERN_DEBUG "%s", msg);
  774. }
  775. }
  776. if (i % 8 != 0) {
  777. sprintf(item, "\n");
  778. strcat(msg, item);
  779. printk(KERN_DEBUG "%s", msg);
  780. }
  781. printk(KERN_DEBUG "\n");
  782. return 0;
  783. }
  784. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  785. struct atm_vcc *vcc)
  786. {
  787. int old_len;
  788. unsigned long flags;
  789. SKB_CB(skb)->vcc = vcc;
  790. spin_lock_irqsave(&card->tx_queue_lock, flags);
  791. old_len = skb_queue_len(&card->tx_queue[port]);
  792. skb_queue_tail(&card->tx_queue[port], skb);
  793. if (!old_len)
  794. card->tx_mask |= (1 << port);
  795. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  796. /* Theoretically we could just schedule the tasklet here, but
  797. that introduces latency we don't want -- it's noticeable */
  798. if (!old_len)
  799. fpga_tx(card);
  800. }
  801. static uint32_t fpga_tx(struct solos_card *card)
  802. {
  803. uint32_t tx_pending, card_flags;
  804. uint32_t tx_started = 0;
  805. struct sk_buff *skb;
  806. struct atm_vcc *vcc;
  807. unsigned char port;
  808. unsigned long flags;
  809. spin_lock_irqsave(&card->tx_lock, flags);
  810. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  811. /*
  812. * The queue lock is required for _writing_ to tx_mask, but we're
  813. * OK to read it here without locking. The only potential update
  814. * that we could race with is in fpga_queue() where it sets a bit
  815. * for a new port... but it's going to call this function again if
  816. * it's doing that, anyway.
  817. */
  818. tx_pending = card->tx_mask & ~card_flags;
  819. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  820. if (tx_pending & 1) {
  821. struct sk_buff *oldskb = card->tx_skb[port];
  822. if (oldskb)
  823. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  824. oldskb->len, PCI_DMA_TODEVICE);
  825. spin_lock(&card->tx_queue_lock);
  826. skb = skb_dequeue(&card->tx_queue[port]);
  827. if (!skb)
  828. card->tx_mask &= ~(1 << port);
  829. spin_unlock(&card->tx_queue_lock);
  830. if (skb && !card->using_dma) {
  831. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  832. tx_started |= 1 << port;
  833. oldskb = skb; /* We're done with this skb already */
  834. } else if (skb && card->using_dma) {
  835. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  836. skb->len, PCI_DMA_TODEVICE);
  837. iowrite32(SKB_CB(skb)->dma_addr,
  838. card->config_regs + TX_DMA_ADDR(port));
  839. }
  840. if (!oldskb)
  841. continue;
  842. /* Clean up and free oldskb now it's gone */
  843. if (atmdebug) {
  844. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  845. port);
  846. print_buffer(oldskb);
  847. }
  848. vcc = SKB_CB(oldskb)->vcc;
  849. if (vcc) {
  850. atomic_inc(&vcc->stats->tx);
  851. solos_pop(vcc, oldskb);
  852. } else
  853. dev_kfree_skb_irq(oldskb);
  854. }
  855. }
  856. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  857. if (tx_started)
  858. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  859. spin_unlock_irqrestore(&card->tx_lock, flags);
  860. return card_flags;
  861. }
  862. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  863. {
  864. struct solos_card *card = vcc->dev->dev_data;
  865. struct pkt_hdr *header;
  866. int pktlen;
  867. pktlen = skb->len;
  868. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  869. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  870. solos_pop(vcc, skb);
  871. return 0;
  872. }
  873. if (!skb_clone_writable(skb, sizeof(*header))) {
  874. int expand_by = 0;
  875. int ret;
  876. if (skb_headroom(skb) < sizeof(*header))
  877. expand_by = sizeof(*header) - skb_headroom(skb);
  878. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  879. if (ret) {
  880. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  881. solos_pop(vcc, skb);
  882. return ret;
  883. }
  884. }
  885. header = (void *)skb_push(skb, sizeof(*header));
  886. /* This does _not_ include the size of the header */
  887. header->size = cpu_to_le16(pktlen);
  888. header->vpi = cpu_to_le16(vcc->vpi);
  889. header->vci = cpu_to_le16(vcc->vci);
  890. header->type = cpu_to_le16(PKT_DATA);
  891. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  892. return 0;
  893. }
  894. static struct atmdev_ops fpga_ops = {
  895. .open = popen,
  896. .close = pclose,
  897. .ioctl = NULL,
  898. .getsockopt = NULL,
  899. .setsockopt = NULL,
  900. .send = psend,
  901. .send_oam = NULL,
  902. .phy_put = NULL,
  903. .phy_get = NULL,
  904. .change_qos = NULL,
  905. .proc_read = NULL,
  906. .owner = THIS_MODULE
  907. };
  908. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  909. {
  910. int err;
  911. uint16_t fpga_ver;
  912. uint8_t major_ver, minor_ver;
  913. uint32_t data32;
  914. struct solos_card *card;
  915. card = kzalloc(sizeof(*card), GFP_KERNEL);
  916. if (!card)
  917. return -ENOMEM;
  918. card->dev = dev;
  919. init_waitqueue_head(&card->fw_wq);
  920. init_waitqueue_head(&card->param_wq);
  921. err = pci_enable_device(dev);
  922. if (err) {
  923. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  924. goto out;
  925. }
  926. err = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
  927. if (err) {
  928. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  929. goto out;
  930. }
  931. err = pci_request_regions(dev, "solos");
  932. if (err) {
  933. dev_warn(&dev->dev, "Failed to request regions\n");
  934. goto out;
  935. }
  936. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  937. if (!card->config_regs) {
  938. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  939. goto out_release_regions;
  940. }
  941. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  942. if (!card->buffers) {
  943. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  944. goto out_unmap_config;
  945. }
  946. if (reset) {
  947. iowrite32(1, card->config_regs + FPGA_MODE);
  948. data32 = ioread32(card->config_regs + FPGA_MODE);
  949. iowrite32(0, card->config_regs + FPGA_MODE);
  950. data32 = ioread32(card->config_regs + FPGA_MODE);
  951. }
  952. data32 = ioread32(card->config_regs + FPGA_VER);
  953. fpga_ver = (data32 & 0x0000FFFF);
  954. major_ver = ((data32 & 0xFF000000) >> 24);
  955. minor_ver = ((data32 & 0x00FF0000) >> 16);
  956. card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
  957. if (card->fpga_version > LEGACY_BUFFERS)
  958. card->buffer_size = BUF_SIZE;
  959. else
  960. card->buffer_size = OLD_BUF_SIZE;
  961. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  962. major_ver, minor_ver, fpga_ver);
  963. if (card->fpga_version >= DMA_SUPPORTED){
  964. card->using_dma = 1;
  965. } else {
  966. card->using_dma = 0;
  967. /* Set RX empty flag for all ports */
  968. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  969. }
  970. data32 = ioread32(card->config_regs + PORTS);
  971. card->nr_ports = (data32 & 0x000000FF);
  972. pci_set_drvdata(dev, card);
  973. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  974. spin_lock_init(&card->tx_lock);
  975. spin_lock_init(&card->tx_queue_lock);
  976. spin_lock_init(&card->cli_queue_lock);
  977. spin_lock_init(&card->param_queue_lock);
  978. INIT_LIST_HEAD(&card->param_queue);
  979. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  980. "solos-pci", card);
  981. if (err) {
  982. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  983. goto out_unmap_both;
  984. }
  985. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  986. if (fpga_upgrade)
  987. flash_upgrade(card, 0);
  988. if (firmware_upgrade)
  989. flash_upgrade(card, 1);
  990. if (db_fpga_upgrade)
  991. flash_upgrade(card, 2);
  992. if (db_firmware_upgrade)
  993. flash_upgrade(card, 3);
  994. err = atm_init(card);
  995. if (err)
  996. goto out_free_irq;
  997. return 0;
  998. out_free_irq:
  999. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1000. free_irq(dev->irq, card);
  1001. tasklet_kill(&card->tlet);
  1002. out_unmap_both:
  1003. pci_set_drvdata(dev, NULL);
  1004. pci_iounmap(dev, card->config_regs);
  1005. out_unmap_config:
  1006. pci_iounmap(dev, card->buffers);
  1007. out_release_regions:
  1008. pci_release_regions(dev);
  1009. out:
  1010. kfree(card);
  1011. return err;
  1012. }
  1013. static int atm_init(struct solos_card *card)
  1014. {
  1015. int i;
  1016. for (i = 0; i < card->nr_ports; i++) {
  1017. struct sk_buff *skb;
  1018. struct pkt_hdr *header;
  1019. skb_queue_head_init(&card->tx_queue[i]);
  1020. skb_queue_head_init(&card->cli_queue[i]);
  1021. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  1022. if (!card->atmdev[i]) {
  1023. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  1024. atm_remove(card);
  1025. return -ENODEV;
  1026. }
  1027. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  1028. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  1029. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  1030. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  1031. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  1032. card->atmdev[i]->ci_range.vpi_bits = 8;
  1033. card->atmdev[i]->ci_range.vci_bits = 16;
  1034. card->atmdev[i]->dev_data = card;
  1035. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1036. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  1037. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  1038. if (!skb) {
  1039. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1040. continue;
  1041. }
  1042. header = (void *)skb_put(skb, sizeof(*header));
  1043. header->size = cpu_to_le16(0);
  1044. header->vpi = cpu_to_le16(0);
  1045. header->vci = cpu_to_le16(0);
  1046. header->type = cpu_to_le16(PKT_STATUS);
  1047. fpga_queue(card, i, skb, NULL);
  1048. }
  1049. return 0;
  1050. }
  1051. static void atm_remove(struct solos_card *card)
  1052. {
  1053. int i;
  1054. for (i = 0; i < card->nr_ports; i++) {
  1055. if (card->atmdev[i]) {
  1056. struct sk_buff *skb;
  1057. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1058. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1059. atm_dev_deregister(card->atmdev[i]);
  1060. skb = card->rx_skb[i];
  1061. if (skb) {
  1062. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1063. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  1064. dev_kfree_skb(skb);
  1065. }
  1066. skb = card->tx_skb[i];
  1067. if (skb) {
  1068. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1069. skb->len, PCI_DMA_TODEVICE);
  1070. dev_kfree_skb(skb);
  1071. }
  1072. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1073. dev_kfree_skb(skb);
  1074. }
  1075. }
  1076. }
  1077. static void fpga_remove(struct pci_dev *dev)
  1078. {
  1079. struct solos_card *card = pci_get_drvdata(dev);
  1080. /* Disable IRQs */
  1081. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1082. /* Reset FPGA */
  1083. iowrite32(1, card->config_regs + FPGA_MODE);
  1084. (void)ioread32(card->config_regs + FPGA_MODE);
  1085. atm_remove(card);
  1086. free_irq(dev->irq, card);
  1087. tasklet_kill(&card->tlet);
  1088. /* Release device from reset */
  1089. iowrite32(0, card->config_regs + FPGA_MODE);
  1090. (void)ioread32(card->config_regs + FPGA_MODE);
  1091. pci_iounmap(dev, card->buffers);
  1092. pci_iounmap(dev, card->config_regs);
  1093. pci_release_regions(dev);
  1094. pci_disable_device(dev);
  1095. pci_set_drvdata(dev, NULL);
  1096. kfree(card);
  1097. }
  1098. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1099. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1100. { 0, }
  1101. };
  1102. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1103. static struct pci_driver fpga_driver = {
  1104. .name = "solos",
  1105. .id_table = fpga_pci_tbl,
  1106. .probe = fpga_probe,
  1107. .remove = fpga_remove,
  1108. };
  1109. static int __init solos_pci_init(void)
  1110. {
  1111. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1112. return pci_register_driver(&fpga_driver);
  1113. }
  1114. static void __exit solos_pci_exit(void)
  1115. {
  1116. pci_unregister_driver(&fpga_driver);
  1117. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1118. }
  1119. module_init(solos_pci_init);
  1120. module_exit(solos_pci_exit);