mxl5007t.c 21 KB

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  1. /*
  2. * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
  3. *
  4. * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/i2c.h>
  21. #include <linux/types.h>
  22. #include <linux/videodev2.h>
  23. #include "tuner-i2c.h"
  24. #include "mxl5007t.h"
  25. static DEFINE_MUTEX(mxl5007t_list_mutex);
  26. static LIST_HEAD(hybrid_tuner_instance_list);
  27. static int mxl5007t_debug;
  28. module_param_named(debug, mxl5007t_debug, int, 0644);
  29. MODULE_PARM_DESC(debug, "set debug level");
  30. /* ------------------------------------------------------------------------- */
  31. #define mxl_printk(kern, fmt, arg...) \
  32. printk(kern "%s: " fmt "\n", __func__, ##arg)
  33. #define mxl_err(fmt, arg...) \
  34. mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
  35. #define mxl_warn(fmt, arg...) \
  36. mxl_printk(KERN_WARNING, fmt, ##arg)
  37. #define mxl_info(fmt, arg...) \
  38. mxl_printk(KERN_INFO, fmt, ##arg)
  39. #define mxl_debug(fmt, arg...) \
  40. ({ \
  41. if (mxl5007t_debug) \
  42. mxl_printk(KERN_DEBUG, fmt, ##arg); \
  43. })
  44. #define mxl_fail(ret) \
  45. ({ \
  46. int __ret; \
  47. __ret = (ret < 0); \
  48. if (__ret) \
  49. mxl_printk(KERN_ERR, "error %d on line %d", \
  50. ret, __LINE__); \
  51. __ret; \
  52. })
  53. /* ------------------------------------------------------------------------- */
  54. #define MHz 1000000
  55. enum mxl5007t_mode {
  56. MxL_MODE_ISDBT = 0,
  57. MxL_MODE_DVBT = 1,
  58. MxL_MODE_ATSC = 2,
  59. MxL_MODE_CABLE = 0x10,
  60. };
  61. enum mxl5007t_chip_version {
  62. MxL_UNKNOWN_ID = 0x00,
  63. MxL_5007_V1_F1 = 0x11,
  64. MxL_5007_V1_F2 = 0x12,
  65. MxL_5007_V4 = 0x14,
  66. MxL_5007_V2_100_F1 = 0x21,
  67. MxL_5007_V2_100_F2 = 0x22,
  68. MxL_5007_V2_200_F1 = 0x23,
  69. MxL_5007_V2_200_F2 = 0x24,
  70. };
  71. struct reg_pair_t {
  72. u8 reg;
  73. u8 val;
  74. };
  75. /* ------------------------------------------------------------------------- */
  76. static struct reg_pair_t init_tab[] = {
  77. { 0x02, 0x06 },
  78. { 0x03, 0x48 },
  79. { 0x05, 0x04 },
  80. { 0x06, 0x10 },
  81. { 0x2e, 0x15 }, /* OVERRIDE */
  82. { 0x30, 0x10 }, /* OVERRIDE */
  83. { 0x45, 0x58 }, /* OVERRIDE */
  84. { 0x48, 0x19 }, /* OVERRIDE */
  85. { 0x52, 0x03 }, /* OVERRIDE */
  86. { 0x53, 0x44 }, /* OVERRIDE */
  87. { 0x6a, 0x4b }, /* OVERRIDE */
  88. { 0x76, 0x00 }, /* OVERRIDE */
  89. { 0x78, 0x18 }, /* OVERRIDE */
  90. { 0x7a, 0x17 }, /* OVERRIDE */
  91. { 0x85, 0x06 }, /* OVERRIDE */
  92. { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
  93. { 0, 0 }
  94. };
  95. static struct reg_pair_t init_tab_cable[] = {
  96. { 0x02, 0x06 },
  97. { 0x03, 0x48 },
  98. { 0x05, 0x04 },
  99. { 0x06, 0x10 },
  100. { 0x09, 0x3f },
  101. { 0x0a, 0x3f },
  102. { 0x0b, 0x3f },
  103. { 0x2e, 0x15 }, /* OVERRIDE */
  104. { 0x30, 0x10 }, /* OVERRIDE */
  105. { 0x45, 0x58 }, /* OVERRIDE */
  106. { 0x48, 0x19 }, /* OVERRIDE */
  107. { 0x52, 0x03 }, /* OVERRIDE */
  108. { 0x53, 0x44 }, /* OVERRIDE */
  109. { 0x6a, 0x4b }, /* OVERRIDE */
  110. { 0x76, 0x00 }, /* OVERRIDE */
  111. { 0x78, 0x18 }, /* OVERRIDE */
  112. { 0x7a, 0x17 }, /* OVERRIDE */
  113. { 0x85, 0x06 }, /* OVERRIDE */
  114. { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
  115. { 0, 0 }
  116. };
  117. /* ------------------------------------------------------------------------- */
  118. static struct reg_pair_t reg_pair_rftune[] = {
  119. { 0x0f, 0x00 }, /* abort tune */
  120. { 0x0c, 0x15 },
  121. { 0x0d, 0x40 },
  122. { 0x0e, 0x0e },
  123. { 0x1f, 0x87 }, /* OVERRIDE */
  124. { 0x20, 0x1f }, /* OVERRIDE */
  125. { 0x21, 0x87 }, /* OVERRIDE */
  126. { 0x22, 0x1f }, /* OVERRIDE */
  127. { 0x80, 0x01 }, /* freq dependent */
  128. { 0x0f, 0x01 }, /* start tune */
  129. { 0, 0 }
  130. };
  131. /* ------------------------------------------------------------------------- */
  132. struct mxl5007t_state {
  133. struct list_head hybrid_tuner_instance_list;
  134. struct tuner_i2c_props i2c_props;
  135. struct mutex lock;
  136. struct mxl5007t_config *config;
  137. enum mxl5007t_chip_version chip_id;
  138. struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
  139. struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
  140. struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
  141. enum mxl5007t_if_freq if_freq;
  142. u32 frequency;
  143. u32 bandwidth;
  144. };
  145. /* ------------------------------------------------------------------------- */
  146. /* called by _init and _rftun to manipulate the register arrays */
  147. static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
  148. {
  149. unsigned int i = 0;
  150. while (reg_pair[i].reg || reg_pair[i].val) {
  151. if (reg_pair[i].reg == reg) {
  152. reg_pair[i].val &= ~mask;
  153. reg_pair[i].val |= val;
  154. }
  155. i++;
  156. }
  157. return;
  158. }
  159. static void copy_reg_bits(struct reg_pair_t *reg_pair1,
  160. struct reg_pair_t *reg_pair2)
  161. {
  162. unsigned int i, j;
  163. i = j = 0;
  164. while (reg_pair1[i].reg || reg_pair1[i].val) {
  165. while (reg_pair2[j].reg || reg_pair2[j].val) {
  166. if (reg_pair1[i].reg != reg_pair2[j].reg) {
  167. j++;
  168. continue;
  169. }
  170. reg_pair2[j].val = reg_pair1[i].val;
  171. break;
  172. }
  173. i++;
  174. }
  175. return;
  176. }
  177. /* ------------------------------------------------------------------------- */
  178. static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
  179. enum mxl5007t_mode mode,
  180. s32 if_diff_out_level)
  181. {
  182. switch (mode) {
  183. case MxL_MODE_ATSC:
  184. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
  185. break;
  186. case MxL_MODE_DVBT:
  187. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
  188. break;
  189. case MxL_MODE_ISDBT:
  190. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
  191. break;
  192. case MxL_MODE_CABLE:
  193. set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
  194. set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
  195. 8 - if_diff_out_level);
  196. set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
  197. break;
  198. default:
  199. mxl_fail(-EINVAL);
  200. }
  201. return;
  202. }
  203. static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
  204. enum mxl5007t_if_freq if_freq,
  205. int invert_if)
  206. {
  207. u8 val;
  208. switch (if_freq) {
  209. case MxL_IF_4_MHZ:
  210. val = 0x00;
  211. break;
  212. case MxL_IF_4_5_MHZ:
  213. val = 0x02;
  214. break;
  215. case MxL_IF_4_57_MHZ:
  216. val = 0x03;
  217. break;
  218. case MxL_IF_5_MHZ:
  219. val = 0x04;
  220. break;
  221. case MxL_IF_5_38_MHZ:
  222. val = 0x05;
  223. break;
  224. case MxL_IF_6_MHZ:
  225. val = 0x06;
  226. break;
  227. case MxL_IF_6_28_MHZ:
  228. val = 0x07;
  229. break;
  230. case MxL_IF_9_1915_MHZ:
  231. val = 0x08;
  232. break;
  233. case MxL_IF_35_25_MHZ:
  234. val = 0x09;
  235. break;
  236. case MxL_IF_36_15_MHZ:
  237. val = 0x0a;
  238. break;
  239. case MxL_IF_44_MHZ:
  240. val = 0x0b;
  241. break;
  242. default:
  243. mxl_fail(-EINVAL);
  244. return;
  245. }
  246. set_reg_bits(state->tab_init, 0x02, 0x0f, val);
  247. /* set inverted IF or normal IF */
  248. set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
  249. state->if_freq = if_freq;
  250. return;
  251. }
  252. static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
  253. enum mxl5007t_xtal_freq xtal_freq)
  254. {
  255. switch (xtal_freq) {
  256. case MxL_XTAL_16_MHZ:
  257. /* select xtal freq & ref freq */
  258. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
  259. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
  260. break;
  261. case MxL_XTAL_20_MHZ:
  262. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
  263. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
  264. break;
  265. case MxL_XTAL_20_25_MHZ:
  266. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
  267. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
  268. break;
  269. case MxL_XTAL_20_48_MHZ:
  270. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
  271. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
  272. break;
  273. case MxL_XTAL_24_MHZ:
  274. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
  275. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
  276. break;
  277. case MxL_XTAL_25_MHZ:
  278. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
  279. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
  280. break;
  281. case MxL_XTAL_25_14_MHZ:
  282. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
  283. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
  284. break;
  285. case MxL_XTAL_27_MHZ:
  286. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
  287. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
  288. break;
  289. case MxL_XTAL_28_8_MHZ:
  290. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
  291. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
  292. break;
  293. case MxL_XTAL_32_MHZ:
  294. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
  295. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
  296. break;
  297. case MxL_XTAL_40_MHZ:
  298. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
  299. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
  300. break;
  301. case MxL_XTAL_44_MHZ:
  302. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
  303. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
  304. break;
  305. case MxL_XTAL_48_MHZ:
  306. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
  307. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
  308. break;
  309. case MxL_XTAL_49_3811_MHZ:
  310. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
  311. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
  312. break;
  313. default:
  314. mxl_fail(-EINVAL);
  315. return;
  316. }
  317. return;
  318. }
  319. static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
  320. enum mxl5007t_mode mode)
  321. {
  322. struct mxl5007t_config *cfg = state->config;
  323. memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
  324. memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
  325. mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
  326. mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
  327. mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
  328. set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable);
  329. set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
  330. set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
  331. if (mode >= MxL_MODE_CABLE) {
  332. copy_reg_bits(state->tab_init, state->tab_init_cable);
  333. return state->tab_init_cable;
  334. } else
  335. return state->tab_init;
  336. }
  337. /* ------------------------------------------------------------------------- */
  338. enum mxl5007t_bw_mhz {
  339. MxL_BW_6MHz = 6,
  340. MxL_BW_7MHz = 7,
  341. MxL_BW_8MHz = 8,
  342. };
  343. static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
  344. enum mxl5007t_bw_mhz bw)
  345. {
  346. u8 val;
  347. switch (bw) {
  348. case MxL_BW_6MHz:
  349. val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
  350. * and DIG_MODEINDEX_CSF */
  351. break;
  352. case MxL_BW_7MHz:
  353. val = 0x2a;
  354. break;
  355. case MxL_BW_8MHz:
  356. val = 0x3f;
  357. break;
  358. default:
  359. mxl_fail(-EINVAL);
  360. return;
  361. }
  362. set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
  363. return;
  364. }
  365. static struct
  366. reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
  367. u32 rf_freq, enum mxl5007t_bw_mhz bw)
  368. {
  369. u32 dig_rf_freq = 0;
  370. u32 temp;
  371. u32 frac_divider = 1000000;
  372. unsigned int i;
  373. memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
  374. mxl5007t_set_bw_bits(state, bw);
  375. /* Convert RF frequency into 16 bits =>
  376. * 10 bit integer (MHz) + 6 bit fraction */
  377. dig_rf_freq = rf_freq / MHz;
  378. temp = rf_freq % MHz;
  379. for (i = 0; i < 6; i++) {
  380. dig_rf_freq <<= 1;
  381. frac_divider /= 2;
  382. if (temp > frac_divider) {
  383. temp -= frac_divider;
  384. dig_rf_freq++;
  385. }
  386. }
  387. /* add to have shift center point by 7.8124 kHz */
  388. if (temp > 7812)
  389. dig_rf_freq++;
  390. set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
  391. set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
  392. if (rf_freq >= 333000000)
  393. set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
  394. return state->tab_rftune;
  395. }
  396. /* ------------------------------------------------------------------------- */
  397. static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
  398. {
  399. u8 buf[] = { reg, val };
  400. struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
  401. .buf = buf, .len = 2 };
  402. int ret;
  403. ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
  404. if (ret != 1) {
  405. mxl_err("failed!");
  406. return -EREMOTEIO;
  407. }
  408. return 0;
  409. }
  410. static int mxl5007t_write_regs(struct mxl5007t_state *state,
  411. struct reg_pair_t *reg_pair)
  412. {
  413. unsigned int i = 0;
  414. int ret = 0;
  415. while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
  416. ret = mxl5007t_write_reg(state,
  417. reg_pair[i].reg, reg_pair[i].val);
  418. i++;
  419. }
  420. return ret;
  421. }
  422. static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
  423. {
  424. struct i2c_msg msg[] = {
  425. { .addr = state->i2c_props.addr, .flags = 0,
  426. .buf = &reg, .len = 1 },
  427. { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
  428. .buf = val, .len = 1 },
  429. };
  430. int ret;
  431. ret = i2c_transfer(state->i2c_props.adap, msg, 2);
  432. if (ret != 2) {
  433. mxl_err("failed!");
  434. return -EREMOTEIO;
  435. }
  436. return 0;
  437. }
  438. static int mxl5007t_soft_reset(struct mxl5007t_state *state)
  439. {
  440. u8 d = 0xff;
  441. struct i2c_msg msg = {
  442. .addr = state->i2c_props.addr, .flags = 0,
  443. .buf = &d, .len = 1
  444. };
  445. int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
  446. if (ret != 1) {
  447. mxl_err("failed!");
  448. return -EREMOTEIO;
  449. }
  450. return 0;
  451. }
  452. static int mxl5007t_tuner_init(struct mxl5007t_state *state,
  453. enum mxl5007t_mode mode)
  454. {
  455. struct reg_pair_t *init_regs;
  456. int ret;
  457. ret = mxl5007t_soft_reset(state);
  458. if (mxl_fail(ret))
  459. goto fail;
  460. /* calculate initialization reg array */
  461. init_regs = mxl5007t_calc_init_regs(state, mode);
  462. ret = mxl5007t_write_regs(state, init_regs);
  463. if (mxl_fail(ret))
  464. goto fail;
  465. mdelay(1);
  466. fail:
  467. return ret;
  468. }
  469. static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
  470. enum mxl5007t_bw_mhz bw)
  471. {
  472. struct reg_pair_t *rf_tune_regs;
  473. int ret;
  474. /* calculate channel change reg array */
  475. rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
  476. ret = mxl5007t_write_regs(state, rf_tune_regs);
  477. if (mxl_fail(ret))
  478. goto fail;
  479. msleep(3);
  480. fail:
  481. return ret;
  482. }
  483. /* ------------------------------------------------------------------------- */
  484. static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
  485. int *rf_locked, int *ref_locked)
  486. {
  487. u8 d;
  488. int ret;
  489. *rf_locked = 0;
  490. *ref_locked = 0;
  491. ret = mxl5007t_read_reg(state, 0xd8, &d);
  492. if (mxl_fail(ret))
  493. goto fail;
  494. if ((d & 0x0c) == 0x0c)
  495. *rf_locked = 1;
  496. if ((d & 0x03) == 0x03)
  497. *ref_locked = 1;
  498. fail:
  499. return ret;
  500. }
  501. /* ------------------------------------------------------------------------- */
  502. static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
  503. {
  504. struct mxl5007t_state *state = fe->tuner_priv;
  505. int rf_locked, ref_locked, ret;
  506. *status = 0;
  507. if (fe->ops.i2c_gate_ctrl)
  508. fe->ops.i2c_gate_ctrl(fe, 1);
  509. ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
  510. if (mxl_fail(ret))
  511. goto fail;
  512. mxl_debug("%s%s", rf_locked ? "rf locked " : "",
  513. ref_locked ? "ref locked" : "");
  514. if ((rf_locked) || (ref_locked))
  515. *status |= TUNER_STATUS_LOCKED;
  516. fail:
  517. if (fe->ops.i2c_gate_ctrl)
  518. fe->ops.i2c_gate_ctrl(fe, 0);
  519. return ret;
  520. }
  521. /* ------------------------------------------------------------------------- */
  522. static int mxl5007t_set_params(struct dvb_frontend *fe,
  523. struct dvb_frontend_parameters *params)
  524. {
  525. struct mxl5007t_state *state = fe->tuner_priv;
  526. enum mxl5007t_bw_mhz bw;
  527. enum mxl5007t_mode mode;
  528. int ret;
  529. u32 freq = params->frequency;
  530. if (fe->ops.info.type == FE_ATSC) {
  531. switch (params->u.vsb.modulation) {
  532. case VSB_8:
  533. case VSB_16:
  534. mode = MxL_MODE_ATSC;
  535. break;
  536. case QAM_64:
  537. case QAM_256:
  538. mode = MxL_MODE_CABLE;
  539. break;
  540. default:
  541. mxl_err("modulation not set!");
  542. return -EINVAL;
  543. }
  544. bw = MxL_BW_6MHz;
  545. } else if (fe->ops.info.type == FE_OFDM) {
  546. switch (params->u.ofdm.bandwidth) {
  547. case BANDWIDTH_6_MHZ:
  548. bw = MxL_BW_6MHz;
  549. break;
  550. case BANDWIDTH_7_MHZ:
  551. bw = MxL_BW_7MHz;
  552. break;
  553. case BANDWIDTH_8_MHZ:
  554. bw = MxL_BW_8MHz;
  555. break;
  556. default:
  557. mxl_err("bandwidth not set!");
  558. return -EINVAL;
  559. }
  560. mode = MxL_MODE_DVBT;
  561. } else {
  562. mxl_err("modulation type not supported!");
  563. return -EINVAL;
  564. }
  565. if (fe->ops.i2c_gate_ctrl)
  566. fe->ops.i2c_gate_ctrl(fe, 1);
  567. mutex_lock(&state->lock);
  568. ret = mxl5007t_tuner_init(state, mode);
  569. if (mxl_fail(ret))
  570. goto fail;
  571. ret = mxl5007t_tuner_rf_tune(state, freq, bw);
  572. if (mxl_fail(ret))
  573. goto fail;
  574. state->frequency = freq;
  575. state->bandwidth = (fe->ops.info.type == FE_OFDM) ?
  576. params->u.ofdm.bandwidth : 0;
  577. fail:
  578. mutex_unlock(&state->lock);
  579. if (fe->ops.i2c_gate_ctrl)
  580. fe->ops.i2c_gate_ctrl(fe, 0);
  581. return ret;
  582. }
  583. /* ------------------------------------------------------------------------- */
  584. static int mxl5007t_init(struct dvb_frontend *fe)
  585. {
  586. struct mxl5007t_state *state = fe->tuner_priv;
  587. int ret;
  588. if (fe->ops.i2c_gate_ctrl)
  589. fe->ops.i2c_gate_ctrl(fe, 1);
  590. /* wake from standby */
  591. ret = mxl5007t_write_reg(state, 0x01, 0x01);
  592. mxl_fail(ret);
  593. if (fe->ops.i2c_gate_ctrl)
  594. fe->ops.i2c_gate_ctrl(fe, 0);
  595. return ret;
  596. }
  597. static int mxl5007t_sleep(struct dvb_frontend *fe)
  598. {
  599. struct mxl5007t_state *state = fe->tuner_priv;
  600. int ret;
  601. if (fe->ops.i2c_gate_ctrl)
  602. fe->ops.i2c_gate_ctrl(fe, 1);
  603. /* enter standby mode */
  604. ret = mxl5007t_write_reg(state, 0x01, 0x00);
  605. mxl_fail(ret);
  606. ret = mxl5007t_write_reg(state, 0x0f, 0x00);
  607. mxl_fail(ret);
  608. if (fe->ops.i2c_gate_ctrl)
  609. fe->ops.i2c_gate_ctrl(fe, 0);
  610. return ret;
  611. }
  612. /* ------------------------------------------------------------------------- */
  613. static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  614. {
  615. struct mxl5007t_state *state = fe->tuner_priv;
  616. *frequency = state->frequency;
  617. return 0;
  618. }
  619. static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  620. {
  621. struct mxl5007t_state *state = fe->tuner_priv;
  622. *bandwidth = state->bandwidth;
  623. return 0;
  624. }
  625. static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  626. {
  627. struct mxl5007t_state *state = fe->tuner_priv;
  628. *frequency = 0;
  629. switch (state->if_freq) {
  630. case MxL_IF_4_MHZ:
  631. *frequency = 4000000;
  632. break;
  633. case MxL_IF_4_5_MHZ:
  634. *frequency = 4500000;
  635. break;
  636. case MxL_IF_4_57_MHZ:
  637. *frequency = 4570000;
  638. break;
  639. case MxL_IF_5_MHZ:
  640. *frequency = 5000000;
  641. break;
  642. case MxL_IF_5_38_MHZ:
  643. *frequency = 5380000;
  644. break;
  645. case MxL_IF_6_MHZ:
  646. *frequency = 6000000;
  647. break;
  648. case MxL_IF_6_28_MHZ:
  649. *frequency = 6280000;
  650. break;
  651. case MxL_IF_9_1915_MHZ:
  652. *frequency = 9191500;
  653. break;
  654. case MxL_IF_35_25_MHZ:
  655. *frequency = 35250000;
  656. break;
  657. case MxL_IF_36_15_MHZ:
  658. *frequency = 36150000;
  659. break;
  660. case MxL_IF_44_MHZ:
  661. *frequency = 44000000;
  662. break;
  663. }
  664. return 0;
  665. }
  666. static int mxl5007t_release(struct dvb_frontend *fe)
  667. {
  668. struct mxl5007t_state *state = fe->tuner_priv;
  669. mutex_lock(&mxl5007t_list_mutex);
  670. if (state)
  671. hybrid_tuner_release_state(state);
  672. mutex_unlock(&mxl5007t_list_mutex);
  673. fe->tuner_priv = NULL;
  674. return 0;
  675. }
  676. /* ------------------------------------------------------------------------- */
  677. static struct dvb_tuner_ops mxl5007t_tuner_ops = {
  678. .info = {
  679. .name = "MaxLinear MxL5007T",
  680. },
  681. .init = mxl5007t_init,
  682. .sleep = mxl5007t_sleep,
  683. .set_params = mxl5007t_set_params,
  684. .get_status = mxl5007t_get_status,
  685. .get_frequency = mxl5007t_get_frequency,
  686. .get_bandwidth = mxl5007t_get_bandwidth,
  687. .release = mxl5007t_release,
  688. .get_if_frequency = mxl5007t_get_if_frequency,
  689. };
  690. static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
  691. {
  692. char *name;
  693. int ret;
  694. u8 id;
  695. ret = mxl5007t_read_reg(state, 0xd9, &id);
  696. if (mxl_fail(ret))
  697. goto fail;
  698. switch (id) {
  699. case MxL_5007_V1_F1:
  700. name = "MxL5007.v1.f1";
  701. break;
  702. case MxL_5007_V1_F2:
  703. name = "MxL5007.v1.f2";
  704. break;
  705. case MxL_5007_V2_100_F1:
  706. name = "MxL5007.v2.100.f1";
  707. break;
  708. case MxL_5007_V2_100_F2:
  709. name = "MxL5007.v2.100.f2";
  710. break;
  711. case MxL_5007_V2_200_F1:
  712. name = "MxL5007.v2.200.f1";
  713. break;
  714. case MxL_5007_V2_200_F2:
  715. name = "MxL5007.v2.200.f2";
  716. break;
  717. case MxL_5007_V4:
  718. name = "MxL5007T.v4";
  719. break;
  720. default:
  721. name = "MxL5007T";
  722. printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
  723. id = MxL_UNKNOWN_ID;
  724. }
  725. state->chip_id = id;
  726. mxl_info("%s detected @ %d-%04x", name,
  727. i2c_adapter_id(state->i2c_props.adap),
  728. state->i2c_props.addr);
  729. return 0;
  730. fail:
  731. mxl_warn("unable to identify device @ %d-%04x",
  732. i2c_adapter_id(state->i2c_props.adap),
  733. state->i2c_props.addr);
  734. state->chip_id = MxL_UNKNOWN_ID;
  735. return ret;
  736. }
  737. struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
  738. struct i2c_adapter *i2c, u8 addr,
  739. struct mxl5007t_config *cfg)
  740. {
  741. struct mxl5007t_state *state = NULL;
  742. int instance, ret;
  743. mutex_lock(&mxl5007t_list_mutex);
  744. instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
  745. hybrid_tuner_instance_list,
  746. i2c, addr, "mxl5007t");
  747. switch (instance) {
  748. case 0:
  749. goto fail;
  750. case 1:
  751. /* new tuner instance */
  752. state->config = cfg;
  753. mutex_init(&state->lock);
  754. if (fe->ops.i2c_gate_ctrl)
  755. fe->ops.i2c_gate_ctrl(fe, 1);
  756. ret = mxl5007t_get_chip_id(state);
  757. if (fe->ops.i2c_gate_ctrl)
  758. fe->ops.i2c_gate_ctrl(fe, 0);
  759. /* check return value of mxl5007t_get_chip_id */
  760. if (mxl_fail(ret))
  761. goto fail;
  762. break;
  763. default:
  764. /* existing tuner instance */
  765. break;
  766. }
  767. fe->tuner_priv = state;
  768. mutex_unlock(&mxl5007t_list_mutex);
  769. memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
  770. sizeof(struct dvb_tuner_ops));
  771. return fe;
  772. fail:
  773. mutex_unlock(&mxl5007t_list_mutex);
  774. mxl5007t_release(fe);
  775. return NULL;
  776. }
  777. EXPORT_SYMBOL_GPL(mxl5007t_attach);
  778. MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
  779. MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
  780. MODULE_LICENSE("GPL");
  781. MODULE_VERSION("0.2");
  782. /*
  783. * Overrides for Emacs so that we follow Linus's tabbing style.
  784. * ---------------------------------------------------------------------------
  785. * Local variables:
  786. * c-basic-offset: 8
  787. * End:
  788. */