cm_bf537.c 11 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf537/boards/cm_bf537.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2006 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/mtd/mtd.h>
  34. #include <linux/mtd/partitions.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/usb/isp1362.h>
  38. #include <linux/ata_platform.h>
  39. #include <linux/irq.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/portmux.h>
  43. /*
  44. * Name the Board for the /proc/cpuinfo
  45. */
  46. const char bfin_board_name[] = "Bluetechnix CM BF537";
  47. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  48. /* all SPI peripherals info goes here */
  49. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  50. static struct mtd_partition bfin_spi_flash_partitions[] = {
  51. {
  52. .name = "bootloader",
  53. .size = 0x00020000,
  54. .offset = 0,
  55. .mask_flags = MTD_CAP_ROM
  56. }, {
  57. .name = "kernel",
  58. .size = 0xe0000,
  59. .offset = 0x20000
  60. }, {
  61. .name = "file system",
  62. .size = 0x700000,
  63. .offset = 0x00100000,
  64. }
  65. };
  66. static struct flash_platform_data bfin_spi_flash_data = {
  67. .name = "m25p80",
  68. .parts = bfin_spi_flash_partitions,
  69. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  70. .type = "m25p64",
  71. };
  72. /* SPI flash chip (m25p64) */
  73. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  74. .enable_dma = 0, /* use dma transfer with this chip*/
  75. .bits_per_word = 8,
  76. };
  77. #endif
  78. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  79. /* SPI ADC chip */
  80. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  81. .enable_dma = 1, /* use dma transfer with this chip*/
  82. .bits_per_word = 16,
  83. };
  84. #endif
  85. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  86. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  87. .enable_dma = 0,
  88. .bits_per_word = 16,
  89. };
  90. #endif
  91. #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
  92. static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
  93. .enable_dma = 0,
  94. .bits_per_word = 16,
  95. };
  96. #endif
  97. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  98. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  99. .enable_dma = 1,
  100. .bits_per_word = 8,
  101. };
  102. #endif
  103. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  104. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  105. {
  106. /* the modalias must be the same as spi device driver name */
  107. .modalias = "m25p80", /* Name of spi_driver for this device */
  108. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  109. .bus_num = 0, /* Framework bus number */
  110. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  111. .platform_data = &bfin_spi_flash_data,
  112. .controller_data = &spi_flash_chip_info,
  113. .mode = SPI_MODE_3,
  114. },
  115. #endif
  116. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  117. {
  118. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  119. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  120. .bus_num = 0, /* Framework bus number */
  121. .chip_select = 1, /* Framework chip select. */
  122. .platform_data = NULL, /* No spi_driver specific config */
  123. .controller_data = &spi_adc_chip_info,
  124. },
  125. #endif
  126. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  127. {
  128. .modalias = "ad1836-spi",
  129. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  130. .bus_num = 0,
  131. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  132. .controller_data = &ad1836_spi_chip_info,
  133. },
  134. #endif
  135. #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
  136. {
  137. .modalias = "ad9960-spi",
  138. .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
  139. .bus_num = 0,
  140. .chip_select = 1,
  141. .controller_data = &ad9960_spi_chip_info,
  142. },
  143. #endif
  144. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  145. {
  146. .modalias = "spi_mmc_dummy",
  147. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  148. .bus_num = 0,
  149. .chip_select = 7,
  150. .platform_data = NULL,
  151. .controller_data = &spi_mmc_chip_info,
  152. .mode = SPI_MODE_3,
  153. },
  154. {
  155. .modalias = "spi_mmc",
  156. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  157. .bus_num = 0,
  158. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  159. .platform_data = NULL,
  160. .controller_data = &spi_mmc_chip_info,
  161. .mode = SPI_MODE_3,
  162. },
  163. #endif
  164. };
  165. /* SPI (0) */
  166. static struct resource bfin_spi0_resource[] = {
  167. [0] = {
  168. .start = SPI0_REGBASE,
  169. .end = SPI0_REGBASE + 0xFF,
  170. .flags = IORESOURCE_MEM,
  171. },
  172. [1] = {
  173. .start = CH_SPI,
  174. .end = CH_SPI,
  175. .flags = IORESOURCE_IRQ,
  176. }
  177. };
  178. /* SPI controller data */
  179. static struct bfin5xx_spi_master bfin_spi0_info = {
  180. .num_chipselect = 8,
  181. .enable_dma = 1, /* master has the ability to do dma transfer */
  182. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  183. };
  184. static struct platform_device bfin_spi0_device = {
  185. .name = "bfin-spi",
  186. .id = 0, /* Bus number */
  187. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  188. .resource = bfin_spi0_resource,
  189. .dev = {
  190. .platform_data = &bfin_spi0_info, /* Passed to driver */
  191. },
  192. };
  193. #endif /* spi master and devices */
  194. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  195. static struct platform_device rtc_device = {
  196. .name = "rtc-bfin",
  197. .id = -1,
  198. };
  199. #endif
  200. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  201. static struct platform_device hitachi_fb_device = {
  202. .name = "hitachi-tx09",
  203. };
  204. #endif
  205. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  206. static struct resource smc91x_resources[] = {
  207. {
  208. .start = 0x20200300,
  209. .end = 0x20200300 + 16,
  210. .flags = IORESOURCE_MEM,
  211. }, {
  212. .start = IRQ_PF14,
  213. .end = IRQ_PF14,
  214. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  215. },
  216. };
  217. static struct platform_device smc91x_device = {
  218. .name = "smc91x",
  219. .id = 0,
  220. .num_resources = ARRAY_SIZE(smc91x_resources),
  221. .resource = smc91x_resources,
  222. };
  223. #endif
  224. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  225. static struct resource isp1362_hcd_resources[] = {
  226. {
  227. .start = 0x20308000,
  228. .end = 0x20308000,
  229. .flags = IORESOURCE_MEM,
  230. }, {
  231. .start = 0x20308004,
  232. .end = 0x20308004,
  233. .flags = IORESOURCE_MEM,
  234. }, {
  235. .start = IRQ_PG15,
  236. .end = IRQ_PG15,
  237. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  238. },
  239. };
  240. static struct isp1362_platform_data isp1362_priv = {
  241. .sel15Kres = 1,
  242. .clknotstop = 0,
  243. .oc_enable = 0,
  244. .int_act_high = 0,
  245. .int_edge_triggered = 0,
  246. .remote_wakeup_connected = 0,
  247. .no_power_switching = 1,
  248. .power_switching_mode = 0,
  249. };
  250. static struct platform_device isp1362_hcd_device = {
  251. .name = "isp1362-hcd",
  252. .id = 0,
  253. .dev = {
  254. .platform_data = &isp1362_priv,
  255. },
  256. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  257. .resource = isp1362_hcd_resources,
  258. };
  259. #endif
  260. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  261. static struct resource net2272_bfin_resources[] = {
  262. {
  263. .start = 0x20200000,
  264. .end = 0x20200000 + 0x100,
  265. .flags = IORESOURCE_MEM,
  266. }, {
  267. .start = IRQ_PH14,
  268. .end = IRQ_PH14,
  269. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  270. },
  271. };
  272. static struct platform_device net2272_bfin_device = {
  273. .name = "net2272",
  274. .id = -1,
  275. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  276. .resource = net2272_bfin_resources,
  277. };
  278. #endif
  279. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  280. static struct resource bfin_uart_resources[] = {
  281. {
  282. .start = 0xFFC00400,
  283. .end = 0xFFC004FF,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = 0xFFC02000,
  287. .end = 0xFFC020FF,
  288. .flags = IORESOURCE_MEM,
  289. },
  290. };
  291. static struct platform_device bfin_uart_device = {
  292. .name = "bfin-uart",
  293. .id = 1,
  294. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  295. .resource = bfin_uart_resources,
  296. };
  297. #endif
  298. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  299. static struct platform_device bfin_sport0_uart_device = {
  300. .name = "bfin-sport-uart",
  301. .id = 0,
  302. };
  303. static struct platform_device bfin_sport1_uart_device = {
  304. .name = "bfin-sport-uart",
  305. .id = 1,
  306. };
  307. #endif
  308. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  309. static struct platform_device bfin_mac_device = {
  310. .name = "bfin_mac",
  311. };
  312. #endif
  313. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  314. #define PATA_INT 64
  315. static struct pata_platform_info bfin_pata_platform_data = {
  316. .ioport_shift = 2,
  317. .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
  318. };
  319. static struct resource bfin_pata_resources[] = {
  320. {
  321. .start = 0x2030C000,
  322. .end = 0x2030C01F,
  323. .flags = IORESOURCE_MEM,
  324. },
  325. {
  326. .start = 0x2030D018,
  327. .end = 0x2030D01B,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. {
  331. .start = PATA_INT,
  332. .end = PATA_INT,
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. };
  336. static struct platform_device bfin_pata_device = {
  337. .name = "pata_platform",
  338. .id = -1,
  339. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  340. .resource = bfin_pata_resources,
  341. .dev = {
  342. .platform_data = &bfin_pata_platform_data,
  343. }
  344. };
  345. #endif
  346. static struct platform_device *cm_bf537_devices[] __initdata = {
  347. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  348. &hitachi_fb_device,
  349. #endif
  350. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  351. &rtc_device,
  352. #endif
  353. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  354. &bfin_uart_device,
  355. #endif
  356. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  357. &bfin_sport0_uart_device,
  358. &bfin_sport1_uart_device,
  359. #endif
  360. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  361. &isp1362_hcd_device,
  362. #endif
  363. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  364. &smc91x_device,
  365. #endif
  366. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  367. &bfin_mac_device,
  368. #endif
  369. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  370. &net2272_bfin_device,
  371. #endif
  372. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  373. &bfin_spi0_device,
  374. #endif
  375. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  376. &bfin_pata_device,
  377. #endif
  378. };
  379. static int __init cm_bf537_init(void)
  380. {
  381. printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
  382. platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
  383. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  384. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  385. #endif
  386. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  387. irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
  388. #endif
  389. return 0;
  390. }
  391. arch_initcall(cm_bf537_init);
  392. void bfin_get_ether_addr(char *addr)
  393. {
  394. random_ether_addr(addr);
  395. printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
  396. }
  397. EXPORT_SYMBOL(bfin_get_ether_addr);