be_main.c 137 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. static unsigned int gcrashmode = 0;
  48. static unsigned int num_hba = 0;
  49. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  50. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  51. MODULE_VERSION(BUILD_STR);
  52. MODULE_AUTHOR("Emulex Corporation");
  53. MODULE_LICENSE("GPL");
  54. module_param(be_iopoll_budget, int, 0);
  55. module_param(enable_msix, int, 0);
  56. module_param(be_max_phys_size, uint, S_IRUGO);
  57. MODULE_PARM_DESC(be_max_phys_size,
  58. "Maximum Size (In Kilobytes) of physically contiguous "
  59. "memory that can be allocated. Range is 16 - 128");
  60. #define beiscsi_disp_param(_name)\
  61. ssize_t \
  62. beiscsi_##_name##_disp(struct device *dev,\
  63. struct device_attribute *attrib, char *buf) \
  64. { \
  65. struct Scsi_Host *shost = class_to_shost(dev);\
  66. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  67. uint32_t param_val = 0; \
  68. param_val = phba->attr_##_name;\
  69. return snprintf(buf, PAGE_SIZE, "%d\n",\
  70. phba->attr_##_name);\
  71. }
  72. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  73. int \
  74. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  75. {\
  76. if (val >= _minval && val <= _maxval) {\
  77. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  78. "BA_%d : beiscsi_"#_name" updated "\
  79. "from 0x%x ==> 0x%x\n",\
  80. phba->attr_##_name, val); \
  81. phba->attr_##_name = val;\
  82. return 0;\
  83. } \
  84. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  85. "BA_%d beiscsi_"#_name" attribute "\
  86. "cannot be updated to 0x%x, "\
  87. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  88. return -EINVAL;\
  89. }
  90. #define beiscsi_store_param(_name) \
  91. ssize_t \
  92. beiscsi_##_name##_store(struct device *dev,\
  93. struct device_attribute *attr, const char *buf,\
  94. size_t count) \
  95. { \
  96. struct Scsi_Host *shost = class_to_shost(dev);\
  97. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  98. uint32_t param_val = 0;\
  99. if (!isdigit(buf[0]))\
  100. return -EINVAL;\
  101. if (sscanf(buf, "%i", &param_val) != 1)\
  102. return -EINVAL;\
  103. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  104. return strlen(buf);\
  105. else \
  106. return -EINVAL;\
  107. }
  108. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  109. int \
  110. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  111. { \
  112. if (val >= _minval && val <= _maxval) {\
  113. phba->attr_##_name = val;\
  114. return 0;\
  115. } \
  116. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  117. "BA_%d beiscsi_"#_name" attribute " \
  118. "cannot be updated to 0x%x, "\
  119. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  120. phba->attr_##_name = _defval;\
  121. return -EINVAL;\
  122. }
  123. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  124. static uint beiscsi_##_name = _defval;\
  125. module_param(beiscsi_##_name, uint, S_IRUGO);\
  126. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  127. beiscsi_disp_param(_name)\
  128. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  129. beiscsi_store_param(_name)\
  130. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  131. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  132. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  133. /*
  134. * When new log level added update the
  135. * the MAX allowed value for log_enable
  136. */
  137. BEISCSI_RW_ATTR(log_enable, 0x00,
  138. 0xFF, 0x00, "Enable logging Bit Mask\n"
  139. "\t\t\t\tInitialization Events : 0x01\n"
  140. "\t\t\t\tMailbox Events : 0x02\n"
  141. "\t\t\t\tMiscellaneous Events : 0x04\n"
  142. "\t\t\t\tError Handling : 0x08\n"
  143. "\t\t\t\tIO Path Events : 0x10\n"
  144. "\t\t\t\tConfiguration Path : 0x20\n");
  145. struct device_attribute *beiscsi_attrs[] = {
  146. &dev_attr_beiscsi_log_enable,
  147. NULL,
  148. };
  149. static char const *cqe_desc[] = {
  150. "RESERVED_DESC",
  151. "SOL_CMD_COMPLETE",
  152. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  153. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  154. "CXN_KILLED_BURST_LEN_MISMATCH",
  155. "CXN_KILLED_AHS_RCVD",
  156. "CXN_KILLED_HDR_DIGEST_ERR",
  157. "CXN_KILLED_UNKNOWN_HDR",
  158. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  159. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  160. "CXN_KILLED_RST_RCVD",
  161. "CXN_KILLED_TIMED_OUT",
  162. "CXN_KILLED_RST_SENT",
  163. "CXN_KILLED_FIN_RCVD",
  164. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  165. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  166. "CXN_KILLED_OVER_RUN_RESIDUAL",
  167. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  168. "CMD_KILLED_INVALID_STATSN_RCVD",
  169. "CMD_KILLED_INVALID_R2T_RCVD",
  170. "CMD_CXN_KILLED_LUN_INVALID",
  171. "CMD_CXN_KILLED_ICD_INVALID",
  172. "CMD_CXN_KILLED_ITT_INVALID",
  173. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  174. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  175. "CXN_INVALIDATE_NOTIFY",
  176. "CXN_INVALIDATE_INDEX_NOTIFY",
  177. "CMD_INVALIDATED_NOTIFY",
  178. "UNSOL_HDR_NOTIFY",
  179. "UNSOL_DATA_NOTIFY",
  180. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  181. "DRIVERMSG_NOTIFY",
  182. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  183. "SOL_CMD_KILLED_DIF_ERR",
  184. "CXN_KILLED_SYN_RCVD",
  185. "CXN_KILLED_IMM_DATA_RCVD"
  186. };
  187. static int beiscsi_slave_configure(struct scsi_device *sdev)
  188. {
  189. blk_queue_max_segment_size(sdev->request_queue, 65536);
  190. return 0;
  191. }
  192. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  193. {
  194. struct iscsi_cls_session *cls_session;
  195. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  196. struct beiscsi_io_task *aborted_io_task;
  197. struct iscsi_conn *conn;
  198. struct beiscsi_conn *beiscsi_conn;
  199. struct beiscsi_hba *phba;
  200. struct iscsi_session *session;
  201. struct invalidate_command_table *inv_tbl;
  202. struct be_dma_mem nonemb_cmd;
  203. unsigned int cid, tag, num_invalidate;
  204. cls_session = starget_to_session(scsi_target(sc->device));
  205. session = cls_session->dd_data;
  206. spin_lock_bh(&session->lock);
  207. if (!aborted_task || !aborted_task->sc) {
  208. /* we raced */
  209. spin_unlock_bh(&session->lock);
  210. return SUCCESS;
  211. }
  212. aborted_io_task = aborted_task->dd_data;
  213. if (!aborted_io_task->scsi_cmnd) {
  214. /* raced or invalid command */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. spin_unlock_bh(&session->lock);
  219. conn = aborted_task->conn;
  220. beiscsi_conn = conn->dd_data;
  221. phba = beiscsi_conn->phba;
  222. /* invalidate iocb */
  223. cid = beiscsi_conn->beiscsi_conn_cid;
  224. inv_tbl = phba->inv_tbl;
  225. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  226. inv_tbl->cid = cid;
  227. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  228. num_invalidate = 1;
  229. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  230. sizeof(struct invalidate_commands_params_in),
  231. &nonemb_cmd.dma);
  232. if (nonemb_cmd.va == NULL) {
  233. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  234. "BM_%d : Failed to allocate memory for"
  235. "mgmt_invalidate_icds\n");
  236. return FAILED;
  237. }
  238. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  239. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  240. cid, &nonemb_cmd);
  241. if (!tag) {
  242. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  243. "BM_%d : mgmt_invalidate_icds could not be"
  244. "submitted\n");
  245. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  246. nonemb_cmd.va, nonemb_cmd.dma);
  247. return FAILED;
  248. } else {
  249. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  250. phba->ctrl.mcc_numtag[tag]);
  251. free_mcc_tag(&phba->ctrl, tag);
  252. }
  253. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  254. nonemb_cmd.va, nonemb_cmd.dma);
  255. return iscsi_eh_abort(sc);
  256. }
  257. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  258. {
  259. struct iscsi_task *abrt_task;
  260. struct beiscsi_io_task *abrt_io_task;
  261. struct iscsi_conn *conn;
  262. struct beiscsi_conn *beiscsi_conn;
  263. struct beiscsi_hba *phba;
  264. struct iscsi_session *session;
  265. struct iscsi_cls_session *cls_session;
  266. struct invalidate_command_table *inv_tbl;
  267. struct be_dma_mem nonemb_cmd;
  268. unsigned int cid, tag, i, num_invalidate;
  269. /* invalidate iocbs */
  270. cls_session = starget_to_session(scsi_target(sc->device));
  271. session = cls_session->dd_data;
  272. spin_lock_bh(&session->lock);
  273. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  274. spin_unlock_bh(&session->lock);
  275. return FAILED;
  276. }
  277. conn = session->leadconn;
  278. beiscsi_conn = conn->dd_data;
  279. phba = beiscsi_conn->phba;
  280. cid = beiscsi_conn->beiscsi_conn_cid;
  281. inv_tbl = phba->inv_tbl;
  282. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  283. num_invalidate = 0;
  284. for (i = 0; i < conn->session->cmds_max; i++) {
  285. abrt_task = conn->session->cmds[i];
  286. abrt_io_task = abrt_task->dd_data;
  287. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  288. continue;
  289. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  290. continue;
  291. inv_tbl->cid = cid;
  292. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  293. num_invalidate++;
  294. inv_tbl++;
  295. }
  296. spin_unlock_bh(&session->lock);
  297. inv_tbl = phba->inv_tbl;
  298. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  299. sizeof(struct invalidate_commands_params_in),
  300. &nonemb_cmd.dma);
  301. if (nonemb_cmd.va == NULL) {
  302. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  303. "BM_%d : Failed to allocate memory for"
  304. "mgmt_invalidate_icds\n");
  305. return FAILED;
  306. }
  307. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  308. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  309. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  310. cid, &nonemb_cmd);
  311. if (!tag) {
  312. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  313. "BM_%d : mgmt_invalidate_icds could not be"
  314. " submitted\n");
  315. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  316. nonemb_cmd.va, nonemb_cmd.dma);
  317. return FAILED;
  318. } else {
  319. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  320. phba->ctrl.mcc_numtag[tag]);
  321. free_mcc_tag(&phba->ctrl, tag);
  322. }
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { 0 }
  484. };
  485. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  486. static struct scsi_host_template beiscsi_sht = {
  487. .module = THIS_MODULE,
  488. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  489. .proc_name = DRV_NAME,
  490. .queuecommand = iscsi_queuecommand,
  491. .change_queue_depth = iscsi_change_queue_depth,
  492. .slave_configure = beiscsi_slave_configure,
  493. .target_alloc = iscsi_target_alloc,
  494. .eh_abort_handler = beiscsi_eh_abort,
  495. .eh_device_reset_handler = beiscsi_eh_device_reset,
  496. .eh_target_reset_handler = iscsi_eh_session_reset,
  497. .shost_attrs = beiscsi_attrs,
  498. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  499. .can_queue = BE2_IO_DEPTH,
  500. .this_id = -1,
  501. .max_sectors = BEISCSI_MAX_SECTORS,
  502. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  503. .use_clustering = ENABLE_CLUSTERING,
  504. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  505. };
  506. static struct scsi_transport_template *beiscsi_scsi_transport;
  507. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  508. {
  509. struct beiscsi_hba *phba;
  510. struct Scsi_Host *shost;
  511. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  512. if (!shost) {
  513. dev_err(&pcidev->dev,
  514. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  515. return NULL;
  516. }
  517. shost->dma_boundary = pcidev->dma_mask;
  518. shost->max_id = BE2_MAX_SESSIONS;
  519. shost->max_channel = 0;
  520. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  521. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  522. shost->transportt = beiscsi_scsi_transport;
  523. phba = iscsi_host_priv(shost);
  524. memset(phba, 0, sizeof(*phba));
  525. phba->shost = shost;
  526. phba->pcidev = pci_dev_get(pcidev);
  527. pci_set_drvdata(pcidev, phba);
  528. phba->interface_handle = 0xFFFFFFFF;
  529. if (iscsi_host_add(shost, &phba->pcidev->dev))
  530. goto free_devices;
  531. return phba;
  532. free_devices:
  533. pci_dev_put(phba->pcidev);
  534. iscsi_host_free(phba->shost);
  535. return NULL;
  536. }
  537. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  538. {
  539. if (phba->csr_va) {
  540. iounmap(phba->csr_va);
  541. phba->csr_va = NULL;
  542. }
  543. if (phba->db_va) {
  544. iounmap(phba->db_va);
  545. phba->db_va = NULL;
  546. }
  547. if (phba->pci_va) {
  548. iounmap(phba->pci_va);
  549. phba->pci_va = NULL;
  550. }
  551. }
  552. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  553. struct pci_dev *pcidev)
  554. {
  555. u8 __iomem *addr;
  556. int pcicfg_reg;
  557. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  558. pci_resource_len(pcidev, 2));
  559. if (addr == NULL)
  560. return -ENOMEM;
  561. phba->ctrl.csr = addr;
  562. phba->csr_va = addr;
  563. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  564. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  565. if (addr == NULL)
  566. goto pci_map_err;
  567. phba->ctrl.db = addr;
  568. phba->db_va = addr;
  569. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  570. if (phba->generation == BE_GEN2)
  571. pcicfg_reg = 1;
  572. else
  573. pcicfg_reg = 0;
  574. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  575. pci_resource_len(pcidev, pcicfg_reg));
  576. if (addr == NULL)
  577. goto pci_map_err;
  578. phba->ctrl.pcicfg = addr;
  579. phba->pci_va = addr;
  580. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  581. return 0;
  582. pci_map_err:
  583. beiscsi_unmap_pci_function(phba);
  584. return -ENOMEM;
  585. }
  586. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  587. {
  588. int ret;
  589. ret = pci_enable_device(pcidev);
  590. if (ret) {
  591. dev_err(&pcidev->dev,
  592. "beiscsi_enable_pci - enable device failed\n");
  593. return ret;
  594. }
  595. pci_set_master(pcidev);
  596. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  597. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  598. if (ret) {
  599. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  600. pci_disable_device(pcidev);
  601. return ret;
  602. }
  603. }
  604. return 0;
  605. }
  606. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  607. {
  608. struct be_ctrl_info *ctrl = &phba->ctrl;
  609. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  610. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  611. int status = 0;
  612. ctrl->pdev = pdev;
  613. status = beiscsi_map_pci_bars(phba, pdev);
  614. if (status)
  615. return status;
  616. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  617. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  618. mbox_mem_alloc->size,
  619. &mbox_mem_alloc->dma);
  620. if (!mbox_mem_alloc->va) {
  621. beiscsi_unmap_pci_function(phba);
  622. return -ENOMEM;
  623. }
  624. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  625. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  626. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  627. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  628. spin_lock_init(&ctrl->mbox_lock);
  629. spin_lock_init(&phba->ctrl.mcc_lock);
  630. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  631. return status;
  632. }
  633. static void beiscsi_get_params(struct beiscsi_hba *phba)
  634. {
  635. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  636. - (phba->fw_config.iscsi_cid_count
  637. + BE2_TMFS
  638. + BE2_NOPOUT_REQ));
  639. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  640. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  641. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  642. phba->params.num_sge_per_io = BE2_SGE;
  643. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  644. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  645. phba->params.eq_timer = 64;
  646. phba->params.num_eq_entries =
  647. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  648. + BE2_TMFS) / 512) + 1) * 512;
  649. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  650. ? 1024 : phba->params.num_eq_entries;
  651. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  652. "BM_%d : phba->params.num_eq_entries=%d\n",
  653. phba->params.num_eq_entries);
  654. phba->params.num_cq_entries =
  655. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  656. + BE2_TMFS) / 512) + 1) * 512;
  657. phba->params.wrbs_per_cxn = 256;
  658. }
  659. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  660. unsigned int id, unsigned int clr_interrupt,
  661. unsigned int num_processed,
  662. unsigned char rearm, unsigned char event)
  663. {
  664. u32 val = 0;
  665. val |= id & DB_EQ_RING_ID_MASK;
  666. if (rearm)
  667. val |= 1 << DB_EQ_REARM_SHIFT;
  668. if (clr_interrupt)
  669. val |= 1 << DB_EQ_CLR_SHIFT;
  670. if (event)
  671. val |= 1 << DB_EQ_EVNT_SHIFT;
  672. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  673. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  674. }
  675. /**
  676. * be_isr_mcc - The isr routine of the driver.
  677. * @irq: Not used
  678. * @dev_id: Pointer to host adapter structure
  679. */
  680. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  681. {
  682. struct beiscsi_hba *phba;
  683. struct be_eq_entry *eqe = NULL;
  684. struct be_queue_info *eq;
  685. struct be_queue_info *mcc;
  686. unsigned int num_eq_processed;
  687. struct be_eq_obj *pbe_eq;
  688. unsigned long flags;
  689. pbe_eq = dev_id;
  690. eq = &pbe_eq->q;
  691. phba = pbe_eq->phba;
  692. mcc = &phba->ctrl.mcc_obj.cq;
  693. eqe = queue_tail_node(eq);
  694. num_eq_processed = 0;
  695. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  696. & EQE_VALID_MASK) {
  697. if (((eqe->dw[offsetof(struct amap_eq_entry,
  698. resource_id) / 32] &
  699. EQE_RESID_MASK) >> 16) == mcc->id) {
  700. spin_lock_irqsave(&phba->isr_lock, flags);
  701. phba->todo_mcc_cq = 1;
  702. spin_unlock_irqrestore(&phba->isr_lock, flags);
  703. }
  704. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  705. queue_tail_inc(eq);
  706. eqe = queue_tail_node(eq);
  707. num_eq_processed++;
  708. }
  709. if (phba->todo_mcc_cq)
  710. queue_work(phba->wq, &phba->work_cqs);
  711. if (num_eq_processed)
  712. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  713. return IRQ_HANDLED;
  714. }
  715. /**
  716. * be_isr_msix - The isr routine of the driver.
  717. * @irq: Not used
  718. * @dev_id: Pointer to host adapter structure
  719. */
  720. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  721. {
  722. struct beiscsi_hba *phba;
  723. struct be_eq_entry *eqe = NULL;
  724. struct be_queue_info *eq;
  725. struct be_queue_info *cq;
  726. unsigned int num_eq_processed;
  727. struct be_eq_obj *pbe_eq;
  728. unsigned long flags;
  729. pbe_eq = dev_id;
  730. eq = &pbe_eq->q;
  731. cq = pbe_eq->cq;
  732. eqe = queue_tail_node(eq);
  733. phba = pbe_eq->phba;
  734. num_eq_processed = 0;
  735. if (blk_iopoll_enabled) {
  736. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  737. & EQE_VALID_MASK) {
  738. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  739. blk_iopoll_sched(&pbe_eq->iopoll);
  740. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  741. queue_tail_inc(eq);
  742. eqe = queue_tail_node(eq);
  743. num_eq_processed++;
  744. }
  745. if (num_eq_processed)
  746. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  747. return IRQ_HANDLED;
  748. } else {
  749. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  750. & EQE_VALID_MASK) {
  751. spin_lock_irqsave(&phba->isr_lock, flags);
  752. phba->todo_cq = 1;
  753. spin_unlock_irqrestore(&phba->isr_lock, flags);
  754. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  755. queue_tail_inc(eq);
  756. eqe = queue_tail_node(eq);
  757. num_eq_processed++;
  758. }
  759. if (phba->todo_cq)
  760. queue_work(phba->wq, &phba->work_cqs);
  761. if (num_eq_processed)
  762. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  763. return IRQ_HANDLED;
  764. }
  765. }
  766. /**
  767. * be_isr - The isr routine of the driver.
  768. * @irq: Not used
  769. * @dev_id: Pointer to host adapter structure
  770. */
  771. static irqreturn_t be_isr(int irq, void *dev_id)
  772. {
  773. struct beiscsi_hba *phba;
  774. struct hwi_controller *phwi_ctrlr;
  775. struct hwi_context_memory *phwi_context;
  776. struct be_eq_entry *eqe = NULL;
  777. struct be_queue_info *eq;
  778. struct be_queue_info *cq;
  779. struct be_queue_info *mcc;
  780. unsigned long flags, index;
  781. unsigned int num_mcceq_processed, num_ioeq_processed;
  782. struct be_ctrl_info *ctrl;
  783. struct be_eq_obj *pbe_eq;
  784. int isr;
  785. phba = dev_id;
  786. ctrl = &phba->ctrl;
  787. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  788. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  789. if (!isr)
  790. return IRQ_NONE;
  791. phwi_ctrlr = phba->phwi_ctrlr;
  792. phwi_context = phwi_ctrlr->phwi_ctxt;
  793. pbe_eq = &phwi_context->be_eq[0];
  794. eq = &phwi_context->be_eq[0].q;
  795. mcc = &phba->ctrl.mcc_obj.cq;
  796. index = 0;
  797. eqe = queue_tail_node(eq);
  798. num_ioeq_processed = 0;
  799. num_mcceq_processed = 0;
  800. if (blk_iopoll_enabled) {
  801. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  802. & EQE_VALID_MASK) {
  803. if (((eqe->dw[offsetof(struct amap_eq_entry,
  804. resource_id) / 32] &
  805. EQE_RESID_MASK) >> 16) == mcc->id) {
  806. spin_lock_irqsave(&phba->isr_lock, flags);
  807. phba->todo_mcc_cq = 1;
  808. spin_unlock_irqrestore(&phba->isr_lock, flags);
  809. num_mcceq_processed++;
  810. } else {
  811. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  812. blk_iopoll_sched(&pbe_eq->iopoll);
  813. num_ioeq_processed++;
  814. }
  815. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  816. queue_tail_inc(eq);
  817. eqe = queue_tail_node(eq);
  818. }
  819. if (num_ioeq_processed || num_mcceq_processed) {
  820. if (phba->todo_mcc_cq)
  821. queue_work(phba->wq, &phba->work_cqs);
  822. if ((num_mcceq_processed) && (!num_ioeq_processed))
  823. hwi_ring_eq_db(phba, eq->id, 0,
  824. (num_ioeq_processed +
  825. num_mcceq_processed) , 1, 1);
  826. else
  827. hwi_ring_eq_db(phba, eq->id, 0,
  828. (num_ioeq_processed +
  829. num_mcceq_processed), 0, 1);
  830. return IRQ_HANDLED;
  831. } else
  832. return IRQ_NONE;
  833. } else {
  834. cq = &phwi_context->be_cq[0];
  835. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  836. & EQE_VALID_MASK) {
  837. if (((eqe->dw[offsetof(struct amap_eq_entry,
  838. resource_id) / 32] &
  839. EQE_RESID_MASK) >> 16) != cq->id) {
  840. spin_lock_irqsave(&phba->isr_lock, flags);
  841. phba->todo_mcc_cq = 1;
  842. spin_unlock_irqrestore(&phba->isr_lock, flags);
  843. } else {
  844. spin_lock_irqsave(&phba->isr_lock, flags);
  845. phba->todo_cq = 1;
  846. spin_unlock_irqrestore(&phba->isr_lock, flags);
  847. }
  848. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  849. queue_tail_inc(eq);
  850. eqe = queue_tail_node(eq);
  851. num_ioeq_processed++;
  852. }
  853. if (phba->todo_cq || phba->todo_mcc_cq)
  854. queue_work(phba->wq, &phba->work_cqs);
  855. if (num_ioeq_processed) {
  856. hwi_ring_eq_db(phba, eq->id, 0,
  857. num_ioeq_processed, 1, 1);
  858. return IRQ_HANDLED;
  859. } else
  860. return IRQ_NONE;
  861. }
  862. }
  863. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  864. {
  865. struct pci_dev *pcidev = phba->pcidev;
  866. struct hwi_controller *phwi_ctrlr;
  867. struct hwi_context_memory *phwi_context;
  868. int ret, msix_vec, i, j;
  869. phwi_ctrlr = phba->phwi_ctrlr;
  870. phwi_context = phwi_ctrlr->phwi_ctxt;
  871. if (phba->msix_enabled) {
  872. for (i = 0; i < phba->num_cpus; i++) {
  873. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  874. GFP_KERNEL);
  875. if (!phba->msi_name[i]) {
  876. ret = -ENOMEM;
  877. goto free_msix_irqs;
  878. }
  879. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  880. phba->shost->host_no, i);
  881. msix_vec = phba->msix_entries[i].vector;
  882. ret = request_irq(msix_vec, be_isr_msix, 0,
  883. phba->msi_name[i],
  884. &phwi_context->be_eq[i]);
  885. if (ret) {
  886. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  887. "BM_%d : beiscsi_init_irqs-Failed to"
  888. "register msix for i = %d\n",
  889. i);
  890. kfree(phba->msi_name[i]);
  891. goto free_msix_irqs;
  892. }
  893. }
  894. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  895. if (!phba->msi_name[i]) {
  896. ret = -ENOMEM;
  897. goto free_msix_irqs;
  898. }
  899. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  900. phba->shost->host_no);
  901. msix_vec = phba->msix_entries[i].vector;
  902. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  903. &phwi_context->be_eq[i]);
  904. if (ret) {
  905. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  906. "BM_%d : beiscsi_init_irqs-"
  907. "Failed to register beiscsi_msix_mcc\n");
  908. kfree(phba->msi_name[i]);
  909. goto free_msix_irqs;
  910. }
  911. } else {
  912. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  913. "beiscsi", phba);
  914. if (ret) {
  915. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  916. "BM_%d : beiscsi_init_irqs-"
  917. "Failed to register irq\\n");
  918. return ret;
  919. }
  920. }
  921. return 0;
  922. free_msix_irqs:
  923. for (j = i - 1; j >= 0; j--) {
  924. kfree(phba->msi_name[j]);
  925. msix_vec = phba->msix_entries[j].vector;
  926. free_irq(msix_vec, &phwi_context->be_eq[j]);
  927. }
  928. return ret;
  929. }
  930. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  931. unsigned int id, unsigned int num_processed,
  932. unsigned char rearm, unsigned char event)
  933. {
  934. u32 val = 0;
  935. val |= id & DB_CQ_RING_ID_MASK;
  936. if (rearm)
  937. val |= 1 << DB_CQ_REARM_SHIFT;
  938. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  939. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  940. }
  941. static unsigned int
  942. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  943. struct beiscsi_hba *phba,
  944. unsigned short cid,
  945. struct pdu_base *ppdu,
  946. unsigned long pdu_len,
  947. void *pbuffer, unsigned long buf_len)
  948. {
  949. struct iscsi_conn *conn = beiscsi_conn->conn;
  950. struct iscsi_session *session = conn->session;
  951. struct iscsi_task *task;
  952. struct beiscsi_io_task *io_task;
  953. struct iscsi_hdr *login_hdr;
  954. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  955. PDUBASE_OPCODE_MASK) {
  956. case ISCSI_OP_NOOP_IN:
  957. pbuffer = NULL;
  958. buf_len = 0;
  959. break;
  960. case ISCSI_OP_ASYNC_EVENT:
  961. break;
  962. case ISCSI_OP_REJECT:
  963. WARN_ON(!pbuffer);
  964. WARN_ON(!(buf_len == 48));
  965. beiscsi_log(phba, KERN_ERR,
  966. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  967. "BM_%d : In ISCSI_OP_REJECT\n");
  968. break;
  969. case ISCSI_OP_LOGIN_RSP:
  970. case ISCSI_OP_TEXT_RSP:
  971. task = conn->login_task;
  972. io_task = task->dd_data;
  973. login_hdr = (struct iscsi_hdr *)ppdu;
  974. login_hdr->itt = io_task->libiscsi_itt;
  975. break;
  976. default:
  977. beiscsi_log(phba, KERN_WARNING,
  978. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  979. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  980. (ppdu->
  981. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  982. & PDUBASE_OPCODE_MASK));
  983. return 1;
  984. }
  985. spin_lock_bh(&session->lock);
  986. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  987. spin_unlock_bh(&session->lock);
  988. return 0;
  989. }
  990. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  991. {
  992. struct sgl_handle *psgl_handle;
  993. if (phba->io_sgl_hndl_avbl) {
  994. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  995. "BM_%d : In alloc_io_sgl_handle,"
  996. " io_sgl_alloc_index=%d\n",
  997. phba->io_sgl_alloc_index);
  998. psgl_handle = phba->io_sgl_hndl_base[phba->
  999. io_sgl_alloc_index];
  1000. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  1001. phba->io_sgl_hndl_avbl--;
  1002. if (phba->io_sgl_alloc_index == (phba->params.
  1003. ios_per_ctrl - 1))
  1004. phba->io_sgl_alloc_index = 0;
  1005. else
  1006. phba->io_sgl_alloc_index++;
  1007. } else
  1008. psgl_handle = NULL;
  1009. return psgl_handle;
  1010. }
  1011. static void
  1012. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1013. {
  1014. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1015. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1016. phba->io_sgl_free_index);
  1017. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1018. /*
  1019. * this can happen if clean_task is called on a task that
  1020. * failed in xmit_task or alloc_pdu.
  1021. */
  1022. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1023. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1024. "value there=%p\n", phba->io_sgl_free_index,
  1025. phba->io_sgl_hndl_base
  1026. [phba->io_sgl_free_index]);
  1027. return;
  1028. }
  1029. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1030. phba->io_sgl_hndl_avbl++;
  1031. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1032. phba->io_sgl_free_index = 0;
  1033. else
  1034. phba->io_sgl_free_index++;
  1035. }
  1036. /**
  1037. * alloc_wrb_handle - To allocate a wrb handle
  1038. * @phba: The hba pointer
  1039. * @cid: The cid to use for allocation
  1040. *
  1041. * This happens under session_lock until submission to chip
  1042. */
  1043. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1044. {
  1045. struct hwi_wrb_context *pwrb_context;
  1046. struct hwi_controller *phwi_ctrlr;
  1047. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1048. phwi_ctrlr = phba->phwi_ctrlr;
  1049. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1050. if (pwrb_context->wrb_handles_available >= 2) {
  1051. pwrb_handle = pwrb_context->pwrb_handle_base[
  1052. pwrb_context->alloc_index];
  1053. pwrb_context->wrb_handles_available--;
  1054. if (pwrb_context->alloc_index ==
  1055. (phba->params.wrbs_per_cxn - 1))
  1056. pwrb_context->alloc_index = 0;
  1057. else
  1058. pwrb_context->alloc_index++;
  1059. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1060. pwrb_context->alloc_index];
  1061. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1062. } else
  1063. pwrb_handle = NULL;
  1064. return pwrb_handle;
  1065. }
  1066. /**
  1067. * free_wrb_handle - To free the wrb handle back to pool
  1068. * @phba: The hba pointer
  1069. * @pwrb_context: The context to free from
  1070. * @pwrb_handle: The wrb_handle to free
  1071. *
  1072. * This happens under session_lock until submission to chip
  1073. */
  1074. static void
  1075. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1076. struct wrb_handle *pwrb_handle)
  1077. {
  1078. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1079. pwrb_context->wrb_handles_available++;
  1080. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1081. pwrb_context->free_index = 0;
  1082. else
  1083. pwrb_context->free_index++;
  1084. beiscsi_log(phba, KERN_INFO,
  1085. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1086. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1087. "wrb_handles_available=%d\n",
  1088. pwrb_handle, pwrb_context->free_index,
  1089. pwrb_context->wrb_handles_available);
  1090. }
  1091. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1092. {
  1093. struct sgl_handle *psgl_handle;
  1094. if (phba->eh_sgl_hndl_avbl) {
  1095. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1096. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1097. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1098. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1099. phba->eh_sgl_alloc_index,
  1100. phba->eh_sgl_alloc_index);
  1101. phba->eh_sgl_hndl_avbl--;
  1102. if (phba->eh_sgl_alloc_index ==
  1103. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1104. 1))
  1105. phba->eh_sgl_alloc_index = 0;
  1106. else
  1107. phba->eh_sgl_alloc_index++;
  1108. } else
  1109. psgl_handle = NULL;
  1110. return psgl_handle;
  1111. }
  1112. void
  1113. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1114. {
  1115. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1116. "BM_%d : In free_mgmt_sgl_handle,"
  1117. "eh_sgl_free_index=%d\n",
  1118. phba->eh_sgl_free_index);
  1119. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1120. /*
  1121. * this can happen if clean_task is called on a task that
  1122. * failed in xmit_task or alloc_pdu.
  1123. */
  1124. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1125. "BM_%d : Double Free in eh SGL ,"
  1126. "eh_sgl_free_index=%d\n",
  1127. phba->eh_sgl_free_index);
  1128. return;
  1129. }
  1130. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1131. phba->eh_sgl_hndl_avbl++;
  1132. if (phba->eh_sgl_free_index ==
  1133. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1134. phba->eh_sgl_free_index = 0;
  1135. else
  1136. phba->eh_sgl_free_index++;
  1137. }
  1138. static void
  1139. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1140. struct iscsi_task *task, struct sol_cqe *psol)
  1141. {
  1142. struct beiscsi_io_task *io_task = task->dd_data;
  1143. struct be_status_bhs *sts_bhs =
  1144. (struct be_status_bhs *)io_task->cmd_bhs;
  1145. struct iscsi_conn *conn = beiscsi_conn->conn;
  1146. unsigned char *sense;
  1147. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1148. u8 rsp, status, flags;
  1149. exp_cmdsn = (psol->
  1150. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1151. & SOL_EXP_CMD_SN_MASK);
  1152. max_cmdsn = ((psol->
  1153. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1154. & SOL_EXP_CMD_SN_MASK) +
  1155. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1156. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1157. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1158. & SOL_RESP_MASK) >> 16);
  1159. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1160. & SOL_STS_MASK) >> 8);
  1161. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1162. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1163. if (!task->sc) {
  1164. if (io_task->scsi_cmnd)
  1165. scsi_dma_unmap(io_task->scsi_cmnd);
  1166. return;
  1167. }
  1168. task->sc->result = (DID_OK << 16) | status;
  1169. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1170. task->sc->result = DID_ERROR << 16;
  1171. goto unmap;
  1172. }
  1173. /* bidi not initially supported */
  1174. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1175. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1176. 32] & SOL_RES_CNT_MASK);
  1177. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1178. task->sc->result = DID_ERROR << 16;
  1179. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1180. scsi_set_resid(task->sc, resid);
  1181. if (!status && (scsi_bufflen(task->sc) - resid <
  1182. task->sc->underflow))
  1183. task->sc->result = DID_ERROR << 16;
  1184. }
  1185. }
  1186. if (status == SAM_STAT_CHECK_CONDITION) {
  1187. u16 sense_len;
  1188. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1189. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1190. sense_len = be16_to_cpu(*slen);
  1191. memcpy(task->sc->sense_buffer, sense,
  1192. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1193. }
  1194. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1195. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1196. & SOL_RES_CNT_MASK)
  1197. conn->rxdata_octets += (psol->
  1198. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1199. & SOL_RES_CNT_MASK);
  1200. }
  1201. unmap:
  1202. scsi_dma_unmap(io_task->scsi_cmnd);
  1203. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1204. }
  1205. static void
  1206. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1207. struct iscsi_task *task, struct sol_cqe *psol)
  1208. {
  1209. struct iscsi_logout_rsp *hdr;
  1210. struct beiscsi_io_task *io_task = task->dd_data;
  1211. struct iscsi_conn *conn = beiscsi_conn->conn;
  1212. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1213. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1214. hdr->t2wait = 5;
  1215. hdr->t2retain = 0;
  1216. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1217. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1218. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1219. 32] & SOL_RESP_MASK);
  1220. hdr->exp_cmdsn = cpu_to_be32(psol->
  1221. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1222. & SOL_EXP_CMD_SN_MASK);
  1223. hdr->max_cmdsn = be32_to_cpu((psol->
  1224. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1225. & SOL_EXP_CMD_SN_MASK) +
  1226. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1227. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1228. hdr->dlength[0] = 0;
  1229. hdr->dlength[1] = 0;
  1230. hdr->dlength[2] = 0;
  1231. hdr->hlength = 0;
  1232. hdr->itt = io_task->libiscsi_itt;
  1233. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1234. }
  1235. static void
  1236. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1237. struct iscsi_task *task, struct sol_cqe *psol)
  1238. {
  1239. struct iscsi_tm_rsp *hdr;
  1240. struct iscsi_conn *conn = beiscsi_conn->conn;
  1241. struct beiscsi_io_task *io_task = task->dd_data;
  1242. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1243. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1244. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1245. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1246. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1247. 32] & SOL_RESP_MASK);
  1248. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1249. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1250. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1251. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1252. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1253. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1254. hdr->itt = io_task->libiscsi_itt;
  1255. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1256. }
  1257. static void
  1258. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1259. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1260. {
  1261. struct hwi_wrb_context *pwrb_context;
  1262. struct wrb_handle *pwrb_handle = NULL;
  1263. struct hwi_controller *phwi_ctrlr;
  1264. struct iscsi_task *task;
  1265. struct beiscsi_io_task *io_task;
  1266. struct iscsi_conn *conn = beiscsi_conn->conn;
  1267. struct iscsi_session *session = conn->session;
  1268. phwi_ctrlr = phba->phwi_ctrlr;
  1269. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1270. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1271. SOL_CID_MASK) >> 6) -
  1272. phba->fw_config.iscsi_cid_start];
  1273. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1274. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1275. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1276. task = pwrb_handle->pio_handle;
  1277. io_task = task->dd_data;
  1278. spin_lock_bh(&phba->mgmt_sgl_lock);
  1279. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1280. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1281. spin_lock_bh(&session->lock);
  1282. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1283. spin_unlock_bh(&session->lock);
  1284. }
  1285. static void
  1286. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1287. struct iscsi_task *task, struct sol_cqe *psol)
  1288. {
  1289. struct iscsi_nopin *hdr;
  1290. struct iscsi_conn *conn = beiscsi_conn->conn;
  1291. struct beiscsi_io_task *io_task = task->dd_data;
  1292. hdr = (struct iscsi_nopin *)task->hdr;
  1293. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1294. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1295. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1296. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1297. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1298. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1299. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1300. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1301. hdr->opcode = ISCSI_OP_NOOP_IN;
  1302. hdr->itt = io_task->libiscsi_itt;
  1303. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1304. }
  1305. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1306. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1307. {
  1308. struct hwi_wrb_context *pwrb_context;
  1309. struct wrb_handle *pwrb_handle;
  1310. struct iscsi_wrb *pwrb = NULL;
  1311. struct hwi_controller *phwi_ctrlr;
  1312. struct iscsi_task *task;
  1313. unsigned int type;
  1314. struct iscsi_conn *conn = beiscsi_conn->conn;
  1315. struct iscsi_session *session = conn->session;
  1316. phwi_ctrlr = phba->phwi_ctrlr;
  1317. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1318. (struct amap_sol_cqe, cid) / 32]
  1319. & SOL_CID_MASK) >> 6) -
  1320. phba->fw_config.iscsi_cid_start];
  1321. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1322. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1323. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1324. task = pwrb_handle->pio_handle;
  1325. pwrb = pwrb_handle->pwrb;
  1326. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1327. WRB_TYPE_MASK) >> 28;
  1328. spin_lock_bh(&session->lock);
  1329. switch (type) {
  1330. case HWH_TYPE_IO:
  1331. case HWH_TYPE_IO_RD:
  1332. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1333. ISCSI_OP_NOOP_OUT)
  1334. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1335. else
  1336. be_complete_io(beiscsi_conn, task, psol);
  1337. break;
  1338. case HWH_TYPE_LOGOUT:
  1339. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1340. be_complete_logout(beiscsi_conn, task, psol);
  1341. else
  1342. be_complete_tmf(beiscsi_conn, task, psol);
  1343. break;
  1344. case HWH_TYPE_LOGIN:
  1345. beiscsi_log(phba, KERN_ERR,
  1346. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1347. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1348. " hwi_complete_cmd- Solicited path\n");
  1349. break;
  1350. case HWH_TYPE_NOP:
  1351. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1352. break;
  1353. default:
  1354. beiscsi_log(phba, KERN_WARNING,
  1355. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1356. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1357. "wrb_index 0x%x CID 0x%x\n", type,
  1358. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1359. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1360. ((psol->dw[offsetof(struct amap_sol_cqe,
  1361. cid) / 32] & SOL_CID_MASK) >> 6));
  1362. break;
  1363. }
  1364. spin_unlock_bh(&session->lock);
  1365. }
  1366. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1367. *pasync_ctx, unsigned int is_header,
  1368. unsigned int host_write_ptr)
  1369. {
  1370. if (is_header)
  1371. return &pasync_ctx->async_entry[host_write_ptr].
  1372. header_busy_list;
  1373. else
  1374. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1375. }
  1376. static struct async_pdu_handle *
  1377. hwi_get_async_handle(struct beiscsi_hba *phba,
  1378. struct beiscsi_conn *beiscsi_conn,
  1379. struct hwi_async_pdu_context *pasync_ctx,
  1380. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1381. {
  1382. struct be_bus_address phys_addr;
  1383. struct list_head *pbusy_list;
  1384. struct async_pdu_handle *pasync_handle = NULL;
  1385. unsigned char is_header = 0;
  1386. phys_addr.u.a32.address_lo =
  1387. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1388. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1389. & PDUCQE_DPL_MASK) >> 16);
  1390. phys_addr.u.a32.address_hi =
  1391. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1392. phys_addr.u.a64.address =
  1393. *((unsigned long long *)(&phys_addr.u.a64.address));
  1394. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1395. & PDUCQE_CODE_MASK) {
  1396. case UNSOL_HDR_NOTIFY:
  1397. is_header = 1;
  1398. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1399. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1400. index) / 32] & PDUCQE_INDEX_MASK));
  1401. break;
  1402. case UNSOL_DATA_NOTIFY:
  1403. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1404. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1405. index) / 32] & PDUCQE_INDEX_MASK));
  1406. break;
  1407. default:
  1408. pbusy_list = NULL;
  1409. beiscsi_log(phba, KERN_WARNING,
  1410. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1411. "BM_%d : Unexpected code=%d\n",
  1412. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1413. code) / 32] & PDUCQE_CODE_MASK);
  1414. return NULL;
  1415. }
  1416. WARN_ON(list_empty(pbusy_list));
  1417. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1418. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1419. break;
  1420. }
  1421. WARN_ON(!pasync_handle);
  1422. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1423. phba->fw_config.iscsi_cid_start;
  1424. pasync_handle->is_header = is_header;
  1425. pasync_handle->buffer_len = ((pdpdu_cqe->
  1426. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1427. & PDUCQE_DPL_MASK) >> 16);
  1428. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1429. index) / 32] & PDUCQE_INDEX_MASK);
  1430. return pasync_handle;
  1431. }
  1432. static unsigned int
  1433. hwi_update_async_writables(struct beiscsi_hba *phba,
  1434. struct hwi_async_pdu_context *pasync_ctx,
  1435. unsigned int is_header, unsigned int cq_index)
  1436. {
  1437. struct list_head *pbusy_list;
  1438. struct async_pdu_handle *pasync_handle;
  1439. unsigned int num_entries, writables = 0;
  1440. unsigned int *pep_read_ptr, *pwritables;
  1441. num_entries = pasync_ctx->num_entries;
  1442. if (is_header) {
  1443. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1444. pwritables = &pasync_ctx->async_header.writables;
  1445. } else {
  1446. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1447. pwritables = &pasync_ctx->async_data.writables;
  1448. }
  1449. while ((*pep_read_ptr) != cq_index) {
  1450. (*pep_read_ptr)++;
  1451. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1452. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1453. *pep_read_ptr);
  1454. if (writables == 0)
  1455. WARN_ON(list_empty(pbusy_list));
  1456. if (!list_empty(pbusy_list)) {
  1457. pasync_handle = list_entry(pbusy_list->next,
  1458. struct async_pdu_handle,
  1459. link);
  1460. WARN_ON(!pasync_handle);
  1461. pasync_handle->consumed = 1;
  1462. }
  1463. writables++;
  1464. }
  1465. if (!writables) {
  1466. beiscsi_log(phba, KERN_ERR,
  1467. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1468. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1469. cq_index);
  1470. WARN_ON(1);
  1471. }
  1472. *pwritables = *pwritables + writables;
  1473. return 0;
  1474. }
  1475. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1476. unsigned int cri)
  1477. {
  1478. struct hwi_controller *phwi_ctrlr;
  1479. struct hwi_async_pdu_context *pasync_ctx;
  1480. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1481. struct list_head *plist;
  1482. phwi_ctrlr = phba->phwi_ctrlr;
  1483. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1484. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1485. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1486. list_del(&pasync_handle->link);
  1487. if (pasync_handle->is_header) {
  1488. list_add_tail(&pasync_handle->link,
  1489. &pasync_ctx->async_header.free_list);
  1490. pasync_ctx->async_header.free_entries++;
  1491. } else {
  1492. list_add_tail(&pasync_handle->link,
  1493. &pasync_ctx->async_data.free_list);
  1494. pasync_ctx->async_data.free_entries++;
  1495. }
  1496. }
  1497. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1498. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1499. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1500. }
  1501. static struct phys_addr *
  1502. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1503. unsigned int is_header, unsigned int host_write_ptr)
  1504. {
  1505. struct phys_addr *pasync_sge = NULL;
  1506. if (is_header)
  1507. pasync_sge = pasync_ctx->async_header.ring_base;
  1508. else
  1509. pasync_sge = pasync_ctx->async_data.ring_base;
  1510. return pasync_sge + host_write_ptr;
  1511. }
  1512. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1513. unsigned int is_header)
  1514. {
  1515. struct hwi_controller *phwi_ctrlr;
  1516. struct hwi_async_pdu_context *pasync_ctx;
  1517. struct async_pdu_handle *pasync_handle;
  1518. struct list_head *pfree_link, *pbusy_list;
  1519. struct phys_addr *pasync_sge;
  1520. unsigned int ring_id, num_entries;
  1521. unsigned int host_write_num;
  1522. unsigned int writables;
  1523. unsigned int i = 0;
  1524. u32 doorbell = 0;
  1525. phwi_ctrlr = phba->phwi_ctrlr;
  1526. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1527. num_entries = pasync_ctx->num_entries;
  1528. if (is_header) {
  1529. writables = min(pasync_ctx->async_header.writables,
  1530. pasync_ctx->async_header.free_entries);
  1531. pfree_link = pasync_ctx->async_header.free_list.next;
  1532. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1533. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1534. } else {
  1535. writables = min(pasync_ctx->async_data.writables,
  1536. pasync_ctx->async_data.free_entries);
  1537. pfree_link = pasync_ctx->async_data.free_list.next;
  1538. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1539. ring_id = phwi_ctrlr->default_pdu_data.id;
  1540. }
  1541. writables = (writables / 8) * 8;
  1542. if (writables) {
  1543. for (i = 0; i < writables; i++) {
  1544. pbusy_list =
  1545. hwi_get_async_busy_list(pasync_ctx, is_header,
  1546. host_write_num);
  1547. pasync_handle =
  1548. list_entry(pfree_link, struct async_pdu_handle,
  1549. link);
  1550. WARN_ON(!pasync_handle);
  1551. pasync_handle->consumed = 0;
  1552. pfree_link = pfree_link->next;
  1553. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1554. is_header, host_write_num);
  1555. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1556. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1557. list_move(&pasync_handle->link, pbusy_list);
  1558. host_write_num++;
  1559. host_write_num = host_write_num % num_entries;
  1560. }
  1561. if (is_header) {
  1562. pasync_ctx->async_header.host_write_ptr =
  1563. host_write_num;
  1564. pasync_ctx->async_header.free_entries -= writables;
  1565. pasync_ctx->async_header.writables -= writables;
  1566. pasync_ctx->async_header.busy_entries += writables;
  1567. } else {
  1568. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1569. pasync_ctx->async_data.free_entries -= writables;
  1570. pasync_ctx->async_data.writables -= writables;
  1571. pasync_ctx->async_data.busy_entries += writables;
  1572. }
  1573. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1574. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1575. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1576. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1577. << DB_DEF_PDU_CQPROC_SHIFT;
  1578. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1579. }
  1580. }
  1581. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1582. struct beiscsi_conn *beiscsi_conn,
  1583. struct i_t_dpdu_cqe *pdpdu_cqe)
  1584. {
  1585. struct hwi_controller *phwi_ctrlr;
  1586. struct hwi_async_pdu_context *pasync_ctx;
  1587. struct async_pdu_handle *pasync_handle = NULL;
  1588. unsigned int cq_index = -1;
  1589. phwi_ctrlr = phba->phwi_ctrlr;
  1590. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1591. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1592. pdpdu_cqe, &cq_index);
  1593. BUG_ON(pasync_handle->is_header != 0);
  1594. if (pasync_handle->consumed == 0)
  1595. hwi_update_async_writables(phba, pasync_ctx,
  1596. pasync_handle->is_header, cq_index);
  1597. hwi_free_async_msg(phba, pasync_handle->cri);
  1598. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1599. }
  1600. static unsigned int
  1601. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1602. struct beiscsi_hba *phba,
  1603. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1604. {
  1605. struct list_head *plist;
  1606. struct async_pdu_handle *pasync_handle;
  1607. void *phdr = NULL;
  1608. unsigned int hdr_len = 0, buf_len = 0;
  1609. unsigned int status, index = 0, offset = 0;
  1610. void *pfirst_buffer = NULL;
  1611. unsigned int num_buf = 0;
  1612. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1613. list_for_each_entry(pasync_handle, plist, link) {
  1614. if (index == 0) {
  1615. phdr = pasync_handle->pbuffer;
  1616. hdr_len = pasync_handle->buffer_len;
  1617. } else {
  1618. buf_len = pasync_handle->buffer_len;
  1619. if (!num_buf) {
  1620. pfirst_buffer = pasync_handle->pbuffer;
  1621. num_buf++;
  1622. }
  1623. memcpy(pfirst_buffer + offset,
  1624. pasync_handle->pbuffer, buf_len);
  1625. offset += buf_len;
  1626. }
  1627. index++;
  1628. }
  1629. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1630. (beiscsi_conn->beiscsi_conn_cid -
  1631. phba->fw_config.iscsi_cid_start),
  1632. phdr, hdr_len, pfirst_buffer,
  1633. offset);
  1634. hwi_free_async_msg(phba, cri);
  1635. return 0;
  1636. }
  1637. static unsigned int
  1638. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1639. struct beiscsi_hba *phba,
  1640. struct async_pdu_handle *pasync_handle)
  1641. {
  1642. struct hwi_async_pdu_context *pasync_ctx;
  1643. struct hwi_controller *phwi_ctrlr;
  1644. unsigned int bytes_needed = 0, status = 0;
  1645. unsigned short cri = pasync_handle->cri;
  1646. struct pdu_base *ppdu;
  1647. phwi_ctrlr = phba->phwi_ctrlr;
  1648. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1649. list_del(&pasync_handle->link);
  1650. if (pasync_handle->is_header) {
  1651. pasync_ctx->async_header.busy_entries--;
  1652. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1653. hwi_free_async_msg(phba, cri);
  1654. BUG();
  1655. }
  1656. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1657. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1658. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1659. (unsigned short)pasync_handle->buffer_len;
  1660. list_add_tail(&pasync_handle->link,
  1661. &pasync_ctx->async_entry[cri].wait_queue.list);
  1662. ppdu = pasync_handle->pbuffer;
  1663. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1664. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1665. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1666. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1667. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1668. if (status == 0) {
  1669. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1670. bytes_needed;
  1671. if (bytes_needed == 0)
  1672. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1673. pasync_ctx, cri);
  1674. }
  1675. } else {
  1676. pasync_ctx->async_data.busy_entries--;
  1677. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1678. list_add_tail(&pasync_handle->link,
  1679. &pasync_ctx->async_entry[cri].wait_queue.
  1680. list);
  1681. pasync_ctx->async_entry[cri].wait_queue.
  1682. bytes_received +=
  1683. (unsigned short)pasync_handle->buffer_len;
  1684. if (pasync_ctx->async_entry[cri].wait_queue.
  1685. bytes_received >=
  1686. pasync_ctx->async_entry[cri].wait_queue.
  1687. bytes_needed)
  1688. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1689. pasync_ctx, cri);
  1690. }
  1691. }
  1692. return status;
  1693. }
  1694. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1695. struct beiscsi_hba *phba,
  1696. struct i_t_dpdu_cqe *pdpdu_cqe)
  1697. {
  1698. struct hwi_controller *phwi_ctrlr;
  1699. struct hwi_async_pdu_context *pasync_ctx;
  1700. struct async_pdu_handle *pasync_handle = NULL;
  1701. unsigned int cq_index = -1;
  1702. phwi_ctrlr = phba->phwi_ctrlr;
  1703. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1704. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1705. pdpdu_cqe, &cq_index);
  1706. if (pasync_handle->consumed == 0)
  1707. hwi_update_async_writables(phba, pasync_ctx,
  1708. pasync_handle->is_header, cq_index);
  1709. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1710. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1711. }
  1712. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1713. {
  1714. struct be_queue_info *mcc_cq;
  1715. struct be_mcc_compl *mcc_compl;
  1716. unsigned int num_processed = 0;
  1717. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1718. mcc_compl = queue_tail_node(mcc_cq);
  1719. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1720. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1721. if (num_processed >= 32) {
  1722. hwi_ring_cq_db(phba, mcc_cq->id,
  1723. num_processed, 0, 0);
  1724. num_processed = 0;
  1725. }
  1726. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1727. /* Interpret flags as an async trailer */
  1728. if (is_link_state_evt(mcc_compl->flags))
  1729. /* Interpret compl as a async link evt */
  1730. beiscsi_async_link_state_process(phba,
  1731. (struct be_async_event_link_state *) mcc_compl);
  1732. else
  1733. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1734. "BM_%d : Unsupported Async Event, flags"
  1735. " = 0x%08x\n",
  1736. mcc_compl->flags);
  1737. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1738. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1739. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1740. }
  1741. mcc_compl->flags = 0;
  1742. queue_tail_inc(mcc_cq);
  1743. mcc_compl = queue_tail_node(mcc_cq);
  1744. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1745. num_processed++;
  1746. }
  1747. if (num_processed > 0)
  1748. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1749. }
  1750. /**
  1751. * beiscsi_process_cq()- Process the Completion Queue
  1752. * @pbe_eq: Event Q on which the Completion has come
  1753. *
  1754. * return
  1755. * Number of Completion Entries processed.
  1756. **/
  1757. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1758. {
  1759. struct be_queue_info *cq;
  1760. struct sol_cqe *sol;
  1761. struct dmsg_cqe *dmsg;
  1762. unsigned int num_processed = 0;
  1763. unsigned int tot_nump = 0;
  1764. unsigned short code = 0, cid = 0;
  1765. struct beiscsi_conn *beiscsi_conn;
  1766. struct beiscsi_endpoint *beiscsi_ep;
  1767. struct iscsi_endpoint *ep;
  1768. struct beiscsi_hba *phba;
  1769. cq = pbe_eq->cq;
  1770. sol = queue_tail_node(cq);
  1771. phba = pbe_eq->phba;
  1772. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1773. CQE_VALID_MASK) {
  1774. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1775. cid = ((sol->dw[offsetof(struct amap_sol_cqe, cid)/32] &
  1776. CQE_CID_MASK) >> 6);
  1777. code = (sol->dw[offsetof(struct amap_sol_cqe, code)/32] &
  1778. CQE_CODE_MASK);
  1779. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1780. beiscsi_ep = ep->dd_data;
  1781. beiscsi_conn = beiscsi_ep->conn;
  1782. if (num_processed >= 32) {
  1783. hwi_ring_cq_db(phba, cq->id,
  1784. num_processed, 0, 0);
  1785. tot_nump += num_processed;
  1786. num_processed = 0;
  1787. }
  1788. switch (code) {
  1789. case SOL_CMD_COMPLETE:
  1790. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1791. break;
  1792. case DRIVERMSG_NOTIFY:
  1793. beiscsi_log(phba, KERN_INFO,
  1794. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1795. "BM_%d : Received %s[%d] on CID : %d\n",
  1796. cqe_desc[code], code, cid);
  1797. dmsg = (struct dmsg_cqe *)sol;
  1798. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1799. break;
  1800. case UNSOL_HDR_NOTIFY:
  1801. beiscsi_log(phba, KERN_INFO,
  1802. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1803. "BM_%d : Received %s[%d] on CID : %d\n",
  1804. cqe_desc[code], code, cid);
  1805. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1806. (struct i_t_dpdu_cqe *)sol);
  1807. break;
  1808. case UNSOL_DATA_NOTIFY:
  1809. beiscsi_log(phba, KERN_INFO,
  1810. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1811. "BM_%d : Received %s[%d] on CID : %d\n",
  1812. cqe_desc[code], code, cid);
  1813. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1814. (struct i_t_dpdu_cqe *)sol);
  1815. break;
  1816. case CXN_INVALIDATE_INDEX_NOTIFY:
  1817. case CMD_INVALIDATED_NOTIFY:
  1818. case CXN_INVALIDATE_NOTIFY:
  1819. beiscsi_log(phba, KERN_ERR,
  1820. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1821. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1822. cqe_desc[code], code, cid);
  1823. break;
  1824. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1825. case CMD_KILLED_INVALID_STATSN_RCVD:
  1826. case CMD_KILLED_INVALID_R2T_RCVD:
  1827. case CMD_CXN_KILLED_LUN_INVALID:
  1828. case CMD_CXN_KILLED_ICD_INVALID:
  1829. case CMD_CXN_KILLED_ITT_INVALID:
  1830. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1831. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1832. beiscsi_log(phba, KERN_ERR,
  1833. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1834. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1835. cqe_desc[code], code, cid);
  1836. break;
  1837. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1838. beiscsi_log(phba, KERN_ERR,
  1839. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1840. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1841. cqe_desc[code], code, cid);
  1842. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1843. (struct i_t_dpdu_cqe *) sol);
  1844. break;
  1845. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1846. case CXN_KILLED_BURST_LEN_MISMATCH:
  1847. case CXN_KILLED_AHS_RCVD:
  1848. case CXN_KILLED_HDR_DIGEST_ERR:
  1849. case CXN_KILLED_UNKNOWN_HDR:
  1850. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1851. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1852. case CXN_KILLED_TIMED_OUT:
  1853. case CXN_KILLED_FIN_RCVD:
  1854. case CXN_KILLED_RST_SENT:
  1855. case CXN_KILLED_RST_RCVD:
  1856. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1857. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1858. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1859. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1860. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1861. beiscsi_log(phba, KERN_ERR,
  1862. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1863. "BM_%d : Event %s[%d] received on CID : %d\n",
  1864. cqe_desc[code], code, cid);
  1865. if (beiscsi_conn)
  1866. iscsi_conn_failure(beiscsi_conn->conn,
  1867. ISCSI_ERR_CONN_FAILED);
  1868. break;
  1869. default:
  1870. beiscsi_log(phba, KERN_ERR,
  1871. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1872. "BM_%d : Invalid CQE Event Received Code : %d"
  1873. "CID 0x%x...\n",
  1874. code, cid);
  1875. break;
  1876. }
  1877. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1878. queue_tail_inc(cq);
  1879. sol = queue_tail_node(cq);
  1880. num_processed++;
  1881. }
  1882. if (num_processed > 0) {
  1883. tot_nump += num_processed;
  1884. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1885. }
  1886. return tot_nump;
  1887. }
  1888. void beiscsi_process_all_cqs(struct work_struct *work)
  1889. {
  1890. unsigned long flags;
  1891. struct hwi_controller *phwi_ctrlr;
  1892. struct hwi_context_memory *phwi_context;
  1893. struct be_eq_obj *pbe_eq;
  1894. struct beiscsi_hba *phba =
  1895. container_of(work, struct beiscsi_hba, work_cqs);
  1896. phwi_ctrlr = phba->phwi_ctrlr;
  1897. phwi_context = phwi_ctrlr->phwi_ctxt;
  1898. if (phba->msix_enabled)
  1899. pbe_eq = &phwi_context->be_eq[phba->num_cpus];
  1900. else
  1901. pbe_eq = &phwi_context->be_eq[0];
  1902. if (phba->todo_mcc_cq) {
  1903. spin_lock_irqsave(&phba->isr_lock, flags);
  1904. phba->todo_mcc_cq = 0;
  1905. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1906. beiscsi_process_mcc_isr(phba);
  1907. }
  1908. if (phba->todo_cq) {
  1909. spin_lock_irqsave(&phba->isr_lock, flags);
  1910. phba->todo_cq = 0;
  1911. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1912. beiscsi_process_cq(pbe_eq);
  1913. }
  1914. }
  1915. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1916. {
  1917. static unsigned int ret;
  1918. struct beiscsi_hba *phba;
  1919. struct be_eq_obj *pbe_eq;
  1920. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1921. ret = beiscsi_process_cq(pbe_eq);
  1922. if (ret < budget) {
  1923. phba = pbe_eq->phba;
  1924. blk_iopoll_complete(iop);
  1925. beiscsi_log(phba, KERN_INFO,
  1926. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1927. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1928. pbe_eq->q.id);
  1929. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1930. }
  1931. return ret;
  1932. }
  1933. static void
  1934. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1935. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1936. {
  1937. struct iscsi_sge *psgl;
  1938. unsigned int sg_len, index;
  1939. unsigned int sge_len = 0;
  1940. unsigned long long addr;
  1941. struct scatterlist *l_sg;
  1942. unsigned int offset;
  1943. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1944. io_task->bhs_pa.u.a32.address_lo);
  1945. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1946. io_task->bhs_pa.u.a32.address_hi);
  1947. l_sg = sg;
  1948. for (index = 0; (index < num_sg) && (index < 2); index++,
  1949. sg = sg_next(sg)) {
  1950. if (index == 0) {
  1951. sg_len = sg_dma_len(sg);
  1952. addr = (u64) sg_dma_address(sg);
  1953. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1954. ((u32)(addr & 0xFFFFFFFF)));
  1955. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1956. ((u32)(addr >> 32)));
  1957. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1958. sg_len);
  1959. sge_len = sg_len;
  1960. } else {
  1961. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1962. pwrb, sge_len);
  1963. sg_len = sg_dma_len(sg);
  1964. addr = (u64) sg_dma_address(sg);
  1965. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1966. ((u32)(addr & 0xFFFFFFFF)));
  1967. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1968. ((u32)(addr >> 32)));
  1969. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1970. sg_len);
  1971. }
  1972. }
  1973. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1974. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1975. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1976. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1977. io_task->bhs_pa.u.a32.address_hi);
  1978. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1979. io_task->bhs_pa.u.a32.address_lo);
  1980. if (num_sg == 1) {
  1981. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1982. 1);
  1983. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1984. 0);
  1985. } else if (num_sg == 2) {
  1986. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1987. 0);
  1988. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1989. 1);
  1990. } else {
  1991. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1992. 0);
  1993. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1994. 0);
  1995. }
  1996. sg = l_sg;
  1997. psgl++;
  1998. psgl++;
  1999. offset = 0;
  2000. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2001. sg_len = sg_dma_len(sg);
  2002. addr = (u64) sg_dma_address(sg);
  2003. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2004. (addr & 0xFFFFFFFF));
  2005. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2006. (addr >> 32));
  2007. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2008. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2009. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2010. offset += sg_len;
  2011. }
  2012. psgl--;
  2013. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2014. }
  2015. /**
  2016. * hwi_write_buffer()- Populate the WRB with task info
  2017. * @pwrb: ptr to the WRB entry
  2018. * @task: iscsi task which is to be executed
  2019. **/
  2020. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2021. {
  2022. struct iscsi_sge *psgl;
  2023. struct beiscsi_io_task *io_task = task->dd_data;
  2024. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2025. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2026. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2027. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2028. io_task->bhs_pa.u.a32.address_lo);
  2029. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2030. io_task->bhs_pa.u.a32.address_hi);
  2031. if (task->data) {
  2032. if (task->data_count) {
  2033. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  2034. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2035. task->data,
  2036. task->data_count,
  2037. PCI_DMA_TODEVICE);
  2038. io_task->mtask_data_count = task->data_count;
  2039. } else {
  2040. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2041. io_task->mtask_addr = 0;
  2042. }
  2043. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2044. lower_32_bits(io_task->mtask_addr));
  2045. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2046. upper_32_bits(io_task->mtask_addr));
  2047. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2048. task->data_count);
  2049. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2050. } else {
  2051. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2052. io_task->mtask_addr = 0;
  2053. }
  2054. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2056. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2057. io_task->bhs_pa.u.a32.address_hi);
  2058. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2059. io_task->bhs_pa.u.a32.address_lo);
  2060. if (task->data) {
  2061. psgl++;
  2062. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2063. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2064. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2065. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2066. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2067. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2068. psgl++;
  2069. if (task->data) {
  2070. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2071. lower_32_bits(io_task->mtask_addr));
  2072. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2073. upper_32_bits(io_task->mtask_addr));
  2074. }
  2075. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2076. }
  2077. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2078. }
  2079. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2080. {
  2081. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2082. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2083. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2084. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2085. sizeof(struct sol_cqe));
  2086. num_async_pdu_buf_pages =
  2087. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2088. phba->params.defpdu_hdr_sz);
  2089. num_async_pdu_buf_sgl_pages =
  2090. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2091. sizeof(struct phys_addr));
  2092. num_async_pdu_data_pages =
  2093. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2094. phba->params.defpdu_data_sz);
  2095. num_async_pdu_data_sgl_pages =
  2096. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2097. sizeof(struct phys_addr));
  2098. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2099. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2100. BE_ISCSI_PDU_HEADER_SIZE;
  2101. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2102. sizeof(struct hwi_context_memory);
  2103. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2104. * (phba->params.wrbs_per_cxn)
  2105. * phba->params.cxns_per_ctrl;
  2106. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2107. (phba->params.wrbs_per_cxn);
  2108. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2109. phba->params.cxns_per_ctrl);
  2110. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2111. phba->params.icds_per_ctrl;
  2112. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2113. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2114. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2115. num_async_pdu_buf_pages * PAGE_SIZE;
  2116. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2117. num_async_pdu_data_pages * PAGE_SIZE;
  2118. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2119. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2120. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2121. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2122. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2123. phba->params.asyncpdus_per_ctrl *
  2124. sizeof(struct async_pdu_handle);
  2125. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2126. phba->params.asyncpdus_per_ctrl *
  2127. sizeof(struct async_pdu_handle);
  2128. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2129. sizeof(struct hwi_async_pdu_context) +
  2130. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2131. }
  2132. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2133. {
  2134. struct be_mem_descriptor *mem_descr;
  2135. dma_addr_t bus_add;
  2136. struct mem_array *mem_arr, *mem_arr_orig;
  2137. unsigned int i, j, alloc_size, curr_alloc_size;
  2138. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2139. if (!phba->phwi_ctrlr)
  2140. return -ENOMEM;
  2141. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2142. GFP_KERNEL);
  2143. if (!phba->init_mem) {
  2144. kfree(phba->phwi_ctrlr);
  2145. return -ENOMEM;
  2146. }
  2147. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2148. GFP_KERNEL);
  2149. if (!mem_arr_orig) {
  2150. kfree(phba->init_mem);
  2151. kfree(phba->phwi_ctrlr);
  2152. return -ENOMEM;
  2153. }
  2154. mem_descr = phba->init_mem;
  2155. for (i = 0; i < SE_MEM_MAX; i++) {
  2156. j = 0;
  2157. mem_arr = mem_arr_orig;
  2158. alloc_size = phba->mem_req[i];
  2159. memset(mem_arr, 0, sizeof(struct mem_array) *
  2160. BEISCSI_MAX_FRAGS_INIT);
  2161. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2162. do {
  2163. mem_arr->virtual_address = pci_alloc_consistent(
  2164. phba->pcidev,
  2165. curr_alloc_size,
  2166. &bus_add);
  2167. if (!mem_arr->virtual_address) {
  2168. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2169. goto free_mem;
  2170. if (curr_alloc_size -
  2171. rounddown_pow_of_two(curr_alloc_size))
  2172. curr_alloc_size = rounddown_pow_of_two
  2173. (curr_alloc_size);
  2174. else
  2175. curr_alloc_size = curr_alloc_size / 2;
  2176. } else {
  2177. mem_arr->bus_address.u.
  2178. a64.address = (__u64) bus_add;
  2179. mem_arr->size = curr_alloc_size;
  2180. alloc_size -= curr_alloc_size;
  2181. curr_alloc_size = min(be_max_phys_size *
  2182. 1024, alloc_size);
  2183. j++;
  2184. mem_arr++;
  2185. }
  2186. } while (alloc_size);
  2187. mem_descr->num_elements = j;
  2188. mem_descr->size_in_bytes = phba->mem_req[i];
  2189. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2190. GFP_KERNEL);
  2191. if (!mem_descr->mem_array)
  2192. goto free_mem;
  2193. memcpy(mem_descr->mem_array, mem_arr_orig,
  2194. sizeof(struct mem_array) * j);
  2195. mem_descr++;
  2196. }
  2197. kfree(mem_arr_orig);
  2198. return 0;
  2199. free_mem:
  2200. mem_descr->num_elements = j;
  2201. while ((i) || (j)) {
  2202. for (j = mem_descr->num_elements; j > 0; j--) {
  2203. pci_free_consistent(phba->pcidev,
  2204. mem_descr->mem_array[j - 1].size,
  2205. mem_descr->mem_array[j - 1].
  2206. virtual_address,
  2207. (unsigned long)mem_descr->
  2208. mem_array[j - 1].
  2209. bus_address.u.a64.address);
  2210. }
  2211. if (i) {
  2212. i--;
  2213. kfree(mem_descr->mem_array);
  2214. mem_descr--;
  2215. }
  2216. }
  2217. kfree(mem_arr_orig);
  2218. kfree(phba->init_mem);
  2219. kfree(phba->phwi_ctrlr);
  2220. return -ENOMEM;
  2221. }
  2222. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2223. {
  2224. beiscsi_find_mem_req(phba);
  2225. return beiscsi_alloc_mem(phba);
  2226. }
  2227. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2228. {
  2229. struct pdu_data_out *pdata_out;
  2230. struct pdu_nop_out *pnop_out;
  2231. struct be_mem_descriptor *mem_descr;
  2232. mem_descr = phba->init_mem;
  2233. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2234. pdata_out =
  2235. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2236. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2237. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2238. IIOC_SCSI_DATA);
  2239. pnop_out =
  2240. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2241. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2242. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2243. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2244. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2245. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2246. }
  2247. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2248. {
  2249. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2250. struct wrb_handle *pwrb_handle = NULL;
  2251. struct hwi_controller *phwi_ctrlr;
  2252. struct hwi_wrb_context *pwrb_context;
  2253. struct iscsi_wrb *pwrb = NULL;
  2254. unsigned int num_cxn_wrbh = 0;
  2255. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2256. mem_descr_wrbh = phba->init_mem;
  2257. mem_descr_wrbh += HWI_MEM_WRBH;
  2258. mem_descr_wrb = phba->init_mem;
  2259. mem_descr_wrb += HWI_MEM_WRB;
  2260. phwi_ctrlr = phba->phwi_ctrlr;
  2261. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2262. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2263. pwrb_context->pwrb_handle_base =
  2264. kzalloc(sizeof(struct wrb_handle *) *
  2265. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2266. if (!pwrb_context->pwrb_handle_base) {
  2267. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2268. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2269. goto init_wrb_hndl_failed;
  2270. }
  2271. pwrb_context->pwrb_handle_basestd =
  2272. kzalloc(sizeof(struct wrb_handle *) *
  2273. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2274. if (!pwrb_context->pwrb_handle_basestd) {
  2275. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2276. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2277. goto init_wrb_hndl_failed;
  2278. }
  2279. if (!num_cxn_wrbh) {
  2280. pwrb_handle =
  2281. mem_descr_wrbh->mem_array[idx].virtual_address;
  2282. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2283. ((sizeof(struct wrb_handle)) *
  2284. phba->params.wrbs_per_cxn));
  2285. idx++;
  2286. }
  2287. pwrb_context->alloc_index = 0;
  2288. pwrb_context->wrb_handles_available = 0;
  2289. pwrb_context->free_index = 0;
  2290. if (num_cxn_wrbh) {
  2291. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2292. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2293. pwrb_context->pwrb_handle_basestd[j] =
  2294. pwrb_handle;
  2295. pwrb_context->wrb_handles_available++;
  2296. pwrb_handle->wrb_index = j;
  2297. pwrb_handle++;
  2298. }
  2299. num_cxn_wrbh--;
  2300. }
  2301. }
  2302. idx = 0;
  2303. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2304. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2305. if (!num_cxn_wrb) {
  2306. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2307. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2308. ((sizeof(struct iscsi_wrb) *
  2309. phba->params.wrbs_per_cxn));
  2310. idx++;
  2311. }
  2312. if (num_cxn_wrb) {
  2313. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2314. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2315. pwrb_handle->pwrb = pwrb;
  2316. pwrb++;
  2317. }
  2318. num_cxn_wrb--;
  2319. }
  2320. }
  2321. return 0;
  2322. init_wrb_hndl_failed:
  2323. for (j = index; j > 0; j--) {
  2324. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2325. kfree(pwrb_context->pwrb_handle_base);
  2326. kfree(pwrb_context->pwrb_handle_basestd);
  2327. }
  2328. return -ENOMEM;
  2329. }
  2330. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2331. {
  2332. struct hwi_controller *phwi_ctrlr;
  2333. struct hba_parameters *p = &phba->params;
  2334. struct hwi_async_pdu_context *pasync_ctx;
  2335. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2336. unsigned int index, idx, num_per_mem, num_async_data;
  2337. struct be_mem_descriptor *mem_descr;
  2338. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2339. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2340. phwi_ctrlr = phba->phwi_ctrlr;
  2341. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2342. mem_descr->mem_array[0].virtual_address;
  2343. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2344. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2345. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2346. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2347. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2348. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2349. if (mem_descr->mem_array[0].virtual_address) {
  2350. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2351. "BM_%d : hwi_init_async_pdu_ctx"
  2352. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2353. mem_descr->mem_array[0].virtual_address);
  2354. } else
  2355. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2356. "BM_%d : No Virtual address\n");
  2357. pasync_ctx->async_header.va_base =
  2358. mem_descr->mem_array[0].virtual_address;
  2359. pasync_ctx->async_header.pa_base.u.a64.address =
  2360. mem_descr->mem_array[0].bus_address.u.a64.address;
  2361. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2362. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2363. if (mem_descr->mem_array[0].virtual_address) {
  2364. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2365. "BM_%d : hwi_init_async_pdu_ctx"
  2366. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2367. mem_descr->mem_array[0].virtual_address);
  2368. } else
  2369. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2370. "BM_%d : No Virtual address\n");
  2371. pasync_ctx->async_header.ring_base =
  2372. mem_descr->mem_array[0].virtual_address;
  2373. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2374. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2375. if (mem_descr->mem_array[0].virtual_address) {
  2376. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2377. "BM_%d : hwi_init_async_pdu_ctx"
  2378. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2379. mem_descr->mem_array[0].virtual_address);
  2380. } else
  2381. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2382. "BM_%d : No Virtual address\n");
  2383. pasync_ctx->async_header.handle_base =
  2384. mem_descr->mem_array[0].virtual_address;
  2385. pasync_ctx->async_header.writables = 0;
  2386. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2387. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2388. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2389. if (mem_descr->mem_array[0].virtual_address) {
  2390. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2391. "BM_%d : hwi_init_async_pdu_ctx"
  2392. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2393. mem_descr->mem_array[0].virtual_address);
  2394. } else
  2395. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2396. "BM_%d : No Virtual address\n");
  2397. pasync_ctx->async_data.ring_base =
  2398. mem_descr->mem_array[0].virtual_address;
  2399. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2400. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2401. if (!mem_descr->mem_array[0].virtual_address)
  2402. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2403. "BM_%d : No Virtual address\n");
  2404. pasync_ctx->async_data.handle_base =
  2405. mem_descr->mem_array[0].virtual_address;
  2406. pasync_ctx->async_data.writables = 0;
  2407. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2408. pasync_header_h =
  2409. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2410. pasync_data_h =
  2411. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2412. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2413. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2414. if (mem_descr->mem_array[0].virtual_address) {
  2415. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2416. "BM_%d : hwi_init_async_pdu_ctx"
  2417. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2418. mem_descr->mem_array[0].virtual_address);
  2419. } else
  2420. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2421. "BM_%d : No Virtual address\n");
  2422. idx = 0;
  2423. pasync_ctx->async_data.va_base =
  2424. mem_descr->mem_array[idx].virtual_address;
  2425. pasync_ctx->async_data.pa_base.u.a64.address =
  2426. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2427. num_async_data = ((mem_descr->mem_array[idx].size) /
  2428. phba->params.defpdu_data_sz);
  2429. num_per_mem = 0;
  2430. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2431. pasync_header_h->cri = -1;
  2432. pasync_header_h->index = (char)index;
  2433. INIT_LIST_HEAD(&pasync_header_h->link);
  2434. pasync_header_h->pbuffer =
  2435. (void *)((unsigned long)
  2436. (pasync_ctx->async_header.va_base) +
  2437. (p->defpdu_hdr_sz * index));
  2438. pasync_header_h->pa.u.a64.address =
  2439. pasync_ctx->async_header.pa_base.u.a64.address +
  2440. (p->defpdu_hdr_sz * index);
  2441. list_add_tail(&pasync_header_h->link,
  2442. &pasync_ctx->async_header.free_list);
  2443. pasync_header_h++;
  2444. pasync_ctx->async_header.free_entries++;
  2445. pasync_ctx->async_header.writables++;
  2446. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2447. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2448. header_busy_list);
  2449. pasync_data_h->cri = -1;
  2450. pasync_data_h->index = (char)index;
  2451. INIT_LIST_HEAD(&pasync_data_h->link);
  2452. if (!num_async_data) {
  2453. num_per_mem = 0;
  2454. idx++;
  2455. pasync_ctx->async_data.va_base =
  2456. mem_descr->mem_array[idx].virtual_address;
  2457. pasync_ctx->async_data.pa_base.u.a64.address =
  2458. mem_descr->mem_array[idx].
  2459. bus_address.u.a64.address;
  2460. num_async_data = ((mem_descr->mem_array[idx].size) /
  2461. phba->params.defpdu_data_sz);
  2462. }
  2463. pasync_data_h->pbuffer =
  2464. (void *)((unsigned long)
  2465. (pasync_ctx->async_data.va_base) +
  2466. (p->defpdu_data_sz * num_per_mem));
  2467. pasync_data_h->pa.u.a64.address =
  2468. pasync_ctx->async_data.pa_base.u.a64.address +
  2469. (p->defpdu_data_sz * num_per_mem);
  2470. num_per_mem++;
  2471. num_async_data--;
  2472. list_add_tail(&pasync_data_h->link,
  2473. &pasync_ctx->async_data.free_list);
  2474. pasync_data_h++;
  2475. pasync_ctx->async_data.free_entries++;
  2476. pasync_ctx->async_data.writables++;
  2477. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2478. }
  2479. pasync_ctx->async_header.host_write_ptr = 0;
  2480. pasync_ctx->async_header.ep_read_ptr = -1;
  2481. pasync_ctx->async_data.host_write_ptr = 0;
  2482. pasync_ctx->async_data.ep_read_ptr = -1;
  2483. }
  2484. static int
  2485. be_sgl_create_contiguous(void *virtual_address,
  2486. u64 physical_address, u32 length,
  2487. struct be_dma_mem *sgl)
  2488. {
  2489. WARN_ON(!virtual_address);
  2490. WARN_ON(!physical_address);
  2491. WARN_ON(!length > 0);
  2492. WARN_ON(!sgl);
  2493. sgl->va = virtual_address;
  2494. sgl->dma = (unsigned long)physical_address;
  2495. sgl->size = length;
  2496. return 0;
  2497. }
  2498. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2499. {
  2500. memset(sgl, 0, sizeof(*sgl));
  2501. }
  2502. static void
  2503. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2504. struct mem_array *pmem, struct be_dma_mem *sgl)
  2505. {
  2506. if (sgl->va)
  2507. be_sgl_destroy_contiguous(sgl);
  2508. be_sgl_create_contiguous(pmem->virtual_address,
  2509. pmem->bus_address.u.a64.address,
  2510. pmem->size, sgl);
  2511. }
  2512. static void
  2513. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2514. struct mem_array *pmem, struct be_dma_mem *sgl)
  2515. {
  2516. if (sgl->va)
  2517. be_sgl_destroy_contiguous(sgl);
  2518. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2519. pmem->bus_address.u.a64.address,
  2520. pmem->size, sgl);
  2521. }
  2522. static int be_fill_queue(struct be_queue_info *q,
  2523. u16 len, u16 entry_size, void *vaddress)
  2524. {
  2525. struct be_dma_mem *mem = &q->dma_mem;
  2526. memset(q, 0, sizeof(*q));
  2527. q->len = len;
  2528. q->entry_size = entry_size;
  2529. mem->size = len * entry_size;
  2530. mem->va = vaddress;
  2531. if (!mem->va)
  2532. return -ENOMEM;
  2533. memset(mem->va, 0, mem->size);
  2534. return 0;
  2535. }
  2536. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2537. struct hwi_context_memory *phwi_context)
  2538. {
  2539. unsigned int i, num_eq_pages;
  2540. int ret = 0, eq_for_mcc;
  2541. struct be_queue_info *eq;
  2542. struct be_dma_mem *mem;
  2543. void *eq_vaddress;
  2544. dma_addr_t paddr;
  2545. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2546. sizeof(struct be_eq_entry));
  2547. if (phba->msix_enabled)
  2548. eq_for_mcc = 1;
  2549. else
  2550. eq_for_mcc = 0;
  2551. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2552. eq = &phwi_context->be_eq[i].q;
  2553. mem = &eq->dma_mem;
  2554. phwi_context->be_eq[i].phba = phba;
  2555. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2556. num_eq_pages * PAGE_SIZE,
  2557. &paddr);
  2558. if (!eq_vaddress)
  2559. goto create_eq_error;
  2560. mem->va = eq_vaddress;
  2561. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2562. sizeof(struct be_eq_entry), eq_vaddress);
  2563. if (ret) {
  2564. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2565. "BM_%d : be_fill_queue Failed for EQ\n");
  2566. goto create_eq_error;
  2567. }
  2568. mem->dma = paddr;
  2569. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2570. phwi_context->cur_eqd);
  2571. if (ret) {
  2572. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2573. "BM_%d : beiscsi_cmd_eq_create"
  2574. "Failed for EQ\n");
  2575. goto create_eq_error;
  2576. }
  2577. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2578. "BM_%d : eqid = %d\n",
  2579. phwi_context->be_eq[i].q.id);
  2580. }
  2581. return 0;
  2582. create_eq_error:
  2583. for (i = 0; i < (phba->num_cpus + 1); i++) {
  2584. eq = &phwi_context->be_eq[i].q;
  2585. mem = &eq->dma_mem;
  2586. if (mem->va)
  2587. pci_free_consistent(phba->pcidev, num_eq_pages
  2588. * PAGE_SIZE,
  2589. mem->va, mem->dma);
  2590. }
  2591. return ret;
  2592. }
  2593. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2594. struct hwi_context_memory *phwi_context)
  2595. {
  2596. unsigned int i, num_cq_pages;
  2597. int ret = 0;
  2598. struct be_queue_info *cq, *eq;
  2599. struct be_dma_mem *mem;
  2600. struct be_eq_obj *pbe_eq;
  2601. void *cq_vaddress;
  2602. dma_addr_t paddr;
  2603. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2604. sizeof(struct sol_cqe));
  2605. for (i = 0; i < phba->num_cpus; i++) {
  2606. cq = &phwi_context->be_cq[i];
  2607. eq = &phwi_context->be_eq[i].q;
  2608. pbe_eq = &phwi_context->be_eq[i];
  2609. pbe_eq->cq = cq;
  2610. pbe_eq->phba = phba;
  2611. mem = &cq->dma_mem;
  2612. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2613. num_cq_pages * PAGE_SIZE,
  2614. &paddr);
  2615. if (!cq_vaddress)
  2616. goto create_cq_error;
  2617. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2618. sizeof(struct sol_cqe), cq_vaddress);
  2619. if (ret) {
  2620. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2621. "BM_%d : be_fill_queue Failed "
  2622. "for ISCSI CQ\n");
  2623. goto create_cq_error;
  2624. }
  2625. mem->dma = paddr;
  2626. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2627. false, 0);
  2628. if (ret) {
  2629. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2630. "BM_%d : beiscsi_cmd_eq_create"
  2631. "Failed for ISCSI CQ\n");
  2632. goto create_cq_error;
  2633. }
  2634. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2635. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2636. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2637. }
  2638. return 0;
  2639. create_cq_error:
  2640. for (i = 0; i < phba->num_cpus; i++) {
  2641. cq = &phwi_context->be_cq[i];
  2642. mem = &cq->dma_mem;
  2643. if (mem->va)
  2644. pci_free_consistent(phba->pcidev, num_cq_pages
  2645. * PAGE_SIZE,
  2646. mem->va, mem->dma);
  2647. }
  2648. return ret;
  2649. }
  2650. static int
  2651. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2652. struct hwi_context_memory *phwi_context,
  2653. struct hwi_controller *phwi_ctrlr,
  2654. unsigned int def_pdu_ring_sz)
  2655. {
  2656. unsigned int idx;
  2657. int ret;
  2658. struct be_queue_info *dq, *cq;
  2659. struct be_dma_mem *mem;
  2660. struct be_mem_descriptor *mem_descr;
  2661. void *dq_vaddress;
  2662. idx = 0;
  2663. dq = &phwi_context->be_def_hdrq;
  2664. cq = &phwi_context->be_cq[0];
  2665. mem = &dq->dma_mem;
  2666. mem_descr = phba->init_mem;
  2667. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2668. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2669. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2670. sizeof(struct phys_addr),
  2671. sizeof(struct phys_addr), dq_vaddress);
  2672. if (ret) {
  2673. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2674. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2675. return ret;
  2676. }
  2677. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2678. bus_address.u.a64.address;
  2679. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2680. def_pdu_ring_sz,
  2681. phba->params.defpdu_hdr_sz);
  2682. if (ret) {
  2683. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2684. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2685. return ret;
  2686. }
  2687. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2688. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2689. "BM_%d : iscsi def pdu id is %d\n",
  2690. phwi_context->be_def_hdrq.id);
  2691. hwi_post_async_buffers(phba, 1);
  2692. return 0;
  2693. }
  2694. static int
  2695. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2696. struct hwi_context_memory *phwi_context,
  2697. struct hwi_controller *phwi_ctrlr,
  2698. unsigned int def_pdu_ring_sz)
  2699. {
  2700. unsigned int idx;
  2701. int ret;
  2702. struct be_queue_info *dataq, *cq;
  2703. struct be_dma_mem *mem;
  2704. struct be_mem_descriptor *mem_descr;
  2705. void *dq_vaddress;
  2706. idx = 0;
  2707. dataq = &phwi_context->be_def_dataq;
  2708. cq = &phwi_context->be_cq[0];
  2709. mem = &dataq->dma_mem;
  2710. mem_descr = phba->init_mem;
  2711. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2712. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2713. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2714. sizeof(struct phys_addr),
  2715. sizeof(struct phys_addr), dq_vaddress);
  2716. if (ret) {
  2717. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2718. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2719. return ret;
  2720. }
  2721. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2722. bus_address.u.a64.address;
  2723. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2724. def_pdu_ring_sz,
  2725. phba->params.defpdu_data_sz);
  2726. if (ret) {
  2727. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2728. "BM_%d be_cmd_create_default_pdu_queue"
  2729. " Failed for DEF PDU DATA\n");
  2730. return ret;
  2731. }
  2732. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2733. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2734. "BM_%d : iscsi def data id is %d\n",
  2735. phwi_context->be_def_dataq.id);
  2736. hwi_post_async_buffers(phba, 0);
  2737. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2738. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2739. return 0;
  2740. }
  2741. static int
  2742. beiscsi_post_pages(struct beiscsi_hba *phba)
  2743. {
  2744. struct be_mem_descriptor *mem_descr;
  2745. struct mem_array *pm_arr;
  2746. unsigned int page_offset, i;
  2747. struct be_dma_mem sgl;
  2748. int status;
  2749. mem_descr = phba->init_mem;
  2750. mem_descr += HWI_MEM_SGE;
  2751. pm_arr = mem_descr->mem_array;
  2752. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2753. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2754. for (i = 0; i < mem_descr->num_elements; i++) {
  2755. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2756. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2757. page_offset,
  2758. (pm_arr->size / PAGE_SIZE));
  2759. page_offset += pm_arr->size / PAGE_SIZE;
  2760. if (status != 0) {
  2761. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2762. "BM_%d : post sgl failed.\n");
  2763. return status;
  2764. }
  2765. pm_arr++;
  2766. }
  2767. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2768. "BM_%d : POSTED PAGES\n");
  2769. return 0;
  2770. }
  2771. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2772. {
  2773. struct be_dma_mem *mem = &q->dma_mem;
  2774. if (mem->va) {
  2775. pci_free_consistent(phba->pcidev, mem->size,
  2776. mem->va, mem->dma);
  2777. mem->va = NULL;
  2778. }
  2779. }
  2780. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2781. u16 len, u16 entry_size)
  2782. {
  2783. struct be_dma_mem *mem = &q->dma_mem;
  2784. memset(q, 0, sizeof(*q));
  2785. q->len = len;
  2786. q->entry_size = entry_size;
  2787. mem->size = len * entry_size;
  2788. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2789. if (!mem->va)
  2790. return -ENOMEM;
  2791. memset(mem->va, 0, mem->size);
  2792. return 0;
  2793. }
  2794. static int
  2795. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2796. struct hwi_context_memory *phwi_context,
  2797. struct hwi_controller *phwi_ctrlr)
  2798. {
  2799. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2800. u64 pa_addr_lo;
  2801. unsigned int idx, num, i;
  2802. struct mem_array *pwrb_arr;
  2803. void *wrb_vaddr;
  2804. struct be_dma_mem sgl;
  2805. struct be_mem_descriptor *mem_descr;
  2806. int status;
  2807. idx = 0;
  2808. mem_descr = phba->init_mem;
  2809. mem_descr += HWI_MEM_WRB;
  2810. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2811. GFP_KERNEL);
  2812. if (!pwrb_arr) {
  2813. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2814. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2815. return -ENOMEM;
  2816. }
  2817. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2818. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2819. num_wrb_rings = mem_descr->mem_array[idx].size /
  2820. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2821. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2822. if (num_wrb_rings) {
  2823. pwrb_arr[num].virtual_address = wrb_vaddr;
  2824. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2825. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2826. sizeof(struct iscsi_wrb);
  2827. wrb_vaddr += pwrb_arr[num].size;
  2828. pa_addr_lo += pwrb_arr[num].size;
  2829. num_wrb_rings--;
  2830. } else {
  2831. idx++;
  2832. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2833. pa_addr_lo = mem_descr->mem_array[idx].\
  2834. bus_address.u.a64.address;
  2835. num_wrb_rings = mem_descr->mem_array[idx].size /
  2836. (phba->params.wrbs_per_cxn *
  2837. sizeof(struct iscsi_wrb));
  2838. pwrb_arr[num].virtual_address = wrb_vaddr;
  2839. pwrb_arr[num].bus_address.u.a64.address\
  2840. = pa_addr_lo;
  2841. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2842. sizeof(struct iscsi_wrb);
  2843. wrb_vaddr += pwrb_arr[num].size;
  2844. pa_addr_lo += pwrb_arr[num].size;
  2845. num_wrb_rings--;
  2846. }
  2847. }
  2848. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2849. wrb_mem_index = 0;
  2850. offset = 0;
  2851. size = 0;
  2852. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2853. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2854. &phwi_context->be_wrbq[i]);
  2855. if (status != 0) {
  2856. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2857. "BM_%d : wrbq create failed.");
  2858. kfree(pwrb_arr);
  2859. return status;
  2860. }
  2861. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2862. id;
  2863. }
  2864. kfree(pwrb_arr);
  2865. return 0;
  2866. }
  2867. static void free_wrb_handles(struct beiscsi_hba *phba)
  2868. {
  2869. unsigned int index;
  2870. struct hwi_controller *phwi_ctrlr;
  2871. struct hwi_wrb_context *pwrb_context;
  2872. phwi_ctrlr = phba->phwi_ctrlr;
  2873. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2874. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2875. kfree(pwrb_context->pwrb_handle_base);
  2876. kfree(pwrb_context->pwrb_handle_basestd);
  2877. }
  2878. }
  2879. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2880. {
  2881. struct be_queue_info *q;
  2882. struct be_ctrl_info *ctrl = &phba->ctrl;
  2883. q = &phba->ctrl.mcc_obj.q;
  2884. if (q->created)
  2885. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2886. be_queue_free(phba, q);
  2887. q = &phba->ctrl.mcc_obj.cq;
  2888. if (q->created)
  2889. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2890. be_queue_free(phba, q);
  2891. }
  2892. static void hwi_cleanup(struct beiscsi_hba *phba)
  2893. {
  2894. struct be_queue_info *q;
  2895. struct be_ctrl_info *ctrl = &phba->ctrl;
  2896. struct hwi_controller *phwi_ctrlr;
  2897. struct hwi_context_memory *phwi_context;
  2898. int i, eq_num;
  2899. phwi_ctrlr = phba->phwi_ctrlr;
  2900. phwi_context = phwi_ctrlr->phwi_ctxt;
  2901. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2902. q = &phwi_context->be_wrbq[i];
  2903. if (q->created)
  2904. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2905. }
  2906. free_wrb_handles(phba);
  2907. q = &phwi_context->be_def_hdrq;
  2908. if (q->created)
  2909. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2910. q = &phwi_context->be_def_dataq;
  2911. if (q->created)
  2912. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2913. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2914. for (i = 0; i < (phba->num_cpus); i++) {
  2915. q = &phwi_context->be_cq[i];
  2916. if (q->created)
  2917. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2918. }
  2919. if (phba->msix_enabled)
  2920. eq_num = 1;
  2921. else
  2922. eq_num = 0;
  2923. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2924. q = &phwi_context->be_eq[i].q;
  2925. if (q->created)
  2926. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2927. }
  2928. be_mcc_queues_destroy(phba);
  2929. }
  2930. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2931. struct hwi_context_memory *phwi_context)
  2932. {
  2933. struct be_queue_info *q, *cq;
  2934. struct be_ctrl_info *ctrl = &phba->ctrl;
  2935. /* Alloc MCC compl queue */
  2936. cq = &phba->ctrl.mcc_obj.cq;
  2937. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2938. sizeof(struct be_mcc_compl)))
  2939. goto err;
  2940. /* Ask BE to create MCC compl queue; */
  2941. if (phba->msix_enabled) {
  2942. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2943. [phba->num_cpus].q, false, true, 0))
  2944. goto mcc_cq_free;
  2945. } else {
  2946. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2947. false, true, 0))
  2948. goto mcc_cq_free;
  2949. }
  2950. /* Alloc MCC queue */
  2951. q = &phba->ctrl.mcc_obj.q;
  2952. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2953. goto mcc_cq_destroy;
  2954. /* Ask BE to create MCC queue */
  2955. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2956. goto mcc_q_free;
  2957. return 0;
  2958. mcc_q_free:
  2959. be_queue_free(phba, q);
  2960. mcc_cq_destroy:
  2961. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2962. mcc_cq_free:
  2963. be_queue_free(phba, cq);
  2964. err:
  2965. return -ENOMEM;
  2966. }
  2967. static int find_num_cpus(void)
  2968. {
  2969. int num_cpus = 0;
  2970. num_cpus = num_online_cpus();
  2971. if (num_cpus >= MAX_CPUS)
  2972. num_cpus = MAX_CPUS - 1;
  2973. return num_cpus;
  2974. }
  2975. static int hwi_init_port(struct beiscsi_hba *phba)
  2976. {
  2977. struct hwi_controller *phwi_ctrlr;
  2978. struct hwi_context_memory *phwi_context;
  2979. unsigned int def_pdu_ring_sz;
  2980. struct be_ctrl_info *ctrl = &phba->ctrl;
  2981. int status;
  2982. def_pdu_ring_sz =
  2983. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2984. phwi_ctrlr = phba->phwi_ctrlr;
  2985. phwi_context = phwi_ctrlr->phwi_ctxt;
  2986. phwi_context->max_eqd = 0;
  2987. phwi_context->min_eqd = 0;
  2988. phwi_context->cur_eqd = 64;
  2989. be_cmd_fw_initialize(&phba->ctrl);
  2990. status = beiscsi_create_eqs(phba, phwi_context);
  2991. if (status != 0) {
  2992. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2993. "BM_%d : EQ not created\n");
  2994. goto error;
  2995. }
  2996. status = be_mcc_queues_create(phba, phwi_context);
  2997. if (status != 0)
  2998. goto error;
  2999. status = mgmt_check_supported_fw(ctrl, phba);
  3000. if (status != 0) {
  3001. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3002. "BM_%d : Unsupported fw version\n");
  3003. goto error;
  3004. }
  3005. status = beiscsi_create_cqs(phba, phwi_context);
  3006. if (status != 0) {
  3007. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3008. "BM_%d : CQ not created\n");
  3009. goto error;
  3010. }
  3011. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3012. def_pdu_ring_sz);
  3013. if (status != 0) {
  3014. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3015. "BM_%d : Default Header not created\n");
  3016. goto error;
  3017. }
  3018. status = beiscsi_create_def_data(phba, phwi_context,
  3019. phwi_ctrlr, def_pdu_ring_sz);
  3020. if (status != 0) {
  3021. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3022. "BM_%d : Default Data not created\n");
  3023. goto error;
  3024. }
  3025. status = beiscsi_post_pages(phba);
  3026. if (status != 0) {
  3027. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3028. "BM_%d : Post SGL Pages Failed\n");
  3029. goto error;
  3030. }
  3031. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3032. if (status != 0) {
  3033. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3034. "BM_%d : WRB Rings not created\n");
  3035. goto error;
  3036. }
  3037. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3038. "BM_%d : hwi_init_port success\n");
  3039. return 0;
  3040. error:
  3041. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3042. "BM_%d : hwi_init_port failed");
  3043. hwi_cleanup(phba);
  3044. return status;
  3045. }
  3046. static int hwi_init_controller(struct beiscsi_hba *phba)
  3047. {
  3048. struct hwi_controller *phwi_ctrlr;
  3049. phwi_ctrlr = phba->phwi_ctrlr;
  3050. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3051. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3052. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3053. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3054. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3055. phwi_ctrlr->phwi_ctxt);
  3056. } else {
  3057. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3058. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3059. "than one element.Failing to load\n");
  3060. return -ENOMEM;
  3061. }
  3062. iscsi_init_global_templates(phba);
  3063. if (beiscsi_init_wrb_handle(phba))
  3064. return -ENOMEM;
  3065. hwi_init_async_pdu_ctx(phba);
  3066. if (hwi_init_port(phba) != 0) {
  3067. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3068. "BM_%d : hwi_init_controller failed\n");
  3069. return -ENOMEM;
  3070. }
  3071. return 0;
  3072. }
  3073. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3074. {
  3075. struct be_mem_descriptor *mem_descr;
  3076. int i, j;
  3077. mem_descr = phba->init_mem;
  3078. i = 0;
  3079. j = 0;
  3080. for (i = 0; i < SE_MEM_MAX; i++) {
  3081. for (j = mem_descr->num_elements; j > 0; j--) {
  3082. pci_free_consistent(phba->pcidev,
  3083. mem_descr->mem_array[j - 1].size,
  3084. mem_descr->mem_array[j - 1].virtual_address,
  3085. (unsigned long)mem_descr->mem_array[j - 1].
  3086. bus_address.u.a64.address);
  3087. }
  3088. kfree(mem_descr->mem_array);
  3089. mem_descr++;
  3090. }
  3091. kfree(phba->init_mem);
  3092. kfree(phba->phwi_ctrlr);
  3093. }
  3094. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3095. {
  3096. int ret = -ENOMEM;
  3097. ret = beiscsi_get_memory(phba);
  3098. if (ret < 0) {
  3099. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3100. "BM_%d : beiscsi_dev_probe -"
  3101. "Failed in beiscsi_alloc_memory\n");
  3102. return ret;
  3103. }
  3104. ret = hwi_init_controller(phba);
  3105. if (ret)
  3106. goto free_init;
  3107. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3108. "BM_%d : Return success from beiscsi_init_controller");
  3109. return 0;
  3110. free_init:
  3111. beiscsi_free_mem(phba);
  3112. return ret;
  3113. }
  3114. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3115. {
  3116. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3117. struct sgl_handle *psgl_handle;
  3118. struct iscsi_sge *pfrag;
  3119. unsigned int arr_index, i, idx;
  3120. phba->io_sgl_hndl_avbl = 0;
  3121. phba->eh_sgl_hndl_avbl = 0;
  3122. mem_descr_sglh = phba->init_mem;
  3123. mem_descr_sglh += HWI_MEM_SGLH;
  3124. if (1 == mem_descr_sglh->num_elements) {
  3125. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3126. phba->params.ios_per_ctrl,
  3127. GFP_KERNEL);
  3128. if (!phba->io_sgl_hndl_base) {
  3129. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3130. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3131. return -ENOMEM;
  3132. }
  3133. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3134. (phba->params.icds_per_ctrl -
  3135. phba->params.ios_per_ctrl),
  3136. GFP_KERNEL);
  3137. if (!phba->eh_sgl_hndl_base) {
  3138. kfree(phba->io_sgl_hndl_base);
  3139. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3140. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3141. return -ENOMEM;
  3142. }
  3143. } else {
  3144. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3145. "BM_%d : HWI_MEM_SGLH is more than one element."
  3146. "Failing to load\n");
  3147. return -ENOMEM;
  3148. }
  3149. arr_index = 0;
  3150. idx = 0;
  3151. while (idx < mem_descr_sglh->num_elements) {
  3152. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3153. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3154. sizeof(struct sgl_handle)); i++) {
  3155. if (arr_index < phba->params.ios_per_ctrl) {
  3156. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3157. phba->io_sgl_hndl_avbl++;
  3158. arr_index++;
  3159. } else {
  3160. phba->eh_sgl_hndl_base[arr_index -
  3161. phba->params.ios_per_ctrl] =
  3162. psgl_handle;
  3163. arr_index++;
  3164. phba->eh_sgl_hndl_avbl++;
  3165. }
  3166. psgl_handle++;
  3167. }
  3168. idx++;
  3169. }
  3170. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3171. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3172. "phba->eh_sgl_hndl_avbl=%d\n",
  3173. phba->io_sgl_hndl_avbl,
  3174. phba->eh_sgl_hndl_avbl);
  3175. mem_descr_sg = phba->init_mem;
  3176. mem_descr_sg += HWI_MEM_SGE;
  3177. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3178. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3179. mem_descr_sg->num_elements);
  3180. arr_index = 0;
  3181. idx = 0;
  3182. while (idx < mem_descr_sg->num_elements) {
  3183. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3184. for (i = 0;
  3185. i < (mem_descr_sg->mem_array[idx].size) /
  3186. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3187. i++) {
  3188. if (arr_index < phba->params.ios_per_ctrl)
  3189. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3190. else
  3191. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3192. phba->params.ios_per_ctrl];
  3193. psgl_handle->pfrag = pfrag;
  3194. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3195. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3196. pfrag += phba->params.num_sge_per_io;
  3197. psgl_handle->sgl_index =
  3198. phba->fw_config.iscsi_icd_start + arr_index++;
  3199. }
  3200. idx++;
  3201. }
  3202. phba->io_sgl_free_index = 0;
  3203. phba->io_sgl_alloc_index = 0;
  3204. phba->eh_sgl_free_index = 0;
  3205. phba->eh_sgl_alloc_index = 0;
  3206. return 0;
  3207. }
  3208. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3209. {
  3210. int i, new_cid;
  3211. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3212. GFP_KERNEL);
  3213. if (!phba->cid_array) {
  3214. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3215. "BM_%d : Failed to allocate memory in "
  3216. "hba_setup_cid_tbls\n");
  3217. return -ENOMEM;
  3218. }
  3219. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3220. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3221. if (!phba->ep_array) {
  3222. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3223. "BM_%d : Failed to allocate memory in "
  3224. "hba_setup_cid_tbls\n");
  3225. kfree(phba->cid_array);
  3226. return -ENOMEM;
  3227. }
  3228. new_cid = phba->fw_config.iscsi_cid_start;
  3229. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3230. phba->cid_array[i] = new_cid;
  3231. new_cid += 2;
  3232. }
  3233. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3234. return 0;
  3235. }
  3236. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3237. {
  3238. struct be_ctrl_info *ctrl = &phba->ctrl;
  3239. struct hwi_controller *phwi_ctrlr;
  3240. struct hwi_context_memory *phwi_context;
  3241. struct be_queue_info *eq;
  3242. u8 __iomem *addr;
  3243. u32 reg, i;
  3244. u32 enabled;
  3245. phwi_ctrlr = phba->phwi_ctrlr;
  3246. phwi_context = phwi_ctrlr->phwi_ctxt;
  3247. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3248. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3249. reg = ioread32(addr);
  3250. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3251. if (!enabled) {
  3252. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3253. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3254. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3255. iowrite32(reg, addr);
  3256. }
  3257. if (!phba->msix_enabled) {
  3258. eq = &phwi_context->be_eq[0].q;
  3259. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3260. "BM_%d : eq->id=%d\n", eq->id);
  3261. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3262. } else {
  3263. for (i = 0; i <= phba->num_cpus; i++) {
  3264. eq = &phwi_context->be_eq[i].q;
  3265. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3266. "BM_%d : eq->id=%d\n", eq->id);
  3267. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3268. }
  3269. }
  3270. }
  3271. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3272. {
  3273. struct be_ctrl_info *ctrl = &phba->ctrl;
  3274. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3275. u32 reg = ioread32(addr);
  3276. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3277. if (enabled) {
  3278. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3279. iowrite32(reg, addr);
  3280. } else
  3281. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3282. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3283. }
  3284. /**
  3285. * beiscsi_get_boot_info()- Get the boot session info
  3286. * @phba: The device priv structure instance
  3287. *
  3288. * Get the boot target info and store in driver priv structure
  3289. *
  3290. * return values
  3291. * Success: 0
  3292. * Failure: Non-Zero Value
  3293. **/
  3294. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3295. {
  3296. struct be_cmd_get_session_resp *session_resp;
  3297. struct be_mcc_wrb *wrb;
  3298. struct be_dma_mem nonemb_cmd;
  3299. unsigned int tag, wrb_num;
  3300. unsigned short status, extd_status;
  3301. unsigned int s_handle;
  3302. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3303. int ret = -ENOMEM;
  3304. /* Get the session handle of the boot target */
  3305. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3306. if (ret) {
  3307. beiscsi_log(phba, KERN_ERR,
  3308. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3309. "BM_%d : No boot session\n");
  3310. return ret;
  3311. }
  3312. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3313. sizeof(*session_resp),
  3314. &nonemb_cmd.dma);
  3315. if (nonemb_cmd.va == NULL) {
  3316. beiscsi_log(phba, KERN_ERR,
  3317. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3318. "BM_%d : Failed to allocate memory for"
  3319. "beiscsi_get_session_info\n");
  3320. return -ENOMEM;
  3321. }
  3322. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3323. tag = mgmt_get_session_info(phba, s_handle,
  3324. &nonemb_cmd);
  3325. if (!tag) {
  3326. beiscsi_log(phba, KERN_ERR,
  3327. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3328. "BM_%d : beiscsi_get_session_info"
  3329. " Failed\n");
  3330. goto boot_freemem;
  3331. } else
  3332. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3333. phba->ctrl.mcc_numtag[tag]);
  3334. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3335. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3336. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3337. if (status || extd_status) {
  3338. beiscsi_log(phba, KERN_ERR,
  3339. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3340. "BM_%d : beiscsi_get_session_info Failed"
  3341. " status = %d extd_status = %d\n",
  3342. status, extd_status);
  3343. free_mcc_tag(&phba->ctrl, tag);
  3344. goto boot_freemem;
  3345. }
  3346. wrb = queue_get_wrb(mccq, wrb_num);
  3347. free_mcc_tag(&phba->ctrl, tag);
  3348. session_resp = nonemb_cmd.va ;
  3349. memcpy(&phba->boot_sess, &session_resp->session_info,
  3350. sizeof(struct mgmt_session_info));
  3351. ret = 0;
  3352. boot_freemem:
  3353. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3354. nonemb_cmd.va, nonemb_cmd.dma);
  3355. return ret;
  3356. }
  3357. static void beiscsi_boot_release(void *data)
  3358. {
  3359. struct beiscsi_hba *phba = data;
  3360. scsi_host_put(phba->shost);
  3361. }
  3362. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3363. {
  3364. struct iscsi_boot_kobj *boot_kobj;
  3365. /* get boot info using mgmt cmd */
  3366. if (beiscsi_get_boot_info(phba))
  3367. /* Try to see if we can carry on without this */
  3368. return 0;
  3369. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3370. if (!phba->boot_kset)
  3371. return -ENOMEM;
  3372. /* get a ref because the show function will ref the phba */
  3373. if (!scsi_host_get(phba->shost))
  3374. goto free_kset;
  3375. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3376. beiscsi_show_boot_tgt_info,
  3377. beiscsi_tgt_get_attr_visibility,
  3378. beiscsi_boot_release);
  3379. if (!boot_kobj)
  3380. goto put_shost;
  3381. if (!scsi_host_get(phba->shost))
  3382. goto free_kset;
  3383. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3384. beiscsi_show_boot_ini_info,
  3385. beiscsi_ini_get_attr_visibility,
  3386. beiscsi_boot_release);
  3387. if (!boot_kobj)
  3388. goto put_shost;
  3389. if (!scsi_host_get(phba->shost))
  3390. goto free_kset;
  3391. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3392. beiscsi_show_boot_eth_info,
  3393. beiscsi_eth_get_attr_visibility,
  3394. beiscsi_boot_release);
  3395. if (!boot_kobj)
  3396. goto put_shost;
  3397. return 0;
  3398. put_shost:
  3399. scsi_host_put(phba->shost);
  3400. free_kset:
  3401. iscsi_boot_destroy_kset(phba->boot_kset);
  3402. return -ENOMEM;
  3403. }
  3404. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3405. {
  3406. int ret;
  3407. ret = beiscsi_init_controller(phba);
  3408. if (ret < 0) {
  3409. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3410. "BM_%d : beiscsi_dev_probe - Failed in"
  3411. "beiscsi_init_controller\n");
  3412. return ret;
  3413. }
  3414. ret = beiscsi_init_sgl_handle(phba);
  3415. if (ret < 0) {
  3416. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3417. "BM_%d : beiscsi_dev_probe - Failed in"
  3418. "beiscsi_init_sgl_handle\n");
  3419. goto do_cleanup_ctrlr;
  3420. }
  3421. if (hba_setup_cid_tbls(phba)) {
  3422. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3423. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3424. kfree(phba->io_sgl_hndl_base);
  3425. kfree(phba->eh_sgl_hndl_base);
  3426. goto do_cleanup_ctrlr;
  3427. }
  3428. return ret;
  3429. do_cleanup_ctrlr:
  3430. hwi_cleanup(phba);
  3431. return ret;
  3432. }
  3433. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3434. {
  3435. struct hwi_controller *phwi_ctrlr;
  3436. struct hwi_context_memory *phwi_context;
  3437. struct be_queue_info *eq;
  3438. struct be_eq_entry *eqe = NULL;
  3439. int i, eq_msix;
  3440. unsigned int num_processed;
  3441. phwi_ctrlr = phba->phwi_ctrlr;
  3442. phwi_context = phwi_ctrlr->phwi_ctxt;
  3443. if (phba->msix_enabled)
  3444. eq_msix = 1;
  3445. else
  3446. eq_msix = 0;
  3447. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3448. eq = &phwi_context->be_eq[i].q;
  3449. eqe = queue_tail_node(eq);
  3450. num_processed = 0;
  3451. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3452. & EQE_VALID_MASK) {
  3453. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3454. queue_tail_inc(eq);
  3455. eqe = queue_tail_node(eq);
  3456. num_processed++;
  3457. }
  3458. if (num_processed)
  3459. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3460. }
  3461. }
  3462. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3463. {
  3464. int mgmt_status;
  3465. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3466. if (mgmt_status)
  3467. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3468. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3469. hwi_purge_eq(phba);
  3470. hwi_cleanup(phba);
  3471. kfree(phba->io_sgl_hndl_base);
  3472. kfree(phba->eh_sgl_hndl_base);
  3473. kfree(phba->cid_array);
  3474. kfree(phba->ep_array);
  3475. }
  3476. /**
  3477. * beiscsi_cleanup_task()- Free driver resources of the task
  3478. * @task: ptr to the iscsi task
  3479. *
  3480. **/
  3481. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3482. {
  3483. struct beiscsi_io_task *io_task = task->dd_data;
  3484. struct iscsi_conn *conn = task->conn;
  3485. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3486. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3487. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3488. struct hwi_wrb_context *pwrb_context;
  3489. struct hwi_controller *phwi_ctrlr;
  3490. phwi_ctrlr = phba->phwi_ctrlr;
  3491. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3492. - phba->fw_config.iscsi_cid_start];
  3493. if (io_task->cmd_bhs) {
  3494. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3495. io_task->bhs_pa.u.a64.address);
  3496. io_task->cmd_bhs = NULL;
  3497. }
  3498. if (task->sc) {
  3499. if (io_task->pwrb_handle) {
  3500. free_wrb_handle(phba, pwrb_context,
  3501. io_task->pwrb_handle);
  3502. io_task->pwrb_handle = NULL;
  3503. }
  3504. if (io_task->psgl_handle) {
  3505. spin_lock(&phba->io_sgl_lock);
  3506. free_io_sgl_handle(phba, io_task->psgl_handle);
  3507. spin_unlock(&phba->io_sgl_lock);
  3508. io_task->psgl_handle = NULL;
  3509. }
  3510. } else {
  3511. if (!beiscsi_conn->login_in_progress) {
  3512. if (io_task->pwrb_handle) {
  3513. free_wrb_handle(phba, pwrb_context,
  3514. io_task->pwrb_handle);
  3515. io_task->pwrb_handle = NULL;
  3516. }
  3517. if (io_task->psgl_handle) {
  3518. spin_lock(&phba->mgmt_sgl_lock);
  3519. free_mgmt_sgl_handle(phba,
  3520. io_task->psgl_handle);
  3521. spin_unlock(&phba->mgmt_sgl_lock);
  3522. io_task->psgl_handle = NULL;
  3523. }
  3524. if (io_task->mtask_addr) {
  3525. pci_unmap_single(phba->pcidev,
  3526. io_task->mtask_addr,
  3527. io_task->mtask_data_count,
  3528. PCI_DMA_TODEVICE);
  3529. io_task->mtask_addr = 0;
  3530. }
  3531. }
  3532. }
  3533. }
  3534. void
  3535. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3536. struct beiscsi_offload_params *params)
  3537. {
  3538. struct wrb_handle *pwrb_handle;
  3539. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3540. struct be_mem_descriptor *mem_descr;
  3541. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3542. struct iscsi_task *task = beiscsi_conn->task;
  3543. struct iscsi_session *session = task->conn->session;
  3544. u32 doorbell = 0;
  3545. /*
  3546. * We can always use 0 here because it is reserved by libiscsi for
  3547. * login/startup related tasks.
  3548. */
  3549. beiscsi_conn->login_in_progress = 0;
  3550. spin_lock_bh(&session->lock);
  3551. beiscsi_cleanup_task(task);
  3552. spin_unlock_bh(&session->lock);
  3553. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3554. phba->fw_config.iscsi_cid_start));
  3555. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3556. memset(pwrb, 0, sizeof(*pwrb));
  3557. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3558. max_burst_length, pwrb, params->dw[offsetof
  3559. (struct amap_beiscsi_offload_params,
  3560. max_burst_length) / 32]);
  3561. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3562. max_send_data_segment_length, pwrb,
  3563. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3564. max_send_data_segment_length) / 32]);
  3565. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3566. first_burst_length,
  3567. pwrb,
  3568. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3569. first_burst_length) / 32]);
  3570. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3571. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3572. erl) / 32] & OFFLD_PARAMS_ERL));
  3573. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3574. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3575. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3576. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3577. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3578. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3579. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3580. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3581. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3582. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3583. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3584. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3585. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3586. pwrb,
  3587. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3588. exp_statsn) / 32] + 1));
  3589. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3590. 0x7);
  3591. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3592. pwrb, pwrb_handle->wrb_index);
  3593. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3594. pwrb, pwrb_handle->nxt_wrb_index);
  3595. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3596. session_state, pwrb, 0);
  3597. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3598. pwrb, 1);
  3599. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3600. pwrb, 0);
  3601. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3602. 0);
  3603. mem_descr = phba->init_mem;
  3604. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3605. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3606. pad_buffer_addr_hi, pwrb,
  3607. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3608. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3609. pad_buffer_addr_lo, pwrb,
  3610. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3611. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3612. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3613. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3614. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3615. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3616. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3617. }
  3618. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3619. int *index, int *age)
  3620. {
  3621. *index = (int)itt;
  3622. if (age)
  3623. *age = conn->session->age;
  3624. }
  3625. /**
  3626. * beiscsi_alloc_pdu - allocates pdu and related resources
  3627. * @task: libiscsi task
  3628. * @opcode: opcode of pdu for task
  3629. *
  3630. * This is called with the session lock held. It will allocate
  3631. * the wrb and sgl if needed for the command. And it will prep
  3632. * the pdu's itt. beiscsi_parse_pdu will later translate
  3633. * the pdu itt to the libiscsi task itt.
  3634. */
  3635. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3636. {
  3637. struct beiscsi_io_task *io_task = task->dd_data;
  3638. struct iscsi_conn *conn = task->conn;
  3639. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3640. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3641. struct hwi_wrb_context *pwrb_context;
  3642. struct hwi_controller *phwi_ctrlr;
  3643. itt_t itt;
  3644. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3645. dma_addr_t paddr;
  3646. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3647. GFP_ATOMIC, &paddr);
  3648. if (!io_task->cmd_bhs)
  3649. return -ENOMEM;
  3650. io_task->bhs_pa.u.a64.address = paddr;
  3651. io_task->libiscsi_itt = (itt_t)task->itt;
  3652. io_task->conn = beiscsi_conn;
  3653. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3654. task->hdr_max = sizeof(struct be_cmd_bhs);
  3655. io_task->psgl_handle = NULL;
  3656. io_task->pwrb_handle = NULL;
  3657. if (task->sc) {
  3658. spin_lock(&phba->io_sgl_lock);
  3659. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3660. spin_unlock(&phba->io_sgl_lock);
  3661. if (!io_task->psgl_handle)
  3662. goto free_hndls;
  3663. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3664. beiscsi_conn->beiscsi_conn_cid -
  3665. phba->fw_config.iscsi_cid_start);
  3666. if (!io_task->pwrb_handle)
  3667. goto free_io_hndls;
  3668. } else {
  3669. io_task->scsi_cmnd = NULL;
  3670. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3671. if (!beiscsi_conn->login_in_progress) {
  3672. spin_lock(&phba->mgmt_sgl_lock);
  3673. io_task->psgl_handle = (struct sgl_handle *)
  3674. alloc_mgmt_sgl_handle(phba);
  3675. spin_unlock(&phba->mgmt_sgl_lock);
  3676. if (!io_task->psgl_handle)
  3677. goto free_hndls;
  3678. beiscsi_conn->login_in_progress = 1;
  3679. beiscsi_conn->plogin_sgl_handle =
  3680. io_task->psgl_handle;
  3681. io_task->pwrb_handle =
  3682. alloc_wrb_handle(phba,
  3683. beiscsi_conn->beiscsi_conn_cid -
  3684. phba->fw_config.iscsi_cid_start);
  3685. if (!io_task->pwrb_handle)
  3686. goto free_io_hndls;
  3687. beiscsi_conn->plogin_wrb_handle =
  3688. io_task->pwrb_handle;
  3689. } else {
  3690. io_task->psgl_handle =
  3691. beiscsi_conn->plogin_sgl_handle;
  3692. io_task->pwrb_handle =
  3693. beiscsi_conn->plogin_wrb_handle;
  3694. }
  3695. beiscsi_conn->task = task;
  3696. } else {
  3697. spin_lock(&phba->mgmt_sgl_lock);
  3698. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3699. spin_unlock(&phba->mgmt_sgl_lock);
  3700. if (!io_task->psgl_handle)
  3701. goto free_hndls;
  3702. io_task->pwrb_handle =
  3703. alloc_wrb_handle(phba,
  3704. beiscsi_conn->beiscsi_conn_cid -
  3705. phba->fw_config.iscsi_cid_start);
  3706. if (!io_task->pwrb_handle)
  3707. goto free_mgmt_hndls;
  3708. }
  3709. }
  3710. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3711. wrb_index << 16) | (unsigned int)
  3712. (io_task->psgl_handle->sgl_index));
  3713. io_task->pwrb_handle->pio_handle = task;
  3714. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3715. return 0;
  3716. free_io_hndls:
  3717. spin_lock(&phba->io_sgl_lock);
  3718. free_io_sgl_handle(phba, io_task->psgl_handle);
  3719. spin_unlock(&phba->io_sgl_lock);
  3720. goto free_hndls;
  3721. free_mgmt_hndls:
  3722. spin_lock(&phba->mgmt_sgl_lock);
  3723. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3724. spin_unlock(&phba->mgmt_sgl_lock);
  3725. free_hndls:
  3726. phwi_ctrlr = phba->phwi_ctrlr;
  3727. pwrb_context = &phwi_ctrlr->wrb_context[
  3728. beiscsi_conn->beiscsi_conn_cid -
  3729. phba->fw_config.iscsi_cid_start];
  3730. if (io_task->pwrb_handle)
  3731. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3732. io_task->pwrb_handle = NULL;
  3733. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3734. io_task->bhs_pa.u.a64.address);
  3735. io_task->cmd_bhs = NULL;
  3736. beiscsi_log(phba, KERN_ERR,
  3737. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3738. "BM_%d : Alloc of SGL_ICD Failed\n");
  3739. return -ENOMEM;
  3740. }
  3741. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3742. unsigned int num_sg, unsigned int xferlen,
  3743. unsigned int writedir)
  3744. {
  3745. struct beiscsi_io_task *io_task = task->dd_data;
  3746. struct iscsi_conn *conn = task->conn;
  3747. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3748. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3749. struct iscsi_wrb *pwrb = NULL;
  3750. unsigned int doorbell = 0;
  3751. pwrb = io_task->pwrb_handle->pwrb;
  3752. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3753. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3754. if (writedir) {
  3755. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3756. INI_WR_CMD);
  3757. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3758. } else {
  3759. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3760. INI_RD_CMD);
  3761. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3762. }
  3763. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3764. cpu_to_be16(*(unsigned short *)
  3765. &io_task->cmd_bhs->iscsi_hdr.lun));
  3766. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3767. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3768. io_task->pwrb_handle->wrb_index);
  3769. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3770. be32_to_cpu(task->cmdsn));
  3771. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3772. io_task->psgl_handle->sgl_index);
  3773. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3774. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3775. io_task->pwrb_handle->nxt_wrb_index);
  3776. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3777. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3778. doorbell |= (io_task->pwrb_handle->wrb_index &
  3779. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3780. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3781. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3782. return 0;
  3783. }
  3784. static int beiscsi_mtask(struct iscsi_task *task)
  3785. {
  3786. struct beiscsi_io_task *io_task = task->dd_data;
  3787. struct iscsi_conn *conn = task->conn;
  3788. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3789. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3790. struct iscsi_wrb *pwrb = NULL;
  3791. unsigned int doorbell = 0;
  3792. unsigned int cid;
  3793. cid = beiscsi_conn->beiscsi_conn_cid;
  3794. pwrb = io_task->pwrb_handle->pwrb;
  3795. memset(pwrb, 0, sizeof(*pwrb));
  3796. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3797. be32_to_cpu(task->cmdsn));
  3798. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3799. io_task->pwrb_handle->wrb_index);
  3800. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3801. io_task->psgl_handle->sgl_index);
  3802. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3803. case ISCSI_OP_LOGIN:
  3804. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3805. TGT_DM_CMD);
  3806. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3807. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3808. hwi_write_buffer(pwrb, task);
  3809. break;
  3810. case ISCSI_OP_NOOP_OUT:
  3811. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3812. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3813. TGT_DM_CMD);
  3814. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3815. pwrb, 0);
  3816. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3817. } else {
  3818. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3819. INI_RD_CMD);
  3820. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3821. }
  3822. hwi_write_buffer(pwrb, task);
  3823. break;
  3824. case ISCSI_OP_TEXT:
  3825. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3826. TGT_DM_CMD);
  3827. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3828. hwi_write_buffer(pwrb, task);
  3829. break;
  3830. case ISCSI_OP_SCSI_TMFUNC:
  3831. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3832. INI_TMF_CMD);
  3833. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3834. hwi_write_buffer(pwrb, task);
  3835. break;
  3836. case ISCSI_OP_LOGOUT:
  3837. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3838. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3839. HWH_TYPE_LOGOUT);
  3840. hwi_write_buffer(pwrb, task);
  3841. break;
  3842. default:
  3843. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3844. "BM_%d : opcode =%d Not supported\n",
  3845. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3846. return -EINVAL;
  3847. }
  3848. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3849. task->data_count);
  3850. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3851. io_task->pwrb_handle->nxt_wrb_index);
  3852. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3853. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3854. doorbell |= (io_task->pwrb_handle->wrb_index &
  3855. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3856. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3857. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3858. return 0;
  3859. }
  3860. static int beiscsi_task_xmit(struct iscsi_task *task)
  3861. {
  3862. struct beiscsi_io_task *io_task = task->dd_data;
  3863. struct scsi_cmnd *sc = task->sc;
  3864. struct scatterlist *sg;
  3865. int num_sg;
  3866. unsigned int writedir = 0, xferlen = 0;
  3867. if (!sc)
  3868. return beiscsi_mtask(task);
  3869. io_task->scsi_cmnd = sc;
  3870. num_sg = scsi_dma_map(sc);
  3871. if (num_sg < 0) {
  3872. struct iscsi_conn *conn = task->conn;
  3873. struct beiscsi_hba *phba = NULL;
  3874. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  3875. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  3876. "BM_%d : scsi_dma_map Failed\n");
  3877. return num_sg;
  3878. }
  3879. xferlen = scsi_bufflen(sc);
  3880. sg = scsi_sglist(sc);
  3881. if (sc->sc_data_direction == DMA_TO_DEVICE)
  3882. writedir = 1;
  3883. else
  3884. writedir = 0;
  3885. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3886. }
  3887. /**
  3888. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  3889. * @job: job to handle
  3890. */
  3891. static int beiscsi_bsg_request(struct bsg_job *job)
  3892. {
  3893. struct Scsi_Host *shost;
  3894. struct beiscsi_hba *phba;
  3895. struct iscsi_bsg_request *bsg_req = job->request;
  3896. int rc = -EINVAL;
  3897. unsigned int tag;
  3898. struct be_dma_mem nonemb_cmd;
  3899. struct be_cmd_resp_hdr *resp;
  3900. struct iscsi_bsg_reply *bsg_reply = job->reply;
  3901. unsigned short status, extd_status;
  3902. shost = iscsi_job_to_shost(job);
  3903. phba = iscsi_host_priv(shost);
  3904. switch (bsg_req->msgcode) {
  3905. case ISCSI_BSG_HST_VENDOR:
  3906. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3907. job->request_payload.payload_len,
  3908. &nonemb_cmd.dma);
  3909. if (nonemb_cmd.va == NULL) {
  3910. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3911. "BM_%d : Failed to allocate memory for "
  3912. "beiscsi_bsg_request\n");
  3913. return -EIO;
  3914. }
  3915. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  3916. &nonemb_cmd);
  3917. if (!tag) {
  3918. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3919. "BM_%d : be_cmd_get_mac_addr Failed\n");
  3920. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3921. nonemb_cmd.va, nonemb_cmd.dma);
  3922. return -EAGAIN;
  3923. } else
  3924. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3925. phba->ctrl.mcc_numtag[tag]);
  3926. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3927. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3928. free_mcc_tag(&phba->ctrl, tag);
  3929. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  3930. sg_copy_from_buffer(job->reply_payload.sg_list,
  3931. job->reply_payload.sg_cnt,
  3932. nonemb_cmd.va, (resp->response_length
  3933. + sizeof(*resp)));
  3934. bsg_reply->reply_payload_rcv_len = resp->response_length;
  3935. bsg_reply->result = status;
  3936. bsg_job_done(job, bsg_reply->result,
  3937. bsg_reply->reply_payload_rcv_len);
  3938. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3939. nonemb_cmd.va, nonemb_cmd.dma);
  3940. if (status || extd_status) {
  3941. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3942. "BM_%d : be_cmd_get_mac_addr Failed"
  3943. " status = %d extd_status = %d\n",
  3944. status, extd_status);
  3945. return -EIO;
  3946. }
  3947. break;
  3948. default:
  3949. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3950. "BM_%d : Unsupported bsg command: 0x%x\n",
  3951. bsg_req->msgcode);
  3952. break;
  3953. }
  3954. return rc;
  3955. }
  3956. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  3957. {
  3958. /* Set the logging parameter */
  3959. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  3960. }
  3961. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  3962. {
  3963. struct hwi_controller *phwi_ctrlr;
  3964. struct hwi_context_memory *phwi_context;
  3965. struct be_eq_obj *pbe_eq;
  3966. unsigned int i, msix_vec;
  3967. u8 *real_offset = 0;
  3968. u32 value = 0;
  3969. phwi_ctrlr = phba->phwi_ctrlr;
  3970. phwi_context = phwi_ctrlr->phwi_ctxt;
  3971. hwi_disable_intr(phba);
  3972. if (phba->msix_enabled) {
  3973. for (i = 0; i <= phba->num_cpus; i++) {
  3974. msix_vec = phba->msix_entries[i].vector;
  3975. free_irq(msix_vec, &phwi_context->be_eq[i]);
  3976. kfree(phba->msi_name[i]);
  3977. }
  3978. } else
  3979. if (phba->pcidev->irq)
  3980. free_irq(phba->pcidev->irq, phba);
  3981. pci_disable_msix(phba->pcidev);
  3982. destroy_workqueue(phba->wq);
  3983. if (blk_iopoll_enabled)
  3984. for (i = 0; i < phba->num_cpus; i++) {
  3985. pbe_eq = &phwi_context->be_eq[i];
  3986. blk_iopoll_disable(&pbe_eq->iopoll);
  3987. }
  3988. beiscsi_clean_port(phba);
  3989. beiscsi_free_mem(phba);
  3990. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3991. value = readl((void *)real_offset);
  3992. if (value & 0x00010000) {
  3993. value &= 0xfffeffff;
  3994. writel(value, (void *)real_offset);
  3995. }
  3996. beiscsi_unmap_pci_function(phba);
  3997. pci_free_consistent(phba->pcidev,
  3998. phba->ctrl.mbox_mem_alloced.size,
  3999. phba->ctrl.mbox_mem_alloced.va,
  4000. phba->ctrl.mbox_mem_alloced.dma);
  4001. }
  4002. static void beiscsi_remove(struct pci_dev *pcidev)
  4003. {
  4004. struct beiscsi_hba *phba = NULL;
  4005. phba = pci_get_drvdata(pcidev);
  4006. if (!phba) {
  4007. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4008. return;
  4009. }
  4010. beiscsi_destroy_def_ifaces(phba);
  4011. beiscsi_quiesce(phba);
  4012. iscsi_boot_destroy_kset(phba->boot_kset);
  4013. iscsi_host_remove(phba->shost);
  4014. pci_dev_put(phba->pcidev);
  4015. iscsi_host_free(phba->shost);
  4016. pci_disable_device(pcidev);
  4017. }
  4018. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4019. {
  4020. struct beiscsi_hba *phba = NULL;
  4021. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4022. if (!phba) {
  4023. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4024. return;
  4025. }
  4026. beiscsi_quiesce(phba);
  4027. pci_disable_device(pcidev);
  4028. }
  4029. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4030. {
  4031. int i, status;
  4032. for (i = 0; i <= phba->num_cpus; i++)
  4033. phba->msix_entries[i].entry = i;
  4034. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4035. (phba->num_cpus + 1));
  4036. if (!status)
  4037. phba->msix_enabled = true;
  4038. return;
  4039. }
  4040. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  4041. const struct pci_device_id *id)
  4042. {
  4043. struct beiscsi_hba *phba = NULL;
  4044. struct hwi_controller *phwi_ctrlr;
  4045. struct hwi_context_memory *phwi_context;
  4046. struct be_eq_obj *pbe_eq;
  4047. int ret, num_cpus, i;
  4048. u8 *real_offset = 0;
  4049. u32 value = 0;
  4050. ret = beiscsi_enable_pci(pcidev);
  4051. if (ret < 0) {
  4052. dev_err(&pcidev->dev,
  4053. "beiscsi_dev_probe - Failed to enable pci device\n");
  4054. return ret;
  4055. }
  4056. phba = beiscsi_hba_alloc(pcidev);
  4057. if (!phba) {
  4058. dev_err(&pcidev->dev,
  4059. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4060. goto disable_pci;
  4061. }
  4062. /* Initialize Driver configuration Paramters */
  4063. beiscsi_hba_attrs_init(phba);
  4064. switch (pcidev->device) {
  4065. case BE_DEVICE_ID1:
  4066. case OC_DEVICE_ID1:
  4067. case OC_DEVICE_ID2:
  4068. phba->generation = BE_GEN2;
  4069. break;
  4070. case BE_DEVICE_ID2:
  4071. case OC_DEVICE_ID3:
  4072. phba->generation = BE_GEN3;
  4073. break;
  4074. default:
  4075. phba->generation = 0;
  4076. }
  4077. if (enable_msix)
  4078. num_cpus = find_num_cpus();
  4079. else
  4080. num_cpus = 1;
  4081. phba->num_cpus = num_cpus;
  4082. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4083. "BM_%d : num_cpus = %d\n",
  4084. phba->num_cpus);
  4085. if (enable_msix) {
  4086. beiscsi_msix_enable(phba);
  4087. if (!phba->msix_enabled)
  4088. phba->num_cpus = 1;
  4089. }
  4090. ret = be_ctrl_init(phba, pcidev);
  4091. if (ret) {
  4092. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4093. "BM_%d : beiscsi_dev_probe-"
  4094. "Failed in be_ctrl_init\n");
  4095. goto hba_free;
  4096. }
  4097. if (!num_hba) {
  4098. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  4099. value = readl((void *)real_offset);
  4100. if (value & 0x00010000) {
  4101. gcrashmode++;
  4102. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4103. "BM_%d : Loading Driver in crashdump mode\n");
  4104. ret = beiscsi_cmd_reset_function(phba);
  4105. if (ret) {
  4106. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4107. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4108. goto hba_free;
  4109. }
  4110. ret = be_chk_reset_complete(phba);
  4111. if (ret) {
  4112. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4113. "BM_%d : Failed to get out of reset."
  4114. "Aborting Crashdump\n");
  4115. goto hba_free;
  4116. }
  4117. } else {
  4118. value |= 0x00010000;
  4119. writel(value, (void *)real_offset);
  4120. num_hba++;
  4121. }
  4122. }
  4123. spin_lock_init(&phba->io_sgl_lock);
  4124. spin_lock_init(&phba->mgmt_sgl_lock);
  4125. spin_lock_init(&phba->isr_lock);
  4126. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4127. if (ret != 0) {
  4128. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4129. "BM_%d : Error getting fw config\n");
  4130. goto free_port;
  4131. }
  4132. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4133. beiscsi_get_params(phba);
  4134. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4135. ret = beiscsi_init_port(phba);
  4136. if (ret < 0) {
  4137. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4138. "BM_%d : beiscsi_dev_probe-"
  4139. "Failed in beiscsi_init_port\n");
  4140. goto free_port;
  4141. }
  4142. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4143. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4144. phba->ctrl.mcc_tag[i] = i + 1;
  4145. phba->ctrl.mcc_numtag[i + 1] = 0;
  4146. phba->ctrl.mcc_tag_available++;
  4147. }
  4148. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4149. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
  4150. phba->shost->host_no);
  4151. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4152. if (!phba->wq) {
  4153. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4154. "BM_%d : beiscsi_dev_probe-"
  4155. "Failed to allocate work queue\n");
  4156. goto free_twq;
  4157. }
  4158. INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
  4159. phwi_ctrlr = phba->phwi_ctrlr;
  4160. phwi_context = phwi_ctrlr->phwi_ctxt;
  4161. if (blk_iopoll_enabled) {
  4162. for (i = 0; i < phba->num_cpus; i++) {
  4163. pbe_eq = &phwi_context->be_eq[i];
  4164. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4165. be_iopoll);
  4166. blk_iopoll_enable(&pbe_eq->iopoll);
  4167. }
  4168. }
  4169. ret = beiscsi_init_irqs(phba);
  4170. if (ret < 0) {
  4171. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4172. "BM_%d : beiscsi_dev_probe-"
  4173. "Failed to beiscsi_init_irqs\n");
  4174. goto free_blkenbld;
  4175. }
  4176. hwi_enable_intr(phba);
  4177. if (beiscsi_setup_boot_info(phba))
  4178. /*
  4179. * log error but continue, because we may not be using
  4180. * iscsi boot.
  4181. */
  4182. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4183. "BM_%d : Could not set up "
  4184. "iSCSI boot info.\n");
  4185. beiscsi_create_def_ifaces(phba);
  4186. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4187. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4188. return 0;
  4189. free_blkenbld:
  4190. destroy_workqueue(phba->wq);
  4191. if (blk_iopoll_enabled)
  4192. for (i = 0; i < phba->num_cpus; i++) {
  4193. pbe_eq = &phwi_context->be_eq[i];
  4194. blk_iopoll_disable(&pbe_eq->iopoll);
  4195. }
  4196. free_twq:
  4197. beiscsi_clean_port(phba);
  4198. beiscsi_free_mem(phba);
  4199. free_port:
  4200. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  4201. value = readl((void *)real_offset);
  4202. if (value & 0x00010000) {
  4203. value &= 0xfffeffff;
  4204. writel(value, (void *)real_offset);
  4205. }
  4206. pci_free_consistent(phba->pcidev,
  4207. phba->ctrl.mbox_mem_alloced.size,
  4208. phba->ctrl.mbox_mem_alloced.va,
  4209. phba->ctrl.mbox_mem_alloced.dma);
  4210. beiscsi_unmap_pci_function(phba);
  4211. hba_free:
  4212. if (phba->msix_enabled)
  4213. pci_disable_msix(phba->pcidev);
  4214. iscsi_host_remove(phba->shost);
  4215. pci_dev_put(phba->pcidev);
  4216. iscsi_host_free(phba->shost);
  4217. disable_pci:
  4218. pci_disable_device(pcidev);
  4219. return ret;
  4220. }
  4221. struct iscsi_transport beiscsi_iscsi_transport = {
  4222. .owner = THIS_MODULE,
  4223. .name = DRV_NAME,
  4224. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4225. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4226. .create_session = beiscsi_session_create,
  4227. .destroy_session = beiscsi_session_destroy,
  4228. .create_conn = beiscsi_conn_create,
  4229. .bind_conn = beiscsi_conn_bind,
  4230. .destroy_conn = iscsi_conn_teardown,
  4231. .attr_is_visible = be2iscsi_attr_is_visible,
  4232. .set_iface_param = be2iscsi_iface_set_param,
  4233. .get_iface_param = be2iscsi_iface_get_param,
  4234. .set_param = beiscsi_set_param,
  4235. .get_conn_param = iscsi_conn_get_param,
  4236. .get_session_param = iscsi_session_get_param,
  4237. .get_host_param = beiscsi_get_host_param,
  4238. .start_conn = beiscsi_conn_start,
  4239. .stop_conn = iscsi_conn_stop,
  4240. .send_pdu = iscsi_conn_send_pdu,
  4241. .xmit_task = beiscsi_task_xmit,
  4242. .cleanup_task = beiscsi_cleanup_task,
  4243. .alloc_pdu = beiscsi_alloc_pdu,
  4244. .parse_pdu_itt = beiscsi_parse_pdu,
  4245. .get_stats = beiscsi_conn_get_stats,
  4246. .get_ep_param = beiscsi_ep_get_param,
  4247. .ep_connect = beiscsi_ep_connect,
  4248. .ep_poll = beiscsi_ep_poll,
  4249. .ep_disconnect = beiscsi_ep_disconnect,
  4250. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4251. .bsg_request = beiscsi_bsg_request,
  4252. };
  4253. static struct pci_driver beiscsi_pci_driver = {
  4254. .name = DRV_NAME,
  4255. .probe = beiscsi_dev_probe,
  4256. .remove = beiscsi_remove,
  4257. .shutdown = beiscsi_shutdown,
  4258. .id_table = beiscsi_pci_id_table
  4259. };
  4260. static int __init beiscsi_module_init(void)
  4261. {
  4262. int ret;
  4263. beiscsi_scsi_transport =
  4264. iscsi_register_transport(&beiscsi_iscsi_transport);
  4265. if (!beiscsi_scsi_transport) {
  4266. printk(KERN_ERR
  4267. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4268. return -ENOMEM;
  4269. }
  4270. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4271. &beiscsi_iscsi_transport);
  4272. ret = pci_register_driver(&beiscsi_pci_driver);
  4273. if (ret) {
  4274. printk(KERN_ERR
  4275. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4276. goto unregister_iscsi_transport;
  4277. }
  4278. return 0;
  4279. unregister_iscsi_transport:
  4280. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4281. return ret;
  4282. }
  4283. static void __exit beiscsi_module_exit(void)
  4284. {
  4285. pci_unregister_driver(&beiscsi_pci_driver);
  4286. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4287. }
  4288. module_init(beiscsi_module_init);
  4289. module_exit(beiscsi_module_exit);