qlcnic_ctx.c 26 KB

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  1. /*
  2. * Copyright (C) 2009 - QLogic Corporation.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called "COPYING".
  22. *
  23. */
  24. #include "qlcnic.h"
  25. static u32
  26. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  27. {
  28. u32 rsp;
  29. int timeout = 0;
  30. do {
  31. /* give atleast 1ms for firmware to respond */
  32. msleep(1);
  33. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  34. return QLCNIC_CDRP_RSP_TIMEOUT;
  35. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
  36. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  37. return rsp;
  38. }
  39. u32
  40. qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
  41. u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
  42. {
  43. u32 rsp;
  44. u32 signature;
  45. u32 rcode = QLCNIC_RCODE_SUCCESS;
  46. struct pci_dev *pdev = adapter->pdev;
  47. signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version);
  48. /* Acquire semaphore before accessing CRB */
  49. if (qlcnic_api_lock(adapter))
  50. return QLCNIC_RCODE_TIMEOUT;
  51. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  52. QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1);
  53. QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2);
  54. QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3);
  55. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd));
  56. rsp = qlcnic_poll_rsp(adapter);
  57. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  58. dev_err(&pdev->dev, "card response timeout.\n");
  59. rcode = QLCNIC_RCODE_TIMEOUT;
  60. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  61. rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  62. dev_err(&pdev->dev, "failed card response code:0x%x\n",
  63. rcode);
  64. }
  65. /* Release semaphore */
  66. qlcnic_api_unlock(adapter);
  67. return rcode;
  68. }
  69. int
  70. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  71. {
  72. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  73. if (recv_ctx->state == QLCNIC_HOST_CTX_STATE_ACTIVE) {
  74. if (qlcnic_issue_cmd(adapter,
  75. adapter->ahw.pci_func,
  76. adapter->fw_hal_version,
  77. recv_ctx->context_id,
  78. mtu,
  79. 0,
  80. QLCNIC_CDRP_CMD_SET_MTU)) {
  81. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  82. return -EIO;
  83. }
  84. }
  85. return 0;
  86. }
  87. static int
  88. qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  89. {
  90. void *addr;
  91. struct qlcnic_hostrq_rx_ctx *prq;
  92. struct qlcnic_cardrsp_rx_ctx *prsp;
  93. struct qlcnic_hostrq_rds_ring *prq_rds;
  94. struct qlcnic_hostrq_sds_ring *prq_sds;
  95. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  96. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  97. struct qlcnic_host_rds_ring *rds_ring;
  98. struct qlcnic_host_sds_ring *sds_ring;
  99. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  100. u64 phys_addr;
  101. int i, nrds_rings, nsds_rings;
  102. size_t rq_size, rsp_size;
  103. u32 cap, reg, val, reg2;
  104. int err;
  105. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  106. nrds_rings = adapter->max_rds_rings;
  107. nsds_rings = adapter->max_sds_rings;
  108. rq_size =
  109. SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  110. nsds_rings);
  111. rsp_size =
  112. SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  113. nsds_rings);
  114. addr = pci_alloc_consistent(adapter->pdev,
  115. rq_size, &hostrq_phys_addr);
  116. if (addr == NULL)
  117. return -ENOMEM;
  118. prq = (struct qlcnic_hostrq_rx_ctx *)addr;
  119. addr = pci_alloc_consistent(adapter->pdev,
  120. rsp_size, &cardrsp_phys_addr);
  121. if (addr == NULL) {
  122. err = -ENOMEM;
  123. goto out_free_rq;
  124. }
  125. prsp = (struct qlcnic_cardrsp_rx_ctx *)addr;
  126. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  127. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  128. | QLCNIC_CAP0_VALIDOFF);
  129. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  130. prq->valid_field_offset = offsetof(struct qlcnic_hostrq_rx_ctx,
  131. msix_handler);
  132. prq->txrx_sds_binding = nsds_rings - 1;
  133. prq->capabilities[0] = cpu_to_le32(cap);
  134. prq->host_int_crb_mode =
  135. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  136. prq->host_rds_crb_mode =
  137. cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
  138. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  139. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  140. prq->rds_ring_offset = cpu_to_le32(0);
  141. val = le32_to_cpu(prq->rds_ring_offset) +
  142. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  143. prq->sds_ring_offset = cpu_to_le32(val);
  144. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  145. le32_to_cpu(prq->rds_ring_offset));
  146. for (i = 0; i < nrds_rings; i++) {
  147. rds_ring = &recv_ctx->rds_rings[i];
  148. rds_ring->producer = 0;
  149. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  150. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  151. prq_rds[i].ring_kind = cpu_to_le32(i);
  152. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  153. }
  154. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  155. le32_to_cpu(prq->sds_ring_offset));
  156. for (i = 0; i < nsds_rings; i++) {
  157. sds_ring = &recv_ctx->sds_rings[i];
  158. sds_ring->consumer = 0;
  159. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  160. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  161. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  162. prq_sds[i].msi_index = cpu_to_le16(i);
  163. }
  164. phys_addr = hostrq_phys_addr;
  165. err = qlcnic_issue_cmd(adapter,
  166. adapter->ahw.pci_func,
  167. adapter->fw_hal_version,
  168. (u32)(phys_addr >> 32),
  169. (u32)(phys_addr & 0xffffffff),
  170. rq_size,
  171. QLCNIC_CDRP_CMD_CREATE_RX_CTX);
  172. if (err) {
  173. dev_err(&adapter->pdev->dev,
  174. "Failed to create rx ctx in firmware%d\n", err);
  175. goto out_free_rsp;
  176. }
  177. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  178. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  179. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  180. rds_ring = &recv_ctx->rds_rings[i];
  181. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  182. if (adapter->fw_hal_version == QLCNIC_FW_BASE)
  183. rds_ring->crb_rcv_producer = qlcnic_get_ioaddr(adapter,
  184. QLCNIC_REG(reg - 0x200));
  185. else
  186. rds_ring->crb_rcv_producer = adapter->ahw.pci_base0 +
  187. reg;
  188. }
  189. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  190. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  191. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  192. sds_ring = &recv_ctx->sds_rings[i];
  193. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  194. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  195. if (adapter->fw_hal_version == QLCNIC_FW_BASE) {
  196. sds_ring->crb_sts_consumer = qlcnic_get_ioaddr(adapter,
  197. QLCNIC_REG(reg - 0x200));
  198. sds_ring->crb_intr_mask = qlcnic_get_ioaddr(adapter,
  199. QLCNIC_REG(reg2 - 0x200));
  200. } else {
  201. sds_ring->crb_sts_consumer = adapter->ahw.pci_base0 +
  202. reg;
  203. sds_ring->crb_intr_mask = adapter->ahw.pci_base0 + reg2;
  204. }
  205. }
  206. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  207. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  208. recv_ctx->virt_port = prsp->virt_port;
  209. out_free_rsp:
  210. pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
  211. out_free_rq:
  212. pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
  213. return err;
  214. }
  215. static void
  216. qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter)
  217. {
  218. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  219. if (qlcnic_issue_cmd(adapter,
  220. adapter->ahw.pci_func,
  221. adapter->fw_hal_version,
  222. recv_ctx->context_id,
  223. QLCNIC_DESTROY_CTX_RESET,
  224. 0,
  225. QLCNIC_CDRP_CMD_DESTROY_RX_CTX)) {
  226. dev_err(&adapter->pdev->dev,
  227. "Failed to destroy rx ctx in firmware\n");
  228. }
  229. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  230. }
  231. static int
  232. qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter)
  233. {
  234. struct qlcnic_hostrq_tx_ctx *prq;
  235. struct qlcnic_hostrq_cds_ring *prq_cds;
  236. struct qlcnic_cardrsp_tx_ctx *prsp;
  237. void *rq_addr, *rsp_addr;
  238. size_t rq_size, rsp_size;
  239. u32 temp;
  240. int err;
  241. u64 phys_addr;
  242. dma_addr_t rq_phys_addr, rsp_phys_addr;
  243. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  244. /* reset host resources */
  245. tx_ring->producer = 0;
  246. tx_ring->sw_consumer = 0;
  247. *(tx_ring->hw_consumer) = 0;
  248. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  249. rq_addr = pci_alloc_consistent(adapter->pdev,
  250. rq_size, &rq_phys_addr);
  251. if (!rq_addr)
  252. return -ENOMEM;
  253. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  254. rsp_addr = pci_alloc_consistent(adapter->pdev,
  255. rsp_size, &rsp_phys_addr);
  256. if (!rsp_addr) {
  257. err = -ENOMEM;
  258. goto out_free_rq;
  259. }
  260. memset(rq_addr, 0, rq_size);
  261. prq = (struct qlcnic_hostrq_tx_ctx *)rq_addr;
  262. memset(rsp_addr, 0, rsp_size);
  263. prsp = (struct qlcnic_cardrsp_tx_ctx *)rsp_addr;
  264. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  265. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  266. QLCNIC_CAP0_LSO);
  267. prq->capabilities[0] = cpu_to_le32(temp);
  268. prq->host_int_crb_mode =
  269. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  270. prq->interrupt_ctl = 0;
  271. prq->msi_index = 0;
  272. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  273. prq_cds = &prq->cds_ring;
  274. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  275. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  276. phys_addr = rq_phys_addr;
  277. err = qlcnic_issue_cmd(adapter,
  278. adapter->ahw.pci_func,
  279. adapter->fw_hal_version,
  280. (u32)(phys_addr >> 32),
  281. ((u32)phys_addr & 0xffffffff),
  282. rq_size,
  283. QLCNIC_CDRP_CMD_CREATE_TX_CTX);
  284. if (err == QLCNIC_RCODE_SUCCESS) {
  285. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  286. if (adapter->fw_hal_version == QLCNIC_FW_BASE)
  287. tx_ring->crb_cmd_producer = qlcnic_get_ioaddr(adapter,
  288. QLCNIC_REG(temp - 0x200));
  289. else
  290. tx_ring->crb_cmd_producer = adapter->ahw.pci_base0 +
  291. temp;
  292. adapter->tx_context_id =
  293. le16_to_cpu(prsp->context_id);
  294. } else {
  295. dev_err(&adapter->pdev->dev,
  296. "Failed to create tx ctx in firmware%d\n", err);
  297. err = -EIO;
  298. }
  299. pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
  300. out_free_rq:
  301. pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
  302. return err;
  303. }
  304. static void
  305. qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter)
  306. {
  307. if (qlcnic_issue_cmd(adapter,
  308. adapter->ahw.pci_func,
  309. adapter->fw_hal_version,
  310. adapter->tx_context_id,
  311. QLCNIC_DESTROY_CTX_RESET,
  312. 0,
  313. QLCNIC_CDRP_CMD_DESTROY_TX_CTX)) {
  314. dev_err(&adapter->pdev->dev,
  315. "Failed to destroy tx ctx in firmware\n");
  316. }
  317. }
  318. int
  319. qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val)
  320. {
  321. if (qlcnic_issue_cmd(adapter,
  322. adapter->ahw.pci_func,
  323. adapter->fw_hal_version,
  324. reg,
  325. 0,
  326. 0,
  327. QLCNIC_CDRP_CMD_READ_PHY)) {
  328. return -EIO;
  329. }
  330. return QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  331. }
  332. int
  333. qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val)
  334. {
  335. return qlcnic_issue_cmd(adapter,
  336. adapter->ahw.pci_func,
  337. adapter->fw_hal_version,
  338. reg,
  339. val,
  340. 0,
  341. QLCNIC_CDRP_CMD_WRITE_PHY);
  342. }
  343. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  344. {
  345. void *addr;
  346. int err;
  347. int ring;
  348. struct qlcnic_recv_context *recv_ctx;
  349. struct qlcnic_host_rds_ring *rds_ring;
  350. struct qlcnic_host_sds_ring *sds_ring;
  351. struct qlcnic_host_tx_ring *tx_ring;
  352. struct pci_dev *pdev = adapter->pdev;
  353. recv_ctx = &adapter->recv_ctx;
  354. tx_ring = adapter->tx_ring;
  355. tx_ring->hw_consumer = (__le32 *)pci_alloc_consistent(pdev, sizeof(u32),
  356. &tx_ring->hw_cons_phys_addr);
  357. if (tx_ring->hw_consumer == NULL) {
  358. dev_err(&pdev->dev, "failed to allocate tx consumer\n");
  359. return -ENOMEM;
  360. }
  361. *(tx_ring->hw_consumer) = 0;
  362. /* cmd desc ring */
  363. addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
  364. &tx_ring->phys_addr);
  365. if (addr == NULL) {
  366. dev_err(&pdev->dev, "failed to allocate tx desc ring\n");
  367. err = -ENOMEM;
  368. goto err_out_free;
  369. }
  370. tx_ring->desc_head = (struct cmd_desc_type0 *)addr;
  371. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  372. rds_ring = &recv_ctx->rds_rings[ring];
  373. addr = pci_alloc_consistent(adapter->pdev,
  374. RCV_DESC_RINGSIZE(rds_ring),
  375. &rds_ring->phys_addr);
  376. if (addr == NULL) {
  377. dev_err(&pdev->dev,
  378. "failed to allocate rds ring [%d]\n", ring);
  379. err = -ENOMEM;
  380. goto err_out_free;
  381. }
  382. rds_ring->desc_head = (struct rcv_desc *)addr;
  383. }
  384. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  385. sds_ring = &recv_ctx->sds_rings[ring];
  386. addr = pci_alloc_consistent(adapter->pdev,
  387. STATUS_DESC_RINGSIZE(sds_ring),
  388. &sds_ring->phys_addr);
  389. if (addr == NULL) {
  390. dev_err(&pdev->dev,
  391. "failed to allocate sds ring [%d]\n", ring);
  392. err = -ENOMEM;
  393. goto err_out_free;
  394. }
  395. sds_ring->desc_head = (struct status_desc *)addr;
  396. }
  397. return 0;
  398. err_out_free:
  399. qlcnic_free_hw_resources(adapter);
  400. return err;
  401. }
  402. int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter)
  403. {
  404. int err;
  405. err = qlcnic_fw_cmd_create_rx_ctx(adapter);
  406. if (err)
  407. return err;
  408. err = qlcnic_fw_cmd_create_tx_ctx(adapter);
  409. if (err) {
  410. qlcnic_fw_cmd_destroy_rx_ctx(adapter);
  411. return err;
  412. }
  413. set_bit(__QLCNIC_FW_ATTACHED, &adapter->state);
  414. return 0;
  415. }
  416. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  417. {
  418. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  419. qlcnic_fw_cmd_destroy_rx_ctx(adapter);
  420. qlcnic_fw_cmd_destroy_tx_ctx(adapter);
  421. /* Allow dma queues to drain after context reset */
  422. msleep(20);
  423. }
  424. }
  425. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  426. {
  427. struct qlcnic_recv_context *recv_ctx;
  428. struct qlcnic_host_rds_ring *rds_ring;
  429. struct qlcnic_host_sds_ring *sds_ring;
  430. struct qlcnic_host_tx_ring *tx_ring;
  431. int ring;
  432. recv_ctx = &adapter->recv_ctx;
  433. tx_ring = adapter->tx_ring;
  434. if (tx_ring->hw_consumer != NULL) {
  435. pci_free_consistent(adapter->pdev,
  436. sizeof(u32),
  437. tx_ring->hw_consumer,
  438. tx_ring->hw_cons_phys_addr);
  439. tx_ring->hw_consumer = NULL;
  440. }
  441. if (tx_ring->desc_head != NULL) {
  442. pci_free_consistent(adapter->pdev,
  443. TX_DESC_RINGSIZE(tx_ring),
  444. tx_ring->desc_head, tx_ring->phys_addr);
  445. tx_ring->desc_head = NULL;
  446. }
  447. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  448. rds_ring = &recv_ctx->rds_rings[ring];
  449. if (rds_ring->desc_head != NULL) {
  450. pci_free_consistent(adapter->pdev,
  451. RCV_DESC_RINGSIZE(rds_ring),
  452. rds_ring->desc_head,
  453. rds_ring->phys_addr);
  454. rds_ring->desc_head = NULL;
  455. }
  456. }
  457. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  458. sds_ring = &recv_ctx->sds_rings[ring];
  459. if (sds_ring->desc_head != NULL) {
  460. pci_free_consistent(adapter->pdev,
  461. STATUS_DESC_RINGSIZE(sds_ring),
  462. sds_ring->desc_head,
  463. sds_ring->phys_addr);
  464. sds_ring->desc_head = NULL;
  465. }
  466. }
  467. }
  468. /* Set MAC address of a NIC partition */
  469. int qlcnic_set_mac_address(struct qlcnic_adapter *adapter, u8* mac)
  470. {
  471. int err = 0;
  472. u32 arg1, arg2, arg3;
  473. arg1 = adapter->ahw.pci_func | BIT_9;
  474. arg2 = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
  475. arg3 = mac[4] | (mac[5] << 16);
  476. err = qlcnic_issue_cmd(adapter,
  477. adapter->ahw.pci_func,
  478. adapter->fw_hal_version,
  479. arg1,
  480. arg2,
  481. arg3,
  482. QLCNIC_CDRP_CMD_MAC_ADDRESS);
  483. if (err != QLCNIC_RCODE_SUCCESS) {
  484. dev_err(&adapter->pdev->dev,
  485. "Failed to set mac address%d\n", err);
  486. err = -EIO;
  487. }
  488. return err;
  489. }
  490. /* Get MAC address of a NIC partition */
  491. int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
  492. {
  493. int err;
  494. u32 arg1;
  495. arg1 = adapter->ahw.pci_func | BIT_8;
  496. err = qlcnic_issue_cmd(adapter,
  497. adapter->ahw.pci_func,
  498. adapter->fw_hal_version,
  499. arg1,
  500. 0,
  501. 0,
  502. QLCNIC_CDRP_CMD_MAC_ADDRESS);
  503. if (err == QLCNIC_RCODE_SUCCESS)
  504. qlcnic_fetch_mac(adapter, QLCNIC_ARG1_CRB_OFFSET,
  505. QLCNIC_ARG2_CRB_OFFSET, 0, mac);
  506. else {
  507. dev_err(&adapter->pdev->dev,
  508. "Failed to get mac address%d\n", err);
  509. err = -EIO;
  510. }
  511. return err;
  512. }
  513. /* Get info of a NIC partition */
  514. int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, u8 func_id)
  515. {
  516. int err;
  517. dma_addr_t nic_dma_t;
  518. struct qlcnic_info *nic_info;
  519. void *nic_info_addr;
  520. size_t nic_size = sizeof(struct qlcnic_info);
  521. nic_info_addr = pci_alloc_consistent(adapter->pdev,
  522. nic_size, &nic_dma_t);
  523. if (!nic_info_addr)
  524. return -ENOMEM;
  525. memset(nic_info_addr, 0, nic_size);
  526. nic_info = (struct qlcnic_info *) nic_info_addr;
  527. err = qlcnic_issue_cmd(adapter,
  528. adapter->ahw.pci_func,
  529. adapter->fw_hal_version,
  530. MSD(nic_dma_t),
  531. LSD(nic_dma_t),
  532. (func_id << 16 | nic_size),
  533. QLCNIC_CDRP_CMD_GET_NIC_INFO);
  534. if (err == QLCNIC_RCODE_SUCCESS) {
  535. adapter->physical_port = le16_to_cpu(nic_info->phys_port);
  536. adapter->switch_mode = le16_to_cpu(nic_info->switch_mode);
  537. adapter->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  538. adapter->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  539. adapter->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  540. adapter->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  541. adapter->max_mtu = le16_to_cpu(nic_info->max_mtu);
  542. adapter->capabilities = le32_to_cpu(nic_info->capabilities);
  543. adapter->max_mac_filters = nic_info->max_mac_filters;
  544. if (adapter->capabilities & BIT_6)
  545. adapter->flags |= QLCNIC_ESWITCH_ENABLED;
  546. else
  547. adapter->flags &= ~QLCNIC_ESWITCH_ENABLED;
  548. dev_info(&adapter->pdev->dev,
  549. "phy port: %d switch_mode: %d,\n"
  550. "\tmax_tx_q: %d max_rx_q: %d min_tx_bw: 0x%x,\n"
  551. "\tmax_tx_bw: 0x%x max_mtu:0x%x, capabilities: 0x%x\n",
  552. adapter->physical_port, adapter->switch_mode,
  553. adapter->max_tx_ques, adapter->max_rx_ques,
  554. adapter->min_tx_bw, adapter->max_tx_bw,
  555. adapter->max_mtu, adapter->capabilities);
  556. } else {
  557. dev_err(&adapter->pdev->dev,
  558. "Failed to get nic info%d\n", err);
  559. err = -EIO;
  560. }
  561. pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t);
  562. return err;
  563. }
  564. /* Configure a NIC partition */
  565. int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, struct qlcnic_info *nic)
  566. {
  567. int err = -EIO;
  568. u32 func_state;
  569. dma_addr_t nic_dma_t;
  570. void *nic_info_addr;
  571. struct qlcnic_info *nic_info;
  572. size_t nic_size = sizeof(struct qlcnic_info);
  573. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  574. return err;
  575. if (qlcnic_api_lock(adapter))
  576. return err;
  577. func_state = QLCRD32(adapter, QLCNIC_CRB_DEV_REF_COUNT);
  578. if (QLC_DEV_CHECK_ACTIVE(func_state, nic->pci_func)) {
  579. qlcnic_api_unlock(adapter);
  580. return err;
  581. }
  582. qlcnic_api_unlock(adapter);
  583. nic_info_addr = pci_alloc_consistent(adapter->pdev, nic_size,
  584. &nic_dma_t);
  585. if (!nic_info_addr)
  586. return -ENOMEM;
  587. memset(nic_info_addr, 0, nic_size);
  588. nic_info = (struct qlcnic_info *)nic_info_addr;
  589. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  590. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  591. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  592. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  593. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  594. nic_info->max_mac_filters = nic->max_mac_filters;
  595. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  596. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  597. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  598. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  599. err = qlcnic_issue_cmd(adapter,
  600. adapter->ahw.pci_func,
  601. adapter->fw_hal_version,
  602. MSD(nic_dma_t),
  603. LSD(nic_dma_t),
  604. nic_size,
  605. QLCNIC_CDRP_CMD_SET_NIC_INFO);
  606. if (err != QLCNIC_RCODE_SUCCESS) {
  607. dev_err(&adapter->pdev->dev,
  608. "Failed to set nic info%d\n", err);
  609. err = -EIO;
  610. }
  611. pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t);
  612. return err;
  613. }
  614. /* Get PCI Info of a partition */
  615. int qlcnic_get_pci_info(struct qlcnic_adapter *adapter)
  616. {
  617. int err = 0, i;
  618. dma_addr_t pci_info_dma_t;
  619. struct qlcnic_pci_info *npar;
  620. void *pci_info_addr;
  621. size_t npar_size = sizeof(struct qlcnic_pci_info);
  622. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  623. pci_info_addr = pci_alloc_consistent(adapter->pdev, pci_size,
  624. &pci_info_dma_t);
  625. if (!pci_info_addr)
  626. return -ENOMEM;
  627. memset(pci_info_addr, 0, pci_size);
  628. if (!adapter->npars)
  629. adapter->npars = kzalloc(pci_size, GFP_KERNEL);
  630. if (!adapter->npars) {
  631. err = -ENOMEM;
  632. goto err_npar;
  633. }
  634. if (!adapter->eswitch)
  635. adapter->eswitch = kzalloc(sizeof(struct qlcnic_eswitch) *
  636. QLCNIC_NIU_MAX_XG_PORTS, GFP_KERNEL);
  637. if (!adapter->eswitch) {
  638. err = -ENOMEM;
  639. goto err_eswitch;
  640. }
  641. npar = (struct qlcnic_pci_info *) pci_info_addr;
  642. err = qlcnic_issue_cmd(adapter,
  643. adapter->ahw.pci_func,
  644. adapter->fw_hal_version,
  645. MSD(pci_info_dma_t),
  646. LSD(pci_info_dma_t),
  647. pci_size,
  648. QLCNIC_CDRP_CMD_GET_PCI_INFO);
  649. if (err == QLCNIC_RCODE_SUCCESS) {
  650. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++) {
  651. adapter->npars[i].id = le32_to_cpu(npar->id);
  652. adapter->npars[i].active = le32_to_cpu(npar->active);
  653. adapter->npars[i].type = le32_to_cpu(npar->type);
  654. adapter->npars[i].default_port =
  655. le32_to_cpu(npar->default_port);
  656. adapter->npars[i].tx_min_bw =
  657. le32_to_cpu(npar->tx_min_bw);
  658. adapter->npars[i].tx_max_bw =
  659. le32_to_cpu(npar->tx_max_bw);
  660. memcpy(adapter->npars[i].mac, npar->mac, ETH_ALEN);
  661. }
  662. } else {
  663. dev_err(&adapter->pdev->dev,
  664. "Failed to get PCI Info%d\n", err);
  665. kfree(adapter->npars);
  666. err = -EIO;
  667. }
  668. goto err_npar;
  669. err_eswitch:
  670. kfree(adapter->npars);
  671. adapter->npars = NULL;
  672. err_npar:
  673. pci_free_consistent(adapter->pdev, pci_size, pci_info_addr,
  674. pci_info_dma_t);
  675. return err;
  676. }
  677. /* Reset a NIC partition */
  678. int qlcnic_reset_partition(struct qlcnic_adapter *adapter, u8 func_no)
  679. {
  680. int err = -EIO;
  681. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  682. return err;
  683. err = qlcnic_issue_cmd(adapter,
  684. adapter->ahw.pci_func,
  685. adapter->fw_hal_version,
  686. func_no,
  687. 0,
  688. 0,
  689. QLCNIC_CDRP_CMD_RESET_NPAR);
  690. if (err != QLCNIC_RCODE_SUCCESS) {
  691. dev_err(&adapter->pdev->dev,
  692. "Failed to issue reset partition%d\n", err);
  693. err = -EIO;
  694. }
  695. return err;
  696. }
  697. /* Get eSwitch Capabilities */
  698. int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *adapter, u8 port,
  699. struct qlcnic_eswitch *eswitch)
  700. {
  701. int err = -EIO;
  702. u32 arg1, arg2;
  703. if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC)
  704. return err;
  705. err = qlcnic_issue_cmd(adapter,
  706. adapter->ahw.pci_func,
  707. adapter->fw_hal_version,
  708. port,
  709. 0,
  710. 0,
  711. QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY);
  712. if (err == QLCNIC_RCODE_SUCCESS) {
  713. arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  714. arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET);
  715. eswitch->port = arg1 & 0xf;
  716. eswitch->active_vports = LSB(arg2);
  717. eswitch->max_ucast_filters = MSB(arg2);
  718. eswitch->max_active_vlans = LSB(MSW(arg2));
  719. if (arg1 & BIT_6)
  720. eswitch->flags |= QLCNIC_SWITCH_VLAN_FILTERING;
  721. if (arg1 & BIT_7)
  722. eswitch->flags |= QLCNIC_SWITCH_PROMISC_MODE;
  723. if (arg1 & BIT_8)
  724. eswitch->flags |= QLCNIC_SWITCH_PORT_MIRRORING;
  725. } else {
  726. dev_err(&adapter->pdev->dev,
  727. "Failed to get eswitch capabilities%d\n", err);
  728. }
  729. return err;
  730. }
  731. /* Get current status of eswitch */
  732. int qlcnic_get_eswitch_status(struct qlcnic_adapter *adapter, u8 port,
  733. struct qlcnic_eswitch *eswitch)
  734. {
  735. int err = -EIO;
  736. u32 arg1, arg2;
  737. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  738. return err;
  739. err = qlcnic_issue_cmd(adapter,
  740. adapter->ahw.pci_func,
  741. adapter->fw_hal_version,
  742. port,
  743. 0,
  744. 0,
  745. QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS);
  746. if (err == QLCNIC_RCODE_SUCCESS) {
  747. arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  748. arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET);
  749. eswitch->port = arg1 & 0xf;
  750. eswitch->active_vports = LSB(arg2);
  751. eswitch->active_ucast_filters = MSB(arg2);
  752. eswitch->active_vlans = LSB(MSW(arg2));
  753. if (arg1 & BIT_6)
  754. eswitch->flags |= QLCNIC_SWITCH_VLAN_FILTERING;
  755. if (arg1 & BIT_8)
  756. eswitch->flags |= QLCNIC_SWITCH_PORT_MIRRORING;
  757. } else {
  758. dev_err(&adapter->pdev->dev,
  759. "Failed to get eswitch status%d\n", err);
  760. }
  761. return err;
  762. }
  763. /* Enable/Disable eSwitch */
  764. int qlcnic_toggle_eswitch(struct qlcnic_adapter *adapter, u8 id, u8 enable)
  765. {
  766. int err = -EIO;
  767. u32 arg1, arg2;
  768. struct qlcnic_eswitch *eswitch;
  769. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  770. return err;
  771. eswitch = &adapter->eswitch[id];
  772. if (!eswitch)
  773. return err;
  774. arg1 = eswitch->port | (enable ? BIT_4 : 0);
  775. arg2 = eswitch->active_vports | (eswitch->max_ucast_filters << 8) |
  776. (eswitch->max_active_vlans << 16);
  777. err = qlcnic_issue_cmd(adapter,
  778. adapter->ahw.pci_func,
  779. adapter->fw_hal_version,
  780. arg1,
  781. arg2,
  782. 0,
  783. QLCNIC_CDRP_CMD_TOGGLE_ESWITCH);
  784. if (err != QLCNIC_RCODE_SUCCESS) {
  785. dev_err(&adapter->pdev->dev,
  786. "Failed to enable eswitch%d\n", eswitch->port);
  787. eswitch->flags &= ~QLCNIC_SWITCH_ENABLE;
  788. err = -EIO;
  789. } else {
  790. eswitch->flags |= QLCNIC_SWITCH_ENABLE;
  791. dev_info(&adapter->pdev->dev,
  792. "Enabled eSwitch for port %d\n", eswitch->port);
  793. }
  794. return err;
  795. }
  796. /* Configure eSwitch for port mirroring */
  797. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  798. u8 enable_mirroring, u8 pci_func)
  799. {
  800. int err = -EIO;
  801. u32 arg1;
  802. if (adapter->op_mode != QLCNIC_MGMT_FUNC ||
  803. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  804. return err;
  805. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  806. arg1 |= pci_func << 8;
  807. err = qlcnic_issue_cmd(adapter,
  808. adapter->ahw.pci_func,
  809. adapter->fw_hal_version,
  810. arg1,
  811. 0,
  812. 0,
  813. QLCNIC_CDRP_CMD_SET_PORTMIRRORING);
  814. if (err != QLCNIC_RCODE_SUCCESS) {
  815. dev_err(&adapter->pdev->dev,
  816. "Failed to configure port mirroring%d on eswitch:%d\n",
  817. pci_func, id);
  818. } else {
  819. dev_info(&adapter->pdev->dev,
  820. "Configured eSwitch %d for port mirroring:%d\n",
  821. id, pci_func);
  822. }
  823. return err;
  824. }
  825. /* Configure eSwitch port */
  826. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter, u8 id,
  827. int vlan_tagging, u8 discard_tagged, u8 promsc_mode,
  828. u8 mac_learn, u8 pci_func, u16 vlan_id)
  829. {
  830. int err = -EIO;
  831. u32 arg1;
  832. struct qlcnic_eswitch *eswitch;
  833. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  834. return err;
  835. eswitch = &adapter->eswitch[id];
  836. if (!(eswitch->flags & QLCNIC_SWITCH_ENABLE))
  837. return err;
  838. arg1 = eswitch->port | (discard_tagged ? BIT_4 : 0);
  839. arg1 |= (promsc_mode ? BIT_6 : 0) | (mac_learn ? BIT_7 : 0);
  840. arg1 |= pci_func << 8;
  841. if (vlan_tagging)
  842. arg1 |= BIT_5 | (vlan_id << 16);
  843. err = qlcnic_issue_cmd(adapter,
  844. adapter->ahw.pci_func,
  845. adapter->fw_hal_version,
  846. arg1,
  847. 0,
  848. 0,
  849. QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH);
  850. if (err != QLCNIC_RCODE_SUCCESS) {
  851. dev_err(&adapter->pdev->dev,
  852. "Failed to configure eswitch port%d\n", eswitch->port);
  853. eswitch->flags |= QLCNIC_SWITCH_ENABLE;
  854. } else {
  855. eswitch->flags &= ~QLCNIC_SWITCH_ENABLE;
  856. dev_info(&adapter->pdev->dev,
  857. "Configured eSwitch for port %d\n", eswitch->port);
  858. }
  859. return err;
  860. }