rs690.c 25 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include "drmP.h"
  29. #include "radeon.h"
  30. #include "atom.h"
  31. #include "rs690d.h"
  32. static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  33. {
  34. unsigned i;
  35. uint32_t tmp;
  36. for (i = 0; i < rdev->usec_timeout; i++) {
  37. /* read MC_STATUS */
  38. tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  39. if (G_000090_MC_SYSTEM_IDLE(tmp))
  40. return 0;
  41. udelay(1);
  42. }
  43. return -1;
  44. }
  45. static void rs690_gpu_init(struct radeon_device *rdev)
  46. {
  47. /* FIXME: HDP same place on rs690 ? */
  48. r100_hdp_reset(rdev);
  49. /* FIXME: is this correct ? */
  50. r420_pipes_init(rdev);
  51. if (rs690_mc_wait_for_idle(rdev)) {
  52. printk(KERN_WARNING "Failed to wait MC idle while "
  53. "programming pipes. Bad things might happen.\n");
  54. }
  55. }
  56. void rs690_pm_info(struct radeon_device *rdev)
  57. {
  58. int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  59. struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
  60. struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
  61. void *ptr;
  62. uint16_t data_offset;
  63. uint8_t frev, crev;
  64. fixed20_12 tmp;
  65. atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  66. &frev, &crev, &data_offset);
  67. ptr = rdev->mode_info.atom_context->bios + data_offset;
  68. info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
  69. info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
  70. /* Get various system informations from bios */
  71. switch (crev) {
  72. case 1:
  73. tmp.full = rfixed_const(100);
  74. rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
  75. rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  76. rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
  77. rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
  78. rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
  79. break;
  80. case 2:
  81. tmp.full = rfixed_const(100);
  82. rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
  83. rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  84. rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
  85. rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
  86. rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
  87. rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
  88. rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
  89. break;
  90. default:
  91. tmp.full = rfixed_const(100);
  92. /* We assume the slower possible clock ie worst case */
  93. /* DDR 333Mhz */
  94. rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
  95. /* FIXME: system clock ? */
  96. rdev->pm.igp_system_mclk.full = rfixed_const(100);
  97. rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
  98. rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
  99. rdev->pm.igp_ht_link_width.full = rfixed_const(8);
  100. DRM_ERROR("No integrated system info for your GPU, using safe default\n");
  101. break;
  102. }
  103. /* Compute various bandwidth */
  104. /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
  105. tmp.full = rfixed_const(4);
  106. rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
  107. /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
  108. * = ht_clk * ht_width / 5
  109. */
  110. tmp.full = rfixed_const(5);
  111. rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
  112. rdev->pm.igp_ht_link_width);
  113. rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
  114. if (tmp.full < rdev->pm.max_bandwidth.full) {
  115. /* HT link is a limiting factor */
  116. rdev->pm.max_bandwidth.full = tmp.full;
  117. }
  118. /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
  119. * = (sideport_clk * 14) / 10
  120. */
  121. tmp.full = rfixed_const(14);
  122. rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
  123. tmp.full = rfixed_const(10);
  124. rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
  125. }
  126. void rs690_mc_init(struct radeon_device *rdev)
  127. {
  128. fixed20_12 a;
  129. u64 base;
  130. rs400_gart_adjust_size(rdev);
  131. rdev->mc.vram_is_ddr = true;
  132. rdev->mc.vram_width = 128;
  133. rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  134. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  135. rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  136. rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  137. base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
  138. base = G_000100_MC_FB_START(base) << 16;
  139. rs690_pm_info(rdev);
  140. /* FIXME: we should enforce default clock in case GPU is not in
  141. * default setup
  142. */
  143. a.full = rfixed_const(100);
  144. rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
  145. rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
  146. a.full = rfixed_const(16);
  147. /* core_bandwidth = sclk(Mhz) * 16 */
  148. rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
  149. rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  150. radeon_vram_location(rdev, &rdev->mc, base);
  151. radeon_gtt_location(rdev, &rdev->mc);
  152. }
  153. void rs690_line_buffer_adjust(struct radeon_device *rdev,
  154. struct drm_display_mode *mode1,
  155. struct drm_display_mode *mode2)
  156. {
  157. u32 tmp;
  158. /*
  159. * Line Buffer Setup
  160. * There is a single line buffer shared by both display controllers.
  161. * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
  162. * the display controllers. The paritioning can either be done
  163. * manually or via one of four preset allocations specified in bits 1:0:
  164. * 0 - line buffer is divided in half and shared between crtc
  165. * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
  166. * 2 - D1 gets the whole buffer
  167. * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
  168. * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
  169. * allocation mode. In manual allocation mode, D1 always starts at 0,
  170. * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
  171. */
  172. tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
  173. tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
  174. /* auto */
  175. if (mode1 && mode2) {
  176. if (mode1->hdisplay > mode2->hdisplay) {
  177. if (mode1->hdisplay > 2560)
  178. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
  179. else
  180. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
  181. } else if (mode2->hdisplay > mode1->hdisplay) {
  182. if (mode2->hdisplay > 2560)
  183. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
  184. else
  185. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
  186. } else
  187. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
  188. } else if (mode1) {
  189. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
  190. } else if (mode2) {
  191. tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
  192. }
  193. WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
  194. }
  195. struct rs690_watermark {
  196. u32 lb_request_fifo_depth;
  197. fixed20_12 num_line_pair;
  198. fixed20_12 estimated_width;
  199. fixed20_12 worst_case_latency;
  200. fixed20_12 consumption_rate;
  201. fixed20_12 active_time;
  202. fixed20_12 dbpp;
  203. fixed20_12 priority_mark_max;
  204. fixed20_12 priority_mark;
  205. fixed20_12 sclk;
  206. };
  207. void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
  208. struct radeon_crtc *crtc,
  209. struct rs690_watermark *wm)
  210. {
  211. struct drm_display_mode *mode = &crtc->base.mode;
  212. fixed20_12 a, b, c;
  213. fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
  214. fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
  215. /* FIXME: detect IGP with sideport memory, i don't think there is any
  216. * such product available
  217. */
  218. bool sideport = false;
  219. if (!crtc->base.enabled) {
  220. /* FIXME: wouldn't it better to set priority mark to maximum */
  221. wm->lb_request_fifo_depth = 4;
  222. return;
  223. }
  224. if (crtc->vsc.full > rfixed_const(2))
  225. wm->num_line_pair.full = rfixed_const(2);
  226. else
  227. wm->num_line_pair.full = rfixed_const(1);
  228. b.full = rfixed_const(mode->crtc_hdisplay);
  229. c.full = rfixed_const(256);
  230. a.full = rfixed_div(b, c);
  231. request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
  232. request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
  233. if (a.full < rfixed_const(4)) {
  234. wm->lb_request_fifo_depth = 4;
  235. } else {
  236. wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
  237. }
  238. /* Determine consumption rate
  239. * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
  240. * vtaps = number of vertical taps,
  241. * vsc = vertical scaling ratio, defined as source/destination
  242. * hsc = horizontal scaling ration, defined as source/destination
  243. */
  244. a.full = rfixed_const(mode->clock);
  245. b.full = rfixed_const(1000);
  246. a.full = rfixed_div(a, b);
  247. pclk.full = rfixed_div(b, a);
  248. if (crtc->rmx_type != RMX_OFF) {
  249. b.full = rfixed_const(2);
  250. if (crtc->vsc.full > b.full)
  251. b.full = crtc->vsc.full;
  252. b.full = rfixed_mul(b, crtc->hsc);
  253. c.full = rfixed_const(2);
  254. b.full = rfixed_div(b, c);
  255. consumption_time.full = rfixed_div(pclk, b);
  256. } else {
  257. consumption_time.full = pclk.full;
  258. }
  259. a.full = rfixed_const(1);
  260. wm->consumption_rate.full = rfixed_div(a, consumption_time);
  261. /* Determine line time
  262. * LineTime = total time for one line of displayhtotal
  263. * LineTime = total number of horizontal pixels
  264. * pclk = pixel clock period(ns)
  265. */
  266. a.full = rfixed_const(crtc->base.mode.crtc_htotal);
  267. line_time.full = rfixed_mul(a, pclk);
  268. /* Determine active time
  269. * ActiveTime = time of active region of display within one line,
  270. * hactive = total number of horizontal active pixels
  271. * htotal = total number of horizontal pixels
  272. */
  273. a.full = rfixed_const(crtc->base.mode.crtc_htotal);
  274. b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
  275. wm->active_time.full = rfixed_mul(line_time, b);
  276. wm->active_time.full = rfixed_div(wm->active_time, a);
  277. /* Maximun bandwidth is the minimun bandwidth of all component */
  278. rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
  279. if (sideport) {
  280. if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
  281. rdev->pm.sideport_bandwidth.full)
  282. rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
  283. read_delay_latency.full = rfixed_const(370 * 800 * 1000);
  284. read_delay_latency.full = rfixed_div(read_delay_latency,
  285. rdev->pm.igp_sideport_mclk);
  286. } else {
  287. if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
  288. rdev->pm.k8_bandwidth.full)
  289. rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
  290. if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
  291. rdev->pm.ht_bandwidth.full)
  292. rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
  293. read_delay_latency.full = rfixed_const(5000);
  294. }
  295. /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
  296. a.full = rfixed_const(16);
  297. rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
  298. a.full = rfixed_const(1000);
  299. rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
  300. /* Determine chunk time
  301. * ChunkTime = the time it takes the DCP to send one chunk of data
  302. * to the LB which consists of pipeline delay and inter chunk gap
  303. * sclk = system clock(ns)
  304. */
  305. a.full = rfixed_const(256 * 13);
  306. chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
  307. a.full = rfixed_const(10);
  308. chunk_time.full = rfixed_div(chunk_time, a);
  309. /* Determine the worst case latency
  310. * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
  311. * WorstCaseLatency = worst case time from urgent to when the MC starts
  312. * to return data
  313. * READ_DELAY_IDLE_MAX = constant of 1us
  314. * ChunkTime = time it takes the DCP to send one chunk of data to the LB
  315. * which consists of pipeline delay and inter chunk gap
  316. */
  317. if (rfixed_trunc(wm->num_line_pair) > 1) {
  318. a.full = rfixed_const(3);
  319. wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
  320. wm->worst_case_latency.full += read_delay_latency.full;
  321. } else {
  322. a.full = rfixed_const(2);
  323. wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
  324. wm->worst_case_latency.full += read_delay_latency.full;
  325. }
  326. /* Determine the tolerable latency
  327. * TolerableLatency = Any given request has only 1 line time
  328. * for the data to be returned
  329. * LBRequestFifoDepth = Number of chunk requests the LB can
  330. * put into the request FIFO for a display
  331. * LineTime = total time for one line of display
  332. * ChunkTime = the time it takes the DCP to send one chunk
  333. * of data to the LB which consists of
  334. * pipeline delay and inter chunk gap
  335. */
  336. if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
  337. tolerable_latency.full = line_time.full;
  338. } else {
  339. tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
  340. tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
  341. tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
  342. tolerable_latency.full = line_time.full - tolerable_latency.full;
  343. }
  344. /* We assume worst case 32bits (4 bytes) */
  345. wm->dbpp.full = rfixed_const(4 * 8);
  346. /* Determine the maximum priority mark
  347. * width = viewport width in pixels
  348. */
  349. a.full = rfixed_const(16);
  350. wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
  351. wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
  352. wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
  353. /* Determine estimated width */
  354. estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
  355. estimated_width.full = rfixed_div(estimated_width, consumption_time);
  356. if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
  357. wm->priority_mark.full = rfixed_const(10);
  358. } else {
  359. a.full = rfixed_const(16);
  360. wm->priority_mark.full = rfixed_div(estimated_width, a);
  361. wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
  362. wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
  363. }
  364. }
  365. void rs690_bandwidth_update(struct radeon_device *rdev)
  366. {
  367. struct drm_display_mode *mode0 = NULL;
  368. struct drm_display_mode *mode1 = NULL;
  369. struct rs690_watermark wm0;
  370. struct rs690_watermark wm1;
  371. u32 tmp;
  372. fixed20_12 priority_mark02, priority_mark12, fill_rate;
  373. fixed20_12 a, b;
  374. if (rdev->mode_info.crtcs[0]->base.enabled)
  375. mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  376. if (rdev->mode_info.crtcs[1]->base.enabled)
  377. mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  378. /*
  379. * Set display0/1 priority up in the memory controller for
  380. * modes if the user specifies HIGH for displaypriority
  381. * option.
  382. */
  383. if (rdev->disp_priority == 2) {
  384. tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
  385. tmp &= C_000104_MC_DISP0R_INIT_LAT;
  386. tmp &= C_000104_MC_DISP1R_INIT_LAT;
  387. if (mode0)
  388. tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
  389. if (mode1)
  390. tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
  391. WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
  392. }
  393. rs690_line_buffer_adjust(rdev, mode0, mode1);
  394. if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
  395. WREG32(R_006C9C_DCP_CONTROL, 0);
  396. if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
  397. WREG32(R_006C9C_DCP_CONTROL, 2);
  398. rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
  399. rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
  400. tmp = (wm0.lb_request_fifo_depth - 1);
  401. tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
  402. WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
  403. if (mode0 && mode1) {
  404. if (rfixed_trunc(wm0.dbpp) > 64)
  405. a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
  406. else
  407. a.full = wm0.num_line_pair.full;
  408. if (rfixed_trunc(wm1.dbpp) > 64)
  409. b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
  410. else
  411. b.full = wm1.num_line_pair.full;
  412. a.full += b.full;
  413. fill_rate.full = rfixed_div(wm0.sclk, a);
  414. if (wm0.consumption_rate.full > fill_rate.full) {
  415. b.full = wm0.consumption_rate.full - fill_rate.full;
  416. b.full = rfixed_mul(b, wm0.active_time);
  417. a.full = rfixed_mul(wm0.worst_case_latency,
  418. wm0.consumption_rate);
  419. a.full = a.full + b.full;
  420. b.full = rfixed_const(16 * 1000);
  421. priority_mark02.full = rfixed_div(a, b);
  422. } else {
  423. a.full = rfixed_mul(wm0.worst_case_latency,
  424. wm0.consumption_rate);
  425. b.full = rfixed_const(16 * 1000);
  426. priority_mark02.full = rfixed_div(a, b);
  427. }
  428. if (wm1.consumption_rate.full > fill_rate.full) {
  429. b.full = wm1.consumption_rate.full - fill_rate.full;
  430. b.full = rfixed_mul(b, wm1.active_time);
  431. a.full = rfixed_mul(wm1.worst_case_latency,
  432. wm1.consumption_rate);
  433. a.full = a.full + b.full;
  434. b.full = rfixed_const(16 * 1000);
  435. priority_mark12.full = rfixed_div(a, b);
  436. } else {
  437. a.full = rfixed_mul(wm1.worst_case_latency,
  438. wm1.consumption_rate);
  439. b.full = rfixed_const(16 * 1000);
  440. priority_mark12.full = rfixed_div(a, b);
  441. }
  442. if (wm0.priority_mark.full > priority_mark02.full)
  443. priority_mark02.full = wm0.priority_mark.full;
  444. if (rfixed_trunc(priority_mark02) < 0)
  445. priority_mark02.full = 0;
  446. if (wm0.priority_mark_max.full > priority_mark02.full)
  447. priority_mark02.full = wm0.priority_mark_max.full;
  448. if (wm1.priority_mark.full > priority_mark12.full)
  449. priority_mark12.full = wm1.priority_mark.full;
  450. if (rfixed_trunc(priority_mark12) < 0)
  451. priority_mark12.full = 0;
  452. if (wm1.priority_mark_max.full > priority_mark12.full)
  453. priority_mark12.full = wm1.priority_mark_max.full;
  454. WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
  455. WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
  456. WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
  457. WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
  458. } else if (mode0) {
  459. if (rfixed_trunc(wm0.dbpp) > 64)
  460. a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
  461. else
  462. a.full = wm0.num_line_pair.full;
  463. fill_rate.full = rfixed_div(wm0.sclk, a);
  464. if (wm0.consumption_rate.full > fill_rate.full) {
  465. b.full = wm0.consumption_rate.full - fill_rate.full;
  466. b.full = rfixed_mul(b, wm0.active_time);
  467. a.full = rfixed_mul(wm0.worst_case_latency,
  468. wm0.consumption_rate);
  469. a.full = a.full + b.full;
  470. b.full = rfixed_const(16 * 1000);
  471. priority_mark02.full = rfixed_div(a, b);
  472. } else {
  473. a.full = rfixed_mul(wm0.worst_case_latency,
  474. wm0.consumption_rate);
  475. b.full = rfixed_const(16 * 1000);
  476. priority_mark02.full = rfixed_div(a, b);
  477. }
  478. if (wm0.priority_mark.full > priority_mark02.full)
  479. priority_mark02.full = wm0.priority_mark.full;
  480. if (rfixed_trunc(priority_mark02) < 0)
  481. priority_mark02.full = 0;
  482. if (wm0.priority_mark_max.full > priority_mark02.full)
  483. priority_mark02.full = wm0.priority_mark_max.full;
  484. WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
  485. WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
  486. WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
  487. S_006D48_D2MODE_PRIORITY_A_OFF(1));
  488. WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
  489. S_006D4C_D2MODE_PRIORITY_B_OFF(1));
  490. } else {
  491. if (rfixed_trunc(wm1.dbpp) > 64)
  492. a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
  493. else
  494. a.full = wm1.num_line_pair.full;
  495. fill_rate.full = rfixed_div(wm1.sclk, a);
  496. if (wm1.consumption_rate.full > fill_rate.full) {
  497. b.full = wm1.consumption_rate.full - fill_rate.full;
  498. b.full = rfixed_mul(b, wm1.active_time);
  499. a.full = rfixed_mul(wm1.worst_case_latency,
  500. wm1.consumption_rate);
  501. a.full = a.full + b.full;
  502. b.full = rfixed_const(16 * 1000);
  503. priority_mark12.full = rfixed_div(a, b);
  504. } else {
  505. a.full = rfixed_mul(wm1.worst_case_latency,
  506. wm1.consumption_rate);
  507. b.full = rfixed_const(16 * 1000);
  508. priority_mark12.full = rfixed_div(a, b);
  509. }
  510. if (wm1.priority_mark.full > priority_mark12.full)
  511. priority_mark12.full = wm1.priority_mark.full;
  512. if (rfixed_trunc(priority_mark12) < 0)
  513. priority_mark12.full = 0;
  514. if (wm1.priority_mark_max.full > priority_mark12.full)
  515. priority_mark12.full = wm1.priority_mark_max.full;
  516. WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
  517. S_006548_D1MODE_PRIORITY_A_OFF(1));
  518. WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
  519. S_00654C_D1MODE_PRIORITY_B_OFF(1));
  520. WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
  521. WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
  522. }
  523. }
  524. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  525. {
  526. uint32_t r;
  527. WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
  528. r = RREG32(R_00007C_MC_DATA);
  529. WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
  530. return r;
  531. }
  532. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  533. {
  534. WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
  535. S_000078_MC_IND_WR_EN(1));
  536. WREG32(R_00007C_MC_DATA, v);
  537. WREG32(R_000078_MC_INDEX, 0x7F);
  538. }
  539. void rs690_mc_program(struct radeon_device *rdev)
  540. {
  541. struct rv515_mc_save save;
  542. /* Stops all mc clients */
  543. rv515_mc_stop(rdev, &save);
  544. /* Wait for mc idle */
  545. if (rs690_mc_wait_for_idle(rdev))
  546. dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  547. /* Program MC, should be a 32bits limited address space */
  548. WREG32_MC(R_000100_MCCFG_FB_LOCATION,
  549. S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
  550. S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
  551. WREG32(R_000134_HDP_FB_LOCATION,
  552. S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  553. rv515_mc_resume(rdev, &save);
  554. }
  555. static int rs690_startup(struct radeon_device *rdev)
  556. {
  557. int r;
  558. rs690_mc_program(rdev);
  559. /* Resume clock */
  560. rv515_clock_startup(rdev);
  561. /* Initialize GPU configuration (# pipes, ...) */
  562. rs690_gpu_init(rdev);
  563. /* Initialize GART (initialize after TTM so we can allocate
  564. * memory through TTM but finalize after TTM) */
  565. r = rs400_gart_enable(rdev);
  566. if (r)
  567. return r;
  568. /* Enable IRQ */
  569. rs600_irq_set(rdev);
  570. rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  571. /* 1M ring buffer */
  572. r = r100_cp_init(rdev, 1024 * 1024);
  573. if (r) {
  574. dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  575. return r;
  576. }
  577. r = r100_wb_init(rdev);
  578. if (r)
  579. dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  580. r = r100_ib_init(rdev);
  581. if (r) {
  582. dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  583. return r;
  584. }
  585. return 0;
  586. }
  587. int rs690_resume(struct radeon_device *rdev)
  588. {
  589. /* Make sur GART are not working */
  590. rs400_gart_disable(rdev);
  591. /* Resume clock before doing reset */
  592. rv515_clock_startup(rdev);
  593. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  594. if (radeon_gpu_reset(rdev)) {
  595. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  596. RREG32(R_000E40_RBBM_STATUS),
  597. RREG32(R_0007C0_CP_STAT));
  598. }
  599. /* post */
  600. atom_asic_init(rdev->mode_info.atom_context);
  601. /* Resume clock after posting */
  602. rv515_clock_startup(rdev);
  603. /* Initialize surface registers */
  604. radeon_surface_init(rdev);
  605. return rs690_startup(rdev);
  606. }
  607. int rs690_suspend(struct radeon_device *rdev)
  608. {
  609. r100_cp_disable(rdev);
  610. r100_wb_disable(rdev);
  611. rs600_irq_disable(rdev);
  612. rs400_gart_disable(rdev);
  613. return 0;
  614. }
  615. void rs690_fini(struct radeon_device *rdev)
  616. {
  617. r100_cp_fini(rdev);
  618. r100_wb_fini(rdev);
  619. r100_ib_fini(rdev);
  620. radeon_gem_fini(rdev);
  621. rs400_gart_fini(rdev);
  622. radeon_irq_kms_fini(rdev);
  623. radeon_fence_driver_fini(rdev);
  624. radeon_bo_fini(rdev);
  625. radeon_atombios_fini(rdev);
  626. kfree(rdev->bios);
  627. rdev->bios = NULL;
  628. }
  629. int rs690_init(struct radeon_device *rdev)
  630. {
  631. int r;
  632. /* Disable VGA */
  633. rv515_vga_render_disable(rdev);
  634. /* Initialize scratch registers */
  635. radeon_scratch_init(rdev);
  636. /* Initialize surface registers */
  637. radeon_surface_init(rdev);
  638. /* TODO: disable VGA need to use VGA request */
  639. /* BIOS*/
  640. if (!radeon_get_bios(rdev)) {
  641. if (ASIC_IS_AVIVO(rdev))
  642. return -EINVAL;
  643. }
  644. if (rdev->is_atom_bios) {
  645. r = radeon_atombios_init(rdev);
  646. if (r)
  647. return r;
  648. } else {
  649. dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
  650. return -EINVAL;
  651. }
  652. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  653. if (radeon_gpu_reset(rdev)) {
  654. dev_warn(rdev->dev,
  655. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  656. RREG32(R_000E40_RBBM_STATUS),
  657. RREG32(R_0007C0_CP_STAT));
  658. }
  659. /* check if cards are posted or not */
  660. if (radeon_boot_test_post_card(rdev) == false)
  661. return -EINVAL;
  662. /* Initialize clocks */
  663. radeon_get_clock_info(rdev->ddev);
  664. /* Initialize power management */
  665. radeon_pm_init(rdev);
  666. /* initialize memory controller */
  667. rs690_mc_init(rdev);
  668. rv515_debugfs(rdev);
  669. /* Fence driver */
  670. r = radeon_fence_driver_init(rdev);
  671. if (r)
  672. return r;
  673. r = radeon_irq_kms_init(rdev);
  674. if (r)
  675. return r;
  676. /* Memory manager */
  677. r = radeon_bo_init(rdev);
  678. if (r)
  679. return r;
  680. r = rs400_gart_init(rdev);
  681. if (r)
  682. return r;
  683. rs600_set_safe_registers(rdev);
  684. rdev->accel_working = true;
  685. r = rs690_startup(rdev);
  686. if (r) {
  687. /* Somethings want wront with the accel init stop accel */
  688. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  689. r100_cp_fini(rdev);
  690. r100_wb_fini(rdev);
  691. r100_ib_fini(rdev);
  692. rs400_gart_fini(rdev);
  693. radeon_irq_kms_fini(rdev);
  694. rdev->accel_working = false;
  695. }
  696. return 0;
  697. }