iwl-3945.c 73 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * Intel Linux Wireless <ilw@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/pci.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/delay.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/wireless.h>
  35. #include <linux/firmware.h>
  36. #include <linux/etherdevice.h>
  37. #include <asm/unaligned.h>
  38. #include <net/mac80211.h>
  39. #include "iwl-3945-core.h"
  40. #include "iwl-3945.h"
  41. #include "iwl-helpers.h"
  42. #include "iwl-3945-rs.h"
  43. #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
  44. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  45. IWL_RATE_##r##M_IEEE, \
  46. IWL_RATE_##ip##M_INDEX, \
  47. IWL_RATE_##in##M_INDEX, \
  48. IWL_RATE_##rp##M_INDEX, \
  49. IWL_RATE_##rn##M_INDEX, \
  50. IWL_RATE_##pp##M_INDEX, \
  51. IWL_RATE_##np##M_INDEX, \
  52. IWL_RATE_##r##M_INDEX_TABLE, \
  53. IWL_RATE_##ip##M_INDEX_TABLE }
  54. /*
  55. * Parameter order:
  56. * rate, prev rate, next rate, prev tgg rate, next tgg rate
  57. *
  58. * If there isn't a valid next or previous rate then INV is used which
  59. * maps to IWL_RATE_INVALID
  60. *
  61. */
  62. const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
  63. IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
  64. IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
  65. IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  66. IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
  67. IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  68. IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
  69. IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  70. IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  71. IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  72. IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  73. IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  74. IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  75. };
  76. /* 1 = enable the iwl3945_disable_events() function */
  77. #define IWL_EVT_DISABLE (0)
  78. #define IWL_EVT_DISABLE_SIZE (1532/32)
  79. /**
  80. * iwl3945_disable_events - Disable selected events in uCode event log
  81. *
  82. * Disable an event by writing "1"s into "disable"
  83. * bitmap in SRAM. Bit position corresponds to Event # (id/type).
  84. * Default values of 0 enable uCode events to be logged.
  85. * Use for only special debugging. This function is just a placeholder as-is,
  86. * you'll need to provide the special bits! ...
  87. * ... and set IWL_EVT_DISABLE to 1. */
  88. void iwl3945_disable_events(struct iwl3945_priv *priv)
  89. {
  90. int ret;
  91. int i;
  92. u32 base; /* SRAM address of event log header */
  93. u32 disable_ptr; /* SRAM address of event-disable bitmap array */
  94. u32 array_size; /* # of u32 entries in array */
  95. u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
  96. 0x00000000, /* 31 - 0 Event id numbers */
  97. 0x00000000, /* 63 - 32 */
  98. 0x00000000, /* 95 - 64 */
  99. 0x00000000, /* 127 - 96 */
  100. 0x00000000, /* 159 - 128 */
  101. 0x00000000, /* 191 - 160 */
  102. 0x00000000, /* 223 - 192 */
  103. 0x00000000, /* 255 - 224 */
  104. 0x00000000, /* 287 - 256 */
  105. 0x00000000, /* 319 - 288 */
  106. 0x00000000, /* 351 - 320 */
  107. 0x00000000, /* 383 - 352 */
  108. 0x00000000, /* 415 - 384 */
  109. 0x00000000, /* 447 - 416 */
  110. 0x00000000, /* 479 - 448 */
  111. 0x00000000, /* 511 - 480 */
  112. 0x00000000, /* 543 - 512 */
  113. 0x00000000, /* 575 - 544 */
  114. 0x00000000, /* 607 - 576 */
  115. 0x00000000, /* 639 - 608 */
  116. 0x00000000, /* 671 - 640 */
  117. 0x00000000, /* 703 - 672 */
  118. 0x00000000, /* 735 - 704 */
  119. 0x00000000, /* 767 - 736 */
  120. 0x00000000, /* 799 - 768 */
  121. 0x00000000, /* 831 - 800 */
  122. 0x00000000, /* 863 - 832 */
  123. 0x00000000, /* 895 - 864 */
  124. 0x00000000, /* 927 - 896 */
  125. 0x00000000, /* 959 - 928 */
  126. 0x00000000, /* 991 - 960 */
  127. 0x00000000, /* 1023 - 992 */
  128. 0x00000000, /* 1055 - 1024 */
  129. 0x00000000, /* 1087 - 1056 */
  130. 0x00000000, /* 1119 - 1088 */
  131. 0x00000000, /* 1151 - 1120 */
  132. 0x00000000, /* 1183 - 1152 */
  133. 0x00000000, /* 1215 - 1184 */
  134. 0x00000000, /* 1247 - 1216 */
  135. 0x00000000, /* 1279 - 1248 */
  136. 0x00000000, /* 1311 - 1280 */
  137. 0x00000000, /* 1343 - 1312 */
  138. 0x00000000, /* 1375 - 1344 */
  139. 0x00000000, /* 1407 - 1376 */
  140. 0x00000000, /* 1439 - 1408 */
  141. 0x00000000, /* 1471 - 1440 */
  142. 0x00000000, /* 1503 - 1472 */
  143. };
  144. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  145. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  146. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  147. return;
  148. }
  149. ret = iwl3945_grab_nic_access(priv);
  150. if (ret) {
  151. IWL_WARNING("Can not read from adapter at this time.\n");
  152. return;
  153. }
  154. disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
  155. array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
  156. iwl3945_release_nic_access(priv);
  157. if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
  158. IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
  159. disable_ptr);
  160. ret = iwl3945_grab_nic_access(priv);
  161. for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
  162. iwl3945_write_targ_mem(priv,
  163. disable_ptr + (i * sizeof(u32)),
  164. evt_disable[i]);
  165. iwl3945_release_nic_access(priv);
  166. } else {
  167. IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
  168. IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
  169. IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
  170. disable_ptr, array_size);
  171. }
  172. }
  173. static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
  174. {
  175. int idx;
  176. for (idx = 0; idx < IWL_RATE_COUNT; idx++)
  177. if (iwl3945_rates[idx].plcp == plcp)
  178. return idx;
  179. return -1;
  180. }
  181. /**
  182. * iwl3945_get_antenna_flags - Get antenna flags for RXON command
  183. * @priv: eeprom and antenna fields are used to determine antenna flags
  184. *
  185. * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
  186. * priv->antenna specifies the antenna diversity mode:
  187. *
  188. * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  189. * IWL_ANTENNA_MAIN - Force MAIN antenna
  190. * IWL_ANTENNA_AUX - Force AUX antenna
  191. */
  192. __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
  193. {
  194. switch (priv->antenna) {
  195. case IWL_ANTENNA_DIVERSITY:
  196. return 0;
  197. case IWL_ANTENNA_MAIN:
  198. if (priv->eeprom.antenna_switch_type)
  199. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  200. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  201. case IWL_ANTENNA_AUX:
  202. if (priv->eeprom.antenna_switch_type)
  203. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  204. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  205. }
  206. /* bad antenna selector value */
  207. IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
  208. return 0; /* "diversity" is default if error */
  209. }
  210. #ifdef CONFIG_IWL3945_DEBUG
  211. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  212. static const char *iwl3945_get_tx_fail_reason(u32 status)
  213. {
  214. switch (status & TX_STATUS_MSK) {
  215. case TX_STATUS_SUCCESS:
  216. return "SUCCESS";
  217. TX_STATUS_ENTRY(SHORT_LIMIT);
  218. TX_STATUS_ENTRY(LONG_LIMIT);
  219. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  220. TX_STATUS_ENTRY(MGMNT_ABORT);
  221. TX_STATUS_ENTRY(NEXT_FRAG);
  222. TX_STATUS_ENTRY(LIFE_EXPIRE);
  223. TX_STATUS_ENTRY(DEST_PS);
  224. TX_STATUS_ENTRY(ABORTED);
  225. TX_STATUS_ENTRY(BT_RETRY);
  226. TX_STATUS_ENTRY(STA_INVALID);
  227. TX_STATUS_ENTRY(FRAG_DROPPED);
  228. TX_STATUS_ENTRY(TID_DISABLE);
  229. TX_STATUS_ENTRY(FRAME_FLUSHED);
  230. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  231. TX_STATUS_ENTRY(TX_LOCKED);
  232. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  233. }
  234. return "UNKNOWN";
  235. }
  236. #else
  237. static inline const char *iwl3945_get_tx_fail_reason(u32 status)
  238. {
  239. return "";
  240. }
  241. #endif
  242. /*
  243. * get ieee prev rate from rate scale table.
  244. * for A and B mode we need to overright prev
  245. * value
  246. */
  247. int iwl3945_rs_next_rate(struct iwl3945_priv *priv, int rate)
  248. {
  249. int next_rate = iwl3945_get_prev_ieee_rate(rate);
  250. switch (priv->band) {
  251. case IEEE80211_BAND_5GHZ:
  252. if (rate == IWL_RATE_12M_INDEX)
  253. next_rate = IWL_RATE_9M_INDEX;
  254. else if (rate == IWL_RATE_6M_INDEX)
  255. next_rate = IWL_RATE_6M_INDEX;
  256. break;
  257. case IEEE80211_BAND_2GHZ:
  258. if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
  259. iwl3945_is_associated(priv)) {
  260. if (rate == IWL_RATE_11M_INDEX)
  261. next_rate = IWL_RATE_5M_INDEX;
  262. }
  263. break;
  264. default:
  265. break;
  266. }
  267. return next_rate;
  268. }
  269. /**
  270. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  271. *
  272. * When FW advances 'R' index, all entries between old and new 'R' index
  273. * need to be reclaimed. As result, some free space forms. If there is
  274. * enough free space (> low mark), wake the stack that feeds us.
  275. */
  276. static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
  277. int txq_id, int index)
  278. {
  279. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  280. struct iwl3945_queue *q = &txq->q;
  281. struct iwl3945_tx_info *tx_info;
  282. BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
  283. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  284. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  285. tx_info = &txq->txb[txq->q.read_ptr];
  286. ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
  287. tx_info->skb[0] = NULL;
  288. iwl3945_hw_txq_free_tfd(priv, txq);
  289. }
  290. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  291. (txq_id != IWL_CMD_QUEUE_NUM) &&
  292. priv->mac80211_registered)
  293. ieee80211_wake_queue(priv->hw, txq_id);
  294. }
  295. /**
  296. * iwl3945_rx_reply_tx - Handle Tx response
  297. */
  298. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  299. struct iwl3945_rx_mem_buffer *rxb)
  300. {
  301. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  302. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  303. int txq_id = SEQ_TO_QUEUE(sequence);
  304. int index = SEQ_TO_INDEX(sequence);
  305. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  306. struct ieee80211_tx_info *info;
  307. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  308. u32 status = le32_to_cpu(tx_resp->status);
  309. int rate_idx;
  310. int fail;
  311. if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
  312. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  313. "is out of range [0-%d] %d %d\n", txq_id,
  314. index, txq->q.n_bd, txq->q.write_ptr,
  315. txq->q.read_ptr);
  316. return;
  317. }
  318. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
  319. ieee80211_tx_info_clear_status(info);
  320. /* Fill the MRR chain with some info about on-chip retransmissions */
  321. rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
  322. if (info->band == IEEE80211_BAND_5GHZ)
  323. rate_idx -= IWL_FIRST_OFDM_RATE;
  324. fail = tx_resp->failure_frame;
  325. info->status.rates[0].idx = rate_idx;
  326. info->status.rates[0].count = fail + 1; /* add final attempt */
  327. /* tx_status->rts_retry_count = tx_resp->failure_rts; */
  328. info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
  329. IEEE80211_TX_STAT_ACK : 0;
  330. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  331. txq_id, iwl3945_get_tx_fail_reason(status), status,
  332. tx_resp->rate, tx_resp->failure_frame);
  333. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  334. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  335. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  336. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  337. }
  338. /*****************************************************************************
  339. *
  340. * Intel PRO/Wireless 3945ABG/BG Network Connection
  341. *
  342. * RX handler implementations
  343. *
  344. *****************************************************************************/
  345. void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  346. {
  347. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  348. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  349. (int)sizeof(struct iwl3945_notif_statistics),
  350. le32_to_cpu(pkt->len));
  351. memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
  352. iwl3945_led_background(priv);
  353. priv->last_statistics_time = jiffies;
  354. }
  355. /******************************************************************************
  356. *
  357. * Misc. internal state and helper functions
  358. *
  359. ******************************************************************************/
  360. #ifdef CONFIG_IWL3945_DEBUG
  361. /**
  362. * iwl3945_report_frame - dump frame to syslog during debug sessions
  363. *
  364. * You may hack this function to show different aspects of received frames,
  365. * including selective frame dumps.
  366. * group100 parameter selects whether to show 1 out of 100 good frames.
  367. */
  368. static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
  369. struct iwl3945_rx_packet *pkt,
  370. struct ieee80211_hdr *header, int group100)
  371. {
  372. u32 to_us;
  373. u32 print_summary = 0;
  374. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  375. u32 hundred = 0;
  376. u32 dataframe = 0;
  377. __le16 fc;
  378. u16 seq_ctl;
  379. u16 channel;
  380. u16 phy_flags;
  381. u16 length;
  382. u16 status;
  383. u16 bcn_tmr;
  384. u32 tsf_low;
  385. u64 tsf;
  386. u8 rssi;
  387. u8 agc;
  388. u16 sig_avg;
  389. u16 noise_diff;
  390. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  391. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  392. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  393. u8 *data = IWL_RX_DATA(pkt);
  394. /* MAC header */
  395. fc = header->frame_control;
  396. seq_ctl = le16_to_cpu(header->seq_ctrl);
  397. /* metadata */
  398. channel = le16_to_cpu(rx_hdr->channel);
  399. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  400. length = le16_to_cpu(rx_hdr->len);
  401. /* end-of-frame status and timestamp */
  402. status = le32_to_cpu(rx_end->status);
  403. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  404. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  405. tsf = le64_to_cpu(rx_end->timestamp);
  406. /* signal statistics */
  407. rssi = rx_stats->rssi;
  408. agc = rx_stats->agc;
  409. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  410. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  411. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  412. /* if data frame is to us and all is good,
  413. * (optionally) print summary for only 1 out of every 100 */
  414. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  415. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  416. dataframe = 1;
  417. if (!group100)
  418. print_summary = 1; /* print each frame */
  419. else if (priv->framecnt_to_us < 100) {
  420. priv->framecnt_to_us++;
  421. print_summary = 0;
  422. } else {
  423. priv->framecnt_to_us = 0;
  424. print_summary = 1;
  425. hundred = 1;
  426. }
  427. } else {
  428. /* print summary for all other frames */
  429. print_summary = 1;
  430. }
  431. if (print_summary) {
  432. char *title;
  433. int rate;
  434. if (hundred)
  435. title = "100Frames";
  436. else if (ieee80211_has_retry(fc))
  437. title = "Retry";
  438. else if (ieee80211_is_assoc_resp(fc))
  439. title = "AscRsp";
  440. else if (ieee80211_is_reassoc_resp(fc))
  441. title = "RasRsp";
  442. else if (ieee80211_is_probe_resp(fc)) {
  443. title = "PrbRsp";
  444. print_dump = 1; /* dump frame contents */
  445. } else if (ieee80211_is_beacon(fc)) {
  446. title = "Beacon";
  447. print_dump = 1; /* dump frame contents */
  448. } else if (ieee80211_is_atim(fc))
  449. title = "ATIM";
  450. else if (ieee80211_is_auth(fc))
  451. title = "Auth";
  452. else if (ieee80211_is_deauth(fc))
  453. title = "DeAuth";
  454. else if (ieee80211_is_disassoc(fc))
  455. title = "DisAssoc";
  456. else
  457. title = "Frame";
  458. rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
  459. if (rate == -1)
  460. rate = 0;
  461. else
  462. rate = iwl3945_rates[rate].ieee / 2;
  463. /* print frame summary.
  464. * MAC addresses show just the last byte (for brevity),
  465. * but you can hack it to show more, if you'd like to. */
  466. if (dataframe)
  467. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  468. "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
  469. title, le16_to_cpu(fc), header->addr1[5],
  470. length, rssi, channel, rate);
  471. else {
  472. /* src/dst addresses assume managed mode */
  473. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  474. "src=0x%02x, rssi=%u, tim=%lu usec, "
  475. "phy=0x%02x, chnl=%d\n",
  476. title, le16_to_cpu(fc), header->addr1[5],
  477. header->addr3[5], rssi,
  478. tsf_low - priv->scan_start_tsf,
  479. phy_flags, channel);
  480. }
  481. }
  482. if (print_dump)
  483. iwl3945_print_hex_dump(IWL_DL_RX, data, length);
  484. }
  485. #else
  486. static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
  487. struct iwl3945_rx_packet *pkt,
  488. struct ieee80211_hdr *header, int group100)
  489. {
  490. }
  491. #endif
  492. /* This is necessary only for a number of statistics, see the caller. */
  493. static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
  494. struct ieee80211_hdr *header)
  495. {
  496. /* Filter incoming packets to determine if they are targeted toward
  497. * this network, discarding packets coming from ourselves */
  498. switch (priv->iw_mode) {
  499. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  500. /* packets to our IBSS update information */
  501. return !compare_ether_addr(header->addr3, priv->bssid);
  502. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  503. /* packets to our IBSS update information */
  504. return !compare_ether_addr(header->addr2, priv->bssid);
  505. default:
  506. return 1;
  507. }
  508. }
  509. static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
  510. struct iwl3945_rx_mem_buffer *rxb,
  511. struct ieee80211_rx_status *stats)
  512. {
  513. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  514. #ifdef CONFIG_IWL3945_LEDS
  515. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
  516. #endif
  517. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  518. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  519. short len = le16_to_cpu(rx_hdr->len);
  520. /* We received data from the HW, so stop the watchdog */
  521. if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
  522. IWL_DEBUG_DROP("Corruption detected!\n");
  523. return;
  524. }
  525. /* We only process data packets if the interface is open */
  526. if (unlikely(!priv->is_open)) {
  527. IWL_DEBUG_DROP_LIMIT
  528. ("Dropping packet while interface is not open.\n");
  529. return;
  530. }
  531. skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
  532. /* Set the size of the skb to the size of the frame */
  533. skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
  534. if (iwl3945_param_hwcrypto)
  535. iwl3945_set_decrypted_flag(priv, rxb->skb,
  536. le32_to_cpu(rx_end->status), stats);
  537. #ifdef CONFIG_IWL3945_LEDS
  538. if (ieee80211_is_data(hdr->frame_control))
  539. priv->rxtxpackets += len;
  540. #endif
  541. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  542. rxb->skb = NULL;
  543. }
  544. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  545. static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
  546. struct iwl3945_rx_mem_buffer *rxb)
  547. {
  548. struct ieee80211_hdr *header;
  549. struct ieee80211_rx_status rx_status;
  550. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  551. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  552. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  553. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  554. int snr;
  555. u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
  556. u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
  557. u8 network_packet;
  558. rx_status.flag = 0;
  559. rx_status.mactime = le64_to_cpu(rx_end->timestamp);
  560. rx_status.freq =
  561. ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
  562. rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  563. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  564. rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
  565. if (rx_status.band == IEEE80211_BAND_5GHZ)
  566. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  567. rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
  568. RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  569. /* set the preamble flag if appropriate */
  570. if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  571. rx_status.flag |= RX_FLAG_SHORTPRE;
  572. if ((unlikely(rx_stats->phy_count > 20))) {
  573. IWL_DEBUG_DROP
  574. ("dsp size out of range [0,20]: "
  575. "%d/n", rx_stats->phy_count);
  576. return;
  577. }
  578. if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
  579. || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  580. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
  581. return;
  582. }
  583. /* Convert 3945's rssi indicator to dBm */
  584. rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
  585. /* Set default noise value to -127 */
  586. if (priv->last_rx_noise == 0)
  587. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  588. /* 3945 provides noise info for OFDM frames only.
  589. * sig_avg and noise_diff are measured by the 3945's digital signal
  590. * processor (DSP), and indicate linear levels of signal level and
  591. * distortion/noise within the packet preamble after
  592. * automatic gain control (AGC). sig_avg should stay fairly
  593. * constant if the radio's AGC is working well.
  594. * Since these values are linear (not dB or dBm), linear
  595. * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
  596. * Convert linear SNR to dB SNR, then subtract that from rssi dBm
  597. * to obtain noise level in dBm.
  598. * Calculate rx_status.signal (quality indicator in %) based on SNR. */
  599. if (rx_stats_noise_diff) {
  600. snr = rx_stats_sig_avg / rx_stats_noise_diff;
  601. rx_status.noise = rx_status.signal -
  602. iwl3945_calc_db_from_ratio(snr);
  603. rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
  604. rx_status.noise);
  605. /* If noise info not available, calculate signal quality indicator (%)
  606. * using just the dBm signal level. */
  607. } else {
  608. rx_status.noise = priv->last_rx_noise;
  609. rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
  610. }
  611. IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
  612. rx_status.signal, rx_status.noise, rx_status.qual,
  613. rx_stats_sig_avg, rx_stats_noise_diff);
  614. header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
  615. network_packet = iwl3945_is_network_packet(priv, header);
  616. IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
  617. network_packet ? '*' : ' ',
  618. le16_to_cpu(rx_hdr->channel),
  619. rx_status.signal, rx_status.signal,
  620. rx_status.noise, rx_status.rate_idx);
  621. #ifdef CONFIG_IWL3945_DEBUG
  622. if (iwl3945_debug_level & (IWL_DL_RX))
  623. /* Set "1" to report good data frames in groups of 100 */
  624. iwl3945_dbg_report_frame(priv, pkt, header, 1);
  625. #endif
  626. if (network_packet) {
  627. priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
  628. priv->last_tsf = le64_to_cpu(rx_end->timestamp);
  629. priv->last_rx_rssi = rx_status.signal;
  630. priv->last_rx_noise = rx_status.noise;
  631. }
  632. iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
  633. }
  634. int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
  635. dma_addr_t addr, u16 len)
  636. {
  637. int count;
  638. u32 pad;
  639. struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
  640. count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
  641. pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
  642. if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
  643. IWL_ERROR("Error can not send more than %d chunks\n",
  644. NUM_TFD_CHUNKS);
  645. return -EINVAL;
  646. }
  647. tfd->pa[count].addr = cpu_to_le32(addr);
  648. tfd->pa[count].len = cpu_to_le32(len);
  649. count++;
  650. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
  651. TFD_CTL_PAD_SET(pad));
  652. return 0;
  653. }
  654. /**
  655. * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
  656. *
  657. * Does NOT advance any indexes
  658. */
  659. int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  660. {
  661. struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
  662. struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
  663. struct pci_dev *dev = priv->pci_dev;
  664. int i;
  665. int counter;
  666. /* classify bd */
  667. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  668. /* nothing to cleanup after for host commands */
  669. return 0;
  670. /* sanity check */
  671. counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
  672. if (counter > NUM_TFD_CHUNKS) {
  673. IWL_ERROR("Too many chunks: %i\n", counter);
  674. /* @todo issue fatal error, it is quite serious situation */
  675. return 0;
  676. }
  677. /* unmap chunks if any */
  678. for (i = 1; i < counter; i++) {
  679. pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
  680. le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
  681. if (txq->txb[txq->q.read_ptr].skb[0]) {
  682. struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
  683. if (txq->txb[txq->q.read_ptr].skb[0]) {
  684. /* Can be called from interrupt context */
  685. dev_kfree_skb_any(skb);
  686. txq->txb[txq->q.read_ptr].skb[0] = NULL;
  687. }
  688. }
  689. }
  690. return 0;
  691. }
  692. u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
  693. {
  694. int i, start = IWL_AP_ID;
  695. int ret = IWL_INVALID_STATION;
  696. unsigned long flags;
  697. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
  698. (priv->iw_mode == NL80211_IFTYPE_AP))
  699. start = IWL_STA_ID;
  700. if (is_broadcast_ether_addr(addr))
  701. return priv->hw_setting.bcast_sta_id;
  702. spin_lock_irqsave(&priv->sta_lock, flags);
  703. for (i = start; i < priv->hw_setting.max_stations; i++)
  704. if ((priv->stations[i].used) &&
  705. (!compare_ether_addr
  706. (priv->stations[i].sta.sta.addr, addr))) {
  707. ret = i;
  708. goto out;
  709. }
  710. IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
  711. addr, priv->num_stations);
  712. out:
  713. spin_unlock_irqrestore(&priv->sta_lock, flags);
  714. return ret;
  715. }
  716. /**
  717. * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
  718. *
  719. */
  720. void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
  721. struct iwl3945_cmd *cmd,
  722. struct ieee80211_tx_info *info,
  723. struct ieee80211_hdr *hdr, int sta_id, int tx_id)
  724. {
  725. unsigned long flags;
  726. u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
  727. u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
  728. u16 rate_mask;
  729. int rate;
  730. u8 rts_retry_limit;
  731. u8 data_retry_limit;
  732. __le32 tx_flags;
  733. __le16 fc = hdr->frame_control;
  734. rate = iwl3945_rates[rate_index].plcp;
  735. tx_flags = cmd->cmd.tx.tx_flags;
  736. /* We need to figure out how to get the sta->supp_rates while
  737. * in this running context */
  738. rate_mask = IWL_RATES_MASK;
  739. spin_lock_irqsave(&priv->sta_lock, flags);
  740. priv->stations[sta_id].current_rate.rate_n_flags = rate;
  741. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  742. (sta_id != priv->hw_setting.bcast_sta_id) &&
  743. (sta_id != IWL_MULTICAST_ID))
  744. priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
  745. spin_unlock_irqrestore(&priv->sta_lock, flags);
  746. if (tx_id >= IWL_CMD_QUEUE_NUM)
  747. rts_retry_limit = 3;
  748. else
  749. rts_retry_limit = 7;
  750. if (ieee80211_is_probe_resp(fc)) {
  751. data_retry_limit = 3;
  752. if (data_retry_limit < rts_retry_limit)
  753. rts_retry_limit = data_retry_limit;
  754. } else
  755. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  756. if (priv->data_retry_limit != -1)
  757. data_retry_limit = priv->data_retry_limit;
  758. if (ieee80211_is_mgmt(fc)) {
  759. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  760. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  761. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  762. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  763. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  764. if (tx_flags & TX_CMD_FLG_RTS_MSK) {
  765. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  766. tx_flags |= TX_CMD_FLG_CTS_MSK;
  767. }
  768. break;
  769. default:
  770. break;
  771. }
  772. }
  773. cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
  774. cmd->cmd.tx.data_retry_limit = data_retry_limit;
  775. cmd->cmd.tx.rate = rate;
  776. cmd->cmd.tx.tx_flags = tx_flags;
  777. /* OFDM */
  778. cmd->cmd.tx.supp_rates[0] =
  779. ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
  780. /* CCK */
  781. cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
  782. IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
  783. "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
  784. cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
  785. cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
  786. }
  787. u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
  788. {
  789. unsigned long flags_spin;
  790. struct iwl3945_station_entry *station;
  791. if (sta_id == IWL_INVALID_STATION)
  792. return IWL_INVALID_STATION;
  793. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  794. station = &priv->stations[sta_id];
  795. station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
  796. station->sta.rate_n_flags = cpu_to_le16(tx_rate);
  797. station->current_rate.rate_n_flags = tx_rate;
  798. station->sta.mode = STA_CONTROL_MODIFY_MSK;
  799. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  800. iwl3945_send_add_station(priv, &station->sta, flags);
  801. IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
  802. sta_id, tx_rate);
  803. return sta_id;
  804. }
  805. static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
  806. {
  807. int rc;
  808. unsigned long flags;
  809. spin_lock_irqsave(&priv->lock, flags);
  810. rc = iwl3945_grab_nic_access(priv);
  811. if (rc) {
  812. spin_unlock_irqrestore(&priv->lock, flags);
  813. return rc;
  814. }
  815. if (!pwr_max) {
  816. u32 val;
  817. rc = pci_read_config_dword(priv->pci_dev,
  818. PCI_POWER_SOURCE, &val);
  819. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  820. iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  821. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  822. ~APMG_PS_CTRL_MSK_PWR_SRC);
  823. iwl3945_release_nic_access(priv);
  824. iwl3945_poll_bit(priv, CSR_GPIO_IN,
  825. CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
  826. CSR_GPIO_IN_BIT_AUX_POWER, 5000);
  827. } else
  828. iwl3945_release_nic_access(priv);
  829. } else {
  830. iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  831. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  832. ~APMG_PS_CTRL_MSK_PWR_SRC);
  833. iwl3945_release_nic_access(priv);
  834. iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
  835. CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
  836. }
  837. spin_unlock_irqrestore(&priv->lock, flags);
  838. return rc;
  839. }
  840. static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  841. {
  842. int rc;
  843. unsigned long flags;
  844. spin_lock_irqsave(&priv->lock, flags);
  845. rc = iwl3945_grab_nic_access(priv);
  846. if (rc) {
  847. spin_unlock_irqrestore(&priv->lock, flags);
  848. return rc;
  849. }
  850. iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
  851. iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
  852. priv->hw_setting.shared_phys +
  853. offsetof(struct iwl3945_shared, rx_read_ptr[0]));
  854. iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
  855. iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
  856. ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
  857. ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
  858. ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
  859. ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
  860. (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
  861. ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
  862. (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
  863. ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
  864. /* fake read to flush all prev I/O */
  865. iwl3945_read_direct32(priv, FH_RSSR_CTRL);
  866. iwl3945_release_nic_access(priv);
  867. spin_unlock_irqrestore(&priv->lock, flags);
  868. return 0;
  869. }
  870. static int iwl3945_tx_reset(struct iwl3945_priv *priv)
  871. {
  872. int rc;
  873. unsigned long flags;
  874. spin_lock_irqsave(&priv->lock, flags);
  875. rc = iwl3945_grab_nic_access(priv);
  876. if (rc) {
  877. spin_unlock_irqrestore(&priv->lock, flags);
  878. return rc;
  879. }
  880. /* bypass mode */
  881. iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
  882. /* RA 0 is active */
  883. iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
  884. /* all 6 fifo are active */
  885. iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
  886. iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
  887. iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
  888. iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
  889. iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
  890. iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
  891. priv->hw_setting.shared_phys);
  892. iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
  893. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
  894. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
  895. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
  896. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
  897. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
  898. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
  899. ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
  900. iwl3945_release_nic_access(priv);
  901. spin_unlock_irqrestore(&priv->lock, flags);
  902. return 0;
  903. }
  904. /**
  905. * iwl3945_txq_ctx_reset - Reset TX queue context
  906. *
  907. * Destroys all DMA structures and initialize them again
  908. */
  909. static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
  910. {
  911. int rc;
  912. int txq_id, slots_num;
  913. iwl3945_hw_txq_ctx_free(priv);
  914. /* Tx CMD queue */
  915. rc = iwl3945_tx_reset(priv);
  916. if (rc)
  917. goto error;
  918. /* Tx queue(s) */
  919. for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
  920. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  921. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  922. rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  923. txq_id);
  924. if (rc) {
  925. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  926. goto error;
  927. }
  928. }
  929. return rc;
  930. error:
  931. iwl3945_hw_txq_ctx_free(priv);
  932. return rc;
  933. }
  934. int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
  935. {
  936. u8 rev_id;
  937. int rc;
  938. unsigned long flags;
  939. struct iwl3945_rx_queue *rxq = &priv->rxq;
  940. iwl3945_power_init_handle(priv);
  941. spin_lock_irqsave(&priv->lock, flags);
  942. iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
  943. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  944. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  945. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  946. rc = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
  947. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  948. if (rc < 0) {
  949. spin_unlock_irqrestore(&priv->lock, flags);
  950. IWL_DEBUG_INFO("Failed to init the card\n");
  951. return rc;
  952. }
  953. rc = iwl3945_grab_nic_access(priv);
  954. if (rc) {
  955. spin_unlock_irqrestore(&priv->lock, flags);
  956. return rc;
  957. }
  958. iwl3945_write_prph(priv, APMG_CLK_EN_REG,
  959. APMG_CLK_VAL_DMA_CLK_RQT |
  960. APMG_CLK_VAL_BSM_CLK_RQT);
  961. udelay(20);
  962. iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  963. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  964. iwl3945_release_nic_access(priv);
  965. spin_unlock_irqrestore(&priv->lock, flags);
  966. /* Determine HW type */
  967. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  968. if (rc)
  969. return rc;
  970. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  971. iwl3945_nic_set_pwr_src(priv, 1);
  972. spin_lock_irqsave(&priv->lock, flags);
  973. if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
  974. IWL_DEBUG_INFO("RTP type \n");
  975. else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
  976. IWL_DEBUG_INFO("3945 RADIO-MB type\n");
  977. iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  978. CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
  979. } else {
  980. IWL_DEBUG_INFO("3945 RADIO-MM type\n");
  981. iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  982. CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
  983. }
  984. if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
  985. IWL_DEBUG_INFO("SKU OP mode is mrc\n");
  986. iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  987. CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
  988. } else
  989. IWL_DEBUG_INFO("SKU OP mode is basic\n");
  990. if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
  991. IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
  992. priv->eeprom.board_revision);
  993. iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  994. CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
  995. } else {
  996. IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
  997. priv->eeprom.board_revision);
  998. iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
  999. CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
  1000. }
  1001. if (priv->eeprom.almgor_m_version <= 1) {
  1002. iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1003. CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
  1004. IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
  1005. priv->eeprom.almgor_m_version);
  1006. } else {
  1007. IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
  1008. priv->eeprom.almgor_m_version);
  1009. iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1010. CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
  1011. }
  1012. spin_unlock_irqrestore(&priv->lock, flags);
  1013. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  1014. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  1015. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  1016. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  1017. /* Allocate the RX queue, or reset if it is already allocated */
  1018. if (!rxq->bd) {
  1019. rc = iwl3945_rx_queue_alloc(priv);
  1020. if (rc) {
  1021. IWL_ERROR("Unable to initialize Rx queue\n");
  1022. return -ENOMEM;
  1023. }
  1024. } else
  1025. iwl3945_rx_queue_reset(priv, rxq);
  1026. iwl3945_rx_replenish(priv);
  1027. iwl3945_rx_init(priv, rxq);
  1028. spin_lock_irqsave(&priv->lock, flags);
  1029. /* Look at using this instead:
  1030. rxq->need_update = 1;
  1031. iwl3945_rx_queue_update_write_ptr(priv, rxq);
  1032. */
  1033. rc = iwl3945_grab_nic_access(priv);
  1034. if (rc) {
  1035. spin_unlock_irqrestore(&priv->lock, flags);
  1036. return rc;
  1037. }
  1038. iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
  1039. iwl3945_release_nic_access(priv);
  1040. spin_unlock_irqrestore(&priv->lock, flags);
  1041. rc = iwl3945_txq_ctx_reset(priv);
  1042. if (rc)
  1043. return rc;
  1044. set_bit(STATUS_INIT, &priv->status);
  1045. return 0;
  1046. }
  1047. /**
  1048. * iwl3945_hw_txq_ctx_free - Free TXQ Context
  1049. *
  1050. * Destroy all TX DMA queues and structures
  1051. */
  1052. void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
  1053. {
  1054. int txq_id;
  1055. /* Tx queues */
  1056. for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
  1057. iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
  1058. }
  1059. void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
  1060. {
  1061. int queue;
  1062. unsigned long flags;
  1063. spin_lock_irqsave(&priv->lock, flags);
  1064. if (iwl3945_grab_nic_access(priv)) {
  1065. spin_unlock_irqrestore(&priv->lock, flags);
  1066. iwl3945_hw_txq_ctx_free(priv);
  1067. return;
  1068. }
  1069. /* stop SCD */
  1070. iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
  1071. /* reset TFD queues */
  1072. for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
  1073. iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
  1074. iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
  1075. ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
  1076. 1000);
  1077. }
  1078. iwl3945_release_nic_access(priv);
  1079. spin_unlock_irqrestore(&priv->lock, flags);
  1080. iwl3945_hw_txq_ctx_free(priv);
  1081. }
  1082. int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
  1083. {
  1084. int rc = 0;
  1085. u32 reg_val;
  1086. unsigned long flags;
  1087. spin_lock_irqsave(&priv->lock, flags);
  1088. /* set stop master bit */
  1089. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  1090. reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
  1091. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  1092. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  1093. IWL_DEBUG_INFO("Card in power save, master is already "
  1094. "stopped\n");
  1095. else {
  1096. rc = iwl3945_poll_direct_bit(priv, CSR_RESET,
  1097. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  1098. if (rc < 0) {
  1099. spin_unlock_irqrestore(&priv->lock, flags);
  1100. return rc;
  1101. }
  1102. }
  1103. spin_unlock_irqrestore(&priv->lock, flags);
  1104. IWL_DEBUG_INFO("stop master\n");
  1105. return rc;
  1106. }
  1107. int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
  1108. {
  1109. int rc;
  1110. unsigned long flags;
  1111. iwl3945_hw_nic_stop_master(priv);
  1112. spin_lock_irqsave(&priv->lock, flags);
  1113. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  1114. iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
  1115. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  1116. rc = iwl3945_grab_nic_access(priv);
  1117. if (!rc) {
  1118. iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
  1119. APMG_CLK_VAL_BSM_CLK_RQT);
  1120. udelay(10);
  1121. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  1122. CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1123. iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
  1124. iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
  1125. 0xFFFFFFFF);
  1126. /* enable DMA */
  1127. iwl3945_write_prph(priv, APMG_CLK_EN_REG,
  1128. APMG_CLK_VAL_DMA_CLK_RQT |
  1129. APMG_CLK_VAL_BSM_CLK_RQT);
  1130. udelay(10);
  1131. iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
  1132. APMG_PS_CTRL_VAL_RESET_REQ);
  1133. udelay(5);
  1134. iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
  1135. APMG_PS_CTRL_VAL_RESET_REQ);
  1136. iwl3945_release_nic_access(priv);
  1137. }
  1138. /* Clear the 'host command active' bit... */
  1139. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1140. wake_up_interruptible(&priv->wait_command_queue);
  1141. spin_unlock_irqrestore(&priv->lock, flags);
  1142. return rc;
  1143. }
  1144. /**
  1145. * iwl3945_hw_reg_adjust_power_by_temp
  1146. * return index delta into power gain settings table
  1147. */
  1148. static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
  1149. {
  1150. return (new_reading - old_reading) * (-11) / 100;
  1151. }
  1152. /**
  1153. * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
  1154. */
  1155. static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
  1156. {
  1157. return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
  1158. }
  1159. int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
  1160. {
  1161. return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
  1162. }
  1163. /**
  1164. * iwl3945_hw_reg_txpower_get_temperature
  1165. * get the current temperature by reading from NIC
  1166. */
  1167. static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
  1168. {
  1169. int temperature;
  1170. temperature = iwl3945_hw_get_temperature(priv);
  1171. /* driver's okay range is -260 to +25.
  1172. * human readable okay range is 0 to +285 */
  1173. IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
  1174. /* handle insane temp reading */
  1175. if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
  1176. IWL_ERROR("Error bad temperature value %d\n", temperature);
  1177. /* if really really hot(?),
  1178. * substitute the 3rd band/group's temp measured at factory */
  1179. if (priv->last_temperature > 100)
  1180. temperature = priv->eeprom.groups[2].temperature;
  1181. else /* else use most recent "sane" value from driver */
  1182. temperature = priv->last_temperature;
  1183. }
  1184. return temperature; /* raw, not "human readable" */
  1185. }
  1186. /* Adjust Txpower only if temperature variance is greater than threshold.
  1187. *
  1188. * Both are lower than older versions' 9 degrees */
  1189. #define IWL_TEMPERATURE_LIMIT_TIMER 6
  1190. /**
  1191. * is_temp_calib_needed - determines if new calibration is needed
  1192. *
  1193. * records new temperature in tx_mgr->temperature.
  1194. * replaces tx_mgr->last_temperature *only* if calib needed
  1195. * (assumes caller will actually do the calibration!). */
  1196. static int is_temp_calib_needed(struct iwl3945_priv *priv)
  1197. {
  1198. int temp_diff;
  1199. priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
  1200. temp_diff = priv->temperature - priv->last_temperature;
  1201. /* get absolute value */
  1202. if (temp_diff < 0) {
  1203. IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
  1204. temp_diff = -temp_diff;
  1205. } else if (temp_diff == 0)
  1206. IWL_DEBUG_POWER("Same temp,\n");
  1207. else
  1208. IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
  1209. /* if we don't need calibration, *don't* update last_temperature */
  1210. if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
  1211. IWL_DEBUG_POWER("Timed thermal calib not needed\n");
  1212. return 0;
  1213. }
  1214. IWL_DEBUG_POWER("Timed thermal calib needed\n");
  1215. /* assume that caller will actually do calib ...
  1216. * update the "last temperature" value */
  1217. priv->last_temperature = priv->temperature;
  1218. return 1;
  1219. }
  1220. #define IWL_MAX_GAIN_ENTRIES 78
  1221. #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
  1222. #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
  1223. /* radio and DSP power table, each step is 1/2 dB.
  1224. * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
  1225. static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
  1226. {
  1227. {251, 127}, /* 2.4 GHz, highest power */
  1228. {251, 127},
  1229. {251, 127},
  1230. {251, 127},
  1231. {251, 125},
  1232. {251, 110},
  1233. {251, 105},
  1234. {251, 98},
  1235. {187, 125},
  1236. {187, 115},
  1237. {187, 108},
  1238. {187, 99},
  1239. {243, 119},
  1240. {243, 111},
  1241. {243, 105},
  1242. {243, 97},
  1243. {243, 92},
  1244. {211, 106},
  1245. {211, 100},
  1246. {179, 120},
  1247. {179, 113},
  1248. {179, 107},
  1249. {147, 125},
  1250. {147, 119},
  1251. {147, 112},
  1252. {147, 106},
  1253. {147, 101},
  1254. {147, 97},
  1255. {147, 91},
  1256. {115, 107},
  1257. {235, 121},
  1258. {235, 115},
  1259. {235, 109},
  1260. {203, 127},
  1261. {203, 121},
  1262. {203, 115},
  1263. {203, 108},
  1264. {203, 102},
  1265. {203, 96},
  1266. {203, 92},
  1267. {171, 110},
  1268. {171, 104},
  1269. {171, 98},
  1270. {139, 116},
  1271. {227, 125},
  1272. {227, 119},
  1273. {227, 113},
  1274. {227, 107},
  1275. {227, 101},
  1276. {227, 96},
  1277. {195, 113},
  1278. {195, 106},
  1279. {195, 102},
  1280. {195, 95},
  1281. {163, 113},
  1282. {163, 106},
  1283. {163, 102},
  1284. {163, 95},
  1285. {131, 113},
  1286. {131, 106},
  1287. {131, 102},
  1288. {131, 95},
  1289. {99, 113},
  1290. {99, 106},
  1291. {99, 102},
  1292. {99, 95},
  1293. {67, 113},
  1294. {67, 106},
  1295. {67, 102},
  1296. {67, 95},
  1297. {35, 113},
  1298. {35, 106},
  1299. {35, 102},
  1300. {35, 95},
  1301. {3, 113},
  1302. {3, 106},
  1303. {3, 102},
  1304. {3, 95} }, /* 2.4 GHz, lowest power */
  1305. {
  1306. {251, 127}, /* 5.x GHz, highest power */
  1307. {251, 120},
  1308. {251, 114},
  1309. {219, 119},
  1310. {219, 101},
  1311. {187, 113},
  1312. {187, 102},
  1313. {155, 114},
  1314. {155, 103},
  1315. {123, 117},
  1316. {123, 107},
  1317. {123, 99},
  1318. {123, 92},
  1319. {91, 108},
  1320. {59, 125},
  1321. {59, 118},
  1322. {59, 109},
  1323. {59, 102},
  1324. {59, 96},
  1325. {59, 90},
  1326. {27, 104},
  1327. {27, 98},
  1328. {27, 92},
  1329. {115, 118},
  1330. {115, 111},
  1331. {115, 104},
  1332. {83, 126},
  1333. {83, 121},
  1334. {83, 113},
  1335. {83, 105},
  1336. {83, 99},
  1337. {51, 118},
  1338. {51, 111},
  1339. {51, 104},
  1340. {51, 98},
  1341. {19, 116},
  1342. {19, 109},
  1343. {19, 102},
  1344. {19, 98},
  1345. {19, 93},
  1346. {171, 113},
  1347. {171, 107},
  1348. {171, 99},
  1349. {139, 120},
  1350. {139, 113},
  1351. {139, 107},
  1352. {139, 99},
  1353. {107, 120},
  1354. {107, 113},
  1355. {107, 107},
  1356. {107, 99},
  1357. {75, 120},
  1358. {75, 113},
  1359. {75, 107},
  1360. {75, 99},
  1361. {43, 120},
  1362. {43, 113},
  1363. {43, 107},
  1364. {43, 99},
  1365. {11, 120},
  1366. {11, 113},
  1367. {11, 107},
  1368. {11, 99},
  1369. {131, 107},
  1370. {131, 99},
  1371. {99, 120},
  1372. {99, 113},
  1373. {99, 107},
  1374. {99, 99},
  1375. {67, 120},
  1376. {67, 113},
  1377. {67, 107},
  1378. {67, 99},
  1379. {35, 120},
  1380. {35, 113},
  1381. {35, 107},
  1382. {35, 99},
  1383. {3, 120} } /* 5.x GHz, lowest power */
  1384. };
  1385. static inline u8 iwl3945_hw_reg_fix_power_index(int index)
  1386. {
  1387. if (index < 0)
  1388. return 0;
  1389. if (index >= IWL_MAX_GAIN_ENTRIES)
  1390. return IWL_MAX_GAIN_ENTRIES - 1;
  1391. return (u8) index;
  1392. }
  1393. /* Kick off thermal recalibration check every 60 seconds */
  1394. #define REG_RECALIB_PERIOD (60)
  1395. /**
  1396. * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
  1397. *
  1398. * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
  1399. * or 6 Mbit (OFDM) rates.
  1400. */
  1401. static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
  1402. s32 rate_index, const s8 *clip_pwrs,
  1403. struct iwl3945_channel_info *ch_info,
  1404. int band_index)
  1405. {
  1406. struct iwl3945_scan_power_info *scan_power_info;
  1407. s8 power;
  1408. u8 power_index;
  1409. scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
  1410. /* use this channel group's 6Mbit clipping/saturation pwr,
  1411. * but cap at regulatory scan power restriction (set during init
  1412. * based on eeprom channel data) for this channel. */
  1413. power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
  1414. /* further limit to user's max power preference.
  1415. * FIXME: Other spectrum management power limitations do not
  1416. * seem to apply?? */
  1417. power = min(power, priv->user_txpower_limit);
  1418. scan_power_info->requested_power = power;
  1419. /* find difference between new scan *power* and current "normal"
  1420. * Tx *power* for 6Mb. Use this difference (x2) to adjust the
  1421. * current "normal" temperature-compensated Tx power *index* for
  1422. * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
  1423. * *index*. */
  1424. power_index = ch_info->power_info[rate_index].power_table_index
  1425. - (power - ch_info->power_info
  1426. [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
  1427. /* store reference index that we use when adjusting *all* scan
  1428. * powers. So we can accommodate user (all channel) or spectrum
  1429. * management (single channel) power changes "between" temperature
  1430. * feedback compensation procedures.
  1431. * don't force fit this reference index into gain table; it may be a
  1432. * negative number. This will help avoid errors when we're at
  1433. * the lower bounds (highest gains, for warmest temperatures)
  1434. * of the table. */
  1435. /* don't exceed table bounds for "real" setting */
  1436. power_index = iwl3945_hw_reg_fix_power_index(power_index);
  1437. scan_power_info->power_table_index = power_index;
  1438. scan_power_info->tpc.tx_gain =
  1439. power_gain_table[band_index][power_index].tx_gain;
  1440. scan_power_info->tpc.dsp_atten =
  1441. power_gain_table[band_index][power_index].dsp_atten;
  1442. }
  1443. /**
  1444. * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
  1445. *
  1446. * Configures power settings for all rates for the current channel,
  1447. * using values from channel info struct, and send to NIC
  1448. */
  1449. int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
  1450. {
  1451. int rate_idx, i;
  1452. const struct iwl3945_channel_info *ch_info = NULL;
  1453. struct iwl3945_txpowertable_cmd txpower = {
  1454. .channel = priv->active_rxon.channel,
  1455. };
  1456. txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
  1457. ch_info = iwl3945_get_channel_info(priv,
  1458. priv->band,
  1459. le16_to_cpu(priv->active_rxon.channel));
  1460. if (!ch_info) {
  1461. IWL_ERROR
  1462. ("Failed to get channel info for channel %d [%d]\n",
  1463. le16_to_cpu(priv->active_rxon.channel), priv->band);
  1464. return -EINVAL;
  1465. }
  1466. if (!is_channel_valid(ch_info)) {
  1467. IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
  1468. "non-Tx channel.\n");
  1469. return 0;
  1470. }
  1471. /* fill cmd with power settings for all rates for current channel */
  1472. /* Fill OFDM rate */
  1473. for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
  1474. rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
  1475. txpower.power[i].tpc = ch_info->power_info[i].tpc;
  1476. txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
  1477. IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
  1478. le16_to_cpu(txpower.channel),
  1479. txpower.band,
  1480. txpower.power[i].tpc.tx_gain,
  1481. txpower.power[i].tpc.dsp_atten,
  1482. txpower.power[i].rate);
  1483. }
  1484. /* Fill CCK rates */
  1485. for (rate_idx = IWL_FIRST_CCK_RATE;
  1486. rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
  1487. txpower.power[i].tpc = ch_info->power_info[i].tpc;
  1488. txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
  1489. IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
  1490. le16_to_cpu(txpower.channel),
  1491. txpower.band,
  1492. txpower.power[i].tpc.tx_gain,
  1493. txpower.power[i].tpc.dsp_atten,
  1494. txpower.power[i].rate);
  1495. }
  1496. return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
  1497. sizeof(struct iwl3945_txpowertable_cmd), &txpower);
  1498. }
  1499. /**
  1500. * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
  1501. * @ch_info: Channel to update. Uses power_info.requested_power.
  1502. *
  1503. * Replace requested_power and base_power_index ch_info fields for
  1504. * one channel.
  1505. *
  1506. * Called if user or spectrum management changes power preferences.
  1507. * Takes into account h/w and modulation limitations (clip power).
  1508. *
  1509. * This does *not* send anything to NIC, just sets up ch_info for one channel.
  1510. *
  1511. * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
  1512. * properly fill out the scan powers, and actual h/w gain settings,
  1513. * and send changes to NIC
  1514. */
  1515. static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
  1516. struct iwl3945_channel_info *ch_info)
  1517. {
  1518. struct iwl3945_channel_power_info *power_info;
  1519. int power_changed = 0;
  1520. int i;
  1521. const s8 *clip_pwrs;
  1522. int power;
  1523. /* Get this chnlgrp's rate-to-max/clip-powers table */
  1524. clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
  1525. /* Get this channel's rate-to-current-power settings table */
  1526. power_info = ch_info->power_info;
  1527. /* update OFDM Txpower settings */
  1528. for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
  1529. i++, ++power_info) {
  1530. int delta_idx;
  1531. /* limit new power to be no more than h/w capability */
  1532. power = min(ch_info->curr_txpow, clip_pwrs[i]);
  1533. if (power == power_info->requested_power)
  1534. continue;
  1535. /* find difference between old and new requested powers,
  1536. * update base (non-temp-compensated) power index */
  1537. delta_idx = (power - power_info->requested_power) * 2;
  1538. power_info->base_power_index -= delta_idx;
  1539. /* save new requested power value */
  1540. power_info->requested_power = power;
  1541. power_changed = 1;
  1542. }
  1543. /* update CCK Txpower settings, based on OFDM 12M setting ...
  1544. * ... all CCK power settings for a given channel are the *same*. */
  1545. if (power_changed) {
  1546. power =
  1547. ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
  1548. requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
  1549. /* do all CCK rates' iwl3945_channel_power_info structures */
  1550. for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
  1551. power_info->requested_power = power;
  1552. power_info->base_power_index =
  1553. ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
  1554. base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
  1555. ++power_info;
  1556. }
  1557. }
  1558. return 0;
  1559. }
  1560. /**
  1561. * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
  1562. *
  1563. * NOTE: Returned power limit may be less (but not more) than requested,
  1564. * based strictly on regulatory (eeprom and spectrum mgt) limitations
  1565. * (no consideration for h/w clipping limitations).
  1566. */
  1567. static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
  1568. {
  1569. s8 max_power;
  1570. #if 0
  1571. /* if we're using TGd limits, use lower of TGd or EEPROM */
  1572. if (ch_info->tgd_data.max_power != 0)
  1573. max_power = min(ch_info->tgd_data.max_power,
  1574. ch_info->eeprom.max_power_avg);
  1575. /* else just use EEPROM limits */
  1576. else
  1577. #endif
  1578. max_power = ch_info->eeprom.max_power_avg;
  1579. return min(max_power, ch_info->max_power_avg);
  1580. }
  1581. /**
  1582. * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
  1583. *
  1584. * Compensate txpower settings of *all* channels for temperature.
  1585. * This only accounts for the difference between current temperature
  1586. * and the factory calibration temperatures, and bases the new settings
  1587. * on the channel's base_power_index.
  1588. *
  1589. * If RxOn is "associated", this sends the new Txpower to NIC!
  1590. */
  1591. static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
  1592. {
  1593. struct iwl3945_channel_info *ch_info = NULL;
  1594. int delta_index;
  1595. const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
  1596. u8 a_band;
  1597. u8 rate_index;
  1598. u8 scan_tbl_index;
  1599. u8 i;
  1600. int ref_temp;
  1601. int temperature = priv->temperature;
  1602. /* set up new Tx power info for each and every channel, 2.4 and 5.x */
  1603. for (i = 0; i < priv->channel_count; i++) {
  1604. ch_info = &priv->channel_info[i];
  1605. a_band = is_channel_a_band(ch_info);
  1606. /* Get this chnlgrp's factory calibration temperature */
  1607. ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
  1608. temperature;
  1609. /* get power index adjustment based on current and factory
  1610. * temps */
  1611. delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
  1612. ref_temp);
  1613. /* set tx power value for all rates, OFDM and CCK */
  1614. for (rate_index = 0; rate_index < IWL_RATE_COUNT;
  1615. rate_index++) {
  1616. int power_idx =
  1617. ch_info->power_info[rate_index].base_power_index;
  1618. /* temperature compensate */
  1619. power_idx += delta_index;
  1620. /* stay within table range */
  1621. power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
  1622. ch_info->power_info[rate_index].
  1623. power_table_index = (u8) power_idx;
  1624. ch_info->power_info[rate_index].tpc =
  1625. power_gain_table[a_band][power_idx];
  1626. }
  1627. /* Get this chnlgrp's rate-to-max/clip-powers table */
  1628. clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
  1629. /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
  1630. for (scan_tbl_index = 0;
  1631. scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
  1632. s32 actual_index = (scan_tbl_index == 0) ?
  1633. IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
  1634. iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
  1635. actual_index, clip_pwrs,
  1636. ch_info, a_band);
  1637. }
  1638. }
  1639. /* send Txpower command for current channel to ucode */
  1640. return iwl3945_hw_reg_send_txpower(priv);
  1641. }
  1642. int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
  1643. {
  1644. struct iwl3945_channel_info *ch_info;
  1645. s8 max_power;
  1646. u8 a_band;
  1647. u8 i;
  1648. if (priv->user_txpower_limit == power) {
  1649. IWL_DEBUG_POWER("Requested Tx power same as current "
  1650. "limit: %ddBm.\n", power);
  1651. return 0;
  1652. }
  1653. IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
  1654. priv->user_txpower_limit = power;
  1655. /* set up new Tx powers for each and every channel, 2.4 and 5.x */
  1656. for (i = 0; i < priv->channel_count; i++) {
  1657. ch_info = &priv->channel_info[i];
  1658. a_band = is_channel_a_band(ch_info);
  1659. /* find minimum power of all user and regulatory constraints
  1660. * (does not consider h/w clipping limitations) */
  1661. max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
  1662. max_power = min(power, max_power);
  1663. if (max_power != ch_info->curr_txpow) {
  1664. ch_info->curr_txpow = max_power;
  1665. /* this considers the h/w clipping limitations */
  1666. iwl3945_hw_reg_set_new_power(priv, ch_info);
  1667. }
  1668. }
  1669. /* update txpower settings for all channels,
  1670. * send to NIC if associated. */
  1671. is_temp_calib_needed(priv);
  1672. iwl3945_hw_reg_comp_txpower_temp(priv);
  1673. return 0;
  1674. }
  1675. /* will add 3945 channel switch cmd handling later */
  1676. int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
  1677. {
  1678. return 0;
  1679. }
  1680. /**
  1681. * iwl3945_reg_txpower_periodic - called when time to check our temperature.
  1682. *
  1683. * -- reset periodic timer
  1684. * -- see if temp has changed enough to warrant re-calibration ... if so:
  1685. * -- correct coeffs for temp (can reset temp timer)
  1686. * -- save this temp as "last",
  1687. * -- send new set of gain settings to NIC
  1688. * NOTE: This should continue working, even when we're not associated,
  1689. * so we can keep our internal table of scan powers current. */
  1690. void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
  1691. {
  1692. /* This will kick in the "brute force"
  1693. * iwl3945_hw_reg_comp_txpower_temp() below */
  1694. if (!is_temp_calib_needed(priv))
  1695. goto reschedule;
  1696. /* Set up a new set of temp-adjusted TxPowers, send to NIC.
  1697. * This is based *only* on current temperature,
  1698. * ignoring any previous power measurements */
  1699. iwl3945_hw_reg_comp_txpower_temp(priv);
  1700. reschedule:
  1701. queue_delayed_work(priv->workqueue,
  1702. &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
  1703. }
  1704. static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
  1705. {
  1706. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
  1707. thermal_periodic.work);
  1708. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1709. return;
  1710. mutex_lock(&priv->mutex);
  1711. iwl3945_reg_txpower_periodic(priv);
  1712. mutex_unlock(&priv->mutex);
  1713. }
  1714. /**
  1715. * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
  1716. * for the channel.
  1717. *
  1718. * This function is used when initializing channel-info structs.
  1719. *
  1720. * NOTE: These channel groups do *NOT* match the bands above!
  1721. * These channel groups are based on factory-tested channels;
  1722. * on A-band, EEPROM's "group frequency" entries represent the top
  1723. * channel in each group 1-4. Group 5 All B/G channels are in group 0.
  1724. */
  1725. static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
  1726. const struct iwl3945_channel_info *ch_info)
  1727. {
  1728. struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
  1729. u8 group;
  1730. u16 group_index = 0; /* based on factory calib frequencies */
  1731. u8 grp_channel;
  1732. /* Find the group index for the channel ... don't use index 1(?) */
  1733. if (is_channel_a_band(ch_info)) {
  1734. for (group = 1; group < 5; group++) {
  1735. grp_channel = ch_grp[group].group_channel;
  1736. if (ch_info->channel <= grp_channel) {
  1737. group_index = group;
  1738. break;
  1739. }
  1740. }
  1741. /* group 4 has a few channels *above* its factory cal freq */
  1742. if (group == 5)
  1743. group_index = 4;
  1744. } else
  1745. group_index = 0; /* 2.4 GHz, group 0 */
  1746. IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
  1747. group_index);
  1748. return group_index;
  1749. }
  1750. /**
  1751. * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
  1752. *
  1753. * Interpolate to get nominal (i.e. at factory calibration temperature) index
  1754. * into radio/DSP gain settings table for requested power.
  1755. */
  1756. static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
  1757. s8 requested_power,
  1758. s32 setting_index, s32 *new_index)
  1759. {
  1760. const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
  1761. s32 index0, index1;
  1762. s32 power = 2 * requested_power;
  1763. s32 i;
  1764. const struct iwl3945_eeprom_txpower_sample *samples;
  1765. s32 gains0, gains1;
  1766. s32 res;
  1767. s32 denominator;
  1768. chnl_grp = &priv->eeprom.groups[setting_index];
  1769. samples = chnl_grp->samples;
  1770. for (i = 0; i < 5; i++) {
  1771. if (power == samples[i].power) {
  1772. *new_index = samples[i].gain_index;
  1773. return 0;
  1774. }
  1775. }
  1776. if (power > samples[1].power) {
  1777. index0 = 0;
  1778. index1 = 1;
  1779. } else if (power > samples[2].power) {
  1780. index0 = 1;
  1781. index1 = 2;
  1782. } else if (power > samples[3].power) {
  1783. index0 = 2;
  1784. index1 = 3;
  1785. } else {
  1786. index0 = 3;
  1787. index1 = 4;
  1788. }
  1789. denominator = (s32) samples[index1].power - (s32) samples[index0].power;
  1790. if (denominator == 0)
  1791. return -EINVAL;
  1792. gains0 = (s32) samples[index0].gain_index * (1 << 19);
  1793. gains1 = (s32) samples[index1].gain_index * (1 << 19);
  1794. res = gains0 + (gains1 - gains0) *
  1795. ((s32) power - (s32) samples[index0].power) / denominator +
  1796. (1 << 18);
  1797. *new_index = res >> 19;
  1798. return 0;
  1799. }
  1800. static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
  1801. {
  1802. u32 i;
  1803. s32 rate_index;
  1804. const struct iwl3945_eeprom_txpower_group *group;
  1805. IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
  1806. for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
  1807. s8 *clip_pwrs; /* table of power levels for each rate */
  1808. s8 satur_pwr; /* saturation power for each chnl group */
  1809. group = &priv->eeprom.groups[i];
  1810. /* sanity check on factory saturation power value */
  1811. if (group->saturation_power < 40) {
  1812. IWL_WARNING("Error: saturation power is %d, "
  1813. "less than minimum expected 40\n",
  1814. group->saturation_power);
  1815. return;
  1816. }
  1817. /*
  1818. * Derive requested power levels for each rate, based on
  1819. * hardware capabilities (saturation power for band).
  1820. * Basic value is 3dB down from saturation, with further
  1821. * power reductions for highest 3 data rates. These
  1822. * backoffs provide headroom for high rate modulation
  1823. * power peaks, without too much distortion (clipping).
  1824. */
  1825. /* we'll fill in this array with h/w max power levels */
  1826. clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
  1827. /* divide factory saturation power by 2 to find -3dB level */
  1828. satur_pwr = (s8) (group->saturation_power >> 1);
  1829. /* fill in channel group's nominal powers for each rate */
  1830. for (rate_index = 0;
  1831. rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
  1832. switch (rate_index) {
  1833. case IWL_RATE_36M_INDEX_TABLE:
  1834. if (i == 0) /* B/G */
  1835. *clip_pwrs = satur_pwr;
  1836. else /* A */
  1837. *clip_pwrs = satur_pwr - 5;
  1838. break;
  1839. case IWL_RATE_48M_INDEX_TABLE:
  1840. if (i == 0)
  1841. *clip_pwrs = satur_pwr - 7;
  1842. else
  1843. *clip_pwrs = satur_pwr - 10;
  1844. break;
  1845. case IWL_RATE_54M_INDEX_TABLE:
  1846. if (i == 0)
  1847. *clip_pwrs = satur_pwr - 9;
  1848. else
  1849. *clip_pwrs = satur_pwr - 12;
  1850. break;
  1851. default:
  1852. *clip_pwrs = satur_pwr;
  1853. break;
  1854. }
  1855. }
  1856. }
  1857. }
  1858. /**
  1859. * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
  1860. *
  1861. * Second pass (during init) to set up priv->channel_info
  1862. *
  1863. * Set up Tx-power settings in our channel info database for each VALID
  1864. * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
  1865. * and current temperature.
  1866. *
  1867. * Since this is based on current temperature (at init time), these values may
  1868. * not be valid for very long, but it gives us a starting/default point,
  1869. * and allows us to active (i.e. using Tx) scan.
  1870. *
  1871. * This does *not* write values to NIC, just sets up our internal table.
  1872. */
  1873. int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
  1874. {
  1875. struct iwl3945_channel_info *ch_info = NULL;
  1876. struct iwl3945_channel_power_info *pwr_info;
  1877. int delta_index;
  1878. u8 rate_index;
  1879. u8 scan_tbl_index;
  1880. const s8 *clip_pwrs; /* array of power levels for each rate */
  1881. u8 gain, dsp_atten;
  1882. s8 power;
  1883. u8 pwr_index, base_pwr_index, a_band;
  1884. u8 i;
  1885. int temperature;
  1886. /* save temperature reference,
  1887. * so we can determine next time to calibrate */
  1888. temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
  1889. priv->last_temperature = temperature;
  1890. iwl3945_hw_reg_init_channel_groups(priv);
  1891. /* initialize Tx power info for each and every channel, 2.4 and 5.x */
  1892. for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
  1893. i++, ch_info++) {
  1894. a_band = is_channel_a_band(ch_info);
  1895. if (!is_channel_valid(ch_info))
  1896. continue;
  1897. /* find this channel's channel group (*not* "band") index */
  1898. ch_info->group_index =
  1899. iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
  1900. /* Get this chnlgrp's rate->max/clip-powers table */
  1901. clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
  1902. /* calculate power index *adjustment* value according to
  1903. * diff between current temperature and factory temperature */
  1904. delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
  1905. priv->eeprom.groups[ch_info->group_index].
  1906. temperature);
  1907. IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
  1908. ch_info->channel, delta_index, temperature +
  1909. IWL_TEMP_CONVERT);
  1910. /* set tx power value for all OFDM rates */
  1911. for (rate_index = 0; rate_index < IWL_OFDM_RATES;
  1912. rate_index++) {
  1913. s32 uninitialized_var(power_idx);
  1914. int rc;
  1915. /* use channel group's clip-power table,
  1916. * but don't exceed channel's max power */
  1917. s8 pwr = min(ch_info->max_power_avg,
  1918. clip_pwrs[rate_index]);
  1919. pwr_info = &ch_info->power_info[rate_index];
  1920. /* get base (i.e. at factory-measured temperature)
  1921. * power table index for this rate's power */
  1922. rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
  1923. ch_info->group_index,
  1924. &power_idx);
  1925. if (rc) {
  1926. IWL_ERROR("Invalid power index\n");
  1927. return rc;
  1928. }
  1929. pwr_info->base_power_index = (u8) power_idx;
  1930. /* temperature compensate */
  1931. power_idx += delta_index;
  1932. /* stay within range of gain table */
  1933. power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
  1934. /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
  1935. pwr_info->requested_power = pwr;
  1936. pwr_info->power_table_index = (u8) power_idx;
  1937. pwr_info->tpc.tx_gain =
  1938. power_gain_table[a_band][power_idx].tx_gain;
  1939. pwr_info->tpc.dsp_atten =
  1940. power_gain_table[a_band][power_idx].dsp_atten;
  1941. }
  1942. /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
  1943. pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
  1944. power = pwr_info->requested_power +
  1945. IWL_CCK_FROM_OFDM_POWER_DIFF;
  1946. pwr_index = pwr_info->power_table_index +
  1947. IWL_CCK_FROM_OFDM_INDEX_DIFF;
  1948. base_pwr_index = pwr_info->base_power_index +
  1949. IWL_CCK_FROM_OFDM_INDEX_DIFF;
  1950. /* stay within table range */
  1951. pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
  1952. gain = power_gain_table[a_band][pwr_index].tx_gain;
  1953. dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
  1954. /* fill each CCK rate's iwl3945_channel_power_info structure
  1955. * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
  1956. * NOTE: CCK rates start at end of OFDM rates! */
  1957. for (rate_index = 0;
  1958. rate_index < IWL_CCK_RATES; rate_index++) {
  1959. pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
  1960. pwr_info->requested_power = power;
  1961. pwr_info->power_table_index = pwr_index;
  1962. pwr_info->base_power_index = base_pwr_index;
  1963. pwr_info->tpc.tx_gain = gain;
  1964. pwr_info->tpc.dsp_atten = dsp_atten;
  1965. }
  1966. /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
  1967. for (scan_tbl_index = 0;
  1968. scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
  1969. s32 actual_index = (scan_tbl_index == 0) ?
  1970. IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
  1971. iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
  1972. actual_index, clip_pwrs, ch_info, a_band);
  1973. }
  1974. }
  1975. return 0;
  1976. }
  1977. int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
  1978. {
  1979. int rc;
  1980. unsigned long flags;
  1981. spin_lock_irqsave(&priv->lock, flags);
  1982. rc = iwl3945_grab_nic_access(priv);
  1983. if (rc) {
  1984. spin_unlock_irqrestore(&priv->lock, flags);
  1985. return rc;
  1986. }
  1987. iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
  1988. rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS,
  1989. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  1990. if (rc < 0)
  1991. IWL_ERROR("Can't stop Rx DMA.\n");
  1992. iwl3945_release_nic_access(priv);
  1993. spin_unlock_irqrestore(&priv->lock, flags);
  1994. return 0;
  1995. }
  1996. int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  1997. {
  1998. int rc;
  1999. unsigned long flags;
  2000. int txq_id = txq->q.id;
  2001. struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
  2002. shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
  2003. spin_lock_irqsave(&priv->lock, flags);
  2004. rc = iwl3945_grab_nic_access(priv);
  2005. if (rc) {
  2006. spin_unlock_irqrestore(&priv->lock, flags);
  2007. return rc;
  2008. }
  2009. iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
  2010. iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
  2011. iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
  2012. ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
  2013. ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
  2014. ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
  2015. ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
  2016. ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
  2017. iwl3945_release_nic_access(priv);
  2018. /* fake read to flush all prev. writes */
  2019. iwl3945_read32(priv, FH_TSSR_CBB_BASE);
  2020. spin_unlock_irqrestore(&priv->lock, flags);
  2021. return 0;
  2022. }
  2023. int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
  2024. {
  2025. struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
  2026. return le32_to_cpu(shared_data->rx_read_ptr[0]);
  2027. }
  2028. /**
  2029. * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
  2030. */
  2031. int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
  2032. {
  2033. int rc, i, index, prev_index;
  2034. struct iwl3945_rate_scaling_cmd rate_cmd = {
  2035. .reserved = {0, 0, 0},
  2036. };
  2037. struct iwl3945_rate_scaling_info *table = rate_cmd.table;
  2038. for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
  2039. index = iwl3945_rates[i].table_rs_index;
  2040. table[index].rate_n_flags =
  2041. iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
  2042. table[index].try_cnt = priv->retry_rate;
  2043. prev_index = iwl3945_get_prev_ieee_rate(i);
  2044. table[index].next_rate_index =
  2045. iwl3945_rates[prev_index].table_rs_index;
  2046. }
  2047. switch (priv->band) {
  2048. case IEEE80211_BAND_5GHZ:
  2049. IWL_DEBUG_RATE("Select A mode rate scale\n");
  2050. /* If one of the following CCK rates is used,
  2051. * have it fall back to the 6M OFDM rate */
  2052. for (i = IWL_RATE_1M_INDEX_TABLE;
  2053. i <= IWL_RATE_11M_INDEX_TABLE; i++)
  2054. table[i].next_rate_index =
  2055. iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
  2056. /* Don't fall back to CCK rates */
  2057. table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
  2058. IWL_RATE_9M_INDEX_TABLE;
  2059. /* Don't drop out of OFDM rates */
  2060. table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
  2061. iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
  2062. break;
  2063. case IEEE80211_BAND_2GHZ:
  2064. IWL_DEBUG_RATE("Select B/G mode rate scale\n");
  2065. /* If an OFDM rate is used, have it fall back to the
  2066. * 1M CCK rates */
  2067. if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
  2068. iwl3945_is_associated(priv)) {
  2069. index = IWL_FIRST_CCK_RATE;
  2070. for (i = IWL_RATE_6M_INDEX_TABLE;
  2071. i <= IWL_RATE_54M_INDEX_TABLE; i++)
  2072. table[i].next_rate_index =
  2073. iwl3945_rates[index].table_rs_index;
  2074. index = IWL_RATE_11M_INDEX_TABLE;
  2075. /* CCK shouldn't fall back to OFDM... */
  2076. table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
  2077. }
  2078. break;
  2079. default:
  2080. WARN_ON(1);
  2081. break;
  2082. }
  2083. /* Update the rate scaling for control frame Tx */
  2084. rate_cmd.table_id = 0;
  2085. rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
  2086. &rate_cmd);
  2087. if (rc)
  2088. return rc;
  2089. /* Update the rate scaling for data frame Tx */
  2090. rate_cmd.table_id = 1;
  2091. return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
  2092. &rate_cmd);
  2093. }
  2094. /* Called when initializing driver */
  2095. int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
  2096. {
  2097. memset((void *)&priv->hw_setting, 0,
  2098. sizeof(struct iwl3945_driver_hw_info));
  2099. priv->hw_setting.shared_virt =
  2100. pci_alloc_consistent(priv->pci_dev,
  2101. sizeof(struct iwl3945_shared),
  2102. &priv->hw_setting.shared_phys);
  2103. if (!priv->hw_setting.shared_virt) {
  2104. IWL_ERROR("failed to allocate pci memory\n");
  2105. mutex_unlock(&priv->mutex);
  2106. return -ENOMEM;
  2107. }
  2108. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
  2109. priv->hw_setting.max_pkt_size = 2342;
  2110. priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
  2111. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  2112. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  2113. priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
  2114. priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
  2115. priv->hw_setting.tx_ant_num = 2;
  2116. return 0;
  2117. }
  2118. unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
  2119. struct iwl3945_frame *frame, u8 rate)
  2120. {
  2121. struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
  2122. unsigned int frame_size;
  2123. tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
  2124. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2125. tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
  2126. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2127. frame_size = iwl3945_fill_beacon_frame(priv,
  2128. tx_beacon_cmd->frame,
  2129. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2130. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2131. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2132. tx_beacon_cmd->tx.rate = rate;
  2133. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2134. TX_CMD_FLG_TSF_MSK);
  2135. /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
  2136. tx_beacon_cmd->tx.supp_rates[0] =
  2137. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2138. tx_beacon_cmd->tx.supp_rates[1] =
  2139. (IWL_CCK_BASIC_RATES_MASK & 0xF);
  2140. return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
  2141. }
  2142. void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
  2143. {
  2144. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  2145. priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
  2146. }
  2147. void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
  2148. {
  2149. INIT_DELAYED_WORK(&priv->thermal_periodic,
  2150. iwl3945_bg_reg_txpower_periodic);
  2151. }
  2152. void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
  2153. {
  2154. cancel_delayed_work(&priv->thermal_periodic);
  2155. }
  2156. static struct iwl_3945_cfg iwl3945_bg_cfg = {
  2157. .name = "3945BG",
  2158. .fw_name_pre = IWL3945_FW_PRE,
  2159. .ucode_api_max = IWL3945_UCODE_API_MAX,
  2160. .ucode_api_min = IWL3945_UCODE_API_MIN,
  2161. .sku = IWL_SKU_G,
  2162. };
  2163. static struct iwl_3945_cfg iwl3945_abg_cfg = {
  2164. .name = "3945ABG",
  2165. .fw_name_pre = IWL3945_FW_PRE,
  2166. .ucode_api_max = IWL3945_UCODE_API_MAX,
  2167. .ucode_api_min = IWL3945_UCODE_API_MIN,
  2168. .sku = IWL_SKU_A|IWL_SKU_G,
  2169. };
  2170. struct pci_device_id iwl3945_hw_card_ids[] = {
  2171. {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
  2172. {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
  2173. {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
  2174. {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
  2175. {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
  2176. {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
  2177. {0}
  2178. };
  2179. MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);