smsc911x.c 55 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. ***************************************************************************
  21. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  22. * Partly uses io macros from smc91x.c by Nicolas Pitre
  23. *
  24. * Supported devices:
  25. * LAN9115, LAN9116, LAN9117, LAN9118
  26. * LAN9215, LAN9216, LAN9217, LAN9218
  27. * LAN9210, LAN9211
  28. * LAN9220, LAN9221
  29. *
  30. */
  31. #include <linux/crc32.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/ethtool.h>
  36. #include <linux/init.h>
  37. #include <linux/ioport.h>
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/sched.h>
  43. #include <linux/slab.h>
  44. #include <linux/timer.h>
  45. #include <linux/version.h>
  46. #include <linux/bug.h>
  47. #include <linux/bitops.h>
  48. #include <linux/irq.h>
  49. #include <linux/io.h>
  50. #include <linux/phy.h>
  51. #include <linux/smsc911x.h>
  52. #include "smsc911x.h"
  53. #define SMSC_CHIPNAME "smsc911x"
  54. #define SMSC_MDIONAME "smsc911x-mdio"
  55. #define SMSC_DRV_VERSION "2008-10-21"
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(SMSC_DRV_VERSION);
  58. #if USE_DEBUG > 0
  59. static int debug = 16;
  60. #else
  61. static int debug = 3;
  62. #endif
  63. module_param(debug, int, 0);
  64. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  65. struct smsc911x_data {
  66. void __iomem *ioaddr;
  67. unsigned int idrev;
  68. /* used to decide which workarounds apply */
  69. unsigned int generation;
  70. /* device configuration (copied from platform_data during probe) */
  71. struct smsc911x_platform_config config;
  72. /* This needs to be acquired before calling any of below:
  73. * smsc911x_mac_read(), smsc911x_mac_write()
  74. */
  75. spinlock_t mac_lock;
  76. /* spinlock to ensure 16-bit accesses are serialised.
  77. * unused with a 32-bit bus */
  78. spinlock_t dev_lock;
  79. struct phy_device *phy_dev;
  80. struct mii_bus *mii_bus;
  81. int phy_irq[PHY_MAX_ADDR];
  82. unsigned int using_extphy;
  83. int last_duplex;
  84. int last_carrier;
  85. u32 msg_enable;
  86. unsigned int gpio_setting;
  87. unsigned int gpio_orig_setting;
  88. struct net_device *dev;
  89. struct napi_struct napi;
  90. unsigned int software_irq_signal;
  91. #ifdef USE_PHY_WORK_AROUND
  92. #define MIN_PACKET_SIZE (64)
  93. char loopback_tx_pkt[MIN_PACKET_SIZE];
  94. char loopback_rx_pkt[MIN_PACKET_SIZE];
  95. unsigned int resetcount;
  96. #endif
  97. /* Members for Multicast filter workaround */
  98. unsigned int multicast_update_pending;
  99. unsigned int set_bits_mask;
  100. unsigned int clear_bits_mask;
  101. unsigned int hashhi;
  102. unsigned int hashlo;
  103. };
  104. /* The 16-bit access functions are significantly slower, due to the locking
  105. * necessary. If your bus hardware can be configured to do this for you
  106. * (in response to a single 32-bit operation from software), you should use
  107. * the 32-bit access functions instead. */
  108. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  109. {
  110. if (pdata->config.flags & SMSC911X_USE_32BIT)
  111. return readl(pdata->ioaddr + reg);
  112. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  113. u32 data;
  114. unsigned long flags;
  115. /* these two 16-bit reads must be performed consecutively, so
  116. * must not be interrupted by our own ISR (which would start
  117. * another read operation) */
  118. spin_lock_irqsave(&pdata->dev_lock, flags);
  119. data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  120. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  121. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  122. return data;
  123. }
  124. BUG();
  125. return 0;
  126. }
  127. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  128. u32 val)
  129. {
  130. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  131. writel(val, pdata->ioaddr + reg);
  132. return;
  133. }
  134. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  135. unsigned long flags;
  136. /* these two 16-bit writes must be performed consecutively, so
  137. * must not be interrupted by our own ISR (which would start
  138. * another read operation) */
  139. spin_lock_irqsave(&pdata->dev_lock, flags);
  140. writew(val & 0xFFFF, pdata->ioaddr + reg);
  141. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  142. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  143. return;
  144. }
  145. BUG();
  146. }
  147. /* Writes a packet to the TX_DATA_FIFO */
  148. static inline void
  149. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  150. unsigned int wordcount)
  151. {
  152. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  153. writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  154. return;
  155. }
  156. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  157. while (wordcount--)
  158. smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  159. return;
  160. }
  161. BUG();
  162. }
  163. /* Reads a packet out of the RX_DATA_FIFO */
  164. static inline void
  165. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  166. unsigned int wordcount)
  167. {
  168. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  169. readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  170. return;
  171. }
  172. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  173. while (wordcount--)
  174. *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  175. return;
  176. }
  177. BUG();
  178. }
  179. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  180. * and smsc911x_mac_write, so assumes mac_lock is held */
  181. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  182. {
  183. int i;
  184. u32 val;
  185. SMSC_ASSERT_MAC_LOCK(pdata);
  186. for (i = 0; i < 40; i++) {
  187. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  188. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  189. return 0;
  190. }
  191. SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
  192. "MAC_CSR_CMD: 0x%08X", val);
  193. return -EIO;
  194. }
  195. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  196. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  197. {
  198. unsigned int temp;
  199. SMSC_ASSERT_MAC_LOCK(pdata);
  200. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  201. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  202. SMSC_WARNING(HW, "MAC busy at entry");
  203. return 0xFFFFFFFF;
  204. }
  205. /* Send the MAC cmd */
  206. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  207. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  208. /* Workaround for hardware read-after-write restriction */
  209. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  210. /* Wait for the read to complete */
  211. if (likely(smsc911x_mac_complete(pdata) == 0))
  212. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  213. SMSC_WARNING(HW, "MAC busy after read");
  214. return 0xFFFFFFFF;
  215. }
  216. /* Set a mac register, mac_lock must be acquired before calling */
  217. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  218. unsigned int offset, u32 val)
  219. {
  220. unsigned int temp;
  221. SMSC_ASSERT_MAC_LOCK(pdata);
  222. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  223. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  224. SMSC_WARNING(HW,
  225. "smsc911x_mac_write failed, MAC busy at entry");
  226. return;
  227. }
  228. /* Send data to write */
  229. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  230. /* Write the actual data */
  231. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  232. MAC_CSR_CMD_CSR_BUSY_));
  233. /* Workaround for hardware read-after-write restriction */
  234. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  235. /* Wait for the write to complete */
  236. if (likely(smsc911x_mac_complete(pdata) == 0))
  237. return;
  238. SMSC_WARNING(HW,
  239. "smsc911x_mac_write failed, MAC busy after write");
  240. }
  241. /* Get a phy register */
  242. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  243. {
  244. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  245. unsigned long flags;
  246. unsigned int addr;
  247. int i, reg;
  248. spin_lock_irqsave(&pdata->mac_lock, flags);
  249. /* Confirm MII not busy */
  250. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  251. SMSC_WARNING(HW,
  252. "MII is busy in smsc911x_mii_read???");
  253. reg = -EIO;
  254. goto out;
  255. }
  256. /* Set the address, index & direction (read from PHY) */
  257. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  258. smsc911x_mac_write(pdata, MII_ACC, addr);
  259. /* Wait for read to complete w/ timeout */
  260. for (i = 0; i < 100; i++)
  261. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  262. reg = smsc911x_mac_read(pdata, MII_DATA);
  263. goto out;
  264. }
  265. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  266. reg = -EIO;
  267. out:
  268. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  269. return reg;
  270. }
  271. /* Set a phy register */
  272. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  273. u16 val)
  274. {
  275. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  276. unsigned long flags;
  277. unsigned int addr;
  278. int i, reg;
  279. spin_lock_irqsave(&pdata->mac_lock, flags);
  280. /* Confirm MII not busy */
  281. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  282. SMSC_WARNING(HW,
  283. "MII is busy in smsc911x_mii_write???");
  284. reg = -EIO;
  285. goto out;
  286. }
  287. /* Put the data to write in the MAC */
  288. smsc911x_mac_write(pdata, MII_DATA, val);
  289. /* Set the address, index & direction (write to PHY) */
  290. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  291. MII_ACC_MII_WRITE_;
  292. smsc911x_mac_write(pdata, MII_ACC, addr);
  293. /* Wait for write to complete w/ timeout */
  294. for (i = 0; i < 100; i++)
  295. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  296. reg = 0;
  297. goto out;
  298. }
  299. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  300. reg = -EIO;
  301. out:
  302. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  303. return reg;
  304. }
  305. /* Autodetects and initialises external phy for SMSC9115 and SMSC9117 flavors.
  306. * If something goes wrong, returns -ENODEV to revert back to internal phy.
  307. * Performed at initialisation only, so interrupts are enabled */
  308. static int smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  309. {
  310. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  311. /* External phy is requested, supported, and detected */
  312. if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  313. /* Switch to external phy. Assuming tx and rx are stopped
  314. * because smsc911x_phy_initialise is called before
  315. * smsc911x_rx_initialise and tx_initialise. */
  316. /* Disable phy clocks to the MAC */
  317. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  318. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  319. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  320. udelay(10); /* Enough time for clocks to stop */
  321. /* Switch to external phy */
  322. hwcfg |= HW_CFG_EXT_PHY_EN_;
  323. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  324. /* Enable phy clocks to the MAC */
  325. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  326. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  327. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  328. udelay(10); /* Enough time for clocks to restart */
  329. hwcfg |= HW_CFG_SMI_SEL_;
  330. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  331. SMSC_TRACE(HW, "Successfully switched to external PHY");
  332. pdata->using_extphy = 1;
  333. } else {
  334. SMSC_WARNING(HW, "No external PHY detected, "
  335. "Using internal PHY instead.");
  336. /* Use internal phy */
  337. return -ENODEV;
  338. }
  339. return 0;
  340. }
  341. /* Fetches a tx status out of the status fifo */
  342. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  343. {
  344. unsigned int result =
  345. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  346. if (result != 0)
  347. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  348. return result;
  349. }
  350. /* Fetches the next rx status */
  351. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  352. {
  353. unsigned int result =
  354. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  355. if (result != 0)
  356. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  357. return result;
  358. }
  359. #ifdef USE_PHY_WORK_AROUND
  360. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  361. {
  362. unsigned int tries;
  363. u32 wrsz;
  364. u32 rdsz;
  365. ulong bufp;
  366. for (tries = 0; tries < 10; tries++) {
  367. unsigned int txcmd_a;
  368. unsigned int txcmd_b;
  369. unsigned int status;
  370. unsigned int pktlength;
  371. unsigned int i;
  372. /* Zero-out rx packet memory */
  373. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  374. /* Write tx packet to 118 */
  375. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  376. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  377. txcmd_a |= MIN_PACKET_SIZE;
  378. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  379. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  380. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  381. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  382. wrsz = MIN_PACKET_SIZE + 3;
  383. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  384. wrsz >>= 2;
  385. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  386. /* Wait till transmit is done */
  387. i = 60;
  388. do {
  389. udelay(5);
  390. status = smsc911x_tx_get_txstatus(pdata);
  391. } while ((i--) && (!status));
  392. if (!status) {
  393. SMSC_WARNING(HW, "Failed to transmit "
  394. "during loopback test");
  395. continue;
  396. }
  397. if (status & TX_STS_ES_) {
  398. SMSC_WARNING(HW, "Transmit encountered "
  399. "errors during loopback test");
  400. continue;
  401. }
  402. /* Wait till receive is done */
  403. i = 60;
  404. do {
  405. udelay(5);
  406. status = smsc911x_rx_get_rxstatus(pdata);
  407. } while ((i--) && (!status));
  408. if (!status) {
  409. SMSC_WARNING(HW,
  410. "Failed to receive during loopback test");
  411. continue;
  412. }
  413. if (status & RX_STS_ES_) {
  414. SMSC_WARNING(HW, "Receive encountered "
  415. "errors during loopback test");
  416. continue;
  417. }
  418. pktlength = ((status & 0x3FFF0000UL) >> 16);
  419. bufp = (ulong)pdata->loopback_rx_pkt;
  420. rdsz = pktlength + 3;
  421. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  422. rdsz >>= 2;
  423. smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  424. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  425. SMSC_WARNING(HW, "Unexpected packet size "
  426. "during loop back test, size=%d, will retry",
  427. pktlength);
  428. } else {
  429. unsigned int j;
  430. int mismatch = 0;
  431. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  432. if (pdata->loopback_tx_pkt[j]
  433. != pdata->loopback_rx_pkt[j]) {
  434. mismatch = 1;
  435. break;
  436. }
  437. }
  438. if (!mismatch) {
  439. SMSC_TRACE(HW, "Successfully verified "
  440. "loopback packet");
  441. return 0;
  442. } else {
  443. SMSC_WARNING(HW, "Data mismatch "
  444. "during loop back test, will retry");
  445. }
  446. }
  447. }
  448. return -EIO;
  449. }
  450. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  451. {
  452. struct phy_device *phy_dev = pdata->phy_dev;
  453. unsigned int temp;
  454. unsigned int i = 100000;
  455. BUG_ON(!phy_dev);
  456. BUG_ON(!phy_dev->bus);
  457. SMSC_TRACE(HW, "Performing PHY BCR Reset");
  458. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  459. do {
  460. msleep(1);
  461. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  462. MII_BMCR);
  463. } while ((i--) && (temp & BMCR_RESET));
  464. if (temp & BMCR_RESET) {
  465. SMSC_WARNING(HW, "PHY reset failed to complete.");
  466. return -EIO;
  467. }
  468. /* Extra delay required because the phy may not be completed with
  469. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  470. * enough delay but using 1ms here to be safe */
  471. msleep(1);
  472. return 0;
  473. }
  474. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  475. {
  476. struct smsc911x_data *pdata = netdev_priv(dev);
  477. struct phy_device *phy_dev = pdata->phy_dev;
  478. int result = -EIO;
  479. unsigned int i, val;
  480. unsigned long flags;
  481. /* Initialise tx packet using broadcast destination address */
  482. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  483. /* Use incrementing source address */
  484. for (i = 6; i < 12; i++)
  485. pdata->loopback_tx_pkt[i] = (char)i;
  486. /* Set length type field */
  487. pdata->loopback_tx_pkt[12] = 0x00;
  488. pdata->loopback_tx_pkt[13] = 0x00;
  489. for (i = 14; i < MIN_PACKET_SIZE; i++)
  490. pdata->loopback_tx_pkt[i] = (char)i;
  491. val = smsc911x_reg_read(pdata, HW_CFG);
  492. val &= HW_CFG_TX_FIF_SZ_;
  493. val |= HW_CFG_SF_;
  494. smsc911x_reg_write(pdata, HW_CFG, val);
  495. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  496. smsc911x_reg_write(pdata, RX_CFG,
  497. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  498. for (i = 0; i < 10; i++) {
  499. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  500. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  501. BMCR_LOOPBACK | BMCR_FULLDPLX);
  502. /* Enable MAC tx/rx, FD */
  503. spin_lock_irqsave(&pdata->mac_lock, flags);
  504. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  505. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  506. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  507. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  508. result = 0;
  509. break;
  510. }
  511. pdata->resetcount++;
  512. /* Disable MAC rx */
  513. spin_lock_irqsave(&pdata->mac_lock, flags);
  514. smsc911x_mac_write(pdata, MAC_CR, 0);
  515. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  516. smsc911x_phy_reset(pdata);
  517. }
  518. /* Disable MAC */
  519. spin_lock_irqsave(&pdata->mac_lock, flags);
  520. smsc911x_mac_write(pdata, MAC_CR, 0);
  521. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  522. /* Cancel PHY loopback mode */
  523. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  524. smsc911x_reg_write(pdata, TX_CFG, 0);
  525. smsc911x_reg_write(pdata, RX_CFG, 0);
  526. return result;
  527. }
  528. #endif /* USE_PHY_WORK_AROUND */
  529. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  530. {
  531. struct phy_device *phy_dev = pdata->phy_dev;
  532. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  533. u32 flow;
  534. unsigned long flags;
  535. if (phy_dev->duplex == DUPLEX_FULL) {
  536. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  537. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  538. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  539. if (cap & FLOW_CTRL_RX)
  540. flow = 0xFFFF0002;
  541. else
  542. flow = 0;
  543. if (cap & FLOW_CTRL_TX)
  544. afc |= 0xF;
  545. else
  546. afc &= ~0xF;
  547. SMSC_TRACE(HW, "rx pause %s, tx pause %s",
  548. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  549. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  550. } else {
  551. SMSC_TRACE(HW, "half duplex");
  552. flow = 0;
  553. afc |= 0xF;
  554. }
  555. spin_lock_irqsave(&pdata->mac_lock, flags);
  556. smsc911x_mac_write(pdata, FLOW, flow);
  557. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  558. smsc911x_reg_write(pdata, AFC_CFG, afc);
  559. }
  560. /* Update link mode if anything has changed. Called periodically when the
  561. * PHY is in polling mode, even if nothing has changed. */
  562. static void smsc911x_phy_adjust_link(struct net_device *dev)
  563. {
  564. struct smsc911x_data *pdata = netdev_priv(dev);
  565. struct phy_device *phy_dev = pdata->phy_dev;
  566. unsigned long flags;
  567. int carrier;
  568. if (phy_dev->duplex != pdata->last_duplex) {
  569. unsigned int mac_cr;
  570. SMSC_TRACE(HW, "duplex state has changed");
  571. spin_lock_irqsave(&pdata->mac_lock, flags);
  572. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  573. if (phy_dev->duplex) {
  574. SMSC_TRACE(HW,
  575. "configuring for full duplex mode");
  576. mac_cr |= MAC_CR_FDPX_;
  577. } else {
  578. SMSC_TRACE(HW,
  579. "configuring for half duplex mode");
  580. mac_cr &= ~MAC_CR_FDPX_;
  581. }
  582. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  583. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  584. smsc911x_phy_update_flowcontrol(pdata);
  585. pdata->last_duplex = phy_dev->duplex;
  586. }
  587. carrier = netif_carrier_ok(dev);
  588. if (carrier != pdata->last_carrier) {
  589. SMSC_TRACE(HW, "carrier state has changed");
  590. if (carrier) {
  591. SMSC_TRACE(HW, "configuring for carrier OK");
  592. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  593. (!pdata->using_extphy)) {
  594. /* Restore orginal GPIO configuration */
  595. pdata->gpio_setting = pdata->gpio_orig_setting;
  596. smsc911x_reg_write(pdata, GPIO_CFG,
  597. pdata->gpio_setting);
  598. }
  599. } else {
  600. SMSC_TRACE(HW, "configuring for no carrier");
  601. /* Check global setting that LED1
  602. * usage is 10/100 indicator */
  603. pdata->gpio_setting = smsc911x_reg_read(pdata,
  604. GPIO_CFG);
  605. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
  606. && (!pdata->using_extphy)) {
  607. /* Force 10/100 LED off, after saving
  608. * orginal GPIO configuration */
  609. pdata->gpio_orig_setting = pdata->gpio_setting;
  610. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  611. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  612. | GPIO_CFG_GPIODIR0_
  613. | GPIO_CFG_GPIOD0_);
  614. smsc911x_reg_write(pdata, GPIO_CFG,
  615. pdata->gpio_setting);
  616. }
  617. }
  618. pdata->last_carrier = carrier;
  619. }
  620. }
  621. static int smsc911x_mii_probe(struct net_device *dev)
  622. {
  623. struct smsc911x_data *pdata = netdev_priv(dev);
  624. struct phy_device *phydev = NULL;
  625. int phy_addr;
  626. /* find the first phy */
  627. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  628. if (pdata->mii_bus->phy_map[phy_addr]) {
  629. phydev = pdata->mii_bus->phy_map[phy_addr];
  630. SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
  631. phy_addr, phydev->addr, phydev->phy_id);
  632. break;
  633. }
  634. }
  635. if (!phydev) {
  636. pr_err("%s: no PHY found\n", dev->name);
  637. return -ENODEV;
  638. }
  639. phydev = phy_connect(dev, phydev->dev.bus_id,
  640. &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
  641. if (IS_ERR(phydev)) {
  642. pr_err("%s: Could not attach to PHY\n", dev->name);
  643. return PTR_ERR(phydev);
  644. }
  645. pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  646. dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
  647. /* mask with MAC supported features */
  648. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  649. SUPPORTED_Asym_Pause);
  650. phydev->advertising = phydev->supported;
  651. pdata->phy_dev = phydev;
  652. pdata->last_duplex = -1;
  653. pdata->last_carrier = -1;
  654. #ifdef USE_PHY_WORK_AROUND
  655. if (smsc911x_phy_loopbacktest(dev) < 0) {
  656. SMSC_WARNING(HW, "Failed Loop Back Test");
  657. return -ENODEV;
  658. }
  659. SMSC_TRACE(HW, "Passed Loop Back Test");
  660. #endif /* USE_PHY_WORK_AROUND */
  661. SMSC_TRACE(HW, "phy initialised succesfully");
  662. return 0;
  663. }
  664. static int __devinit smsc911x_mii_init(struct platform_device *pdev,
  665. struct net_device *dev)
  666. {
  667. struct smsc911x_data *pdata = netdev_priv(dev);
  668. int err = -ENXIO, i;
  669. pdata->mii_bus = mdiobus_alloc();
  670. if (!pdata->mii_bus) {
  671. err = -ENOMEM;
  672. goto err_out_1;
  673. }
  674. pdata->mii_bus->name = SMSC_MDIONAME;
  675. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  676. pdata->mii_bus->priv = pdata;
  677. pdata->mii_bus->read = smsc911x_mii_read;
  678. pdata->mii_bus->write = smsc911x_mii_write;
  679. pdata->mii_bus->irq = pdata->phy_irq;
  680. for (i = 0; i < PHY_MAX_ADDR; ++i)
  681. pdata->mii_bus->irq[i] = PHY_POLL;
  682. pdata->mii_bus->parent = &pdev->dev;
  683. pdata->using_extphy = 0;
  684. switch (pdata->idrev & 0xFFFF0000) {
  685. case 0x01170000:
  686. case 0x01150000:
  687. case 0x117A0000:
  688. case 0x115A0000:
  689. /* External PHY supported, try to autodetect */
  690. if (smsc911x_phy_initialise_external(pdata) < 0) {
  691. SMSC_TRACE(HW, "No external PHY detected, "
  692. "using internal PHY");
  693. }
  694. break;
  695. default:
  696. SMSC_TRACE(HW, "External PHY is not supported, "
  697. "using internal PHY");
  698. break;
  699. }
  700. if (!pdata->using_extphy) {
  701. /* Mask all PHYs except ID 1 (internal) */
  702. pdata->mii_bus->phy_mask = ~(1 << 1);
  703. }
  704. if (mdiobus_register(pdata->mii_bus)) {
  705. SMSC_WARNING(PROBE, "Error registering mii bus");
  706. goto err_out_free_bus_2;
  707. }
  708. if (smsc911x_mii_probe(dev) < 0) {
  709. SMSC_WARNING(PROBE, "Error registering mii bus");
  710. goto err_out_unregister_bus_3;
  711. }
  712. return 0;
  713. err_out_unregister_bus_3:
  714. mdiobus_unregister(pdata->mii_bus);
  715. err_out_free_bus_2:
  716. mdiobus_free(pdata->mii_bus);
  717. err_out_1:
  718. return err;
  719. }
  720. /* Gets the number of tx statuses in the fifo */
  721. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  722. {
  723. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  724. & TX_FIFO_INF_TSUSED_) >> 16;
  725. }
  726. /* Reads tx statuses and increments counters where necessary */
  727. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  728. {
  729. struct smsc911x_data *pdata = netdev_priv(dev);
  730. unsigned int tx_stat;
  731. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  732. if (unlikely(tx_stat & 0x80000000)) {
  733. /* In this driver the packet tag is used as the packet
  734. * length. Since a packet length can never reach the
  735. * size of 0x8000, this bit is reserved. It is worth
  736. * noting that the "reserved bit" in the warning above
  737. * does not reference a hardware defined reserved bit
  738. * but rather a driver defined one.
  739. */
  740. SMSC_WARNING(HW,
  741. "Packet tag reserved bit is high");
  742. } else {
  743. if (unlikely(tx_stat & 0x00008000)) {
  744. dev->stats.tx_errors++;
  745. } else {
  746. dev->stats.tx_packets++;
  747. dev->stats.tx_bytes += (tx_stat >> 16);
  748. }
  749. if (unlikely(tx_stat & 0x00000100)) {
  750. dev->stats.collisions += 16;
  751. dev->stats.tx_aborted_errors += 1;
  752. } else {
  753. dev->stats.collisions +=
  754. ((tx_stat >> 3) & 0xF);
  755. }
  756. if (unlikely(tx_stat & 0x00000800))
  757. dev->stats.tx_carrier_errors += 1;
  758. if (unlikely(tx_stat & 0x00000200)) {
  759. dev->stats.collisions++;
  760. dev->stats.tx_aborted_errors++;
  761. }
  762. }
  763. }
  764. }
  765. /* Increments the Rx error counters */
  766. static void
  767. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  768. {
  769. int crc_err = 0;
  770. if (unlikely(rxstat & 0x00008000)) {
  771. dev->stats.rx_errors++;
  772. if (unlikely(rxstat & 0x00000002)) {
  773. dev->stats.rx_crc_errors++;
  774. crc_err = 1;
  775. }
  776. }
  777. if (likely(!crc_err)) {
  778. if (unlikely((rxstat & 0x00001020) == 0x00001020)) {
  779. /* Frame type indicates length,
  780. * and length error is set */
  781. dev->stats.rx_length_errors++;
  782. }
  783. if (rxstat & RX_STS_MCAST_)
  784. dev->stats.multicast++;
  785. }
  786. }
  787. /* Quickly dumps bad packets */
  788. static void
  789. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
  790. {
  791. unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
  792. if (likely(pktwords >= 4)) {
  793. unsigned int timeout = 500;
  794. unsigned int val;
  795. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  796. do {
  797. udelay(1);
  798. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  799. } while (--timeout && (val & RX_DP_CTRL_RX_FFWD_));
  800. if (unlikely(timeout == 0))
  801. SMSC_WARNING(HW, "Timed out waiting for "
  802. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  803. } else {
  804. unsigned int temp;
  805. while (pktwords--)
  806. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  807. }
  808. }
  809. /* NAPI poll function */
  810. static int smsc911x_poll(struct napi_struct *napi, int budget)
  811. {
  812. struct smsc911x_data *pdata =
  813. container_of(napi, struct smsc911x_data, napi);
  814. struct net_device *dev = pdata->dev;
  815. int npackets = 0;
  816. while (likely(netif_running(dev)) && (npackets < budget)) {
  817. unsigned int pktlength;
  818. unsigned int pktwords;
  819. struct sk_buff *skb;
  820. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  821. if (!rxstat) {
  822. unsigned int temp;
  823. /* We processed all packets available. Tell NAPI it can
  824. * stop polling then re-enable rx interrupts */
  825. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  826. netif_rx_complete(napi);
  827. temp = smsc911x_reg_read(pdata, INT_EN);
  828. temp |= INT_EN_RSFL_EN_;
  829. smsc911x_reg_write(pdata, INT_EN, temp);
  830. break;
  831. }
  832. /* Count packet for NAPI scheduling, even if it has an error.
  833. * Error packets still require cycles to discard */
  834. npackets++;
  835. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  836. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  837. smsc911x_rx_counterrors(dev, rxstat);
  838. if (unlikely(rxstat & RX_STS_ES_)) {
  839. SMSC_WARNING(RX_ERR,
  840. "Discarding packet with error bit set");
  841. /* Packet has an error, discard it and continue with
  842. * the next */
  843. smsc911x_rx_fastforward(pdata, pktwords);
  844. dev->stats.rx_dropped++;
  845. continue;
  846. }
  847. skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
  848. if (unlikely(!skb)) {
  849. SMSC_WARNING(RX_ERR,
  850. "Unable to allocate skb for rx packet");
  851. /* Drop the packet and stop this polling iteration */
  852. smsc911x_rx_fastforward(pdata, pktwords);
  853. dev->stats.rx_dropped++;
  854. break;
  855. }
  856. skb->data = skb->head;
  857. skb_reset_tail_pointer(skb);
  858. /* Align IP on 16B boundary */
  859. skb_reserve(skb, NET_IP_ALIGN);
  860. skb_put(skb, pktlength - 4);
  861. smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
  862. pktwords);
  863. skb->protocol = eth_type_trans(skb, dev);
  864. skb->ip_summed = CHECKSUM_NONE;
  865. netif_receive_skb(skb);
  866. /* Update counters */
  867. dev->stats.rx_packets++;
  868. dev->stats.rx_bytes += (pktlength - 4);
  869. dev->last_rx = jiffies;
  870. }
  871. /* Return total received packets */
  872. return npackets;
  873. }
  874. /* Returns hash bit number for given MAC address
  875. * Example:
  876. * 01 00 5E 00 00 01 -> returns bit number 31 */
  877. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  878. {
  879. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  880. }
  881. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  882. {
  883. /* Performs the multicast & mac_cr update. This is called when
  884. * safe on the current hardware, and with the mac_lock held */
  885. unsigned int mac_cr;
  886. SMSC_ASSERT_MAC_LOCK(pdata);
  887. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  888. mac_cr |= pdata->set_bits_mask;
  889. mac_cr &= ~(pdata->clear_bits_mask);
  890. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  891. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  892. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  893. SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  894. mac_cr, pdata->hashhi, pdata->hashlo);
  895. }
  896. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  897. {
  898. unsigned int mac_cr;
  899. /* This function is only called for older LAN911x devices
  900. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  901. * be modified during Rx - newer devices immediately update the
  902. * registers.
  903. *
  904. * This is called from interrupt context */
  905. spin_lock(&pdata->mac_lock);
  906. /* Check Rx has stopped */
  907. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  908. SMSC_WARNING(DRV, "Rx not stopped");
  909. /* Perform the update - safe to do now Rx has stopped */
  910. smsc911x_rx_multicast_update(pdata);
  911. /* Re-enable Rx */
  912. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  913. mac_cr |= MAC_CR_RXEN_;
  914. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  915. pdata->multicast_update_pending = 0;
  916. spin_unlock(&pdata->mac_lock);
  917. }
  918. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  919. {
  920. unsigned int timeout;
  921. unsigned int temp;
  922. /* Reset the LAN911x */
  923. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  924. timeout = 10;
  925. do {
  926. udelay(10);
  927. temp = smsc911x_reg_read(pdata, HW_CFG);
  928. } while ((--timeout) && (temp & HW_CFG_SRST_));
  929. if (unlikely(temp & HW_CFG_SRST_)) {
  930. SMSC_WARNING(DRV, "Failed to complete reset");
  931. return -EIO;
  932. }
  933. return 0;
  934. }
  935. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  936. static void
  937. smsc911x_set_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  938. {
  939. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  940. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  941. (dev_addr[1] << 8) | dev_addr[0];
  942. SMSC_ASSERT_MAC_LOCK(pdata);
  943. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  944. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  945. }
  946. static int smsc911x_open(struct net_device *dev)
  947. {
  948. struct smsc911x_data *pdata = netdev_priv(dev);
  949. unsigned int timeout;
  950. unsigned int temp;
  951. unsigned int intcfg;
  952. /* if the phy is not yet registered, retry later*/
  953. if (!pdata->phy_dev) {
  954. SMSC_WARNING(HW, "phy_dev is NULL");
  955. return -EAGAIN;
  956. }
  957. if (!is_valid_ether_addr(dev->dev_addr)) {
  958. SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
  959. return -EADDRNOTAVAIL;
  960. }
  961. /* Reset the LAN911x */
  962. if (smsc911x_soft_reset(pdata)) {
  963. SMSC_WARNING(HW, "soft reset failed");
  964. return -EIO;
  965. }
  966. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  967. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  968. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  969. timeout = 50;
  970. while ((timeout--) &&
  971. (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
  972. udelay(10);
  973. }
  974. if (unlikely(timeout == 0))
  975. SMSC_WARNING(IFUP,
  976. "Timed out waiting for EEPROM busy bit to clear");
  977. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  978. /* The soft reset above cleared the device's MAC address,
  979. * restore it from local copy (set in probe) */
  980. spin_lock_irq(&pdata->mac_lock);
  981. smsc911x_set_mac_address(pdata, dev->dev_addr);
  982. spin_unlock_irq(&pdata->mac_lock);
  983. /* Initialise irqs, but leave all sources disabled */
  984. smsc911x_reg_write(pdata, INT_EN, 0);
  985. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  986. /* Set interrupt deassertion to 100uS */
  987. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  988. if (pdata->config.irq_polarity) {
  989. SMSC_TRACE(IFUP, "irq polarity: active high");
  990. intcfg |= INT_CFG_IRQ_POL_;
  991. } else {
  992. SMSC_TRACE(IFUP, "irq polarity: active low");
  993. }
  994. if (pdata->config.irq_type) {
  995. SMSC_TRACE(IFUP, "irq type: push-pull");
  996. intcfg |= INT_CFG_IRQ_TYPE_;
  997. } else {
  998. SMSC_TRACE(IFUP, "irq type: open drain");
  999. }
  1000. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1001. SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
  1002. pdata->software_irq_signal = 0;
  1003. smp_wmb();
  1004. temp = smsc911x_reg_read(pdata, INT_EN);
  1005. temp |= INT_EN_SW_INT_EN_;
  1006. smsc911x_reg_write(pdata, INT_EN, temp);
  1007. timeout = 1000;
  1008. while (timeout--) {
  1009. if (pdata->software_irq_signal)
  1010. break;
  1011. msleep(1);
  1012. }
  1013. if (!pdata->software_irq_signal) {
  1014. dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
  1015. dev->irq);
  1016. return -ENODEV;
  1017. }
  1018. SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
  1019. dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1020. (unsigned long)pdata->ioaddr, dev->irq);
  1021. /* Reset the last known duplex and carrier */
  1022. pdata->last_duplex = -1;
  1023. pdata->last_carrier = -1;
  1024. /* Bring the PHY up */
  1025. phy_start(pdata->phy_dev);
  1026. temp = smsc911x_reg_read(pdata, HW_CFG);
  1027. /* Preserve TX FIFO size and external PHY configuration */
  1028. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1029. temp |= HW_CFG_SF_;
  1030. smsc911x_reg_write(pdata, HW_CFG, temp);
  1031. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1032. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1033. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1034. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1035. /* set RX Data offset to 2 bytes for alignment */
  1036. smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
  1037. /* enable NAPI polling before enabling RX interrupts */
  1038. napi_enable(&pdata->napi);
  1039. temp = smsc911x_reg_read(pdata, INT_EN);
  1040. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_);
  1041. smsc911x_reg_write(pdata, INT_EN, temp);
  1042. spin_lock_irq(&pdata->mac_lock);
  1043. temp = smsc911x_mac_read(pdata, MAC_CR);
  1044. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1045. smsc911x_mac_write(pdata, MAC_CR, temp);
  1046. spin_unlock_irq(&pdata->mac_lock);
  1047. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1048. netif_start_queue(dev);
  1049. return 0;
  1050. }
  1051. /* Entry point for stopping the interface */
  1052. static int smsc911x_stop(struct net_device *dev)
  1053. {
  1054. struct smsc911x_data *pdata = netdev_priv(dev);
  1055. unsigned int temp;
  1056. /* Disable all device interrupts */
  1057. temp = smsc911x_reg_read(pdata, INT_CFG);
  1058. temp &= ~INT_CFG_IRQ_EN_;
  1059. smsc911x_reg_write(pdata, INT_CFG, temp);
  1060. /* Stop Tx and Rx polling */
  1061. netif_stop_queue(dev);
  1062. napi_disable(&pdata->napi);
  1063. /* At this point all Rx and Tx activity is stopped */
  1064. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1065. smsc911x_tx_update_txcounters(dev);
  1066. /* Bring the PHY down */
  1067. if (pdata->phy_dev)
  1068. phy_stop(pdata->phy_dev);
  1069. SMSC_TRACE(IFDOWN, "Interface stopped");
  1070. return 0;
  1071. }
  1072. /* Entry point for transmitting a packet */
  1073. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1074. {
  1075. struct smsc911x_data *pdata = netdev_priv(dev);
  1076. unsigned int freespace;
  1077. unsigned int tx_cmd_a;
  1078. unsigned int tx_cmd_b;
  1079. unsigned int temp;
  1080. u32 wrsz;
  1081. ulong bufp;
  1082. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1083. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1084. SMSC_WARNING(TX_ERR,
  1085. "Tx data fifo low, space available: %d", freespace);
  1086. /* Word alignment adjustment */
  1087. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1088. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1089. tx_cmd_a |= (unsigned int)skb->len;
  1090. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1091. tx_cmd_b |= (unsigned int)skb->len;
  1092. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1093. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1094. bufp = (ulong)skb->data & (~0x3);
  1095. wrsz = (u32)skb->len + 3;
  1096. wrsz += (u32)((ulong)skb->data & 0x3);
  1097. wrsz >>= 2;
  1098. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1099. freespace -= (skb->len + 32);
  1100. dev_kfree_skb(skb);
  1101. dev->trans_start = jiffies;
  1102. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1103. smsc911x_tx_update_txcounters(dev);
  1104. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1105. netif_stop_queue(dev);
  1106. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1107. temp &= 0x00FFFFFF;
  1108. temp |= 0x32000000;
  1109. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1110. }
  1111. return NETDEV_TX_OK;
  1112. }
  1113. /* Entry point for getting status counters */
  1114. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1115. {
  1116. struct smsc911x_data *pdata = netdev_priv(dev);
  1117. smsc911x_tx_update_txcounters(dev);
  1118. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1119. return &dev->stats;
  1120. }
  1121. /* Entry point for setting addressing modes */
  1122. static void smsc911x_set_multicast_list(struct net_device *dev)
  1123. {
  1124. struct smsc911x_data *pdata = netdev_priv(dev);
  1125. unsigned long flags;
  1126. if (dev->flags & IFF_PROMISC) {
  1127. /* Enabling promiscuous mode */
  1128. pdata->set_bits_mask = MAC_CR_PRMS_;
  1129. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1130. pdata->hashhi = 0;
  1131. pdata->hashlo = 0;
  1132. } else if (dev->flags & IFF_ALLMULTI) {
  1133. /* Enabling all multicast mode */
  1134. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1135. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1136. pdata->hashhi = 0;
  1137. pdata->hashlo = 0;
  1138. } else if (dev->mc_count > 0) {
  1139. /* Enabling specific multicast addresses */
  1140. unsigned int hash_high = 0;
  1141. unsigned int hash_low = 0;
  1142. unsigned int count = 0;
  1143. struct dev_mc_list *mc_list = dev->mc_list;
  1144. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1145. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1146. while (mc_list) {
  1147. count++;
  1148. if ((mc_list->dmi_addrlen) == ETH_ALEN) {
  1149. unsigned int bitnum =
  1150. smsc911x_hash(mc_list->dmi_addr);
  1151. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1152. if (bitnum & 0x20)
  1153. hash_high |= mask;
  1154. else
  1155. hash_low |= mask;
  1156. } else {
  1157. SMSC_WARNING(DRV, "dmi_addrlen != 6");
  1158. }
  1159. mc_list = mc_list->next;
  1160. }
  1161. if (count != (unsigned int)dev->mc_count)
  1162. SMSC_WARNING(DRV, "mc_count != dev->mc_count");
  1163. pdata->hashhi = hash_high;
  1164. pdata->hashlo = hash_low;
  1165. } else {
  1166. /* Enabling local MAC address only */
  1167. pdata->set_bits_mask = 0;
  1168. pdata->clear_bits_mask =
  1169. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1170. pdata->hashhi = 0;
  1171. pdata->hashlo = 0;
  1172. }
  1173. spin_lock_irqsave(&pdata->mac_lock, flags);
  1174. if (pdata->generation <= 1) {
  1175. /* Older hardware revision - cannot change these flags while
  1176. * receiving data */
  1177. if (!pdata->multicast_update_pending) {
  1178. unsigned int temp;
  1179. SMSC_TRACE(HW, "scheduling mcast update");
  1180. pdata->multicast_update_pending = 1;
  1181. /* Request the hardware to stop, then perform the
  1182. * update when we get an RX_STOP interrupt */
  1183. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1184. temp = smsc911x_reg_read(pdata, INT_EN);
  1185. temp |= INT_EN_RXSTOP_INT_EN_;
  1186. smsc911x_reg_write(pdata, INT_EN, temp);
  1187. temp = smsc911x_mac_read(pdata, MAC_CR);
  1188. temp &= ~(MAC_CR_RXEN_);
  1189. smsc911x_mac_write(pdata, MAC_CR, temp);
  1190. } else {
  1191. /* There is another update pending, this should now
  1192. * use the newer values */
  1193. }
  1194. } else {
  1195. /* Newer hardware revision - can write immediately */
  1196. smsc911x_rx_multicast_update(pdata);
  1197. }
  1198. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1199. }
  1200. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1201. {
  1202. struct net_device *dev = dev_id;
  1203. struct smsc911x_data *pdata = netdev_priv(dev);
  1204. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1205. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1206. int serviced = IRQ_NONE;
  1207. u32 temp;
  1208. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1209. temp = smsc911x_reg_read(pdata, INT_EN);
  1210. temp &= (~INT_EN_SW_INT_EN_);
  1211. smsc911x_reg_write(pdata, INT_EN, temp);
  1212. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1213. pdata->software_irq_signal = 1;
  1214. smp_wmb();
  1215. serviced = IRQ_HANDLED;
  1216. }
  1217. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1218. /* Called when there is a multicast update scheduled and
  1219. * it is now safe to complete the update */
  1220. SMSC_TRACE(INTR, "RX Stop interrupt");
  1221. temp = smsc911x_reg_read(pdata, INT_EN);
  1222. temp &= (~INT_EN_RXSTOP_INT_EN_);
  1223. smsc911x_reg_write(pdata, INT_EN, temp);
  1224. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1225. smsc911x_rx_multicast_update_workaround(pdata);
  1226. serviced = IRQ_HANDLED;
  1227. }
  1228. if (intsts & inten & INT_STS_TDFA_) {
  1229. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1230. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1231. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1232. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1233. netif_wake_queue(dev);
  1234. serviced = IRQ_HANDLED;
  1235. }
  1236. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1237. SMSC_TRACE(INTR, "RX Error interrupt");
  1238. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1239. serviced = IRQ_HANDLED;
  1240. }
  1241. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1242. if (likely(netif_rx_schedule_prep(&pdata->napi))) {
  1243. /* Disable Rx interrupts */
  1244. temp = smsc911x_reg_read(pdata, INT_EN);
  1245. temp &= (~INT_EN_RSFL_EN_);
  1246. smsc911x_reg_write(pdata, INT_EN, temp);
  1247. /* Schedule a NAPI poll */
  1248. __netif_rx_schedule(&pdata->napi);
  1249. } else {
  1250. SMSC_WARNING(RX_ERR,
  1251. "netif_rx_schedule_prep failed");
  1252. }
  1253. serviced = IRQ_HANDLED;
  1254. }
  1255. return serviced;
  1256. }
  1257. #ifdef CONFIG_NET_POLL_CONTROLLER
  1258. static void smsc911x_poll_controller(struct net_device *dev)
  1259. {
  1260. disable_irq(dev->irq);
  1261. smsc911x_irqhandler(0, dev);
  1262. enable_irq(dev->irq);
  1263. }
  1264. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1265. /* Standard ioctls for mii-tool */
  1266. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1267. {
  1268. struct smsc911x_data *pdata = netdev_priv(dev);
  1269. if (!netif_running(dev) || !pdata->phy_dev)
  1270. return -EINVAL;
  1271. return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
  1272. }
  1273. static int
  1274. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1275. {
  1276. struct smsc911x_data *pdata = netdev_priv(dev);
  1277. cmd->maxtxpkt = 1;
  1278. cmd->maxrxpkt = 1;
  1279. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1280. }
  1281. static int
  1282. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1283. {
  1284. struct smsc911x_data *pdata = netdev_priv(dev);
  1285. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1286. }
  1287. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1288. struct ethtool_drvinfo *info)
  1289. {
  1290. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1291. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1292. strlcpy(info->bus_info, dev->dev.parent->bus_id,
  1293. sizeof(info->bus_info));
  1294. }
  1295. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1296. {
  1297. struct smsc911x_data *pdata = netdev_priv(dev);
  1298. return phy_start_aneg(pdata->phy_dev);
  1299. }
  1300. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1301. {
  1302. struct smsc911x_data *pdata = netdev_priv(dev);
  1303. return pdata->msg_enable;
  1304. }
  1305. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1306. {
  1307. struct smsc911x_data *pdata = netdev_priv(dev);
  1308. pdata->msg_enable = level;
  1309. }
  1310. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1311. {
  1312. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1313. sizeof(u32);
  1314. }
  1315. static void
  1316. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1317. void *buf)
  1318. {
  1319. struct smsc911x_data *pdata = netdev_priv(dev);
  1320. struct phy_device *phy_dev = pdata->phy_dev;
  1321. unsigned long flags;
  1322. unsigned int i;
  1323. unsigned int j = 0;
  1324. u32 *data = buf;
  1325. regs->version = pdata->idrev;
  1326. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1327. data[j++] = smsc911x_reg_read(pdata, i);
  1328. for (i = MAC_CR; i <= WUCSR; i++) {
  1329. spin_lock_irqsave(&pdata->mac_lock, flags);
  1330. data[j++] = smsc911x_mac_read(pdata, i);
  1331. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1332. }
  1333. for (i = 0; i <= 31; i++)
  1334. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1335. }
  1336. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1337. {
  1338. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1339. temp &= ~GPIO_CFG_EEPR_EN_;
  1340. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1341. msleep(1);
  1342. }
  1343. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1344. {
  1345. int timeout = 100;
  1346. u32 e2cmd;
  1347. SMSC_TRACE(DRV, "op 0x%08x", op);
  1348. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1349. SMSC_WARNING(DRV, "Busy at start");
  1350. return -EBUSY;
  1351. }
  1352. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1353. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1354. do {
  1355. msleep(1);
  1356. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1357. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1358. if (!timeout) {
  1359. SMSC_TRACE(DRV, "TIMED OUT");
  1360. return -EAGAIN;
  1361. }
  1362. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1363. SMSC_TRACE(DRV, "Error occured during eeprom operation");
  1364. return -EINVAL;
  1365. }
  1366. return 0;
  1367. }
  1368. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1369. u8 address, u8 *data)
  1370. {
  1371. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1372. int ret;
  1373. SMSC_TRACE(DRV, "address 0x%x", address);
  1374. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1375. if (!ret)
  1376. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1377. return ret;
  1378. }
  1379. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1380. u8 address, u8 data)
  1381. {
  1382. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1383. int ret;
  1384. SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
  1385. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1386. if (!ret) {
  1387. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1388. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1389. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1390. }
  1391. return ret;
  1392. }
  1393. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1394. {
  1395. return SMSC911X_EEPROM_SIZE;
  1396. }
  1397. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1398. struct ethtool_eeprom *eeprom, u8 *data)
  1399. {
  1400. struct smsc911x_data *pdata = netdev_priv(dev);
  1401. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1402. int len;
  1403. int i;
  1404. smsc911x_eeprom_enable_access(pdata);
  1405. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1406. for (i = 0; i < len; i++) {
  1407. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1408. if (ret < 0) {
  1409. eeprom->len = 0;
  1410. return ret;
  1411. }
  1412. }
  1413. memcpy(data, &eeprom_data[eeprom->offset], len);
  1414. eeprom->len = len;
  1415. return 0;
  1416. }
  1417. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1418. struct ethtool_eeprom *eeprom, u8 *data)
  1419. {
  1420. int ret;
  1421. struct smsc911x_data *pdata = netdev_priv(dev);
  1422. smsc911x_eeprom_enable_access(pdata);
  1423. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1424. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1425. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1426. /* Single byte write, according to man page */
  1427. eeprom->len = 1;
  1428. return ret;
  1429. }
  1430. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1431. .get_settings = smsc911x_ethtool_getsettings,
  1432. .set_settings = smsc911x_ethtool_setsettings,
  1433. .get_link = ethtool_op_get_link,
  1434. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1435. .nway_reset = smsc911x_ethtool_nwayreset,
  1436. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1437. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1438. .get_regs_len = smsc911x_ethtool_getregslen,
  1439. .get_regs = smsc911x_ethtool_getregs,
  1440. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1441. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1442. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1443. };
  1444. static const struct net_device_ops smsc911x_netdev_ops = {
  1445. .ndo_open = smsc911x_open,
  1446. .ndo_stop = smsc911x_stop,
  1447. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1448. .ndo_get_stats = smsc911x_get_stats,
  1449. .ndo_set_multicast_list = smsc911x_set_multicast_list,
  1450. .ndo_do_ioctl = smsc911x_do_ioctl,
  1451. .ndo_validate_addr = eth_validate_addr,
  1452. .ndo_set_mac_address = eth_mac_addr,
  1453. #ifdef CONFIG_NET_POLL_CONTROLLER
  1454. .ndo_poll_controller = smsc911x_poll_controller,
  1455. #endif
  1456. };
  1457. /* Initializing private device structures, only called from probe */
  1458. static int __devinit smsc911x_init(struct net_device *dev)
  1459. {
  1460. struct smsc911x_data *pdata = netdev_priv(dev);
  1461. unsigned int byte_test;
  1462. SMSC_TRACE(PROBE, "Driver Parameters:");
  1463. SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
  1464. (unsigned long)pdata->ioaddr);
  1465. SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
  1466. SMSC_TRACE(PROBE, "PHY will be autodetected.");
  1467. spin_lock_init(&pdata->dev_lock);
  1468. if (pdata->ioaddr == 0) {
  1469. SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
  1470. return -ENODEV;
  1471. }
  1472. /* Check byte ordering */
  1473. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1474. SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
  1475. if (byte_test == 0x43218765) {
  1476. SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
  1477. "applying WORD_SWAP");
  1478. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1479. /* 1 dummy read of BYTE_TEST is needed after a write to
  1480. * WORD_SWAP before its contents are valid */
  1481. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1482. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1483. }
  1484. if (byte_test != 0x87654321) {
  1485. SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
  1486. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1487. SMSC_WARNING(PROBE,
  1488. "top 16 bits equal to bottom 16 bits");
  1489. SMSC_TRACE(PROBE, "This may mean the chip is set "
  1490. "for 32 bit while the bus is reading 16 bit");
  1491. }
  1492. return -ENODEV;
  1493. }
  1494. /* Default generation to zero (all workarounds apply) */
  1495. pdata->generation = 0;
  1496. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1497. switch (pdata->idrev & 0xFFFF0000) {
  1498. case 0x01180000:
  1499. case 0x01170000:
  1500. case 0x01160000:
  1501. case 0x01150000:
  1502. /* LAN911[5678] family */
  1503. pdata->generation = pdata->idrev & 0x0000FFFF;
  1504. break;
  1505. case 0x118A0000:
  1506. case 0x117A0000:
  1507. case 0x116A0000:
  1508. case 0x115A0000:
  1509. /* LAN921[5678] family */
  1510. pdata->generation = 3;
  1511. break;
  1512. case 0x92100000:
  1513. case 0x92110000:
  1514. case 0x92200000:
  1515. case 0x92210000:
  1516. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1517. pdata->generation = 4;
  1518. break;
  1519. default:
  1520. SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
  1521. pdata->idrev);
  1522. return -ENODEV;
  1523. }
  1524. SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
  1525. pdata->idrev, pdata->generation);
  1526. if (pdata->generation == 0)
  1527. SMSC_WARNING(PROBE,
  1528. "This driver is not intended for this chip revision");
  1529. /* Reset the LAN911x */
  1530. if (smsc911x_soft_reset(pdata))
  1531. return -ENODEV;
  1532. /* Disable all interrupt sources until we bring the device up */
  1533. smsc911x_reg_write(pdata, INT_EN, 0);
  1534. ether_setup(dev);
  1535. dev->flags |= IFF_MULTICAST;
  1536. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1537. dev->netdev_ops = &smsc911x_netdev_ops;
  1538. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1539. return 0;
  1540. }
  1541. static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
  1542. {
  1543. struct net_device *dev;
  1544. struct smsc911x_data *pdata;
  1545. struct resource *res;
  1546. dev = platform_get_drvdata(pdev);
  1547. BUG_ON(!dev);
  1548. pdata = netdev_priv(dev);
  1549. BUG_ON(!pdata);
  1550. BUG_ON(!pdata->ioaddr);
  1551. BUG_ON(!pdata->phy_dev);
  1552. SMSC_TRACE(IFDOWN, "Stopping driver.");
  1553. phy_disconnect(pdata->phy_dev);
  1554. pdata->phy_dev = NULL;
  1555. mdiobus_unregister(pdata->mii_bus);
  1556. mdiobus_free(pdata->mii_bus);
  1557. platform_set_drvdata(pdev, NULL);
  1558. unregister_netdev(dev);
  1559. free_irq(dev->irq, dev);
  1560. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1561. "smsc911x-memory");
  1562. if (!res)
  1563. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1564. release_mem_region(res->start, res->end - res->start);
  1565. iounmap(pdata->ioaddr);
  1566. free_netdev(dev);
  1567. return 0;
  1568. }
  1569. static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
  1570. {
  1571. struct net_device *dev;
  1572. struct smsc911x_data *pdata;
  1573. struct smsc911x_platform_config *config = pdev->dev.platform_data;
  1574. struct resource *res;
  1575. unsigned int intcfg = 0;
  1576. int res_size;
  1577. int retval;
  1578. DECLARE_MAC_BUF(mac);
  1579. pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
  1580. /* platform data specifies irq & dynamic bus configuration */
  1581. if (!pdev->dev.platform_data) {
  1582. pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
  1583. retval = -ENODEV;
  1584. goto out_0;
  1585. }
  1586. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1587. "smsc911x-memory");
  1588. if (!res)
  1589. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1590. if (!res) {
  1591. pr_warning("%s: Could not allocate resource.\n",
  1592. SMSC_CHIPNAME);
  1593. retval = -ENODEV;
  1594. goto out_0;
  1595. }
  1596. res_size = res->end - res->start;
  1597. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1598. retval = -EBUSY;
  1599. goto out_0;
  1600. }
  1601. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1602. if (!dev) {
  1603. pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
  1604. retval = -ENOMEM;
  1605. goto out_release_io_1;
  1606. }
  1607. SET_NETDEV_DEV(dev, &pdev->dev);
  1608. pdata = netdev_priv(dev);
  1609. dev->irq = platform_get_irq(pdev, 0);
  1610. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1611. /* copy config parameters across to pdata */
  1612. memcpy(&pdata->config, config, sizeof(pdata->config));
  1613. pdata->dev = dev;
  1614. pdata->msg_enable = ((1 << debug) - 1);
  1615. if (pdata->ioaddr == NULL) {
  1616. SMSC_WARNING(PROBE,
  1617. "Error smsc911x base address invalid");
  1618. retval = -ENOMEM;
  1619. goto out_free_netdev_2;
  1620. }
  1621. retval = smsc911x_init(dev);
  1622. if (retval < 0)
  1623. goto out_unmap_io_3;
  1624. /* configure irq polarity and type before connecting isr */
  1625. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  1626. intcfg |= INT_CFG_IRQ_POL_;
  1627. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  1628. intcfg |= INT_CFG_IRQ_TYPE_;
  1629. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1630. /* Ensure interrupts are globally disabled before connecting ISR */
  1631. smsc911x_reg_write(pdata, INT_EN, 0);
  1632. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1633. retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED,
  1634. dev->name, dev);
  1635. if (retval) {
  1636. SMSC_WARNING(PROBE,
  1637. "Unable to claim requested irq: %d", dev->irq);
  1638. goto out_unmap_io_3;
  1639. }
  1640. platform_set_drvdata(pdev, dev);
  1641. retval = register_netdev(dev);
  1642. if (retval) {
  1643. SMSC_WARNING(PROBE,
  1644. "Error %i registering device", retval);
  1645. goto out_unset_drvdata_4;
  1646. } else {
  1647. SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
  1648. }
  1649. spin_lock_init(&pdata->mac_lock);
  1650. retval = smsc911x_mii_init(pdev, dev);
  1651. if (retval) {
  1652. SMSC_WARNING(PROBE,
  1653. "Error %i initialising mii", retval);
  1654. goto out_unregister_netdev_5;
  1655. }
  1656. spin_lock_irq(&pdata->mac_lock);
  1657. /* Check if mac address has been specified when bringing interface up */
  1658. if (is_valid_ether_addr(dev->dev_addr)) {
  1659. smsc911x_set_mac_address(pdata, dev->dev_addr);
  1660. SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
  1661. } else {
  1662. /* Try reading mac address from device. if EEPROM is present
  1663. * it will already have been set */
  1664. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1665. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1666. dev->dev_addr[0] = (u8)(mac_low32);
  1667. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1668. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1669. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1670. dev->dev_addr[4] = (u8)(mac_high16);
  1671. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1672. if (is_valid_ether_addr(dev->dev_addr)) {
  1673. /* eeprom values are valid so use them */
  1674. SMSC_TRACE(PROBE,
  1675. "Mac Address is read from LAN911x EEPROM");
  1676. } else {
  1677. /* eeprom values are invalid, generate random MAC */
  1678. random_ether_addr(dev->dev_addr);
  1679. smsc911x_set_mac_address(pdata, dev->dev_addr);
  1680. SMSC_TRACE(PROBE,
  1681. "MAC Address is set to random_ether_addr");
  1682. }
  1683. }
  1684. spin_unlock_irq(&pdata->mac_lock);
  1685. dev_info(&dev->dev, "MAC Address: %s\n",
  1686. print_mac(mac, dev->dev_addr));
  1687. return 0;
  1688. out_unregister_netdev_5:
  1689. unregister_netdev(dev);
  1690. out_unset_drvdata_4:
  1691. platform_set_drvdata(pdev, NULL);
  1692. free_irq(dev->irq, dev);
  1693. out_unmap_io_3:
  1694. iounmap(pdata->ioaddr);
  1695. out_free_netdev_2:
  1696. free_netdev(dev);
  1697. out_release_io_1:
  1698. release_mem_region(res->start, res->end - res->start);
  1699. out_0:
  1700. return retval;
  1701. }
  1702. static struct platform_driver smsc911x_driver = {
  1703. .probe = smsc911x_drv_probe,
  1704. .remove = smsc911x_drv_remove,
  1705. .driver = {
  1706. .name = SMSC_CHIPNAME,
  1707. },
  1708. };
  1709. /* Entry point for loading the module */
  1710. static int __init smsc911x_init_module(void)
  1711. {
  1712. return platform_driver_register(&smsc911x_driver);
  1713. }
  1714. /* entry point for unloading the module */
  1715. static void __exit smsc911x_cleanup_module(void)
  1716. {
  1717. platform_driver_unregister(&smsc911x_driver);
  1718. }
  1719. module_init(smsc911x_init_module);
  1720. module_exit(smsc911x_cleanup_module);