netxen_nic_ctx.c 17 KB

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  1. /*
  2. * Copyright (C) 2003 - 2008 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. */
  30. #include "netxen_nic_hw.h"
  31. #include "netxen_nic.h"
  32. #include "netxen_nic_phan_reg.h"
  33. #define NXHAL_VERSION 1
  34. static int
  35. netxen_api_lock(struct netxen_adapter *adapter)
  36. {
  37. u32 done = 0, timeout = 0;
  38. for (;;) {
  39. /* Acquire PCIE HW semaphore5 */
  40. netxen_nic_read_w0(adapter,
  41. NETXEN_PCIE_REG(PCIE_SEM5_LOCK), &done);
  42. if (done == 1)
  43. break;
  44. if (++timeout >= NX_OS_CRB_RETRY_COUNT) {
  45. printk(KERN_ERR "%s: lock timeout.\n", __func__);
  46. return -1;
  47. }
  48. msleep(1);
  49. }
  50. #if 0
  51. netxen_nic_write_w1(adapter,
  52. NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER);
  53. #endif
  54. return 0;
  55. }
  56. static int
  57. netxen_api_unlock(struct netxen_adapter *adapter)
  58. {
  59. u32 val;
  60. /* Release PCIE HW semaphore5 */
  61. netxen_nic_read_w0(adapter,
  62. NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK), &val);
  63. return 0;
  64. }
  65. static u32
  66. netxen_poll_rsp(struct netxen_adapter *adapter)
  67. {
  68. u32 rsp = NX_CDRP_RSP_OK;
  69. int timeout = 0;
  70. do {
  71. /* give atleast 1ms for firmware to respond */
  72. msleep(1);
  73. if (++timeout > NX_OS_CRB_RETRY_COUNT)
  74. return NX_CDRP_RSP_TIMEOUT;
  75. netxen_nic_read_w1(adapter, NX_CDRP_CRB_OFFSET, &rsp);
  76. } while (!NX_CDRP_IS_RSP(rsp));
  77. return rsp;
  78. }
  79. static u32
  80. netxen_issue_cmd(struct netxen_adapter *adapter,
  81. u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
  82. {
  83. u32 rsp;
  84. u32 signature = 0;
  85. u32 rcode = NX_RCODE_SUCCESS;
  86. signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version);
  87. /* Acquire semaphore before accessing CRB */
  88. if (netxen_api_lock(adapter))
  89. return NX_RCODE_TIMEOUT;
  90. netxen_nic_write_w1(adapter, NX_SIGN_CRB_OFFSET, signature);
  91. netxen_nic_write_w1(adapter, NX_ARG1_CRB_OFFSET, arg1);
  92. netxen_nic_write_w1(adapter, NX_ARG2_CRB_OFFSET, arg2);
  93. netxen_nic_write_w1(adapter, NX_ARG3_CRB_OFFSET, arg3);
  94. netxen_nic_write_w1(adapter, NX_CDRP_CRB_OFFSET,
  95. NX_CDRP_FORM_CMD(cmd));
  96. rsp = netxen_poll_rsp(adapter);
  97. if (rsp == NX_CDRP_RSP_TIMEOUT) {
  98. printk(KERN_ERR "%s: card response timeout.\n",
  99. netxen_nic_driver_name);
  100. rcode = NX_RCODE_TIMEOUT;
  101. } else if (rsp == NX_CDRP_RSP_FAIL) {
  102. netxen_nic_read_w1(adapter, NX_ARG1_CRB_OFFSET, &rcode);
  103. printk(KERN_ERR "%s: failed card response code:0x%x\n",
  104. netxen_nic_driver_name, rcode);
  105. }
  106. /* Release semaphore */
  107. netxen_api_unlock(adapter);
  108. return rcode;
  109. }
  110. int
  111. nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
  112. {
  113. u32 rcode = NX_RCODE_SUCCESS;
  114. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0];
  115. if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
  116. rcode = netxen_issue_cmd(adapter,
  117. adapter->ahw.pci_func,
  118. NXHAL_VERSION,
  119. recv_ctx->context_id,
  120. mtu,
  121. 0,
  122. NX_CDRP_CMD_SET_MTU);
  123. if (rcode != NX_RCODE_SUCCESS)
  124. return -EIO;
  125. return 0;
  126. }
  127. static int
  128. nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
  129. {
  130. void *addr;
  131. nx_hostrq_rx_ctx_t *prq;
  132. nx_cardrsp_rx_ctx_t *prsp;
  133. nx_hostrq_rds_ring_t *prq_rds;
  134. nx_hostrq_sds_ring_t *prq_sds;
  135. nx_cardrsp_rds_ring_t *prsp_rds;
  136. nx_cardrsp_sds_ring_t *prsp_sds;
  137. struct nx_host_rds_ring *rds_ring;
  138. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  139. u64 phys_addr;
  140. int i, nrds_rings, nsds_rings;
  141. size_t rq_size, rsp_size;
  142. u32 cap, reg, val;
  143. int err;
  144. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0];
  145. /* only one sds ring for now */
  146. nrds_rings = adapter->max_rds_rings;
  147. nsds_rings = 1;
  148. rq_size =
  149. SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
  150. rsp_size =
  151. SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
  152. addr = pci_alloc_consistent(adapter->pdev,
  153. rq_size, &hostrq_phys_addr);
  154. if (addr == NULL)
  155. return -ENOMEM;
  156. prq = (nx_hostrq_rx_ctx_t *)addr;
  157. addr = pci_alloc_consistent(adapter->pdev,
  158. rsp_size, &cardrsp_phys_addr);
  159. if (addr == NULL) {
  160. err = -ENOMEM;
  161. goto out_free_rq;
  162. }
  163. prsp = (nx_cardrsp_rx_ctx_t *)addr;
  164. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  165. cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
  166. cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
  167. prq->capabilities[0] = cpu_to_le32(cap);
  168. prq->host_int_crb_mode =
  169. cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
  170. prq->host_rds_crb_mode =
  171. cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
  172. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  173. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  174. prq->rds_ring_offset = cpu_to_le32(0);
  175. val = le32_to_cpu(prq->rds_ring_offset) +
  176. (sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
  177. prq->sds_ring_offset = cpu_to_le32(val);
  178. prq_rds = (nx_hostrq_rds_ring_t *)(prq->data +
  179. le32_to_cpu(prq->rds_ring_offset));
  180. for (i = 0; i < nrds_rings; i++) {
  181. rds_ring = &recv_ctx->rds_rings[i];
  182. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  183. prq_rds[i].ring_size = cpu_to_le32(rds_ring->max_rx_desc_count);
  184. prq_rds[i].ring_kind = cpu_to_le32(i);
  185. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  186. }
  187. prq_sds = (nx_hostrq_sds_ring_t *)(prq->data +
  188. le32_to_cpu(prq->sds_ring_offset));
  189. prq_sds[0].host_phys_addr =
  190. cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
  191. prq_sds[0].ring_size = cpu_to_le32(adapter->max_rx_desc_count);
  192. /* only one msix vector for now */
  193. prq_sds[0].msi_index = cpu_to_le16(0);
  194. phys_addr = hostrq_phys_addr;
  195. err = netxen_issue_cmd(adapter,
  196. adapter->ahw.pci_func,
  197. NXHAL_VERSION,
  198. (u32)(phys_addr >> 32),
  199. (u32)(phys_addr & 0xffffffff),
  200. rq_size,
  201. NX_CDRP_CMD_CREATE_RX_CTX);
  202. if (err) {
  203. printk(KERN_WARNING
  204. "Failed to create rx ctx in firmware%d\n", err);
  205. goto out_free_rsp;
  206. }
  207. prsp_rds = ((nx_cardrsp_rds_ring_t *)
  208. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  209. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  210. rds_ring = &recv_ctx->rds_rings[i];
  211. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  212. rds_ring->crb_rcv_producer = NETXEN_NIC_REG(reg - 0x200);
  213. }
  214. prsp_sds = ((nx_cardrsp_sds_ring_t *)
  215. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  216. reg = le32_to_cpu(prsp_sds[0].host_consumer_crb);
  217. recv_ctx->crb_sts_consumer = NETXEN_NIC_REG(reg - 0x200);
  218. reg = le32_to_cpu(prsp_sds[0].interrupt_crb);
  219. adapter->crb_intr_mask = NETXEN_NIC_REG(reg - 0x200);
  220. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  221. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  222. recv_ctx->virt_port = prsp->virt_port;
  223. out_free_rsp:
  224. pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
  225. out_free_rq:
  226. pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
  227. return err;
  228. }
  229. static void
  230. nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
  231. {
  232. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0];
  233. if (netxen_issue_cmd(adapter,
  234. adapter->ahw.pci_func,
  235. NXHAL_VERSION,
  236. recv_ctx->context_id,
  237. NX_DESTROY_CTX_RESET,
  238. 0,
  239. NX_CDRP_CMD_DESTROY_RX_CTX)) {
  240. printk(KERN_WARNING
  241. "%s: Failed to destroy rx ctx in firmware\n",
  242. netxen_nic_driver_name);
  243. }
  244. }
  245. static int
  246. nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
  247. {
  248. nx_hostrq_tx_ctx_t *prq;
  249. nx_hostrq_cds_ring_t *prq_cds;
  250. nx_cardrsp_tx_ctx_t *prsp;
  251. void *rq_addr, *rsp_addr;
  252. size_t rq_size, rsp_size;
  253. u32 temp;
  254. int err = 0;
  255. u64 offset, phys_addr;
  256. dma_addr_t rq_phys_addr, rsp_phys_addr;
  257. rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
  258. rq_addr = pci_alloc_consistent(adapter->pdev,
  259. rq_size, &rq_phys_addr);
  260. if (!rq_addr)
  261. return -ENOMEM;
  262. rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
  263. rsp_addr = pci_alloc_consistent(adapter->pdev,
  264. rsp_size, &rsp_phys_addr);
  265. if (!rsp_addr) {
  266. err = -ENOMEM;
  267. goto out_free_rq;
  268. }
  269. memset(rq_addr, 0, rq_size);
  270. prq = (nx_hostrq_tx_ctx_t *)rq_addr;
  271. memset(rsp_addr, 0, rsp_size);
  272. prsp = (nx_cardrsp_tx_ctx_t *)rsp_addr;
  273. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  274. temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
  275. prq->capabilities[0] = cpu_to_le32(temp);
  276. prq->host_int_crb_mode =
  277. cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
  278. prq->interrupt_ctl = 0;
  279. prq->msi_index = 0;
  280. prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
  281. offset = adapter->ctx_desc_phys_addr+sizeof(struct netxen_ring_ctx);
  282. prq->cmd_cons_dma_addr = cpu_to_le64(offset);
  283. prq_cds = &prq->cds_ring;
  284. prq_cds->host_phys_addr =
  285. cpu_to_le64(adapter->ahw.cmd_desc_phys_addr);
  286. prq_cds->ring_size = cpu_to_le32(adapter->max_tx_desc_count);
  287. phys_addr = rq_phys_addr;
  288. err = netxen_issue_cmd(adapter,
  289. adapter->ahw.pci_func,
  290. NXHAL_VERSION,
  291. (u32)(phys_addr >> 32),
  292. ((u32)phys_addr & 0xffffffff),
  293. rq_size,
  294. NX_CDRP_CMD_CREATE_TX_CTX);
  295. if (err == NX_RCODE_SUCCESS) {
  296. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  297. adapter->crb_addr_cmd_producer =
  298. NETXEN_NIC_REG(temp - 0x200);
  299. #if 0
  300. adapter->tx_state =
  301. le32_to_cpu(prsp->host_ctx_state);
  302. #endif
  303. adapter->tx_context_id =
  304. le16_to_cpu(prsp->context_id);
  305. } else {
  306. printk(KERN_WARNING
  307. "Failed to create tx ctx in firmware%d\n", err);
  308. err = -EIO;
  309. }
  310. pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
  311. out_free_rq:
  312. pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
  313. return err;
  314. }
  315. static void
  316. nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
  317. {
  318. if (netxen_issue_cmd(adapter,
  319. adapter->ahw.pci_func,
  320. NXHAL_VERSION,
  321. adapter->tx_context_id,
  322. NX_DESTROY_CTX_RESET,
  323. 0,
  324. NX_CDRP_CMD_DESTROY_TX_CTX)) {
  325. printk(KERN_WARNING
  326. "%s: Failed to destroy tx ctx in firmware\n",
  327. netxen_nic_driver_name);
  328. }
  329. }
  330. static u64 ctx_addr_sig_regs[][3] = {
  331. {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
  332. {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
  333. {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
  334. {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
  335. };
  336. #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
  337. #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
  338. #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
  339. #define lower32(x) ((u32)((x) & 0xffffffff))
  340. #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
  341. static struct netxen_recv_crb recv_crb_registers[] = {
  342. /* Instance 0 */
  343. {
  344. /* crb_rcv_producer: */
  345. {
  346. NETXEN_NIC_REG(0x100),
  347. /* Jumbo frames */
  348. NETXEN_NIC_REG(0x110),
  349. /* LRO */
  350. NETXEN_NIC_REG(0x120)
  351. },
  352. /* crb_sts_consumer: */
  353. NETXEN_NIC_REG(0x138),
  354. },
  355. /* Instance 1 */
  356. {
  357. /* crb_rcv_producer: */
  358. {
  359. NETXEN_NIC_REG(0x144),
  360. /* Jumbo frames */
  361. NETXEN_NIC_REG(0x154),
  362. /* LRO */
  363. NETXEN_NIC_REG(0x164)
  364. },
  365. /* crb_sts_consumer: */
  366. NETXEN_NIC_REG(0x17c),
  367. },
  368. /* Instance 2 */
  369. {
  370. /* crb_rcv_producer: */
  371. {
  372. NETXEN_NIC_REG(0x1d8),
  373. /* Jumbo frames */
  374. NETXEN_NIC_REG(0x1f8),
  375. /* LRO */
  376. NETXEN_NIC_REG(0x208)
  377. },
  378. /* crb_sts_consumer: */
  379. NETXEN_NIC_REG(0x220),
  380. },
  381. /* Instance 3 */
  382. {
  383. /* crb_rcv_producer: */
  384. {
  385. NETXEN_NIC_REG(0x22c),
  386. /* Jumbo frames */
  387. NETXEN_NIC_REG(0x23c),
  388. /* LRO */
  389. NETXEN_NIC_REG(0x24c)
  390. },
  391. /* crb_sts_consumer: */
  392. NETXEN_NIC_REG(0x264),
  393. },
  394. };
  395. static int
  396. netxen_init_old_ctx(struct netxen_adapter *adapter)
  397. {
  398. struct netxen_recv_context *recv_ctx;
  399. struct nx_host_rds_ring *rds_ring;
  400. int ctx, ring;
  401. int func_id = adapter->portnum;
  402. adapter->ctx_desc->cmd_ring_addr =
  403. cpu_to_le64(adapter->ahw.cmd_desc_phys_addr);
  404. adapter->ctx_desc->cmd_ring_size =
  405. cpu_to_le32(adapter->max_tx_desc_count);
  406. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  407. recv_ctx = &adapter->recv_ctx[ctx];
  408. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  409. rds_ring = &recv_ctx->rds_rings[ring];
  410. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
  411. cpu_to_le64(rds_ring->phys_addr);
  412. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
  413. cpu_to_le32(rds_ring->max_rx_desc_count);
  414. }
  415. adapter->ctx_desc->sts_ring_addr =
  416. cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
  417. adapter->ctx_desc->sts_ring_size =
  418. cpu_to_le32(adapter->max_rx_desc_count);
  419. }
  420. adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id),
  421. lower32(adapter->ctx_desc_phys_addr));
  422. adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id),
  423. upper32(adapter->ctx_desc_phys_addr));
  424. adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id),
  425. NETXEN_CTX_SIGNATURE | func_id);
  426. return 0;
  427. }
  428. static uint32_t sw_int_mask[4] = {
  429. CRB_SW_INT_MASK_0, CRB_SW_INT_MASK_1,
  430. CRB_SW_INT_MASK_2, CRB_SW_INT_MASK_3
  431. };
  432. int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
  433. {
  434. struct netxen_hardware_context *hw = &adapter->ahw;
  435. u32 state = 0;
  436. void *addr;
  437. int err = 0;
  438. int ctx, ring;
  439. struct netxen_recv_context *recv_ctx;
  440. struct nx_host_rds_ring *rds_ring;
  441. err = netxen_receive_peg_ready(adapter);
  442. if (err) {
  443. printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n",
  444. state);
  445. return err;
  446. }
  447. addr = pci_alloc_consistent(adapter->pdev,
  448. sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
  449. &adapter->ctx_desc_phys_addr);
  450. if (addr == NULL) {
  451. DPRINTK(ERR, "failed to allocate hw context\n");
  452. return -ENOMEM;
  453. }
  454. memset(addr, 0, sizeof(struct netxen_ring_ctx));
  455. adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
  456. adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
  457. adapter->ctx_desc->cmd_consumer_offset =
  458. cpu_to_le64(adapter->ctx_desc_phys_addr +
  459. sizeof(struct netxen_ring_ctx));
  460. adapter->cmd_consumer =
  461. (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
  462. /* cmd desc ring */
  463. addr = pci_alloc_consistent(adapter->pdev,
  464. sizeof(struct cmd_desc_type0) *
  465. adapter->max_tx_desc_count,
  466. &hw->cmd_desc_phys_addr);
  467. if (addr == NULL) {
  468. printk(KERN_ERR "%s failed to allocate tx desc ring\n",
  469. netxen_nic_driver_name);
  470. return -ENOMEM;
  471. }
  472. hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
  473. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  474. recv_ctx = &adapter->recv_ctx[ctx];
  475. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  476. /* rx desc ring */
  477. rds_ring = &recv_ctx->rds_rings[ring];
  478. addr = pci_alloc_consistent(adapter->pdev,
  479. RCV_DESC_RINGSIZE,
  480. &rds_ring->phys_addr);
  481. if (addr == NULL) {
  482. printk(KERN_ERR "%s failed to allocate rx "
  483. "desc ring[%d]\n",
  484. netxen_nic_driver_name, ring);
  485. err = -ENOMEM;
  486. goto err_out_free;
  487. }
  488. rds_ring->desc_head = (struct rcv_desc *)addr;
  489. if (adapter->fw_major < 4)
  490. rds_ring->crb_rcv_producer =
  491. recv_crb_registers[adapter->portnum].
  492. crb_rcv_producer[ring];
  493. }
  494. /* status desc ring */
  495. addr = pci_alloc_consistent(adapter->pdev,
  496. STATUS_DESC_RINGSIZE,
  497. &recv_ctx->rcv_status_desc_phys_addr);
  498. if (addr == NULL) {
  499. printk(KERN_ERR "%s failed to allocate sts desc ring\n",
  500. netxen_nic_driver_name);
  501. err = -ENOMEM;
  502. goto err_out_free;
  503. }
  504. recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
  505. if (adapter->fw_major < 4)
  506. recv_ctx->crb_sts_consumer =
  507. recv_crb_registers[adapter->portnum].
  508. crb_sts_consumer;
  509. }
  510. if (adapter->fw_major >= 4) {
  511. adapter->intr_scheme = INTR_SCHEME_PERPORT;
  512. adapter->msi_mode = MSI_MODE_MULTIFUNC;
  513. err = nx_fw_cmd_create_rx_ctx(adapter);
  514. if (err)
  515. goto err_out_free;
  516. err = nx_fw_cmd_create_tx_ctx(adapter);
  517. if (err)
  518. goto err_out_free;
  519. } else {
  520. adapter->intr_scheme = adapter->pci_read_normalize(adapter,
  521. CRB_NIC_CAPABILITIES_FW);
  522. adapter->msi_mode = adapter->pci_read_normalize(adapter,
  523. CRB_NIC_MSI_MODE_FW);
  524. adapter->crb_intr_mask = sw_int_mask[adapter->portnum];
  525. err = netxen_init_old_ctx(adapter);
  526. if (err) {
  527. netxen_free_hw_resources(adapter);
  528. return err;
  529. }
  530. }
  531. return 0;
  532. err_out_free:
  533. netxen_free_hw_resources(adapter);
  534. return err;
  535. }
  536. void netxen_free_hw_resources(struct netxen_adapter *adapter)
  537. {
  538. struct netxen_recv_context *recv_ctx;
  539. struct nx_host_rds_ring *rds_ring;
  540. int ctx, ring;
  541. if (adapter->fw_major >= 4) {
  542. nx_fw_cmd_destroy_tx_ctx(adapter);
  543. nx_fw_cmd_destroy_rx_ctx(adapter);
  544. }
  545. if (adapter->ctx_desc != NULL) {
  546. pci_free_consistent(adapter->pdev,
  547. sizeof(struct netxen_ring_ctx) +
  548. sizeof(uint32_t),
  549. adapter->ctx_desc,
  550. adapter->ctx_desc_phys_addr);
  551. adapter->ctx_desc = NULL;
  552. }
  553. if (adapter->ahw.cmd_desc_head != NULL) {
  554. pci_free_consistent(adapter->pdev,
  555. sizeof(struct cmd_desc_type0) *
  556. adapter->max_tx_desc_count,
  557. adapter->ahw.cmd_desc_head,
  558. adapter->ahw.cmd_desc_phys_addr);
  559. adapter->ahw.cmd_desc_head = NULL;
  560. }
  561. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  562. recv_ctx = &adapter->recv_ctx[ctx];
  563. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  564. rds_ring = &recv_ctx->rds_rings[ring];
  565. if (rds_ring->desc_head != NULL) {
  566. pci_free_consistent(adapter->pdev,
  567. RCV_DESC_RINGSIZE,
  568. rds_ring->desc_head,
  569. rds_ring->phys_addr);
  570. rds_ring->desc_head = NULL;
  571. }
  572. }
  573. if (recv_ctx->rcv_status_desc_head != NULL) {
  574. pci_free_consistent(adapter->pdev,
  575. STATUS_DESC_RINGSIZE,
  576. recv_ctx->rcv_status_desc_head,
  577. recv_ctx->rcv_status_desc_phys_addr);
  578. recv_ctx->rcv_status_desc_head = NULL;
  579. }
  580. }
  581. }