via-ircc.c 42 KB

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  1. /********************************************************************
  2. Filename: via-ircc.c
  3. Version: 1.0
  4. Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
  5. Author: VIA Technologies,inc
  6. Date : 08/06/2003
  7. Copyright (c) 1998-2003 VIA Technologies, Inc.
  8. This program is free software; you can redistribute it and/or modify it under
  9. the terms of the GNU General Public License as published by the Free Software
  10. Foundation; either version 2, or (at your option) any later version.
  11. This program is distributed in the hope that it will be useful, but WITHOUT
  12. ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. See the GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  19. F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  20. Comment :
  21. jul/09/2002 : only implement two kind of dongle currently.
  22. Oct/02/2002 : work on VT8231 and VT8233 .
  23. Aug/06/2003 : change driver format to pci driver .
  24. 2004-02-16: <sda@bdit.de>
  25. - Removed unneeded 'legacy' pci stuff.
  26. - Make sure SIR mode is set (hw_init()) before calling mode-dependant stuff.
  27. - On speed change from core, don't send SIR frame with new speed.
  28. Use current speed and change speeds later.
  29. - Make module-param dongle_id actually work.
  30. - New dongle_id 17 (0x11): TDFS4500. Single-ended SIR only.
  31. Tested with home-grown PCB on EPIA boards.
  32. - Code cleanup.
  33. ********************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/types.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/ioport.h>
  40. #include <linux/delay.h>
  41. #include <linux/slab.h>
  42. #include <linux/init.h>
  43. #include <linux/rtnetlink.h>
  44. #include <linux/pci.h>
  45. #include <linux/dma-mapping.h>
  46. #include <asm/io.h>
  47. #include <asm/dma.h>
  48. #include <asm/byteorder.h>
  49. #include <linux/pm.h>
  50. #include <net/irda/wrapper.h>
  51. #include <net/irda/irda.h>
  52. #include <net/irda/irda_device.h>
  53. #include "via-ircc.h"
  54. #define VIA_MODULE_NAME "via-ircc"
  55. #define CHIP_IO_EXTENT 0x40
  56. static char *driver_name = VIA_MODULE_NAME;
  57. /* Module parameters */
  58. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  59. static int dongle_id = 0; /* default: probe */
  60. /* We can't guess the type of connected dongle, user *must* supply it. */
  61. module_param(dongle_id, int, 0);
  62. /* FIXME : we should not need this, because instances should be automatically
  63. * managed by the PCI layer. Especially that we seem to only be using the
  64. * first entry. Jean II */
  65. /* Max 4 instances for now */
  66. static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  67. /* Some prototypes */
  68. static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  69. static int via_ircc_close(struct via_ircc_cb *self);
  70. static int via_ircc_dma_receive(struct via_ircc_cb *self);
  71. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  72. int iobase);
  73. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  74. struct net_device *dev);
  75. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  76. struct net_device *dev);
  77. static void via_hw_init(struct via_ircc_cb *self);
  78. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  79. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id);
  80. static int via_ircc_is_receiving(struct via_ircc_cb *self);
  81. static int via_ircc_read_dongle_id(int iobase);
  82. static int via_ircc_net_open(struct net_device *dev);
  83. static int via_ircc_net_close(struct net_device *dev);
  84. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  85. int cmd);
  86. static void via_ircc_change_dongle_speed(int iobase, int speed,
  87. int dongle_id);
  88. static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
  89. static void hwreset(struct via_ircc_cb *self);
  90. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
  91. static int upload_rxdata(struct via_ircc_cb *self, int iobase);
  92. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
  93. static void __devexit via_remove_one (struct pci_dev *pdev);
  94. /* FIXME : Should use udelay() instead, even if we are x86 only - Jean II */
  95. static void iodelay(int udelay)
  96. {
  97. u8 data;
  98. int i;
  99. for (i = 0; i < udelay; i++) {
  100. data = inb(0x80);
  101. }
  102. }
  103. static struct pci_device_id via_pci_tbl[] = {
  104. { PCI_VENDOR_ID_VIA, 0x8231, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
  105. { PCI_VENDOR_ID_VIA, 0x3109, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
  106. { PCI_VENDOR_ID_VIA, 0x3074, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
  107. { PCI_VENDOR_ID_VIA, 0x3147, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
  108. { PCI_VENDOR_ID_VIA, 0x3177, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
  109. { 0, }
  110. };
  111. MODULE_DEVICE_TABLE(pci,via_pci_tbl);
  112. static struct pci_driver via_driver = {
  113. .name = VIA_MODULE_NAME,
  114. .id_table = via_pci_tbl,
  115. .probe = via_init_one,
  116. .remove = __devexit_p(via_remove_one),
  117. };
  118. /*
  119. * Function via_ircc_init ()
  120. *
  121. * Initialize chip. Just find out chip type and resource.
  122. */
  123. static int __init via_ircc_init(void)
  124. {
  125. int rc;
  126. IRDA_DEBUG(3, "%s()\n", __func__);
  127. rc = pci_register_driver(&via_driver);
  128. if (rc < 0) {
  129. IRDA_DEBUG(0, "%s(): error rc = %d, returning -ENODEV...\n",
  130. __func__, rc);
  131. return -ENODEV;
  132. }
  133. return 0;
  134. }
  135. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
  136. {
  137. int rc;
  138. u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
  139. u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
  140. chipio_t info;
  141. IRDA_DEBUG(2, "%s(): Device ID=(0X%X)\n", __func__, id->device);
  142. rc = pci_enable_device (pcidev);
  143. if (rc) {
  144. IRDA_DEBUG(0, "%s(): error rc = %d\n", __func__, rc);
  145. return -ENODEV;
  146. }
  147. // South Bridge exist
  148. if ( ReadLPCReg(0x20) != 0x3C )
  149. Chipset=0x3096;
  150. else
  151. Chipset=0x3076;
  152. if (Chipset==0x3076) {
  153. IRDA_DEBUG(2, "%s(): Chipset = 3076\n", __func__);
  154. WriteLPCReg(7,0x0c );
  155. temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
  156. if((temp&0x01)==1) { // BIOS close or no FIR
  157. WriteLPCReg(0x1d, 0x82 );
  158. WriteLPCReg(0x23,0x18);
  159. temp=ReadLPCReg(0xF0);
  160. if((temp&0x01)==0) {
  161. temp=(ReadLPCReg(0x74)&0x03); //DMA
  162. FirDRQ0=temp + 4;
  163. temp=(ReadLPCReg(0x74)&0x0C) >> 2;
  164. FirDRQ1=temp + 4;
  165. } else {
  166. temp=(ReadLPCReg(0x74)&0x0C) >> 2; //DMA
  167. FirDRQ0=temp + 4;
  168. FirDRQ1=FirDRQ0;
  169. }
  170. FirIRQ=(ReadLPCReg(0x70)&0x0f); //IRQ
  171. FirIOBase=ReadLPCReg(0x60 ) << 8; //IO Space :high byte
  172. FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
  173. FirIOBase=FirIOBase ;
  174. info.fir_base=FirIOBase;
  175. info.irq=FirIRQ;
  176. info.dma=FirDRQ1;
  177. info.dma2=FirDRQ0;
  178. pci_read_config_byte(pcidev,0x40,&bTmp);
  179. pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
  180. pci_read_config_byte(pcidev,0x42,&bTmp);
  181. pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
  182. pci_write_config_byte(pcidev,0x5a,0xc0);
  183. WriteLPCReg(0x28, 0x70 );
  184. if (via_ircc_open(0, &info,0x3076) == 0)
  185. rc=0;
  186. } else
  187. rc = -ENODEV; //IR not turn on
  188. } else { //Not VT1211
  189. IRDA_DEBUG(2, "%s(): Chipset = 3096\n", __func__);
  190. pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
  191. if((bTmp&0x01)==1) { // BIOS enable FIR
  192. //Enable Double DMA clock
  193. pci_read_config_byte(pcidev,0x42,&oldPCI_40);
  194. pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
  195. pci_read_config_byte(pcidev,0x40,&oldPCI_40);
  196. pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
  197. pci_read_config_byte(pcidev,0x44,&oldPCI_44);
  198. pci_write_config_byte(pcidev,0x44,0x4e);
  199. //---------- read configuration from Function0 of south bridge
  200. if((bTmp&0x02)==0) {
  201. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  202. FirDRQ0 = (bTmp1 & 0x30) >> 4;
  203. pci_read_config_byte(pcidev,0x44,&bTmp1);
  204. FirDRQ1 = (bTmp1 & 0xc0) >> 6;
  205. } else {
  206. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  207. FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
  208. FirDRQ1=0;
  209. }
  210. pci_read_config_byte(pcidev,0x47,&bTmp1); //IRQ
  211. FirIRQ = bTmp1 & 0x0f;
  212. pci_read_config_byte(pcidev,0x69,&bTmp);
  213. FirIOBase = bTmp << 8;//hight byte
  214. pci_read_config_byte(pcidev,0x68,&bTmp);
  215. FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
  216. //-------------------------
  217. info.fir_base=FirIOBase;
  218. info.irq=FirIRQ;
  219. info.dma=FirDRQ1;
  220. info.dma2=FirDRQ0;
  221. if (via_ircc_open(0, &info,0x3096) == 0)
  222. rc=0;
  223. } else
  224. rc = -ENODEV; //IR not turn on !!!!!
  225. }//Not VT1211
  226. IRDA_DEBUG(2, "%s(): End - rc = %d\n", __func__, rc);
  227. return rc;
  228. }
  229. /*
  230. * Function via_ircc_clean ()
  231. *
  232. * Close all configured chips
  233. *
  234. */
  235. static void via_ircc_clean(void)
  236. {
  237. int i;
  238. IRDA_DEBUG(3, "%s()\n", __func__);
  239. for (i=0; i < ARRAY_SIZE(dev_self); i++) {
  240. if (dev_self[i])
  241. via_ircc_close(dev_self[i]);
  242. }
  243. }
  244. static void __devexit via_remove_one (struct pci_dev *pdev)
  245. {
  246. IRDA_DEBUG(3, "%s()\n", __func__);
  247. /* FIXME : This is ugly. We should use pci_get_drvdata(pdev);
  248. * to get our driver instance and call directly via_ircc_close().
  249. * See vlsi_ir for details...
  250. * Jean II */
  251. via_ircc_clean();
  252. /* FIXME : This should be in via_ircc_close(), because here we may
  253. * theoritically disable still configured devices :-( - Jean II */
  254. pci_disable_device(pdev);
  255. }
  256. static void __exit via_ircc_cleanup(void)
  257. {
  258. IRDA_DEBUG(3, "%s()\n", __func__);
  259. /* FIXME : This should be redundant, as pci_unregister_driver()
  260. * should call via_remove_one() on each device.
  261. * Jean II */
  262. via_ircc_clean();
  263. /* Cleanup all instances of the driver */
  264. pci_unregister_driver (&via_driver);
  265. }
  266. /*
  267. * Function via_ircc_open (iobase, irq)
  268. *
  269. * Open driver instance
  270. *
  271. */
  272. static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
  273. {
  274. struct net_device *dev;
  275. struct via_ircc_cb *self;
  276. int err;
  277. IRDA_DEBUG(3, "%s()\n", __func__);
  278. if (i >= ARRAY_SIZE(dev_self))
  279. return -ENOMEM;
  280. /* Allocate new instance of the driver */
  281. dev = alloc_irdadev(sizeof(struct via_ircc_cb));
  282. if (dev == NULL)
  283. return -ENOMEM;
  284. self = netdev_priv(dev);
  285. self->netdev = dev;
  286. spin_lock_init(&self->lock);
  287. /* FIXME : We should store our driver instance in the PCI layer,
  288. * using pci_set_drvdata(), not in this array.
  289. * See vlsi_ir for details... - Jean II */
  290. /* FIXME : 'i' is always 0 (see via_init_one()) :-( - Jean II */
  291. /* Need to store self somewhere */
  292. dev_self[i] = self;
  293. self->index = i;
  294. /* Initialize Resource */
  295. self->io.cfg_base = info->cfg_base;
  296. self->io.fir_base = info->fir_base;
  297. self->io.irq = info->irq;
  298. self->io.fir_ext = CHIP_IO_EXTENT;
  299. self->io.dma = info->dma;
  300. self->io.dma2 = info->dma2;
  301. self->io.fifo_size = 32;
  302. self->chip_id = id;
  303. self->st_fifo.len = 0;
  304. self->RxDataReady = 0;
  305. /* Reserve the ioports that we need */
  306. if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
  307. IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
  308. __func__, self->io.fir_base);
  309. err = -ENODEV;
  310. goto err_out1;
  311. }
  312. /* Initialize QoS for this device */
  313. irda_init_max_qos_capabilies(&self->qos);
  314. /* Check if user has supplied the dongle id or not */
  315. if (!dongle_id)
  316. dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
  317. self->io.dongle_id = dongle_id;
  318. /* The only value we must override it the baudrate */
  319. /* Maximum speeds and capabilities are dongle-dependant. */
  320. switch( self->io.dongle_id ){
  321. case 0x0d:
  322. self->qos.baud_rate.bits =
  323. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
  324. IR_576000 | IR_1152000 | (IR_4000000 << 8);
  325. break;
  326. default:
  327. self->qos.baud_rate.bits =
  328. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
  329. break;
  330. }
  331. /* Following was used for testing:
  332. *
  333. * self->qos.baud_rate.bits = IR_9600;
  334. *
  335. * Is is no good, as it prohibits (error-prone) speed-changes.
  336. */
  337. self->qos.min_turn_time.bits = qos_mtt_bits;
  338. irda_qos_bits_to_value(&self->qos);
  339. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  340. self->rx_buff.truesize = 14384 + 2048;
  341. self->tx_buff.truesize = 14384 + 2048;
  342. /* Allocate memory if needed */
  343. self->rx_buff.head =
  344. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  345. &self->rx_buff_dma, GFP_KERNEL);
  346. if (self->rx_buff.head == NULL) {
  347. err = -ENOMEM;
  348. goto err_out2;
  349. }
  350. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  351. self->tx_buff.head =
  352. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  353. &self->tx_buff_dma, GFP_KERNEL);
  354. if (self->tx_buff.head == NULL) {
  355. err = -ENOMEM;
  356. goto err_out3;
  357. }
  358. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  359. self->rx_buff.in_frame = FALSE;
  360. self->rx_buff.state = OUTSIDE_FRAME;
  361. self->tx_buff.data = self->tx_buff.head;
  362. self->rx_buff.data = self->rx_buff.head;
  363. /* Reset Tx queue info */
  364. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  365. self->tx_fifo.tail = self->tx_buff.head;
  366. /* Override the network functions we need to use */
  367. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  368. dev->open = via_ircc_net_open;
  369. dev->stop = via_ircc_net_close;
  370. dev->do_ioctl = via_ircc_net_ioctl;
  371. err = register_netdev(dev);
  372. if (err)
  373. goto err_out4;
  374. IRDA_MESSAGE("IrDA: Registered device %s (via-ircc)\n", dev->name);
  375. /* Initialise the hardware..
  376. */
  377. self->io.speed = 9600;
  378. via_hw_init(self);
  379. return 0;
  380. err_out4:
  381. dma_free_coherent(NULL, self->tx_buff.truesize,
  382. self->tx_buff.head, self->tx_buff_dma);
  383. err_out3:
  384. dma_free_coherent(NULL, self->rx_buff.truesize,
  385. self->rx_buff.head, self->rx_buff_dma);
  386. err_out2:
  387. release_region(self->io.fir_base, self->io.fir_ext);
  388. err_out1:
  389. free_netdev(dev);
  390. dev_self[i] = NULL;
  391. return err;
  392. }
  393. /*
  394. * Function via_ircc_close (self)
  395. *
  396. * Close driver instance
  397. *
  398. */
  399. static int via_ircc_close(struct via_ircc_cb *self)
  400. {
  401. int iobase;
  402. IRDA_DEBUG(3, "%s()\n", __func__);
  403. IRDA_ASSERT(self != NULL, return -1;);
  404. iobase = self->io.fir_base;
  405. ResetChip(iobase, 5); //hardware reset.
  406. /* Remove netdevice */
  407. unregister_netdev(self->netdev);
  408. /* Release the PORT that this driver is using */
  409. IRDA_DEBUG(2, "%s(), Releasing Region %03x\n",
  410. __func__, self->io.fir_base);
  411. release_region(self->io.fir_base, self->io.fir_ext);
  412. if (self->tx_buff.head)
  413. dma_free_coherent(NULL, self->tx_buff.truesize,
  414. self->tx_buff.head, self->tx_buff_dma);
  415. if (self->rx_buff.head)
  416. dma_free_coherent(NULL, self->rx_buff.truesize,
  417. self->rx_buff.head, self->rx_buff_dma);
  418. dev_self[self->index] = NULL;
  419. free_netdev(self->netdev);
  420. return 0;
  421. }
  422. /*
  423. * Function via_hw_init(self)
  424. *
  425. * Returns non-negative on success.
  426. *
  427. * Formerly via_ircc_setup
  428. */
  429. static void via_hw_init(struct via_ircc_cb *self)
  430. {
  431. int iobase = self->io.fir_base;
  432. IRDA_DEBUG(3, "%s()\n", __func__);
  433. SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
  434. // FIFO Init
  435. EnRXFIFOReadyInt(iobase, OFF);
  436. EnRXFIFOHalfLevelInt(iobase, OFF);
  437. EnTXFIFOHalfLevelInt(iobase, OFF);
  438. EnTXFIFOUnderrunEOMInt(iobase, ON);
  439. EnTXFIFOReadyInt(iobase, OFF);
  440. InvertTX(iobase, OFF);
  441. InvertRX(iobase, OFF);
  442. if (ReadLPCReg(0x20) == 0x3c)
  443. WriteLPCReg(0xF0, 0); // for VT1211
  444. /* Int Init */
  445. EnRXSpecInt(iobase, ON);
  446. /* The following is basically hwreset */
  447. /* If this is the case, why not just call hwreset() ? Jean II */
  448. ResetChip(iobase, 5);
  449. EnableDMA(iobase, OFF);
  450. EnableTX(iobase, OFF);
  451. EnableRX(iobase, OFF);
  452. EnRXDMA(iobase, OFF);
  453. EnTXDMA(iobase, OFF);
  454. RXStart(iobase, OFF);
  455. TXStart(iobase, OFF);
  456. InitCard(iobase);
  457. CommonInit(iobase);
  458. SIRFilter(iobase, ON);
  459. SetSIR(iobase, ON);
  460. CRC16(iobase, ON);
  461. EnTXCRC(iobase, 0);
  462. WriteReg(iobase, I_ST_CT_0, 0x00);
  463. SetBaudRate(iobase, 9600);
  464. SetPulseWidth(iobase, 12);
  465. SetSendPreambleCount(iobase, 0);
  466. self->io.speed = 9600;
  467. self->st_fifo.len = 0;
  468. via_ircc_change_dongle_speed(iobase, self->io.speed,
  469. self->io.dongle_id);
  470. WriteReg(iobase, I_ST_CT_0, 0x80);
  471. }
  472. /*
  473. * Function via_ircc_read_dongle_id (void)
  474. *
  475. */
  476. static int via_ircc_read_dongle_id(int iobase)
  477. {
  478. int dongle_id = 9; /* Default to IBM */
  479. IRDA_ERROR("via-ircc: dongle probing not supported, please specify dongle_id module parameter.\n");
  480. return dongle_id;
  481. }
  482. /*
  483. * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
  484. * Change speed of the attach dongle
  485. * only implement two type of dongle currently.
  486. */
  487. static void via_ircc_change_dongle_speed(int iobase, int speed,
  488. int dongle_id)
  489. {
  490. u8 mode = 0;
  491. /* speed is unused, as we use IsSIROn()/IsMIROn() */
  492. speed = speed;
  493. IRDA_DEBUG(1, "%s(): change_dongle_speed to %d for 0x%x, %d\n",
  494. __func__, speed, iobase, dongle_id);
  495. switch (dongle_id) {
  496. /* Note: The dongle_id's listed here are derived from
  497. * nsc-ircc.c */
  498. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  499. UseOneRX(iobase, ON); // use one RX pin RX1,RX2
  500. InvertTX(iobase, OFF);
  501. InvertRX(iobase, OFF);
  502. EnRX2(iobase, ON); //sir to rx2
  503. EnGPIOtoRX2(iobase, OFF);
  504. if (IsSIROn(iobase)) { //sir
  505. // Mode select Off
  506. SlowIRRXLowActive(iobase, ON);
  507. udelay(1000);
  508. SlowIRRXLowActive(iobase, OFF);
  509. } else {
  510. if (IsMIROn(iobase)) { //mir
  511. // Mode select On
  512. SlowIRRXLowActive(iobase, OFF);
  513. udelay(20);
  514. } else { // fir
  515. if (IsFIROn(iobase)) { //fir
  516. // Mode select On
  517. SlowIRRXLowActive(iobase, OFF);
  518. udelay(20);
  519. }
  520. }
  521. }
  522. break;
  523. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  524. UseOneRX(iobase, ON); //use ONE RX....RX1
  525. InvertTX(iobase, OFF);
  526. InvertRX(iobase, OFF); // invert RX pin
  527. EnRX2(iobase, ON);
  528. EnGPIOtoRX2(iobase, OFF);
  529. if (IsSIROn(iobase)) { //sir
  530. // Mode select On
  531. SlowIRRXLowActive(iobase, ON);
  532. udelay(20);
  533. // Mode select Off
  534. SlowIRRXLowActive(iobase, OFF);
  535. }
  536. if (IsMIROn(iobase)) { //mir
  537. // Mode select On
  538. SlowIRRXLowActive(iobase, OFF);
  539. udelay(20);
  540. // Mode select Off
  541. SlowIRRXLowActive(iobase, ON);
  542. } else { // fir
  543. if (IsFIROn(iobase)) { //fir
  544. // Mode select On
  545. SlowIRRXLowActive(iobase, OFF);
  546. // TX On
  547. WriteTX(iobase, ON);
  548. udelay(20);
  549. // Mode select OFF
  550. SlowIRRXLowActive(iobase, ON);
  551. udelay(20);
  552. // TX Off
  553. WriteTX(iobase, OFF);
  554. }
  555. }
  556. break;
  557. case 0x0d:
  558. UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
  559. InvertTX(iobase, OFF);
  560. InvertRX(iobase, OFF);
  561. SlowIRRXLowActive(iobase, OFF);
  562. if (IsSIROn(iobase)) { //sir
  563. EnGPIOtoRX2(iobase, OFF);
  564. WriteGIO(iobase, OFF);
  565. EnRX2(iobase, OFF); //sir to rx2
  566. } else { // fir mir
  567. EnGPIOtoRX2(iobase, OFF);
  568. WriteGIO(iobase, OFF);
  569. EnRX2(iobase, OFF); //fir to rx
  570. }
  571. break;
  572. case 0x11: /* Temic TFDS4500 */
  573. IRDA_DEBUG(2, "%s: Temic TFDS4500: One RX pin, TX normal, RX inverted.\n", __func__);
  574. UseOneRX(iobase, ON); //use ONE RX....RX1
  575. InvertTX(iobase, OFF);
  576. InvertRX(iobase, ON); // invert RX pin
  577. EnRX2(iobase, ON); //sir to rx2
  578. EnGPIOtoRX2(iobase, OFF);
  579. if( IsSIROn(iobase) ){ //sir
  580. // Mode select On
  581. SlowIRRXLowActive(iobase, ON);
  582. udelay(20);
  583. // Mode select Off
  584. SlowIRRXLowActive(iobase, OFF);
  585. } else{
  586. IRDA_DEBUG(0, "%s: Warning: TFDS4500 not running in SIR mode !\n", __func__);
  587. }
  588. break;
  589. case 0x0ff: /* Vishay */
  590. if (IsSIROn(iobase))
  591. mode = 0;
  592. else if (IsMIROn(iobase))
  593. mode = 1;
  594. else if (IsFIROn(iobase))
  595. mode = 2;
  596. else if (IsVFIROn(iobase))
  597. mode = 5; //VFIR-16
  598. SI_SetMode(iobase, mode);
  599. break;
  600. default:
  601. IRDA_ERROR("%s: Error: dongle_id %d unsupported !\n",
  602. __func__, dongle_id);
  603. }
  604. }
  605. /*
  606. * Function via_ircc_change_speed (self, baud)
  607. *
  608. * Change the speed of the device
  609. *
  610. */
  611. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
  612. {
  613. struct net_device *dev = self->netdev;
  614. u16 iobase;
  615. u8 value = 0, bTmp;
  616. iobase = self->io.fir_base;
  617. /* Update accounting for new speed */
  618. self->io.speed = speed;
  619. IRDA_DEBUG(1, "%s: change_speed to %d bps.\n", __func__, speed);
  620. WriteReg(iobase, I_ST_CT_0, 0x0);
  621. /* Controller mode sellection */
  622. switch (speed) {
  623. case 2400:
  624. case 9600:
  625. case 19200:
  626. case 38400:
  627. case 57600:
  628. case 115200:
  629. value = (115200/speed)-1;
  630. SetSIR(iobase, ON);
  631. CRC16(iobase, ON);
  632. break;
  633. case 576000:
  634. /* FIXME: this can't be right, as it's the same as 115200,
  635. * and 576000 is MIR, not SIR. */
  636. value = 0;
  637. SetSIR(iobase, ON);
  638. CRC16(iobase, ON);
  639. break;
  640. case 1152000:
  641. value = 0;
  642. SetMIR(iobase, ON);
  643. /* FIXME: CRC ??? */
  644. break;
  645. case 4000000:
  646. value = 0;
  647. SetFIR(iobase, ON);
  648. SetPulseWidth(iobase, 0);
  649. SetSendPreambleCount(iobase, 14);
  650. CRC16(iobase, OFF);
  651. EnTXCRC(iobase, ON);
  652. break;
  653. case 16000000:
  654. value = 0;
  655. SetVFIR(iobase, ON);
  656. /* FIXME: CRC ??? */
  657. break;
  658. default:
  659. value = 0;
  660. break;
  661. }
  662. /* Set baudrate to 0x19[2..7] */
  663. bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
  664. bTmp |= value << 2;
  665. WriteReg(iobase, I_CF_H_1, bTmp);
  666. /* Some dongles may need to be informed about speed changes. */
  667. via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  668. /* Set FIFO size to 64 */
  669. SetFIFO(iobase, 64);
  670. /* Enable IR */
  671. WriteReg(iobase, I_ST_CT_0, 0x80);
  672. // EnTXFIFOHalfLevelInt(iobase,ON);
  673. /* Enable some interrupts so we can receive frames */
  674. //EnAllInt(iobase,ON);
  675. if (IsSIROn(iobase)) {
  676. SIRFilter(iobase, ON);
  677. SIRRecvAny(iobase, ON);
  678. } else {
  679. SIRFilter(iobase, OFF);
  680. SIRRecvAny(iobase, OFF);
  681. }
  682. if (speed > 115200) {
  683. /* Install FIR xmit handler */
  684. dev->hard_start_xmit = via_ircc_hard_xmit_fir;
  685. via_ircc_dma_receive(self);
  686. } else {
  687. /* Install SIR xmit handler */
  688. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  689. }
  690. netif_wake_queue(dev);
  691. }
  692. /*
  693. * Function via_ircc_hard_xmit (skb, dev)
  694. *
  695. * Transmit the frame!
  696. *
  697. */
  698. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  699. struct net_device *dev)
  700. {
  701. struct via_ircc_cb *self;
  702. unsigned long flags;
  703. u16 iobase;
  704. __u32 speed;
  705. self = netdev_priv(dev);
  706. IRDA_ASSERT(self != NULL, return 0;);
  707. iobase = self->io.fir_base;
  708. netif_stop_queue(dev);
  709. /* Check if we need to change the speed */
  710. speed = irda_get_next_speed(skb);
  711. if ((speed != self->io.speed) && (speed != -1)) {
  712. /* Check for empty frame */
  713. if (!skb->len) {
  714. via_ircc_change_speed(self, speed);
  715. dev->trans_start = jiffies;
  716. dev_kfree_skb(skb);
  717. return 0;
  718. } else
  719. self->new_speed = speed;
  720. }
  721. InitCard(iobase);
  722. CommonInit(iobase);
  723. SIRFilter(iobase, ON);
  724. SetSIR(iobase, ON);
  725. CRC16(iobase, ON);
  726. EnTXCRC(iobase, 0);
  727. WriteReg(iobase, I_ST_CT_0, 0x00);
  728. spin_lock_irqsave(&self->lock, flags);
  729. self->tx_buff.data = self->tx_buff.head;
  730. self->tx_buff.len =
  731. async_wrap_skb(skb, self->tx_buff.data,
  732. self->tx_buff.truesize);
  733. dev->stats.tx_bytes += self->tx_buff.len;
  734. /* Send this frame with old speed */
  735. SetBaudRate(iobase, self->io.speed);
  736. SetPulseWidth(iobase, 12);
  737. SetSendPreambleCount(iobase, 0);
  738. WriteReg(iobase, I_ST_CT_0, 0x80);
  739. EnableTX(iobase, ON);
  740. EnableRX(iobase, OFF);
  741. ResetChip(iobase, 0);
  742. ResetChip(iobase, 1);
  743. ResetChip(iobase, 2);
  744. ResetChip(iobase, 3);
  745. ResetChip(iobase, 4);
  746. EnAllInt(iobase, ON);
  747. EnTXDMA(iobase, ON);
  748. EnRXDMA(iobase, OFF);
  749. irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
  750. DMA_TX_MODE);
  751. SetSendByte(iobase, self->tx_buff.len);
  752. RXStart(iobase, OFF);
  753. TXStart(iobase, ON);
  754. dev->trans_start = jiffies;
  755. spin_unlock_irqrestore(&self->lock, flags);
  756. dev_kfree_skb(skb);
  757. return 0;
  758. }
  759. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  760. struct net_device *dev)
  761. {
  762. struct via_ircc_cb *self;
  763. u16 iobase;
  764. __u32 speed;
  765. unsigned long flags;
  766. self = netdev_priv(dev);
  767. iobase = self->io.fir_base;
  768. if (self->st_fifo.len)
  769. return 0;
  770. if (self->chip_id == 0x3076)
  771. iodelay(1500);
  772. else
  773. udelay(1500);
  774. netif_stop_queue(dev);
  775. speed = irda_get_next_speed(skb);
  776. if ((speed != self->io.speed) && (speed != -1)) {
  777. if (!skb->len) {
  778. via_ircc_change_speed(self, speed);
  779. dev->trans_start = jiffies;
  780. dev_kfree_skb(skb);
  781. return 0;
  782. } else
  783. self->new_speed = speed;
  784. }
  785. spin_lock_irqsave(&self->lock, flags);
  786. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  787. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  788. self->tx_fifo.tail += skb->len;
  789. dev->stats.tx_bytes += skb->len;
  790. skb_copy_from_linear_data(skb,
  791. self->tx_fifo.queue[self->tx_fifo.free].start, skb->len);
  792. self->tx_fifo.len++;
  793. self->tx_fifo.free++;
  794. //F01 if (self->tx_fifo.len == 1) {
  795. via_ircc_dma_xmit(self, iobase);
  796. //F01 }
  797. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
  798. dev->trans_start = jiffies;
  799. dev_kfree_skb(skb);
  800. spin_unlock_irqrestore(&self->lock, flags);
  801. return 0;
  802. }
  803. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
  804. {
  805. EnTXDMA(iobase, OFF);
  806. self->io.direction = IO_XMIT;
  807. EnPhys(iobase, ON);
  808. EnableTX(iobase, ON);
  809. EnableRX(iobase, OFF);
  810. ResetChip(iobase, 0);
  811. ResetChip(iobase, 1);
  812. ResetChip(iobase, 2);
  813. ResetChip(iobase, 3);
  814. ResetChip(iobase, 4);
  815. EnAllInt(iobase, ON);
  816. EnTXDMA(iobase, ON);
  817. EnRXDMA(iobase, OFF);
  818. irda_setup_dma(self->io.dma,
  819. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  820. self->tx_buff.head) + self->tx_buff_dma,
  821. self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
  822. IRDA_DEBUG(1, "%s: tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
  823. __func__, self->tx_fifo.ptr,
  824. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  825. self->tx_fifo.len);
  826. SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
  827. RXStart(iobase, OFF);
  828. TXStart(iobase, ON);
  829. return 0;
  830. }
  831. /*
  832. * Function via_ircc_dma_xmit_complete (self)
  833. *
  834. * The transfer of a frame in finished. This function will only be called
  835. * by the interrupt handler
  836. *
  837. */
  838. static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
  839. {
  840. int iobase;
  841. int ret = TRUE;
  842. u8 Tx_status;
  843. IRDA_DEBUG(3, "%s()\n", __func__);
  844. iobase = self->io.fir_base;
  845. /* Disable DMA */
  846. // DisableDmaChannel(self->io.dma);
  847. /* Check for underrrun! */
  848. /* Clear bit, by writing 1 into it */
  849. Tx_status = GetTXStatus(iobase);
  850. if (Tx_status & 0x08) {
  851. self->netdev->stats.tx_errors++;
  852. self->netdev->stats.tx_fifo_errors++;
  853. hwreset(self);
  854. // how to clear underrrun ?
  855. } else {
  856. self->netdev->stats.tx_packets++;
  857. ResetChip(iobase, 3);
  858. ResetChip(iobase, 4);
  859. }
  860. /* Check if we need to change the speed */
  861. if (self->new_speed) {
  862. via_ircc_change_speed(self, self->new_speed);
  863. self->new_speed = 0;
  864. }
  865. /* Finished with this frame, so prepare for next */
  866. if (IsFIROn(iobase)) {
  867. if (self->tx_fifo.len) {
  868. self->tx_fifo.len--;
  869. self->tx_fifo.ptr++;
  870. }
  871. }
  872. IRDA_DEBUG(1,
  873. "%s: tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
  874. __func__,
  875. self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free);
  876. /* F01_S
  877. // Any frames to be sent back-to-back?
  878. if (self->tx_fifo.len) {
  879. // Not finished yet!
  880. via_ircc_dma_xmit(self, iobase);
  881. ret = FALSE;
  882. } else {
  883. F01_E*/
  884. // Reset Tx FIFO info
  885. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  886. self->tx_fifo.tail = self->tx_buff.head;
  887. //F01 }
  888. // Make sure we have room for more frames
  889. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
  890. // Not busy transmitting anymore
  891. // Tell the network layer, that we can accept more frames
  892. netif_wake_queue(self->netdev);
  893. //F01 }
  894. return ret;
  895. }
  896. /*
  897. * Function via_ircc_dma_receive (self)
  898. *
  899. * Set configuration for receive a frame.
  900. *
  901. */
  902. static int via_ircc_dma_receive(struct via_ircc_cb *self)
  903. {
  904. int iobase;
  905. iobase = self->io.fir_base;
  906. IRDA_DEBUG(3, "%s()\n", __func__);
  907. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  908. self->tx_fifo.tail = self->tx_buff.head;
  909. self->RxDataReady = 0;
  910. self->io.direction = IO_RECV;
  911. self->rx_buff.data = self->rx_buff.head;
  912. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  913. self->st_fifo.tail = self->st_fifo.head = 0;
  914. EnPhys(iobase, ON);
  915. EnableTX(iobase, OFF);
  916. EnableRX(iobase, ON);
  917. ResetChip(iobase, 0);
  918. ResetChip(iobase, 1);
  919. ResetChip(iobase, 2);
  920. ResetChip(iobase, 3);
  921. ResetChip(iobase, 4);
  922. EnAllInt(iobase, ON);
  923. EnTXDMA(iobase, OFF);
  924. EnRXDMA(iobase, ON);
  925. irda_setup_dma(self->io.dma2, self->rx_buff_dma,
  926. self->rx_buff.truesize, DMA_RX_MODE);
  927. TXStart(iobase, OFF);
  928. RXStart(iobase, ON);
  929. return 0;
  930. }
  931. /*
  932. * Function via_ircc_dma_receive_complete (self)
  933. *
  934. * Controller Finished with receiving frames,
  935. * and this routine is call by ISR
  936. *
  937. */
  938. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  939. int iobase)
  940. {
  941. struct st_fifo *st_fifo;
  942. struct sk_buff *skb;
  943. int len, i;
  944. u8 status = 0;
  945. iobase = self->io.fir_base;
  946. st_fifo = &self->st_fifo;
  947. if (self->io.speed < 4000000) { //Speed below FIR
  948. len = GetRecvByte(iobase, self);
  949. skb = dev_alloc_skb(len + 1);
  950. if (skb == NULL)
  951. return FALSE;
  952. // Make sure IP header gets aligned
  953. skb_reserve(skb, 1);
  954. skb_put(skb, len - 2);
  955. if (self->chip_id == 0x3076) {
  956. for (i = 0; i < len - 2; i++)
  957. skb->data[i] = self->rx_buff.data[i * 2];
  958. } else {
  959. if (self->chip_id == 0x3096) {
  960. for (i = 0; i < len - 2; i++)
  961. skb->data[i] =
  962. self->rx_buff.data[i];
  963. }
  964. }
  965. // Move to next frame
  966. self->rx_buff.data += len;
  967. self->netdev->stats.rx_bytes += len;
  968. self->netdev->stats.rx_packets++;
  969. skb->dev = self->netdev;
  970. skb_reset_mac_header(skb);
  971. skb->protocol = htons(ETH_P_IRDA);
  972. netif_rx(skb);
  973. return TRUE;
  974. }
  975. else { //FIR mode
  976. len = GetRecvByte(iobase, self);
  977. if (len == 0)
  978. return TRUE; //interrupt only, data maybe move by RxT
  979. if (((len - 4) < 2) || ((len - 4) > 2048)) {
  980. IRDA_DEBUG(1, "%s(): Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
  981. __func__, len, RxCurCount(iobase, self),
  982. self->RxLastCount);
  983. hwreset(self);
  984. return FALSE;
  985. }
  986. IRDA_DEBUG(2, "%s(): fifo.len=%x,len=%x,CurCount=%x..\n",
  987. __func__,
  988. st_fifo->len, len - 4, RxCurCount(iobase, self));
  989. st_fifo->entries[st_fifo->tail].status = status;
  990. st_fifo->entries[st_fifo->tail].len = len;
  991. st_fifo->pending_bytes += len;
  992. st_fifo->tail++;
  993. st_fifo->len++;
  994. if (st_fifo->tail > MAX_RX_WINDOW)
  995. st_fifo->tail = 0;
  996. self->RxDataReady = 0;
  997. // It maybe have MAX_RX_WINDOW package receive by
  998. // receive_complete before Timer IRQ
  999. /* F01_S
  1000. if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
  1001. RXStart(iobase,ON);
  1002. SetTimer(iobase,4);
  1003. }
  1004. else {
  1005. F01_E */
  1006. EnableRX(iobase, OFF);
  1007. EnRXDMA(iobase, OFF);
  1008. RXStart(iobase, OFF);
  1009. //F01_S
  1010. // Put this entry back in fifo
  1011. if (st_fifo->head > MAX_RX_WINDOW)
  1012. st_fifo->head = 0;
  1013. status = st_fifo->entries[st_fifo->head].status;
  1014. len = st_fifo->entries[st_fifo->head].len;
  1015. st_fifo->head++;
  1016. st_fifo->len--;
  1017. skb = dev_alloc_skb(len + 1 - 4);
  1018. /*
  1019. * if frame size,data ptr,or skb ptr are wrong ,the get next
  1020. * entry.
  1021. */
  1022. if ((skb == NULL) || (skb->data == NULL)
  1023. || (self->rx_buff.data == NULL) || (len < 6)) {
  1024. self->netdev->stats.rx_dropped++;
  1025. return TRUE;
  1026. }
  1027. skb_reserve(skb, 1);
  1028. skb_put(skb, len - 4);
  1029. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4);
  1030. IRDA_DEBUG(2, "%s(): len=%x.rx_buff=%p\n", __func__,
  1031. len - 4, self->rx_buff.data);
  1032. // Move to next frame
  1033. self->rx_buff.data += len;
  1034. self->netdev->stats.rx_bytes += len;
  1035. self->netdev->stats.rx_packets++;
  1036. skb->dev = self->netdev;
  1037. skb_reset_mac_header(skb);
  1038. skb->protocol = htons(ETH_P_IRDA);
  1039. netif_rx(skb);
  1040. //F01_E
  1041. } //FIR
  1042. return TRUE;
  1043. }
  1044. /*
  1045. * if frame is received , but no INT ,then use this routine to upload frame.
  1046. */
  1047. static int upload_rxdata(struct via_ircc_cb *self, int iobase)
  1048. {
  1049. struct sk_buff *skb;
  1050. int len;
  1051. struct st_fifo *st_fifo;
  1052. st_fifo = &self->st_fifo;
  1053. len = GetRecvByte(iobase, self);
  1054. IRDA_DEBUG(2, "%s(): len=%x\n", __func__, len);
  1055. if ((len - 4) < 2) {
  1056. self->netdev->stats.rx_dropped++;
  1057. return FALSE;
  1058. }
  1059. skb = dev_alloc_skb(len + 1);
  1060. if (skb == NULL) {
  1061. self->netdev->stats.rx_dropped++;
  1062. return FALSE;
  1063. }
  1064. skb_reserve(skb, 1);
  1065. skb_put(skb, len - 4 + 1);
  1066. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4 + 1);
  1067. st_fifo->tail++;
  1068. st_fifo->len++;
  1069. if (st_fifo->tail > MAX_RX_WINDOW)
  1070. st_fifo->tail = 0;
  1071. // Move to next frame
  1072. self->rx_buff.data += len;
  1073. self->netdev->stats.rx_bytes += len;
  1074. self->netdev->stats.rx_packets++;
  1075. skb->dev = self->netdev;
  1076. skb_reset_mac_header(skb);
  1077. skb->protocol = htons(ETH_P_IRDA);
  1078. netif_rx(skb);
  1079. if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
  1080. RXStart(iobase, ON);
  1081. } else {
  1082. EnableRX(iobase, OFF);
  1083. EnRXDMA(iobase, OFF);
  1084. RXStart(iobase, OFF);
  1085. }
  1086. return TRUE;
  1087. }
  1088. /*
  1089. * Implement back to back receive , use this routine to upload data.
  1090. */
  1091. static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
  1092. {
  1093. struct st_fifo *st_fifo;
  1094. struct sk_buff *skb;
  1095. int len;
  1096. u8 status;
  1097. st_fifo = &self->st_fifo;
  1098. if (CkRxRecv(iobase, self)) {
  1099. // if still receiving ,then return ,don't upload frame
  1100. self->RetryCount = 0;
  1101. SetTimer(iobase, 20);
  1102. self->RxDataReady++;
  1103. return FALSE;
  1104. } else
  1105. self->RetryCount++;
  1106. if ((self->RetryCount >= 1) ||
  1107. ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
  1108. || (st_fifo->len >= (MAX_RX_WINDOW))) {
  1109. while (st_fifo->len > 0) { //upload frame
  1110. // Put this entry back in fifo
  1111. if (st_fifo->head > MAX_RX_WINDOW)
  1112. st_fifo->head = 0;
  1113. status = st_fifo->entries[st_fifo->head].status;
  1114. len = st_fifo->entries[st_fifo->head].len;
  1115. st_fifo->head++;
  1116. st_fifo->len--;
  1117. skb = dev_alloc_skb(len + 1 - 4);
  1118. /*
  1119. * if frame size, data ptr, or skb ptr are wrong,
  1120. * then get next entry.
  1121. */
  1122. if ((skb == NULL) || (skb->data == NULL)
  1123. || (self->rx_buff.data == NULL) || (len < 6)) {
  1124. self->netdev->stats.rx_dropped++;
  1125. continue;
  1126. }
  1127. skb_reserve(skb, 1);
  1128. skb_put(skb, len - 4);
  1129. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4);
  1130. IRDA_DEBUG(2, "%s(): len=%x.head=%x\n", __func__,
  1131. len - 4, st_fifo->head);
  1132. // Move to next frame
  1133. self->rx_buff.data += len;
  1134. self->netdev->stats.rx_bytes += len;
  1135. self->netdev->stats.rx_packets++;
  1136. skb->dev = self->netdev;
  1137. skb_reset_mac_header(skb);
  1138. skb->protocol = htons(ETH_P_IRDA);
  1139. netif_rx(skb);
  1140. } //while
  1141. self->RetryCount = 0;
  1142. IRDA_DEBUG(2,
  1143. "%s(): End of upload HostStatus=%x,RxStatus=%x\n",
  1144. __func__,
  1145. GetHostStatus(iobase), GetRXStatus(iobase));
  1146. /*
  1147. * if frame is receive complete at this routine ,then upload
  1148. * frame.
  1149. */
  1150. if ((GetRXStatus(iobase) & 0x10)
  1151. && (RxCurCount(iobase, self) != self->RxLastCount)) {
  1152. upload_rxdata(self, iobase);
  1153. if (irda_device_txqueue_empty(self->netdev))
  1154. via_ircc_dma_receive(self);
  1155. }
  1156. } // timer detect complete
  1157. else
  1158. SetTimer(iobase, 4);
  1159. return TRUE;
  1160. }
  1161. /*
  1162. * Function via_ircc_interrupt (irq, dev_id)
  1163. *
  1164. * An interrupt from the chip has arrived. Time to do some work
  1165. *
  1166. */
  1167. static irqreturn_t via_ircc_interrupt(int dummy, void *dev_id)
  1168. {
  1169. struct net_device *dev = dev_id;
  1170. struct via_ircc_cb *self = netdev_priv(dev);
  1171. int iobase;
  1172. u8 iHostIntType, iRxIntType, iTxIntType;
  1173. iobase = self->io.fir_base;
  1174. spin_lock(&self->lock);
  1175. iHostIntType = GetHostStatus(iobase);
  1176. IRDA_DEBUG(4, "%s(): iHostIntType %02x: %s %s %s %02x\n",
  1177. __func__, iHostIntType,
  1178. (iHostIntType & 0x40) ? "Timer" : "",
  1179. (iHostIntType & 0x20) ? "Tx" : "",
  1180. (iHostIntType & 0x10) ? "Rx" : "",
  1181. (iHostIntType & 0x0e) >> 1);
  1182. if ((iHostIntType & 0x40) != 0) { //Timer Event
  1183. self->EventFlag.TimeOut++;
  1184. ClearTimerInt(iobase, 1);
  1185. if (self->io.direction == IO_XMIT) {
  1186. via_ircc_dma_xmit(self, iobase);
  1187. }
  1188. if (self->io.direction == IO_RECV) {
  1189. /*
  1190. * frame ready hold too long, must reset.
  1191. */
  1192. if (self->RxDataReady > 30) {
  1193. hwreset(self);
  1194. if (irda_device_txqueue_empty(self->netdev)) {
  1195. via_ircc_dma_receive(self);
  1196. }
  1197. } else { // call this to upload frame.
  1198. RxTimerHandler(self, iobase);
  1199. }
  1200. } //RECV
  1201. } //Timer Event
  1202. if ((iHostIntType & 0x20) != 0) { //Tx Event
  1203. iTxIntType = GetTXStatus(iobase);
  1204. IRDA_DEBUG(4, "%s(): iTxIntType %02x: %s %s %s %s\n",
  1205. __func__, iTxIntType,
  1206. (iTxIntType & 0x08) ? "FIFO underr." : "",
  1207. (iTxIntType & 0x04) ? "EOM" : "",
  1208. (iTxIntType & 0x02) ? "FIFO ready" : "",
  1209. (iTxIntType & 0x01) ? "Early EOM" : "");
  1210. if (iTxIntType & 0x4) {
  1211. self->EventFlag.EOMessage++; // read and will auto clean
  1212. if (via_ircc_dma_xmit_complete(self)) {
  1213. if (irda_device_txqueue_empty
  1214. (self->netdev)) {
  1215. via_ircc_dma_receive(self);
  1216. }
  1217. } else {
  1218. self->EventFlag.Unknown++;
  1219. }
  1220. } //EOP
  1221. } //Tx Event
  1222. //----------------------------------------
  1223. if ((iHostIntType & 0x10) != 0) { //Rx Event
  1224. /* Check if DMA has finished */
  1225. iRxIntType = GetRXStatus(iobase);
  1226. IRDA_DEBUG(4, "%s(): iRxIntType %02x: %s %s %s %s %s %s %s\n",
  1227. __func__, iRxIntType,
  1228. (iRxIntType & 0x80) ? "PHY err." : "",
  1229. (iRxIntType & 0x40) ? "CRC err" : "",
  1230. (iRxIntType & 0x20) ? "FIFO overr." : "",
  1231. (iRxIntType & 0x10) ? "EOF" : "",
  1232. (iRxIntType & 0x08) ? "RxData" : "",
  1233. (iRxIntType & 0x02) ? "RxMaxLen" : "",
  1234. (iRxIntType & 0x01) ? "SIR bad" : "");
  1235. if (!iRxIntType)
  1236. IRDA_DEBUG(3, "%s(): RxIRQ =0\n", __func__);
  1237. if (iRxIntType & 0x10) {
  1238. if (via_ircc_dma_receive_complete(self, iobase)) {
  1239. //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
  1240. via_ircc_dma_receive(self);
  1241. }
  1242. } // No ERR
  1243. else { //ERR
  1244. IRDA_DEBUG(4, "%s(): RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
  1245. __func__, iRxIntType, iHostIntType,
  1246. RxCurCount(iobase, self),
  1247. self->RxLastCount);
  1248. if (iRxIntType & 0x20) { //FIFO OverRun ERR
  1249. ResetChip(iobase, 0);
  1250. ResetChip(iobase, 1);
  1251. } else { //PHY,CRC ERR
  1252. if (iRxIntType != 0x08)
  1253. hwreset(self); //F01
  1254. }
  1255. via_ircc_dma_receive(self);
  1256. } //ERR
  1257. } //Rx Event
  1258. spin_unlock(&self->lock);
  1259. return IRQ_RETVAL(iHostIntType);
  1260. }
  1261. static void hwreset(struct via_ircc_cb *self)
  1262. {
  1263. int iobase;
  1264. iobase = self->io.fir_base;
  1265. IRDA_DEBUG(3, "%s()\n", __func__);
  1266. ResetChip(iobase, 5);
  1267. EnableDMA(iobase, OFF);
  1268. EnableTX(iobase, OFF);
  1269. EnableRX(iobase, OFF);
  1270. EnRXDMA(iobase, OFF);
  1271. EnTXDMA(iobase, OFF);
  1272. RXStart(iobase, OFF);
  1273. TXStart(iobase, OFF);
  1274. InitCard(iobase);
  1275. CommonInit(iobase);
  1276. SIRFilter(iobase, ON);
  1277. SetSIR(iobase, ON);
  1278. CRC16(iobase, ON);
  1279. EnTXCRC(iobase, 0);
  1280. WriteReg(iobase, I_ST_CT_0, 0x00);
  1281. SetBaudRate(iobase, 9600);
  1282. SetPulseWidth(iobase, 12);
  1283. SetSendPreambleCount(iobase, 0);
  1284. WriteReg(iobase, I_ST_CT_0, 0x80);
  1285. /* Restore speed. */
  1286. via_ircc_change_speed(self, self->io.speed);
  1287. self->st_fifo.len = 0;
  1288. }
  1289. /*
  1290. * Function via_ircc_is_receiving (self)
  1291. *
  1292. * Return TRUE is we are currently receiving a frame
  1293. *
  1294. */
  1295. static int via_ircc_is_receiving(struct via_ircc_cb *self)
  1296. {
  1297. int status = FALSE;
  1298. int iobase;
  1299. IRDA_ASSERT(self != NULL, return FALSE;);
  1300. iobase = self->io.fir_base;
  1301. if (CkRxRecv(iobase, self))
  1302. status = TRUE;
  1303. IRDA_DEBUG(2, "%s(): status=%x....\n", __func__, status);
  1304. return status;
  1305. }
  1306. /*
  1307. * Function via_ircc_net_open (dev)
  1308. *
  1309. * Start the device
  1310. *
  1311. */
  1312. static int via_ircc_net_open(struct net_device *dev)
  1313. {
  1314. struct via_ircc_cb *self;
  1315. int iobase;
  1316. char hwname[32];
  1317. IRDA_DEBUG(3, "%s()\n", __func__);
  1318. IRDA_ASSERT(dev != NULL, return -1;);
  1319. self = netdev_priv(dev);
  1320. dev->stats.rx_packets = 0;
  1321. IRDA_ASSERT(self != NULL, return 0;);
  1322. iobase = self->io.fir_base;
  1323. if (request_irq(self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
  1324. IRDA_WARNING("%s, unable to allocate irq=%d\n", driver_name,
  1325. self->io.irq);
  1326. return -EAGAIN;
  1327. }
  1328. /*
  1329. * Always allocate the DMA channel after the IRQ, and clean up on
  1330. * failure.
  1331. */
  1332. if (request_dma(self->io.dma, dev->name)) {
  1333. IRDA_WARNING("%s, unable to allocate dma=%d\n", driver_name,
  1334. self->io.dma);
  1335. free_irq(self->io.irq, self);
  1336. return -EAGAIN;
  1337. }
  1338. if (self->io.dma2 != self->io.dma) {
  1339. if (request_dma(self->io.dma2, dev->name)) {
  1340. IRDA_WARNING("%s, unable to allocate dma2=%d\n",
  1341. driver_name, self->io.dma2);
  1342. free_irq(self->io.irq, self);
  1343. free_dma(self->io.dma);
  1344. return -EAGAIN;
  1345. }
  1346. }
  1347. /* turn on interrupts */
  1348. EnAllInt(iobase, ON);
  1349. EnInternalLoop(iobase, OFF);
  1350. EnExternalLoop(iobase, OFF);
  1351. /* */
  1352. via_ircc_dma_receive(self);
  1353. /* Ready to play! */
  1354. netif_start_queue(dev);
  1355. /*
  1356. * Open new IrLAP layer instance, now that everything should be
  1357. * initialized properly
  1358. */
  1359. sprintf(hwname, "VIA @ 0x%x", iobase);
  1360. self->irlap = irlap_open(dev, &self->qos, hwname);
  1361. self->RxLastCount = 0;
  1362. return 0;
  1363. }
  1364. /*
  1365. * Function via_ircc_net_close (dev)
  1366. *
  1367. * Stop the device
  1368. *
  1369. */
  1370. static int via_ircc_net_close(struct net_device *dev)
  1371. {
  1372. struct via_ircc_cb *self;
  1373. int iobase;
  1374. IRDA_DEBUG(3, "%s()\n", __func__);
  1375. IRDA_ASSERT(dev != NULL, return -1;);
  1376. self = netdev_priv(dev);
  1377. IRDA_ASSERT(self != NULL, return 0;);
  1378. /* Stop device */
  1379. netif_stop_queue(dev);
  1380. /* Stop and remove instance of IrLAP */
  1381. if (self->irlap)
  1382. irlap_close(self->irlap);
  1383. self->irlap = NULL;
  1384. iobase = self->io.fir_base;
  1385. EnTXDMA(iobase, OFF);
  1386. EnRXDMA(iobase, OFF);
  1387. DisableDmaChannel(self->io.dma);
  1388. /* Disable interrupts */
  1389. EnAllInt(iobase, OFF);
  1390. free_irq(self->io.irq, dev);
  1391. free_dma(self->io.dma);
  1392. if (self->io.dma2 != self->io.dma)
  1393. free_dma(self->io.dma2);
  1394. return 0;
  1395. }
  1396. /*
  1397. * Function via_ircc_net_ioctl (dev, rq, cmd)
  1398. *
  1399. * Process IOCTL commands for this device
  1400. *
  1401. */
  1402. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  1403. int cmd)
  1404. {
  1405. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1406. struct via_ircc_cb *self;
  1407. unsigned long flags;
  1408. int ret = 0;
  1409. IRDA_ASSERT(dev != NULL, return -1;);
  1410. self = netdev_priv(dev);
  1411. IRDA_ASSERT(self != NULL, return -1;);
  1412. IRDA_DEBUG(1, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name,
  1413. cmd);
  1414. /* Disable interrupts & save flags */
  1415. spin_lock_irqsave(&self->lock, flags);
  1416. switch (cmd) {
  1417. case SIOCSBANDWIDTH: /* Set bandwidth */
  1418. if (!capable(CAP_NET_ADMIN)) {
  1419. ret = -EPERM;
  1420. goto out;
  1421. }
  1422. via_ircc_change_speed(self, irq->ifr_baudrate);
  1423. break;
  1424. case SIOCSMEDIABUSY: /* Set media busy */
  1425. if (!capable(CAP_NET_ADMIN)) {
  1426. ret = -EPERM;
  1427. goto out;
  1428. }
  1429. irda_device_set_media_busy(self->netdev, TRUE);
  1430. break;
  1431. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1432. irq->ifr_receiving = via_ircc_is_receiving(self);
  1433. break;
  1434. default:
  1435. ret = -EOPNOTSUPP;
  1436. }
  1437. out:
  1438. spin_unlock_irqrestore(&self->lock, flags);
  1439. return ret;
  1440. }
  1441. MODULE_AUTHOR("VIA Technologies,inc");
  1442. MODULE_DESCRIPTION("VIA IrDA Device Driver");
  1443. MODULE_LICENSE("GPL");
  1444. module_init(via_ircc_init);
  1445. module_exit(via_ircc_cleanup);