iwl3945-base.c 221 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-commands.h"
  47. #include "iwl-3945.h"
  48. #include "iwl-3945-fh.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-core.h"
  51. #include "iwl-dev.h"
  52. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  53. struct iwl3945_tx_queue *txq);
  54. /*
  55. * module name, copyright, version, etc.
  56. */
  57. #define DRV_DESCRIPTION \
  58. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  59. #ifdef CONFIG_IWL3945_DEBUG
  60. #define VD "d"
  61. #else
  62. #define VD
  63. #endif
  64. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  65. #define VS "s"
  66. #else
  67. #define VS
  68. #endif
  69. #define IWL39_VERSION "1.2.26k" VD VS
  70. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  71. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  72. #define DRV_VERSION IWL39_VERSION
  73. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  74. MODULE_VERSION(DRV_VERSION);
  75. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  76. MODULE_LICENSE("GPL");
  77. /* module parameters */
  78. struct iwl_mod_params iwl3945_mod_params = {
  79. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  80. /* the rest are 0 by default */
  81. };
  82. static const struct ieee80211_supported_band *iwl3945_get_band(
  83. struct iwl_priv *priv, enum ieee80211_band band)
  84. {
  85. return priv->hw->wiphy->bands[band];
  86. }
  87. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  88. * DMA services
  89. *
  90. * Theory of operation
  91. *
  92. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  93. * of buffer descriptors, each of which points to one or more data buffers for
  94. * the device to read from or fill. Driver and device exchange status of each
  95. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  96. * entries in each circular buffer, to protect against confusing empty and full
  97. * queue states.
  98. *
  99. * The device reads or writes the data in the queues via the device's several
  100. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  101. *
  102. * For Tx queue, there are low mark and high mark limits. If, after queuing
  103. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  104. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  105. * Tx queue resumed.
  106. *
  107. * The 3945 operates with six queues: One receive queue, one transmit queue
  108. * (#4) for sending commands to the device firmware, and four transmit queues
  109. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  110. ***************************************************/
  111. int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
  112. {
  113. return q->write_ptr > q->read_ptr ?
  114. (i >= q->read_ptr && i < q->write_ptr) :
  115. !(i < q->read_ptr && i >= q->write_ptr);
  116. }
  117. /**
  118. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  119. */
  120. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  121. int count, int slots_num, u32 id)
  122. {
  123. q->n_bd = count;
  124. q->n_window = slots_num;
  125. q->id = id;
  126. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  127. * and iwl_queue_dec_wrap are broken. */
  128. BUG_ON(!is_power_of_2(count));
  129. /* slots_num must be power-of-two size, otherwise
  130. * get_cmd_index is broken. */
  131. BUG_ON(!is_power_of_2(slots_num));
  132. q->low_mark = q->n_window / 4;
  133. if (q->low_mark < 4)
  134. q->low_mark = 4;
  135. q->high_mark = q->n_window / 8;
  136. if (q->high_mark < 2)
  137. q->high_mark = 2;
  138. q->write_ptr = q->read_ptr = 0;
  139. return 0;
  140. }
  141. /**
  142. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  143. */
  144. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  145. struct iwl3945_tx_queue *txq, u32 id)
  146. {
  147. struct pci_dev *dev = priv->pci_dev;
  148. /* Driver private data, only for Tx (not command) queues,
  149. * not shared with device. */
  150. if (id != IWL_CMD_QUEUE_NUM) {
  151. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  152. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  153. if (!txq->txb) {
  154. IWL_ERR(priv, "kmalloc for auxiliary BD "
  155. "structures failed\n");
  156. goto error;
  157. }
  158. } else
  159. txq->txb = NULL;
  160. /* Circular buffer of transmit frame descriptors (TFDs),
  161. * shared with device */
  162. txq->bd = pci_alloc_consistent(dev,
  163. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  164. &txq->q.dma_addr);
  165. if (!txq->bd) {
  166. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  167. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  168. goto error;
  169. }
  170. txq->q.id = id;
  171. return 0;
  172. error:
  173. kfree(txq->txb);
  174. txq->txb = NULL;
  175. return -ENOMEM;
  176. }
  177. /**
  178. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  179. */
  180. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  181. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  182. {
  183. struct pci_dev *dev = priv->pci_dev;
  184. int len;
  185. int rc = 0;
  186. /*
  187. * Alloc buffer array for commands (Tx or other types of commands).
  188. * For the command queue (#4), allocate command space + one big
  189. * command for scan, since scan command is very huge; the system will
  190. * not have two scans at the same time, so only one is needed.
  191. * For data Tx queues (all other queues), no super-size command
  192. * space is needed.
  193. */
  194. len = sizeof(struct iwl_cmd) * slots_num;
  195. if (txq_id == IWL_CMD_QUEUE_NUM)
  196. len += IWL_MAX_SCAN_SIZE;
  197. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  198. if (!txq->cmd)
  199. return -ENOMEM;
  200. /* Alloc driver data array and TFD circular buffer */
  201. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  202. if (rc) {
  203. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  204. return -ENOMEM;
  205. }
  206. txq->need_update = 0;
  207. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  208. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  209. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  210. /* Initialize queue high/low-water, head/tail indexes */
  211. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  212. /* Tell device where to find queue, enable DMA channel. */
  213. iwl3945_hw_tx_queue_init(priv, txq);
  214. return 0;
  215. }
  216. /**
  217. * iwl3945_tx_queue_free - Deallocate DMA queue.
  218. * @txq: Transmit queue to deallocate.
  219. *
  220. * Empty queue by removing and destroying all BD's.
  221. * Free all buffers.
  222. * 0-fill, but do not free "txq" descriptor structure.
  223. */
  224. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
  225. {
  226. struct iwl_queue *q = &txq->q;
  227. struct pci_dev *dev = priv->pci_dev;
  228. int len;
  229. if (q->n_bd == 0)
  230. return;
  231. /* first, empty all BD's */
  232. for (; q->write_ptr != q->read_ptr;
  233. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  234. iwl3945_hw_txq_free_tfd(priv, txq);
  235. len = sizeof(struct iwl_cmd) * q->n_window;
  236. if (q->id == IWL_CMD_QUEUE_NUM)
  237. len += IWL_MAX_SCAN_SIZE;
  238. /* De-alloc array of command/tx buffers */
  239. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  240. /* De-alloc circular buffer of TFDs */
  241. if (txq->q.n_bd)
  242. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  243. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  244. /* De-alloc array of per-TFD driver data */
  245. kfree(txq->txb);
  246. txq->txb = NULL;
  247. /* 0-fill queue descriptor structure */
  248. memset(txq, 0, sizeof(*txq));
  249. }
  250. /*************** STATION TABLE MANAGEMENT ****
  251. * mac80211 should be examined to determine if sta_info is duplicating
  252. * the functionality provided here
  253. */
  254. /**************************************************************/
  255. #if 0 /* temporary disable till we add real remove station */
  256. /**
  257. * iwl3945_remove_station - Remove driver's knowledge of station.
  258. *
  259. * NOTE: This does not remove station from device's station table.
  260. */
  261. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  262. {
  263. int index = IWL_INVALID_STATION;
  264. int i;
  265. unsigned long flags;
  266. spin_lock_irqsave(&priv->sta_lock, flags);
  267. if (is_ap)
  268. index = IWL_AP_ID;
  269. else if (is_broadcast_ether_addr(addr))
  270. index = priv->hw_params.bcast_sta_id;
  271. else
  272. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  273. if (priv->stations_39[i].used &&
  274. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  275. addr)) {
  276. index = i;
  277. break;
  278. }
  279. if (unlikely(index == IWL_INVALID_STATION))
  280. goto out;
  281. if (priv->stations_39[index].used) {
  282. priv->stations_39[index].used = 0;
  283. priv->num_stations--;
  284. }
  285. BUG_ON(priv->num_stations < 0);
  286. out:
  287. spin_unlock_irqrestore(&priv->sta_lock, flags);
  288. return 0;
  289. }
  290. #endif
  291. /**
  292. * iwl3945_clear_stations_table - Clear the driver's station table
  293. *
  294. * NOTE: This does not clear or otherwise alter the device's station table.
  295. */
  296. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  297. {
  298. unsigned long flags;
  299. spin_lock_irqsave(&priv->sta_lock, flags);
  300. priv->num_stations = 0;
  301. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  302. spin_unlock_irqrestore(&priv->sta_lock, flags);
  303. }
  304. /**
  305. * iwl3945_add_station - Add station to station tables in driver and device
  306. */
  307. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  308. {
  309. int i;
  310. int index = IWL_INVALID_STATION;
  311. struct iwl3945_station_entry *station;
  312. unsigned long flags_spin;
  313. u8 rate;
  314. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  315. if (is_ap)
  316. index = IWL_AP_ID;
  317. else if (is_broadcast_ether_addr(addr))
  318. index = priv->hw_params.bcast_sta_id;
  319. else
  320. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  321. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  322. addr)) {
  323. index = i;
  324. break;
  325. }
  326. if (!priv->stations_39[i].used &&
  327. index == IWL_INVALID_STATION)
  328. index = i;
  329. }
  330. /* These two conditions has the same outcome but keep them separate
  331. since they have different meaning */
  332. if (unlikely(index == IWL_INVALID_STATION)) {
  333. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  334. return index;
  335. }
  336. if (priv->stations_39[index].used &&
  337. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  338. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  339. return index;
  340. }
  341. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  342. station = &priv->stations_39[index];
  343. station->used = 1;
  344. priv->num_stations++;
  345. /* Set up the REPLY_ADD_STA command to send to device */
  346. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  347. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  348. station->sta.mode = 0;
  349. station->sta.sta.sta_id = index;
  350. station->sta.station_flags = 0;
  351. if (priv->band == IEEE80211_BAND_5GHZ)
  352. rate = IWL_RATE_6M_PLCP;
  353. else
  354. rate = IWL_RATE_1M_PLCP;
  355. /* Turn on both antennas for the station... */
  356. station->sta.rate_n_flags =
  357. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  358. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  359. /* Add station to device's station table */
  360. iwl3945_send_add_station(priv, &station->sta, flags);
  361. return index;
  362. }
  363. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  364. #define IWL_CMD(x) case x: return #x
  365. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  366. /**
  367. * iwl3945_enqueue_hcmd - enqueue a uCode command
  368. * @priv: device private data point
  369. * @cmd: a point to the ucode command structure
  370. *
  371. * The function returns < 0 values to indicate the operation is
  372. * failed. On success, it turns the index (> 0) of command in the
  373. * command queue.
  374. */
  375. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  376. {
  377. struct iwl3945_tx_queue *txq = &priv->txq39[IWL_CMD_QUEUE_NUM];
  378. struct iwl_queue *q = &txq->q;
  379. struct iwl3945_tfd_frame *tfd;
  380. u32 *control_flags;
  381. struct iwl_cmd *out_cmd;
  382. u32 idx;
  383. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  384. dma_addr_t phys_addr;
  385. int pad;
  386. u16 count;
  387. int ret;
  388. unsigned long flags;
  389. /* If any of the command structures end up being larger than
  390. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  391. * we will need to increase the size of the TFD entries */
  392. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  393. !(cmd->meta.flags & CMD_SIZE_HUGE));
  394. if (iwl_is_rfkill(priv)) {
  395. IWL_DEBUG_INFO("Not sending command - RF KILL");
  396. return -EIO;
  397. }
  398. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  399. IWL_ERR(priv, "No space for Tx\n");
  400. return -ENOSPC;
  401. }
  402. spin_lock_irqsave(&priv->hcmd_lock, flags);
  403. tfd = &txq->bd[q->write_ptr];
  404. memset(tfd, 0, sizeof(*tfd));
  405. control_flags = (u32 *) tfd;
  406. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  407. out_cmd = &txq->cmd[idx];
  408. out_cmd->hdr.cmd = cmd->id;
  409. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  410. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  411. /* At this point, the out_cmd now has all of the incoming cmd
  412. * information */
  413. out_cmd->hdr.flags = 0;
  414. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  415. INDEX_TO_SEQ(q->write_ptr));
  416. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  417. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  418. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  419. offsetof(struct iwl_cmd, hdr);
  420. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  421. pad = U32_PAD(cmd->len);
  422. count = TFD_CTL_COUNT_GET(*control_flags);
  423. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  424. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  425. "%d bytes at %d[%d]:%d\n",
  426. get_cmd_string(out_cmd->hdr.cmd),
  427. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  428. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  429. txq->need_update = 1;
  430. /* Increment and update queue's write index */
  431. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  432. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  433. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  434. return ret ? ret : idx;
  435. }
  436. static int iwl3945_send_cmd_async(struct iwl_priv *priv,
  437. struct iwl_host_cmd *cmd)
  438. {
  439. int ret;
  440. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  441. /* An asynchronous command can not expect an SKB to be set. */
  442. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  443. /* An asynchronous command MUST have a callback. */
  444. BUG_ON(!cmd->meta.u.callback);
  445. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  446. return -EBUSY;
  447. ret = iwl3945_enqueue_hcmd(priv, cmd);
  448. if (ret < 0) {
  449. IWL_ERR(priv,
  450. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  451. get_cmd_string(cmd->id), ret);
  452. return ret;
  453. }
  454. return 0;
  455. }
  456. static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
  457. struct iwl_host_cmd *cmd)
  458. {
  459. int cmd_idx;
  460. int ret;
  461. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  462. /* A synchronous command can not have a callback set. */
  463. BUG_ON(cmd->meta.u.callback != NULL);
  464. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  465. IWL_ERR(priv,
  466. "Error sending %s: Already sending a host command\n",
  467. get_cmd_string(cmd->id));
  468. ret = -EBUSY;
  469. goto out;
  470. }
  471. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  472. if (cmd->meta.flags & CMD_WANT_SKB)
  473. cmd->meta.source = &cmd->meta;
  474. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  475. if (cmd_idx < 0) {
  476. ret = cmd_idx;
  477. IWL_ERR(priv,
  478. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  479. get_cmd_string(cmd->id), ret);
  480. goto out;
  481. }
  482. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  483. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  484. HOST_COMPLETE_TIMEOUT);
  485. if (!ret) {
  486. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  487. IWL_ERR(priv, "Error sending %s: time out after %dms\n",
  488. get_cmd_string(cmd->id),
  489. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  490. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  491. ret = -ETIMEDOUT;
  492. goto cancel;
  493. }
  494. }
  495. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  496. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  497. get_cmd_string(cmd->id));
  498. ret = -ECANCELED;
  499. goto fail;
  500. }
  501. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  502. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  503. get_cmd_string(cmd->id));
  504. ret = -EIO;
  505. goto fail;
  506. }
  507. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  508. IWL_ERR(priv, "Error: Response NULL in '%s'\n",
  509. get_cmd_string(cmd->id));
  510. ret = -EIO;
  511. goto cancel;
  512. }
  513. ret = 0;
  514. goto out;
  515. cancel:
  516. if (cmd->meta.flags & CMD_WANT_SKB) {
  517. struct iwl_cmd *qcmd;
  518. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  519. * TX cmd queue. Otherwise in case the cmd comes
  520. * in later, it will possibly set an invalid
  521. * address (cmd->meta.source). */
  522. qcmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  523. qcmd->meta.flags &= ~CMD_WANT_SKB;
  524. }
  525. fail:
  526. if (cmd->meta.u.skb) {
  527. dev_kfree_skb_any(cmd->meta.u.skb);
  528. cmd->meta.u.skb = NULL;
  529. }
  530. out:
  531. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  532. return ret;
  533. }
  534. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  535. {
  536. if (cmd->meta.flags & CMD_ASYNC)
  537. return iwl3945_send_cmd_async(priv, cmd);
  538. return iwl3945_send_cmd_sync(priv, cmd);
  539. }
  540. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  541. {
  542. struct iwl_host_cmd cmd = {
  543. .id = id,
  544. .len = len,
  545. .data = data,
  546. };
  547. return iwl3945_send_cmd_sync(priv, &cmd);
  548. }
  549. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  550. {
  551. struct iwl_host_cmd cmd = {
  552. .id = id,
  553. .len = sizeof(val),
  554. .data = &val,
  555. };
  556. return iwl3945_send_cmd_sync(priv, &cmd);
  557. }
  558. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  559. {
  560. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  561. }
  562. /**
  563. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  564. * @band: 2.4 or 5 GHz band
  565. * @channel: Any channel valid for the requested band
  566. * In addition to setting the staging RXON, priv->band is also set.
  567. *
  568. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  569. * in the staging RXON flag structure based on the band
  570. */
  571. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  572. enum ieee80211_band band,
  573. u16 channel)
  574. {
  575. if (!iwl3945_get_channel_info(priv, band, channel)) {
  576. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  577. channel, band);
  578. return -EINVAL;
  579. }
  580. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  581. (priv->band == band))
  582. return 0;
  583. priv->staging39_rxon.channel = cpu_to_le16(channel);
  584. if (band == IEEE80211_BAND_5GHZ)
  585. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  586. else
  587. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  588. priv->band = band;
  589. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  590. return 0;
  591. }
  592. /**
  593. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  594. *
  595. * NOTE: This is really only useful during development and can eventually
  596. * be #ifdef'd out once the driver is stable and folks aren't actively
  597. * making changes
  598. */
  599. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  600. {
  601. int error = 0;
  602. int counter = 1;
  603. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  604. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  605. error |= le32_to_cpu(rxon->flags &
  606. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  607. RXON_FLG_RADAR_DETECT_MSK));
  608. if (error)
  609. IWL_WARN(priv, "check 24G fields %d | %d\n",
  610. counter++, error);
  611. } else {
  612. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  613. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  614. if (error)
  615. IWL_WARN(priv, "check 52 fields %d | %d\n",
  616. counter++, error);
  617. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  618. if (error)
  619. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  620. counter++, error);
  621. }
  622. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  623. if (error)
  624. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  625. /* make sure basic rates 6Mbps and 1Mbps are supported */
  626. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  627. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  628. if (error)
  629. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  630. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  631. if (error)
  632. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  633. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  634. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  635. if (error)
  636. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  637. counter++, error);
  638. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  639. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  640. if (error)
  641. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  642. counter++, error);
  643. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  644. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  645. if (error)
  646. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  647. counter++, error);
  648. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  649. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  650. RXON_FLG_ANT_A_MSK)) == 0);
  651. if (error)
  652. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  653. if (error)
  654. IWL_WARN(priv, "Tuning to channel %d\n",
  655. le16_to_cpu(rxon->channel));
  656. if (error) {
  657. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  658. return -1;
  659. }
  660. return 0;
  661. }
  662. /**
  663. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  664. * @priv: staging_rxon is compared to active_rxon
  665. *
  666. * If the RXON structure is changing enough to require a new tune,
  667. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  668. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  669. */
  670. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  671. {
  672. /* These items are only settable from the full RXON command */
  673. if (!(iwl3945_is_associated(priv)) ||
  674. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  675. priv->active39_rxon.bssid_addr) ||
  676. compare_ether_addr(priv->staging39_rxon.node_addr,
  677. priv->active39_rxon.node_addr) ||
  678. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  679. priv->active39_rxon.wlap_bssid_addr) ||
  680. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  681. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  682. (priv->staging39_rxon.air_propagation !=
  683. priv->active39_rxon.air_propagation) ||
  684. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  685. return 1;
  686. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  687. * be updated with the RXON_ASSOC command -- however only some
  688. * flag transitions are allowed using RXON_ASSOC */
  689. /* Check if we are not switching bands */
  690. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  691. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  692. return 1;
  693. /* Check if we are switching association toggle */
  694. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  695. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  696. return 1;
  697. return 0;
  698. }
  699. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  700. {
  701. int rc = 0;
  702. struct iwl_rx_packet *res = NULL;
  703. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  704. struct iwl_host_cmd cmd = {
  705. .id = REPLY_RXON_ASSOC,
  706. .len = sizeof(rxon_assoc),
  707. .meta.flags = CMD_WANT_SKB,
  708. .data = &rxon_assoc,
  709. };
  710. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  711. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  712. if ((rxon1->flags == rxon2->flags) &&
  713. (rxon1->filter_flags == rxon2->filter_flags) &&
  714. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  715. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  716. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  717. return 0;
  718. }
  719. rxon_assoc.flags = priv->staging39_rxon.flags;
  720. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  721. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  722. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  723. rxon_assoc.reserved = 0;
  724. rc = iwl3945_send_cmd_sync(priv, &cmd);
  725. if (rc)
  726. return rc;
  727. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  728. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  729. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  730. rc = -EIO;
  731. }
  732. priv->alloc_rxb_skb--;
  733. dev_kfree_skb_any(cmd.meta.u.skb);
  734. return rc;
  735. }
  736. /**
  737. * iwl3945_commit_rxon - commit staging_rxon to hardware
  738. *
  739. * The RXON command in staging_rxon is committed to the hardware and
  740. * the active_rxon structure is updated with the new data. This
  741. * function correctly transitions out of the RXON_ASSOC_MSK state if
  742. * a HW tune is required based on the RXON structure changes.
  743. */
  744. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  745. {
  746. /* cast away the const for active_rxon in this function */
  747. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  748. int rc = 0;
  749. if (!iwl_is_alive(priv))
  750. return -1;
  751. /* always get timestamp with Rx frame */
  752. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  753. /* select antenna */
  754. priv->staging39_rxon.flags &=
  755. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  756. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  757. rc = iwl3945_check_rxon_cmd(priv);
  758. if (rc) {
  759. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  760. return -EINVAL;
  761. }
  762. /* If we don't need to send a full RXON, we can use
  763. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  764. * and other flags for the current radio configuration. */
  765. if (!iwl3945_full_rxon_required(priv)) {
  766. rc = iwl3945_send_rxon_assoc(priv);
  767. if (rc) {
  768. IWL_ERR(priv, "Error setting RXON_ASSOC "
  769. "configuration (%d).\n", rc);
  770. return rc;
  771. }
  772. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  773. return 0;
  774. }
  775. /* If we are currently associated and the new config requires
  776. * an RXON_ASSOC and the new config wants the associated mask enabled,
  777. * we must clear the associated from the active configuration
  778. * before we apply the new config */
  779. if (iwl3945_is_associated(priv) &&
  780. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  781. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  782. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  783. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  784. sizeof(struct iwl3945_rxon_cmd),
  785. &priv->active39_rxon);
  786. /* If the mask clearing failed then we set
  787. * active_rxon back to what it was previously */
  788. if (rc) {
  789. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  790. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  791. "configuration (%d).\n", rc);
  792. return rc;
  793. }
  794. }
  795. IWL_DEBUG_INFO("Sending RXON\n"
  796. "* with%s RXON_FILTER_ASSOC_MSK\n"
  797. "* channel = %d\n"
  798. "* bssid = %pM\n",
  799. ((priv->staging39_rxon.filter_flags &
  800. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  801. le16_to_cpu(priv->staging39_rxon.channel),
  802. priv->staging_rxon.bssid_addr);
  803. /* Apply the new configuration */
  804. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  805. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  806. if (rc) {
  807. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  808. return rc;
  809. }
  810. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  811. iwl3945_clear_stations_table(priv);
  812. /* If we issue a new RXON command which required a tune then we must
  813. * send a new TXPOWER command or we won't be able to Tx any frames */
  814. rc = iwl3945_hw_reg_send_txpower(priv);
  815. if (rc) {
  816. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  817. return rc;
  818. }
  819. /* Add the broadcast address so we can send broadcast frames */
  820. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  821. IWL_INVALID_STATION) {
  822. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  823. return -EIO;
  824. }
  825. /* If we have set the ASSOC_MSK and we are in BSS mode then
  826. * add the IWL_AP_ID to the station rate table */
  827. if (iwl3945_is_associated(priv) &&
  828. (priv->iw_mode == NL80211_IFTYPE_STATION))
  829. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  830. == IWL_INVALID_STATION) {
  831. IWL_ERR(priv, "Error adding AP address for transmit\n");
  832. return -EIO;
  833. }
  834. /* Init the hardware's rate fallback order based on the band */
  835. rc = iwl3945_init_hw_rate_table(priv);
  836. if (rc) {
  837. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  838. return -EIO;
  839. }
  840. return 0;
  841. }
  842. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  843. {
  844. struct iwl_bt_cmd bt_cmd = {
  845. .flags = 3,
  846. .lead_time = 0xAA,
  847. .max_kill = 1,
  848. .kill_ack_mask = 0,
  849. .kill_cts_mask = 0,
  850. };
  851. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  852. sizeof(bt_cmd), &bt_cmd);
  853. }
  854. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  855. {
  856. int rc = 0;
  857. struct iwl_rx_packet *res;
  858. struct iwl_host_cmd cmd = {
  859. .id = REPLY_SCAN_ABORT_CMD,
  860. .meta.flags = CMD_WANT_SKB,
  861. };
  862. /* If there isn't a scan actively going on in the hardware
  863. * then we are in between scan bands and not actually
  864. * actively scanning, so don't send the abort command */
  865. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  866. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  867. return 0;
  868. }
  869. rc = iwl3945_send_cmd_sync(priv, &cmd);
  870. if (rc) {
  871. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  872. return rc;
  873. }
  874. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  875. if (res->u.status != CAN_ABORT_STATUS) {
  876. /* The scan abort will return 1 for success or
  877. * 2 for "failure". A failure condition can be
  878. * due to simply not being in an active scan which
  879. * can occur if we send the scan abort before we
  880. * the microcode has notified us that a scan is
  881. * completed. */
  882. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  883. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  884. clear_bit(STATUS_SCAN_HW, &priv->status);
  885. }
  886. dev_kfree_skb_any(cmd.meta.u.skb);
  887. return rc;
  888. }
  889. static int iwl3945_card_state_sync_callback(struct iwl_priv *priv,
  890. struct iwl_cmd *cmd,
  891. struct sk_buff *skb)
  892. {
  893. return 1;
  894. }
  895. /*
  896. * CARD_STATE_CMD
  897. *
  898. * Use: Sets the device's internal card state to enable, disable, or halt
  899. *
  900. * When in the 'enable' state the card operates as normal.
  901. * When in the 'disable' state, the card enters into a low power mode.
  902. * When in the 'halt' state, the card is shut down and must be fully
  903. * restarted to come back on.
  904. */
  905. static int iwl3945_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  906. {
  907. struct iwl_host_cmd cmd = {
  908. .id = REPLY_CARD_STATE_CMD,
  909. .len = sizeof(u32),
  910. .data = &flags,
  911. .meta.flags = meta_flag,
  912. };
  913. if (meta_flag & CMD_ASYNC)
  914. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  915. return iwl3945_send_cmd(priv, &cmd);
  916. }
  917. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  918. struct iwl_cmd *cmd, struct sk_buff *skb)
  919. {
  920. struct iwl_rx_packet *res = NULL;
  921. if (!skb) {
  922. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  923. return 1;
  924. }
  925. res = (struct iwl_rx_packet *)skb->data;
  926. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  927. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  928. res->hdr.flags);
  929. return 1;
  930. }
  931. switch (res->u.add_sta.status) {
  932. case ADD_STA_SUCCESS_MSK:
  933. break;
  934. default:
  935. break;
  936. }
  937. /* We didn't cache the SKB; let the caller free it */
  938. return 1;
  939. }
  940. int iwl3945_send_add_station(struct iwl_priv *priv,
  941. struct iwl3945_addsta_cmd *sta, u8 flags)
  942. {
  943. struct iwl_rx_packet *res = NULL;
  944. int rc = 0;
  945. struct iwl_host_cmd cmd = {
  946. .id = REPLY_ADD_STA,
  947. .len = sizeof(struct iwl3945_addsta_cmd),
  948. .meta.flags = flags,
  949. .data = sta,
  950. };
  951. if (flags & CMD_ASYNC)
  952. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  953. else
  954. cmd.meta.flags |= CMD_WANT_SKB;
  955. rc = iwl3945_send_cmd(priv, &cmd);
  956. if (rc || (flags & CMD_ASYNC))
  957. return rc;
  958. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  959. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  960. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  961. res->hdr.flags);
  962. rc = -EIO;
  963. }
  964. if (rc == 0) {
  965. switch (res->u.add_sta.status) {
  966. case ADD_STA_SUCCESS_MSK:
  967. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  968. break;
  969. default:
  970. rc = -EIO;
  971. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  972. break;
  973. }
  974. }
  975. priv->alloc_rxb_skb--;
  976. dev_kfree_skb_any(cmd.meta.u.skb);
  977. return rc;
  978. }
  979. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  980. struct ieee80211_key_conf *keyconf,
  981. u8 sta_id)
  982. {
  983. unsigned long flags;
  984. __le16 key_flags = 0;
  985. switch (keyconf->alg) {
  986. case ALG_CCMP:
  987. key_flags |= STA_KEY_FLG_CCMP;
  988. key_flags |= cpu_to_le16(
  989. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  990. key_flags &= ~STA_KEY_FLG_INVALID;
  991. break;
  992. case ALG_TKIP:
  993. case ALG_WEP:
  994. default:
  995. return -EINVAL;
  996. }
  997. spin_lock_irqsave(&priv->sta_lock, flags);
  998. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  999. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  1000. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  1001. keyconf->keylen);
  1002. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  1003. keyconf->keylen);
  1004. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  1005. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1006. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1007. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1008. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1009. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1010. return 0;
  1011. }
  1012. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  1013. {
  1014. unsigned long flags;
  1015. spin_lock_irqsave(&priv->sta_lock, flags);
  1016. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1017. memset(&priv->stations_39[sta_id].sta.key, 0,
  1018. sizeof(struct iwl4965_keyinfo));
  1019. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1020. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1021. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1022. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1023. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1024. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1025. return 0;
  1026. }
  1027. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1028. {
  1029. struct list_head *element;
  1030. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1031. priv->frames_count);
  1032. while (!list_empty(&priv->free_frames)) {
  1033. element = priv->free_frames.next;
  1034. list_del(element);
  1035. kfree(list_entry(element, struct iwl3945_frame, list));
  1036. priv->frames_count--;
  1037. }
  1038. if (priv->frames_count) {
  1039. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  1040. priv->frames_count);
  1041. priv->frames_count = 0;
  1042. }
  1043. }
  1044. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1045. {
  1046. struct iwl3945_frame *frame;
  1047. struct list_head *element;
  1048. if (list_empty(&priv->free_frames)) {
  1049. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1050. if (!frame) {
  1051. IWL_ERR(priv, "Could not allocate frame!\n");
  1052. return NULL;
  1053. }
  1054. priv->frames_count++;
  1055. return frame;
  1056. }
  1057. element = priv->free_frames.next;
  1058. list_del(element);
  1059. return list_entry(element, struct iwl3945_frame, list);
  1060. }
  1061. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1062. {
  1063. memset(frame, 0, sizeof(*frame));
  1064. list_add(&frame->list, &priv->free_frames);
  1065. }
  1066. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1067. struct ieee80211_hdr *hdr,
  1068. int left)
  1069. {
  1070. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1071. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1072. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1073. return 0;
  1074. if (priv->ibss_beacon->len > left)
  1075. return 0;
  1076. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1077. return priv->ibss_beacon->len;
  1078. }
  1079. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1080. {
  1081. u8 i;
  1082. int rate_mask;
  1083. /* Set rate mask*/
  1084. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1085. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1086. else
  1087. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1088. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1089. i = iwl3945_rates[i].next_ieee) {
  1090. if (rate_mask & (1 << i))
  1091. return iwl3945_rates[i].plcp;
  1092. }
  1093. /* No valid rate was found. Assign the lowest one */
  1094. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1095. return IWL_RATE_1M_PLCP;
  1096. else
  1097. return IWL_RATE_6M_PLCP;
  1098. }
  1099. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1100. {
  1101. struct iwl3945_frame *frame;
  1102. unsigned int frame_size;
  1103. int rc;
  1104. u8 rate;
  1105. frame = iwl3945_get_free_frame(priv);
  1106. if (!frame) {
  1107. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  1108. "command.\n");
  1109. return -ENOMEM;
  1110. }
  1111. rate = iwl3945_rate_get_lowest_plcp(priv);
  1112. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1113. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1114. &frame->u.cmd[0]);
  1115. iwl3945_free_frame(priv, frame);
  1116. return rc;
  1117. }
  1118. /******************************************************************************
  1119. *
  1120. * EEPROM related functions
  1121. *
  1122. ******************************************************************************/
  1123. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1124. {
  1125. memcpy(mac, priv->eeprom39.mac_address, 6);
  1126. }
  1127. /*
  1128. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1129. * embedded controller) as EEPROM reader; each read is a series of pulses
  1130. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1131. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1132. * simply claims ownership, which should be safe when this function is called
  1133. * (i.e. before loading uCode!).
  1134. */
  1135. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1136. {
  1137. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1138. return 0;
  1139. }
  1140. /**
  1141. * iwl3945_eeprom_init - read EEPROM contents
  1142. *
  1143. * Load the EEPROM contents from adapter into priv->eeprom39
  1144. *
  1145. * NOTE: This routine uses the non-debug IO access functions.
  1146. */
  1147. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1148. {
  1149. u16 *e = (u16 *)&priv->eeprom39;
  1150. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1151. int sz = sizeof(priv->eeprom39);
  1152. int ret;
  1153. u16 addr;
  1154. /* The EEPROM structure has several padding buffers within it
  1155. * and when adding new EEPROM maps is subject to programmer errors
  1156. * which may be very difficult to identify without explicitly
  1157. * checking the resulting size of the eeprom map. */
  1158. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1159. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1160. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1161. return -ENOENT;
  1162. }
  1163. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1164. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1165. if (ret < 0) {
  1166. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  1167. return -ENOENT;
  1168. }
  1169. /* eeprom is an array of 16bit values */
  1170. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1171. u32 r;
  1172. _iwl_write32(priv, CSR_EEPROM_REG,
  1173. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1174. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1175. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1176. CSR_EEPROM_REG_READ_VALID_MSK,
  1177. IWL_EEPROM_ACCESS_TIMEOUT);
  1178. if (ret < 0) {
  1179. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  1180. return ret;
  1181. }
  1182. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1183. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1184. }
  1185. return 0;
  1186. }
  1187. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1188. {
  1189. if (priv->shared_virt)
  1190. pci_free_consistent(priv->pci_dev,
  1191. sizeof(struct iwl3945_shared),
  1192. priv->shared_virt,
  1193. priv->shared_phys);
  1194. }
  1195. /**
  1196. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1197. *
  1198. * return : set the bit for each supported rate insert in ie
  1199. */
  1200. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1201. u16 basic_rate, int *left)
  1202. {
  1203. u16 ret_rates = 0, bit;
  1204. int i;
  1205. u8 *cnt = ie;
  1206. u8 *rates = ie + 1;
  1207. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1208. if (bit & supported_rate) {
  1209. ret_rates |= bit;
  1210. rates[*cnt] = iwl3945_rates[i].ieee |
  1211. ((bit & basic_rate) ? 0x80 : 0x00);
  1212. (*cnt)++;
  1213. (*left)--;
  1214. if ((*left <= 0) ||
  1215. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1216. break;
  1217. }
  1218. }
  1219. return ret_rates;
  1220. }
  1221. /**
  1222. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1223. */
  1224. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1225. struct ieee80211_mgmt *frame,
  1226. int left)
  1227. {
  1228. int len = 0;
  1229. u8 *pos = NULL;
  1230. u16 active_rates, ret_rates, cck_rates;
  1231. /* Make sure there is enough space for the probe request,
  1232. * two mandatory IEs and the data */
  1233. left -= 24;
  1234. if (left < 0)
  1235. return 0;
  1236. len += 24;
  1237. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1238. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1239. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1240. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1241. frame->seq_ctrl = 0;
  1242. /* fill in our indirect SSID IE */
  1243. /* ...next IE... */
  1244. left -= 2;
  1245. if (left < 0)
  1246. return 0;
  1247. len += 2;
  1248. pos = &(frame->u.probe_req.variable[0]);
  1249. *pos++ = WLAN_EID_SSID;
  1250. *pos++ = 0;
  1251. /* fill in supported rate */
  1252. /* ...next IE... */
  1253. left -= 2;
  1254. if (left < 0)
  1255. return 0;
  1256. /* ... fill it in... */
  1257. *pos++ = WLAN_EID_SUPP_RATES;
  1258. *pos = 0;
  1259. priv->active_rate = priv->rates_mask;
  1260. active_rates = priv->active_rate;
  1261. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1262. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1263. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1264. priv->active_rate_basic, &left);
  1265. active_rates &= ~ret_rates;
  1266. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1267. priv->active_rate_basic, &left);
  1268. active_rates &= ~ret_rates;
  1269. len += 2 + *pos;
  1270. pos += (*pos) + 1;
  1271. if (active_rates == 0)
  1272. goto fill_end;
  1273. /* fill in supported extended rate */
  1274. /* ...next IE... */
  1275. left -= 2;
  1276. if (left < 0)
  1277. return 0;
  1278. /* ... fill it in... */
  1279. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1280. *pos = 0;
  1281. iwl3945_supported_rate_to_ie(pos, active_rates,
  1282. priv->active_rate_basic, &left);
  1283. if (*pos > 0)
  1284. len += 2 + *pos;
  1285. fill_end:
  1286. return (u16)len;
  1287. }
  1288. /*
  1289. * QoS support
  1290. */
  1291. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1292. struct iwl_qosparam_cmd *qos)
  1293. {
  1294. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1295. sizeof(struct iwl_qosparam_cmd), qos);
  1296. }
  1297. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1298. {
  1299. unsigned long flags;
  1300. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1301. return;
  1302. spin_lock_irqsave(&priv->lock, flags);
  1303. priv->qos_data.def_qos_parm.qos_flags = 0;
  1304. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1305. !priv->qos_data.qos_cap.q_AP.txop_request)
  1306. priv->qos_data.def_qos_parm.qos_flags |=
  1307. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1308. if (priv->qos_data.qos_active)
  1309. priv->qos_data.def_qos_parm.qos_flags |=
  1310. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1311. spin_unlock_irqrestore(&priv->lock, flags);
  1312. if (force || iwl3945_is_associated(priv)) {
  1313. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1314. priv->qos_data.qos_active);
  1315. iwl3945_send_qos_params_command(priv,
  1316. &(priv->qos_data.def_qos_parm));
  1317. }
  1318. }
  1319. /*
  1320. * Power management (not Tx power!) functions
  1321. */
  1322. #define MSEC_TO_USEC 1024
  1323. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1324. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1325. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1326. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1327. __constant_cpu_to_le32(X1), \
  1328. __constant_cpu_to_le32(X2), \
  1329. __constant_cpu_to_le32(X3), \
  1330. __constant_cpu_to_le32(X4)}
  1331. /* default power management (not Tx power) table values */
  1332. /* for TIM 0-10 */
  1333. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1334. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1335. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1336. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1337. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1338. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1339. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1340. };
  1341. /* for TIM > 10 */
  1342. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1343. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1344. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1345. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1346. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1347. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1348. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1349. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1350. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1351. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1352. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1353. };
  1354. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1355. {
  1356. int rc = 0, i;
  1357. struct iwl3945_power_mgr *pow_data;
  1358. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1359. u16 pci_pm;
  1360. IWL_DEBUG_POWER("Initialize power \n");
  1361. pow_data = &(priv->power_data_39);
  1362. memset(pow_data, 0, sizeof(*pow_data));
  1363. pow_data->active_index = IWL_POWER_RANGE_0;
  1364. pow_data->dtim_val = 0xffff;
  1365. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1366. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1367. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1368. if (rc != 0)
  1369. return 0;
  1370. else {
  1371. struct iwl_powertable_cmd *cmd;
  1372. IWL_DEBUG_POWER("adjust power command flags\n");
  1373. for (i = 0; i < IWL39_POWER_AC; i++) {
  1374. cmd = &pow_data->pwr_range_0[i].cmd;
  1375. if (pci_pm & 0x1)
  1376. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1377. else
  1378. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1379. }
  1380. }
  1381. return rc;
  1382. }
  1383. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1384. struct iwl_powertable_cmd *cmd, u32 mode)
  1385. {
  1386. int rc = 0, i;
  1387. u8 skip;
  1388. u32 max_sleep = 0;
  1389. struct iwl_power_vec_entry *range;
  1390. u8 period = 0;
  1391. struct iwl3945_power_mgr *pow_data;
  1392. if (mode > IWL_POWER_INDEX_5) {
  1393. IWL_DEBUG_POWER("Error invalid power mode \n");
  1394. return -1;
  1395. }
  1396. pow_data = &(priv->power_data_39);
  1397. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1398. range = &pow_data->pwr_range_0[0];
  1399. else
  1400. range = &pow_data->pwr_range_1[1];
  1401. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1402. #ifdef IWL_MAC80211_DISABLE
  1403. if (priv->assoc_network != NULL) {
  1404. unsigned long flags;
  1405. period = priv->assoc_network->tim.tim_period;
  1406. }
  1407. #endif /*IWL_MAC80211_DISABLE */
  1408. skip = range[mode].no_dtim;
  1409. if (period == 0) {
  1410. period = 1;
  1411. skip = 0;
  1412. }
  1413. if (skip == 0) {
  1414. max_sleep = period;
  1415. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1416. } else {
  1417. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1418. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1419. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1420. }
  1421. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1422. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1423. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1424. }
  1425. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1426. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1427. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1428. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1429. le32_to_cpu(cmd->sleep_interval[0]),
  1430. le32_to_cpu(cmd->sleep_interval[1]),
  1431. le32_to_cpu(cmd->sleep_interval[2]),
  1432. le32_to_cpu(cmd->sleep_interval[3]),
  1433. le32_to_cpu(cmd->sleep_interval[4]));
  1434. return rc;
  1435. }
  1436. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1437. {
  1438. u32 uninitialized_var(final_mode);
  1439. int rc;
  1440. struct iwl_powertable_cmd cmd;
  1441. /* If on battery, set to 3,
  1442. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1443. * else user level */
  1444. switch (mode) {
  1445. case IWL39_POWER_BATTERY:
  1446. final_mode = IWL_POWER_INDEX_3;
  1447. break;
  1448. case IWL39_POWER_AC:
  1449. final_mode = IWL_POWER_MODE_CAM;
  1450. break;
  1451. default:
  1452. final_mode = mode;
  1453. break;
  1454. }
  1455. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1456. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1457. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1458. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1459. if (final_mode == IWL_POWER_MODE_CAM)
  1460. clear_bit(STATUS_POWER_PMI, &priv->status);
  1461. else
  1462. set_bit(STATUS_POWER_PMI, &priv->status);
  1463. return rc;
  1464. }
  1465. /**
  1466. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1467. *
  1468. * NOTE: priv->mutex is not required before calling this function
  1469. */
  1470. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1471. {
  1472. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1473. clear_bit(STATUS_SCANNING, &priv->status);
  1474. return 0;
  1475. }
  1476. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1477. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1478. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1479. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1480. queue_work(priv->workqueue, &priv->abort_scan);
  1481. } else
  1482. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1483. return test_bit(STATUS_SCANNING, &priv->status);
  1484. }
  1485. return 0;
  1486. }
  1487. /**
  1488. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1489. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1490. *
  1491. * NOTE: priv->mutex must be held before calling this function
  1492. */
  1493. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1494. {
  1495. unsigned long now = jiffies;
  1496. int ret;
  1497. ret = iwl3945_scan_cancel(priv);
  1498. if (ret && ms) {
  1499. mutex_unlock(&priv->mutex);
  1500. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1501. test_bit(STATUS_SCANNING, &priv->status))
  1502. msleep(1);
  1503. mutex_lock(&priv->mutex);
  1504. return test_bit(STATUS_SCANNING, &priv->status);
  1505. }
  1506. return ret;
  1507. }
  1508. #define MAX_UCODE_BEACON_INTERVAL 1024
  1509. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1510. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1511. {
  1512. u16 new_val = 0;
  1513. u16 beacon_factor = 0;
  1514. beacon_factor =
  1515. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1516. / MAX_UCODE_BEACON_INTERVAL;
  1517. new_val = beacon_val / beacon_factor;
  1518. return cpu_to_le16(new_val);
  1519. }
  1520. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1521. {
  1522. u64 interval_tm_unit;
  1523. u64 tsf, result;
  1524. unsigned long flags;
  1525. struct ieee80211_conf *conf = NULL;
  1526. u16 beacon_int = 0;
  1527. conf = ieee80211_get_hw_conf(priv->hw);
  1528. spin_lock_irqsave(&priv->lock, flags);
  1529. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1530. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1531. tsf = priv->timestamp;
  1532. beacon_int = priv->beacon_int;
  1533. spin_unlock_irqrestore(&priv->lock, flags);
  1534. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1535. if (beacon_int == 0) {
  1536. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1537. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1538. } else {
  1539. priv->rxon_timing.beacon_interval =
  1540. cpu_to_le16(beacon_int);
  1541. priv->rxon_timing.beacon_interval =
  1542. iwl3945_adjust_beacon_interval(
  1543. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1544. }
  1545. priv->rxon_timing.atim_window = 0;
  1546. } else {
  1547. priv->rxon_timing.beacon_interval =
  1548. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1549. /* TODO: we need to get atim_window from upper stack
  1550. * for now we set to 0 */
  1551. priv->rxon_timing.atim_window = 0;
  1552. }
  1553. interval_tm_unit =
  1554. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1555. result = do_div(tsf, interval_tm_unit);
  1556. priv->rxon_timing.beacon_init_val =
  1557. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1558. IWL_DEBUG_ASSOC
  1559. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1560. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1561. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1562. le16_to_cpu(priv->rxon_timing.atim_window));
  1563. }
  1564. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1565. {
  1566. if (!iwl_is_ready_rf(priv)) {
  1567. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1568. return -EIO;
  1569. }
  1570. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1571. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1572. return -EAGAIN;
  1573. }
  1574. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1575. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1576. "Queuing.\n");
  1577. return -EAGAIN;
  1578. }
  1579. IWL_DEBUG_INFO("Starting scan...\n");
  1580. if (priv->cfg->sku & IWL_SKU_G)
  1581. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1582. if (priv->cfg->sku & IWL_SKU_A)
  1583. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1584. set_bit(STATUS_SCANNING, &priv->status);
  1585. priv->scan_start = jiffies;
  1586. priv->scan_pass_start = priv->scan_start;
  1587. queue_work(priv->workqueue, &priv->request_scan);
  1588. return 0;
  1589. }
  1590. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1591. {
  1592. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1593. if (hw_decrypt)
  1594. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1595. else
  1596. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1597. return 0;
  1598. }
  1599. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1600. enum ieee80211_band band)
  1601. {
  1602. if (band == IEEE80211_BAND_5GHZ) {
  1603. priv->staging39_rxon.flags &=
  1604. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1605. | RXON_FLG_CCK_MSK);
  1606. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1607. } else {
  1608. /* Copied from iwl3945_bg_post_associate() */
  1609. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1610. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1611. else
  1612. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1613. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1614. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1615. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1616. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1617. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1618. }
  1619. }
  1620. /*
  1621. * initialize rxon structure with default values from eeprom
  1622. */
  1623. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1624. int mode)
  1625. {
  1626. const struct iwl_channel_info *ch_info;
  1627. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1628. switch (mode) {
  1629. case NL80211_IFTYPE_AP:
  1630. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1631. break;
  1632. case NL80211_IFTYPE_STATION:
  1633. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1634. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1635. break;
  1636. case NL80211_IFTYPE_ADHOC:
  1637. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1638. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1639. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1640. RXON_FILTER_ACCEPT_GRP_MSK;
  1641. break;
  1642. case NL80211_IFTYPE_MONITOR:
  1643. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1644. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1645. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1646. break;
  1647. default:
  1648. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1649. break;
  1650. }
  1651. #if 0
  1652. /* TODO: Figure out when short_preamble would be set and cache from
  1653. * that */
  1654. if (!hw_to_local(priv->hw)->short_preamble)
  1655. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1656. else
  1657. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1658. #endif
  1659. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1660. le16_to_cpu(priv->active39_rxon.channel));
  1661. if (!ch_info)
  1662. ch_info = &priv->channel_info[0];
  1663. /*
  1664. * in some case A channels are all non IBSS
  1665. * in this case force B/G channel
  1666. */
  1667. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1668. ch_info = &priv->channel_info[0];
  1669. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1670. if (is_channel_a_band(ch_info))
  1671. priv->band = IEEE80211_BAND_5GHZ;
  1672. else
  1673. priv->band = IEEE80211_BAND_2GHZ;
  1674. iwl3945_set_flags_for_phymode(priv, priv->band);
  1675. priv->staging39_rxon.ofdm_basic_rates =
  1676. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1677. priv->staging39_rxon.cck_basic_rates =
  1678. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1679. }
  1680. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1681. {
  1682. if (mode == NL80211_IFTYPE_ADHOC) {
  1683. const struct iwl_channel_info *ch_info;
  1684. ch_info = iwl3945_get_channel_info(priv,
  1685. priv->band,
  1686. le16_to_cpu(priv->staging39_rxon.channel));
  1687. if (!ch_info || !is_channel_ibss(ch_info)) {
  1688. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1689. le16_to_cpu(priv->staging39_rxon.channel));
  1690. return -EINVAL;
  1691. }
  1692. }
  1693. iwl3945_connection_init_rx_config(priv, mode);
  1694. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1695. iwl3945_clear_stations_table(priv);
  1696. /* don't commit rxon if rf-kill is on*/
  1697. if (!iwl_is_ready_rf(priv))
  1698. return -EAGAIN;
  1699. cancel_delayed_work(&priv->scan_check);
  1700. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1701. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1702. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1703. return -EAGAIN;
  1704. }
  1705. iwl3945_commit_rxon(priv);
  1706. return 0;
  1707. }
  1708. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1709. struct ieee80211_tx_info *info,
  1710. struct iwl_cmd *cmd,
  1711. struct sk_buff *skb_frag,
  1712. int last_frag)
  1713. {
  1714. struct iwl3945_hw_key *keyinfo =
  1715. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1716. switch (keyinfo->alg) {
  1717. case ALG_CCMP:
  1718. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1719. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1720. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1721. break;
  1722. case ALG_TKIP:
  1723. #if 0
  1724. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1725. if (last_frag)
  1726. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1727. 8);
  1728. else
  1729. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1730. #endif
  1731. break;
  1732. case ALG_WEP:
  1733. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1734. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1735. if (keyinfo->keylen == 13)
  1736. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1737. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1738. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1739. "with key %d\n", info->control.hw_key->hw_key_idx);
  1740. break;
  1741. default:
  1742. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1743. break;
  1744. }
  1745. }
  1746. /*
  1747. * handle build REPLY_TX command notification.
  1748. */
  1749. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1750. struct iwl_cmd *cmd,
  1751. struct ieee80211_tx_info *info,
  1752. struct ieee80211_hdr *hdr,
  1753. int is_unicast, u8 std_id)
  1754. {
  1755. __le16 fc = hdr->frame_control;
  1756. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1757. u8 rc_flags = info->control.rates[0].flags;
  1758. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1759. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1760. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1761. if (ieee80211_is_mgmt(fc))
  1762. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1763. if (ieee80211_is_probe_resp(fc) &&
  1764. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1765. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1766. } else {
  1767. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1768. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1769. }
  1770. cmd->cmd.tx.sta_id = std_id;
  1771. if (ieee80211_has_morefrags(fc))
  1772. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1773. if (ieee80211_is_data_qos(fc)) {
  1774. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1775. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1776. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1777. } else {
  1778. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1779. }
  1780. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1781. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1782. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1783. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1784. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1785. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1786. }
  1787. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1788. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1789. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1790. if (ieee80211_is_mgmt(fc)) {
  1791. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1792. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1793. else
  1794. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1795. } else {
  1796. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1797. #ifdef CONFIG_IWL3945_LEDS
  1798. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1799. #endif
  1800. }
  1801. cmd->cmd.tx.driver_txop = 0;
  1802. cmd->cmd.tx.tx_flags = tx_flags;
  1803. cmd->cmd.tx.next_frame_len = 0;
  1804. }
  1805. /**
  1806. * iwl3945_get_sta_id - Find station's index within station table
  1807. */
  1808. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1809. {
  1810. int sta_id;
  1811. u16 fc = le16_to_cpu(hdr->frame_control);
  1812. /* If this frame is broadcast or management, use broadcast station id */
  1813. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1814. is_multicast_ether_addr(hdr->addr1))
  1815. return priv->hw_params.bcast_sta_id;
  1816. switch (priv->iw_mode) {
  1817. /* If we are a client station in a BSS network, use the special
  1818. * AP station entry (that's the only station we communicate with) */
  1819. case NL80211_IFTYPE_STATION:
  1820. return IWL_AP_ID;
  1821. /* If we are an AP, then find the station, or use BCAST */
  1822. case NL80211_IFTYPE_AP:
  1823. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1824. if (sta_id != IWL_INVALID_STATION)
  1825. return sta_id;
  1826. return priv->hw_params.bcast_sta_id;
  1827. /* If this frame is going out to an IBSS network, find the station,
  1828. * or create a new station table entry */
  1829. case NL80211_IFTYPE_ADHOC: {
  1830. /* Create new station table entry */
  1831. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1832. if (sta_id != IWL_INVALID_STATION)
  1833. return sta_id;
  1834. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1835. if (sta_id != IWL_INVALID_STATION)
  1836. return sta_id;
  1837. IWL_DEBUG_DROP("Station %pM not in station map. "
  1838. "Defaulting to broadcast...\n",
  1839. hdr->addr1);
  1840. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1841. return priv->hw_params.bcast_sta_id;
  1842. }
  1843. /* If we are in monitor mode, use BCAST. This is required for
  1844. * packet injection. */
  1845. case NL80211_IFTYPE_MONITOR:
  1846. return priv->hw_params.bcast_sta_id;
  1847. default:
  1848. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1849. priv->iw_mode);
  1850. return priv->hw_params.bcast_sta_id;
  1851. }
  1852. }
  1853. /*
  1854. * start REPLY_TX command process
  1855. */
  1856. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1857. {
  1858. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1859. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1860. struct iwl3945_tfd_frame *tfd;
  1861. u32 *control_flags;
  1862. int txq_id = skb_get_queue_mapping(skb);
  1863. struct iwl3945_tx_queue *txq = NULL;
  1864. struct iwl_queue *q = NULL;
  1865. dma_addr_t phys_addr;
  1866. dma_addr_t txcmd_phys;
  1867. struct iwl_cmd *out_cmd = NULL;
  1868. u16 len, idx, len_org, hdr_len;
  1869. u8 id;
  1870. u8 unicast;
  1871. u8 sta_id;
  1872. u8 tid = 0;
  1873. u16 seq_number = 0;
  1874. __le16 fc;
  1875. u8 wait_write_ptr = 0;
  1876. u8 *qc = NULL;
  1877. unsigned long flags;
  1878. int rc;
  1879. spin_lock_irqsave(&priv->lock, flags);
  1880. if (iwl_is_rfkill(priv)) {
  1881. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1882. goto drop_unlock;
  1883. }
  1884. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1885. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1886. goto drop_unlock;
  1887. }
  1888. unicast = !is_multicast_ether_addr(hdr->addr1);
  1889. id = 0;
  1890. fc = hdr->frame_control;
  1891. #ifdef CONFIG_IWL3945_DEBUG
  1892. if (ieee80211_is_auth(fc))
  1893. IWL_DEBUG_TX("Sending AUTH frame\n");
  1894. else if (ieee80211_is_assoc_req(fc))
  1895. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1896. else if (ieee80211_is_reassoc_req(fc))
  1897. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1898. #endif
  1899. /* drop all data frame if we are not associated */
  1900. if (ieee80211_is_data(fc) &&
  1901. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1902. (!iwl3945_is_associated(priv) ||
  1903. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1904. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1905. goto drop_unlock;
  1906. }
  1907. spin_unlock_irqrestore(&priv->lock, flags);
  1908. hdr_len = ieee80211_hdrlen(fc);
  1909. /* Find (or create) index into station table for destination station */
  1910. sta_id = iwl3945_get_sta_id(priv, hdr);
  1911. if (sta_id == IWL_INVALID_STATION) {
  1912. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1913. hdr->addr1);
  1914. goto drop;
  1915. }
  1916. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1917. if (ieee80211_is_data_qos(fc)) {
  1918. qc = ieee80211_get_qos_ctl(hdr);
  1919. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1920. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1921. IEEE80211_SCTL_SEQ;
  1922. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1923. (hdr->seq_ctrl &
  1924. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1925. seq_number += 0x10;
  1926. }
  1927. /* Descriptor for chosen Tx queue */
  1928. txq = &priv->txq39[txq_id];
  1929. q = &txq->q;
  1930. spin_lock_irqsave(&priv->lock, flags);
  1931. /* Set up first empty TFD within this queue's circular TFD buffer */
  1932. tfd = &txq->bd[q->write_ptr];
  1933. memset(tfd, 0, sizeof(*tfd));
  1934. control_flags = (u32 *) tfd;
  1935. idx = get_cmd_index(q, q->write_ptr, 0);
  1936. /* Set up driver data for this TFD */
  1937. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  1938. txq->txb[q->write_ptr].skb[0] = skb;
  1939. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1940. out_cmd = &txq->cmd[idx];
  1941. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1942. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  1943. /*
  1944. * Set up the Tx-command (not MAC!) header.
  1945. * Store the chosen Tx queue and TFD index within the sequence field;
  1946. * after Tx, uCode's Tx response will return this value so driver can
  1947. * locate the frame within the tx queue and do post-tx processing.
  1948. */
  1949. out_cmd->hdr.cmd = REPLY_TX;
  1950. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1951. INDEX_TO_SEQ(q->write_ptr)));
  1952. /* Copy MAC header from skb into command buffer */
  1953. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  1954. /*
  1955. * Use the first empty entry in this queue's command buffer array
  1956. * to contain the Tx command and MAC header concatenated together
  1957. * (payload data will be in another buffer).
  1958. * Size of this varies, due to varying MAC header length.
  1959. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1960. * of the MAC header (device reads on dword boundaries).
  1961. * We'll tell device about this padding later.
  1962. */
  1963. len = sizeof(struct iwl3945_tx_cmd) +
  1964. sizeof(struct iwl_cmd_header) + hdr_len;
  1965. len_org = len;
  1966. len = (len + 3) & ~3;
  1967. if (len_org != len)
  1968. len_org = 1;
  1969. else
  1970. len_org = 0;
  1971. /* Physical address of this Tx command's header (not MAC header!),
  1972. * within command buffer array. */
  1973. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
  1974. offsetof(struct iwl_cmd, hdr);
  1975. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1976. * first entry */
  1977. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  1978. if (info->control.hw_key)
  1979. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1980. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1981. * if any (802.11 null frames have no payload). */
  1982. len = skb->len - hdr_len;
  1983. if (len) {
  1984. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1985. len, PCI_DMA_TODEVICE);
  1986. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  1987. }
  1988. if (!len)
  1989. /* If there is no payload, then we use only one Tx buffer */
  1990. *control_flags = TFD_CTL_COUNT_SET(1);
  1991. else
  1992. /* Else use 2 buffers.
  1993. * Tell 3945 about any padding after MAC header */
  1994. *control_flags = TFD_CTL_COUNT_SET(2) |
  1995. TFD_CTL_PAD_SET(U32_PAD(len));
  1996. /* Total # bytes to be transmitted */
  1997. len = (u16)skb->len;
  1998. out_cmd->cmd.tx.len = cpu_to_le16(len);
  1999. /* TODO need this for burst mode later on */
  2000. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2001. /* set is_hcca to 0; it probably will never be implemented */
  2002. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2003. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2004. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2005. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2006. txq->need_update = 1;
  2007. if (qc)
  2008. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  2009. } else {
  2010. wait_write_ptr = 1;
  2011. txq->need_update = 0;
  2012. }
  2013. iwl_print_hex_dump(priv, IWL_DL_TX, out_cmd->cmd.payload,
  2014. sizeof(out_cmd->cmd.tx));
  2015. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2016. ieee80211_hdrlen(fc));
  2017. /* Tell device the write index *just past* this latest filled TFD */
  2018. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2019. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2020. spin_unlock_irqrestore(&priv->lock, flags);
  2021. if (rc)
  2022. return rc;
  2023. if ((iwl_queue_space(q) < q->high_mark)
  2024. && priv->mac80211_registered) {
  2025. if (wait_write_ptr) {
  2026. spin_lock_irqsave(&priv->lock, flags);
  2027. txq->need_update = 1;
  2028. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2029. spin_unlock_irqrestore(&priv->lock, flags);
  2030. }
  2031. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2032. }
  2033. return 0;
  2034. drop_unlock:
  2035. spin_unlock_irqrestore(&priv->lock, flags);
  2036. drop:
  2037. return -1;
  2038. }
  2039. static void iwl3945_set_rate(struct iwl_priv *priv)
  2040. {
  2041. const struct ieee80211_supported_band *sband = NULL;
  2042. struct ieee80211_rate *rate;
  2043. int i;
  2044. sband = iwl3945_get_band(priv, priv->band);
  2045. if (!sband) {
  2046. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  2047. return;
  2048. }
  2049. priv->active_rate = 0;
  2050. priv->active_rate_basic = 0;
  2051. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2052. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2053. for (i = 0; i < sband->n_bitrates; i++) {
  2054. rate = &sband->bitrates[i];
  2055. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2056. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2057. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2058. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2059. priv->active_rate |= (1 << rate->hw_value);
  2060. }
  2061. }
  2062. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2063. priv->active_rate, priv->active_rate_basic);
  2064. /*
  2065. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2066. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2067. * OFDM
  2068. */
  2069. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2070. priv->staging39_rxon.cck_basic_rates =
  2071. ((priv->active_rate_basic &
  2072. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2073. else
  2074. priv->staging39_rxon.cck_basic_rates =
  2075. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2076. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2077. priv->staging39_rxon.ofdm_basic_rates =
  2078. ((priv->active_rate_basic &
  2079. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2080. IWL_FIRST_OFDM_RATE) & 0xFF;
  2081. else
  2082. priv->staging39_rxon.ofdm_basic_rates =
  2083. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2084. }
  2085. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2086. {
  2087. unsigned long flags;
  2088. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2089. return;
  2090. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2091. disable_radio ? "OFF" : "ON");
  2092. if (disable_radio) {
  2093. iwl3945_scan_cancel(priv);
  2094. /* FIXME: This is a workaround for AP */
  2095. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2096. spin_lock_irqsave(&priv->lock, flags);
  2097. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2098. CSR_UCODE_SW_BIT_RFKILL);
  2099. spin_unlock_irqrestore(&priv->lock, flags);
  2100. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2101. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2102. }
  2103. return;
  2104. }
  2105. spin_lock_irqsave(&priv->lock, flags);
  2106. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2107. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2108. spin_unlock_irqrestore(&priv->lock, flags);
  2109. /* wake up ucode */
  2110. msleep(10);
  2111. spin_lock_irqsave(&priv->lock, flags);
  2112. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2113. if (!iwl_grab_nic_access(priv))
  2114. iwl_release_nic_access(priv);
  2115. spin_unlock_irqrestore(&priv->lock, flags);
  2116. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2117. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2118. "disabled by HW switch\n");
  2119. return;
  2120. }
  2121. if (priv->is_open)
  2122. queue_work(priv->workqueue, &priv->restart);
  2123. return;
  2124. }
  2125. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2126. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2127. {
  2128. u16 fc =
  2129. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2130. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2131. return;
  2132. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2133. return;
  2134. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2135. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2136. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2137. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2138. RX_RES_STATUS_BAD_ICV_MIC)
  2139. stats->flag |= RX_FLAG_MMIC_ERROR;
  2140. case RX_RES_STATUS_SEC_TYPE_WEP:
  2141. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2142. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2143. RX_RES_STATUS_DECRYPT_OK) {
  2144. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2145. stats->flag |= RX_FLAG_DECRYPTED;
  2146. }
  2147. break;
  2148. default:
  2149. break;
  2150. }
  2151. }
  2152. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2153. #include "iwl-spectrum.h"
  2154. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2155. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2156. #define TIME_UNIT 1024
  2157. /*
  2158. * extended beacon time format
  2159. * time in usec will be changed into a 32-bit value in 8:24 format
  2160. * the high 1 byte is the beacon counts
  2161. * the lower 3 bytes is the time in usec within one beacon interval
  2162. */
  2163. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2164. {
  2165. u32 quot;
  2166. u32 rem;
  2167. u32 interval = beacon_interval * 1024;
  2168. if (!interval || !usec)
  2169. return 0;
  2170. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2171. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2172. return (quot << 24) + rem;
  2173. }
  2174. /* base is usually what we get from ucode with each received frame,
  2175. * the same as HW timer counter counting down
  2176. */
  2177. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2178. {
  2179. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2180. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2181. u32 interval = beacon_interval * TIME_UNIT;
  2182. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2183. (addon & BEACON_TIME_MASK_HIGH);
  2184. if (base_low > addon_low)
  2185. res += base_low - addon_low;
  2186. else if (base_low < addon_low) {
  2187. res += interval + base_low - addon_low;
  2188. res += (1 << 24);
  2189. } else
  2190. res += (1 << 24);
  2191. return cpu_to_le32(res);
  2192. }
  2193. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2194. struct ieee80211_measurement_params *params,
  2195. u8 type)
  2196. {
  2197. struct iwl_spectrum_cmd spectrum;
  2198. struct iwl_rx_packet *res;
  2199. struct iwl_host_cmd cmd = {
  2200. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2201. .data = (void *)&spectrum,
  2202. .meta.flags = CMD_WANT_SKB,
  2203. };
  2204. u32 add_time = le64_to_cpu(params->start_time);
  2205. int rc;
  2206. int spectrum_resp_status;
  2207. int duration = le16_to_cpu(params->duration);
  2208. if (iwl3945_is_associated(priv))
  2209. add_time =
  2210. iwl3945_usecs_to_beacons(
  2211. le64_to_cpu(params->start_time) - priv->last_tsf,
  2212. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2213. memset(&spectrum, 0, sizeof(spectrum));
  2214. spectrum.channel_count = cpu_to_le16(1);
  2215. spectrum.flags =
  2216. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2217. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2218. cmd.len = sizeof(spectrum);
  2219. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2220. if (iwl3945_is_associated(priv))
  2221. spectrum.start_time =
  2222. iwl3945_add_beacon_time(priv->last_beacon_time,
  2223. add_time,
  2224. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2225. else
  2226. spectrum.start_time = 0;
  2227. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2228. spectrum.channels[0].channel = params->channel;
  2229. spectrum.channels[0].type = type;
  2230. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2231. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2232. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2233. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2234. if (rc)
  2235. return rc;
  2236. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2237. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2238. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  2239. rc = -EIO;
  2240. }
  2241. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2242. switch (spectrum_resp_status) {
  2243. case 0: /* Command will be handled */
  2244. if (res->u.spectrum.id != 0xff) {
  2245. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2246. res->u.spectrum.id);
  2247. priv->measurement_status &= ~MEASUREMENT_READY;
  2248. }
  2249. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2250. rc = 0;
  2251. break;
  2252. case 1: /* Command will not be handled */
  2253. rc = -EAGAIN;
  2254. break;
  2255. }
  2256. dev_kfree_skb_any(cmd.meta.u.skb);
  2257. return rc;
  2258. }
  2259. #endif
  2260. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2261. struct iwl_rx_mem_buffer *rxb)
  2262. {
  2263. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2264. struct iwl_alive_resp *palive;
  2265. struct delayed_work *pwork;
  2266. palive = &pkt->u.alive_frame;
  2267. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2268. "0x%01X 0x%01X\n",
  2269. palive->is_valid, palive->ver_type,
  2270. palive->ver_subtype);
  2271. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2272. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2273. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2274. sizeof(struct iwl_alive_resp));
  2275. pwork = &priv->init_alive_start;
  2276. } else {
  2277. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2278. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2279. sizeof(struct iwl_alive_resp));
  2280. pwork = &priv->alive_start;
  2281. iwl3945_disable_events(priv);
  2282. }
  2283. /* We delay the ALIVE response by 5ms to
  2284. * give the HW RF Kill time to activate... */
  2285. if (palive->is_valid == UCODE_VALID_OK)
  2286. queue_delayed_work(priv->workqueue, pwork,
  2287. msecs_to_jiffies(5));
  2288. else
  2289. IWL_WARN(priv, "uCode did not respond OK.\n");
  2290. }
  2291. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2292. struct iwl_rx_mem_buffer *rxb)
  2293. {
  2294. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2295. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2296. return;
  2297. }
  2298. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2299. struct iwl_rx_mem_buffer *rxb)
  2300. {
  2301. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2302. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  2303. "seq 0x%04X ser 0x%08X\n",
  2304. le32_to_cpu(pkt->u.err_resp.error_type),
  2305. get_cmd_string(pkt->u.err_resp.cmd_id),
  2306. pkt->u.err_resp.cmd_id,
  2307. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2308. le32_to_cpu(pkt->u.err_resp.error_info));
  2309. }
  2310. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2311. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2312. {
  2313. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2314. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2315. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2316. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2317. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2318. rxon->channel = csa->channel;
  2319. priv->staging39_rxon.channel = csa->channel;
  2320. }
  2321. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2322. struct iwl_rx_mem_buffer *rxb)
  2323. {
  2324. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2325. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2326. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2327. if (!report->state) {
  2328. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2329. "Spectrum Measure Notification: Start\n");
  2330. return;
  2331. }
  2332. memcpy(&priv->measure_report, report, sizeof(*report));
  2333. priv->measurement_status |= MEASUREMENT_READY;
  2334. #endif
  2335. }
  2336. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2337. struct iwl_rx_mem_buffer *rxb)
  2338. {
  2339. #ifdef CONFIG_IWL3945_DEBUG
  2340. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2341. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2342. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2343. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2344. #endif
  2345. }
  2346. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2347. struct iwl_rx_mem_buffer *rxb)
  2348. {
  2349. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2350. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2351. "notification for %s:\n",
  2352. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2353. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2354. le32_to_cpu(pkt->len));
  2355. }
  2356. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2357. {
  2358. struct iwl_priv *priv =
  2359. container_of(work, struct iwl_priv, beacon_update);
  2360. struct sk_buff *beacon;
  2361. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2362. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2363. if (!beacon) {
  2364. IWL_ERR(priv, "update beacon failed\n");
  2365. return;
  2366. }
  2367. mutex_lock(&priv->mutex);
  2368. /* new beacon skb is allocated every time; dispose previous.*/
  2369. if (priv->ibss_beacon)
  2370. dev_kfree_skb(priv->ibss_beacon);
  2371. priv->ibss_beacon = beacon;
  2372. mutex_unlock(&priv->mutex);
  2373. iwl3945_send_beacon_cmd(priv);
  2374. }
  2375. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2376. struct iwl_rx_mem_buffer *rxb)
  2377. {
  2378. #ifdef CONFIG_IWL3945_DEBUG
  2379. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2380. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2381. u8 rate = beacon->beacon_notify_hdr.rate;
  2382. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2383. "tsf %d %d rate %d\n",
  2384. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2385. beacon->beacon_notify_hdr.failure_frame,
  2386. le32_to_cpu(beacon->ibss_mgr_status),
  2387. le32_to_cpu(beacon->high_tsf),
  2388. le32_to_cpu(beacon->low_tsf), rate);
  2389. #endif
  2390. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2391. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2392. queue_work(priv->workqueue, &priv->beacon_update);
  2393. }
  2394. /* Service response to REPLY_SCAN_CMD (0x80) */
  2395. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2396. struct iwl_rx_mem_buffer *rxb)
  2397. {
  2398. #ifdef CONFIG_IWL3945_DEBUG
  2399. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2400. struct iwl_scanreq_notification *notif =
  2401. (struct iwl_scanreq_notification *)pkt->u.raw;
  2402. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2403. #endif
  2404. }
  2405. /* Service SCAN_START_NOTIFICATION (0x82) */
  2406. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2407. struct iwl_rx_mem_buffer *rxb)
  2408. {
  2409. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2410. struct iwl_scanstart_notification *notif =
  2411. (struct iwl_scanstart_notification *)pkt->u.raw;
  2412. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2413. IWL_DEBUG_SCAN("Scan start: "
  2414. "%d [802.11%s] "
  2415. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2416. notif->channel,
  2417. notif->band ? "bg" : "a",
  2418. notif->tsf_high,
  2419. notif->tsf_low, notif->status, notif->beacon_timer);
  2420. }
  2421. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2422. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2423. struct iwl_rx_mem_buffer *rxb)
  2424. {
  2425. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2426. struct iwl_scanresults_notification *notif =
  2427. (struct iwl_scanresults_notification *)pkt->u.raw;
  2428. IWL_DEBUG_SCAN("Scan ch.res: "
  2429. "%d [802.11%s] "
  2430. "(TSF: 0x%08X:%08X) - %d "
  2431. "elapsed=%lu usec (%dms since last)\n",
  2432. notif->channel,
  2433. notif->band ? "bg" : "a",
  2434. le32_to_cpu(notif->tsf_high),
  2435. le32_to_cpu(notif->tsf_low),
  2436. le32_to_cpu(notif->statistics[0]),
  2437. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2438. jiffies_to_msecs(elapsed_jiffies
  2439. (priv->last_scan_jiffies, jiffies)));
  2440. priv->last_scan_jiffies = jiffies;
  2441. priv->next_scan_jiffies = 0;
  2442. }
  2443. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2444. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2445. struct iwl_rx_mem_buffer *rxb)
  2446. {
  2447. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2448. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2449. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2450. scan_notif->scanned_channels,
  2451. scan_notif->tsf_low,
  2452. scan_notif->tsf_high, scan_notif->status);
  2453. /* The HW is no longer scanning */
  2454. clear_bit(STATUS_SCAN_HW, &priv->status);
  2455. /* The scan completion notification came in, so kill that timer... */
  2456. cancel_delayed_work(&priv->scan_check);
  2457. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2458. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2459. "2.4" : "5.2",
  2460. jiffies_to_msecs(elapsed_jiffies
  2461. (priv->scan_pass_start, jiffies)));
  2462. /* Remove this scanned band from the list of pending
  2463. * bands to scan, band G precedes A in order of scanning
  2464. * as seen in iwl3945_bg_request_scan */
  2465. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2466. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2467. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2468. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2469. /* If a request to abort was given, or the scan did not succeed
  2470. * then we reset the scan state machine and terminate,
  2471. * re-queuing another scan if one has been requested */
  2472. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2473. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2474. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2475. } else {
  2476. /* If there are more bands on this scan pass reschedule */
  2477. if (priv->scan_bands > 0)
  2478. goto reschedule;
  2479. }
  2480. priv->last_scan_jiffies = jiffies;
  2481. priv->next_scan_jiffies = 0;
  2482. IWL_DEBUG_INFO("Setting scan to off\n");
  2483. clear_bit(STATUS_SCANNING, &priv->status);
  2484. IWL_DEBUG_INFO("Scan took %dms\n",
  2485. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2486. queue_work(priv->workqueue, &priv->scan_completed);
  2487. return;
  2488. reschedule:
  2489. priv->scan_pass_start = jiffies;
  2490. queue_work(priv->workqueue, &priv->request_scan);
  2491. }
  2492. /* Handle notification from uCode that card's power state is changing
  2493. * due to software, hardware, or critical temperature RFKILL */
  2494. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2495. struct iwl_rx_mem_buffer *rxb)
  2496. {
  2497. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2498. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2499. unsigned long status = priv->status;
  2500. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2501. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2502. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2503. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2504. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2505. if (flags & HW_CARD_DISABLED)
  2506. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2507. else
  2508. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2509. if (flags & SW_CARD_DISABLED)
  2510. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2511. else
  2512. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2513. iwl3945_scan_cancel(priv);
  2514. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2515. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2516. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2517. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2518. queue_work(priv->workqueue, &priv->rf_kill);
  2519. else
  2520. wake_up_interruptible(&priv->wait_command_queue);
  2521. }
  2522. /**
  2523. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2524. *
  2525. * Setup the RX handlers for each of the reply types sent from the uCode
  2526. * to the host.
  2527. *
  2528. * This function chains into the hardware specific files for them to setup
  2529. * any hardware specific handlers as well.
  2530. */
  2531. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2532. {
  2533. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2534. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2535. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2536. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2537. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2538. iwl3945_rx_spectrum_measure_notif;
  2539. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2540. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2541. iwl3945_rx_pm_debug_statistics_notif;
  2542. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2543. /*
  2544. * The same handler is used for both the REPLY to a discrete
  2545. * statistics request from the host as well as for the periodic
  2546. * statistics notifications (after received beacons) from the uCode.
  2547. */
  2548. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2549. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2550. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2551. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2552. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2553. iwl3945_rx_scan_results_notif;
  2554. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2555. iwl3945_rx_scan_complete_notif;
  2556. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2557. /* Set up hardware specific Rx handlers */
  2558. iwl3945_hw_rx_handler_setup(priv);
  2559. }
  2560. /**
  2561. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2562. * When FW advances 'R' index, all entries between old and new 'R' index
  2563. * need to be reclaimed.
  2564. */
  2565. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2566. int txq_id, int index)
  2567. {
  2568. struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
  2569. struct iwl_queue *q = &txq->q;
  2570. int nfreed = 0;
  2571. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2572. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2573. "is out of range [0-%d] %d %d.\n", txq_id,
  2574. index, q->n_bd, q->write_ptr, q->read_ptr);
  2575. return;
  2576. }
  2577. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2578. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2579. if (nfreed > 1) {
  2580. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2581. q->write_ptr, q->read_ptr);
  2582. queue_work(priv->workqueue, &priv->restart);
  2583. break;
  2584. }
  2585. nfreed++;
  2586. }
  2587. }
  2588. /**
  2589. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2590. * @rxb: Rx buffer to reclaim
  2591. *
  2592. * If an Rx buffer has an async callback associated with it the callback
  2593. * will be executed. The attached skb (if present) will only be freed
  2594. * if the callback returns 1
  2595. */
  2596. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2597. struct iwl_rx_mem_buffer *rxb)
  2598. {
  2599. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2600. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2601. int txq_id = SEQ_TO_QUEUE(sequence);
  2602. int index = SEQ_TO_INDEX(sequence);
  2603. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2604. int cmd_index;
  2605. struct iwl_cmd *cmd;
  2606. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2607. cmd_index = get_cmd_index(&priv->txq39[IWL_CMD_QUEUE_NUM].q, index, huge);
  2608. cmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2609. /* Input error checking is done when commands are added to queue. */
  2610. if (cmd->meta.flags & CMD_WANT_SKB) {
  2611. cmd->meta.source->u.skb = rxb->skb;
  2612. rxb->skb = NULL;
  2613. } else if (cmd->meta.u.callback &&
  2614. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2615. rxb->skb = NULL;
  2616. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2617. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2618. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2619. wake_up_interruptible(&priv->wait_command_queue);
  2620. }
  2621. }
  2622. /************************** RX-FUNCTIONS ****************************/
  2623. /*
  2624. * Rx theory of operation
  2625. *
  2626. * The host allocates 32 DMA target addresses and passes the host address
  2627. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2628. * 0 to 31
  2629. *
  2630. * Rx Queue Indexes
  2631. * The host/firmware share two index registers for managing the Rx buffers.
  2632. *
  2633. * The READ index maps to the first position that the firmware may be writing
  2634. * to -- the driver can read up to (but not including) this position and get
  2635. * good data.
  2636. * The READ index is managed by the firmware once the card is enabled.
  2637. *
  2638. * The WRITE index maps to the last position the driver has read from -- the
  2639. * position preceding WRITE is the last slot the firmware can place a packet.
  2640. *
  2641. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2642. * WRITE = READ.
  2643. *
  2644. * During initialization, the host sets up the READ queue position to the first
  2645. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2646. *
  2647. * When the firmware places a packet in a buffer, it will advance the READ index
  2648. * and fire the RX interrupt. The driver can then query the READ index and
  2649. * process as many packets as possible, moving the WRITE index forward as it
  2650. * resets the Rx queue buffers with new memory.
  2651. *
  2652. * The management in the driver is as follows:
  2653. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2654. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2655. * to replenish the iwl->rxq->rx_free.
  2656. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2657. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2658. * 'processed' and 'read' driver indexes as well)
  2659. * + A received packet is processed and handed to the kernel network stack,
  2660. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2661. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2662. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2663. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2664. * were enough free buffers and RX_STALLED is set it is cleared.
  2665. *
  2666. *
  2667. * Driver sequence:
  2668. *
  2669. * iwl3945_rx_queue_alloc() Allocates rx_free
  2670. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2671. * iwl3945_rx_queue_restock
  2672. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2673. * queue, updates firmware pointers, and updates
  2674. * the WRITE index. If insufficient rx_free buffers
  2675. * are available, schedules iwl3945_rx_replenish
  2676. *
  2677. * -- enable interrupts --
  2678. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2679. * READ INDEX, detaching the SKB from the pool.
  2680. * Moves the packet buffer from queue to rx_used.
  2681. * Calls iwl3945_rx_queue_restock to refill any empty
  2682. * slots.
  2683. * ...
  2684. *
  2685. */
  2686. /**
  2687. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2688. */
  2689. static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
  2690. {
  2691. int s = q->read - q->write;
  2692. if (s <= 0)
  2693. s += RX_QUEUE_SIZE;
  2694. /* keep some buffer to not confuse full and empty queue */
  2695. s -= 2;
  2696. if (s < 0)
  2697. s = 0;
  2698. return s;
  2699. }
  2700. /**
  2701. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2702. */
  2703. int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  2704. {
  2705. u32 reg = 0;
  2706. int rc = 0;
  2707. unsigned long flags;
  2708. spin_lock_irqsave(&q->lock, flags);
  2709. if (q->need_update == 0)
  2710. goto exit_unlock;
  2711. /* If power-saving is in use, make sure device is awake */
  2712. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2713. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2714. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2715. iwl_set_bit(priv, CSR_GP_CNTRL,
  2716. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2717. goto exit_unlock;
  2718. }
  2719. rc = iwl_grab_nic_access(priv);
  2720. if (rc)
  2721. goto exit_unlock;
  2722. /* Device expects a multiple of 8 */
  2723. iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2724. q->write & ~0x7);
  2725. iwl_release_nic_access(priv);
  2726. /* Else device is assumed to be awake */
  2727. } else
  2728. /* Device expects a multiple of 8 */
  2729. iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2730. q->need_update = 0;
  2731. exit_unlock:
  2732. spin_unlock_irqrestore(&q->lock, flags);
  2733. return rc;
  2734. }
  2735. /**
  2736. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2737. */
  2738. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2739. dma_addr_t dma_addr)
  2740. {
  2741. return cpu_to_le32((u32)dma_addr);
  2742. }
  2743. /**
  2744. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2745. *
  2746. * If there are slots in the RX queue that need to be restocked,
  2747. * and we have free pre-allocated buffers, fill the ranks as much
  2748. * as we can, pulling from rx_free.
  2749. *
  2750. * This moves the 'write' index forward to catch up with 'processed', and
  2751. * also updates the memory address in the firmware to reference the new
  2752. * target buffer.
  2753. */
  2754. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2755. {
  2756. struct iwl_rx_queue *rxq = &priv->rxq;
  2757. struct list_head *element;
  2758. struct iwl_rx_mem_buffer *rxb;
  2759. unsigned long flags;
  2760. int write, rc;
  2761. spin_lock_irqsave(&rxq->lock, flags);
  2762. write = rxq->write & ~0x7;
  2763. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2764. /* Get next free Rx buffer, remove from free list */
  2765. element = rxq->rx_free.next;
  2766. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2767. list_del(element);
  2768. /* Point to Rx buffer via next RBD in circular buffer */
  2769. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2770. rxq->queue[rxq->write] = rxb;
  2771. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2772. rxq->free_count--;
  2773. }
  2774. spin_unlock_irqrestore(&rxq->lock, flags);
  2775. /* If the pre-allocated buffer pool is dropping low, schedule to
  2776. * refill it */
  2777. if (rxq->free_count <= RX_LOW_WATERMARK)
  2778. queue_work(priv->workqueue, &priv->rx_replenish);
  2779. /* If we've added more space for the firmware to place data, tell it.
  2780. * Increment device's write pointer in multiples of 8. */
  2781. if ((write != (rxq->write & ~0x7))
  2782. || (abs(rxq->write - rxq->read) > 7)) {
  2783. spin_lock_irqsave(&rxq->lock, flags);
  2784. rxq->need_update = 1;
  2785. spin_unlock_irqrestore(&rxq->lock, flags);
  2786. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2787. if (rc)
  2788. return rc;
  2789. }
  2790. return 0;
  2791. }
  2792. /**
  2793. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2794. *
  2795. * When moving to rx_free an SKB is allocated for the slot.
  2796. *
  2797. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2798. * This is called as a scheduled work item (except for during initialization)
  2799. */
  2800. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2801. {
  2802. struct iwl_rx_queue *rxq = &priv->rxq;
  2803. struct list_head *element;
  2804. struct iwl_rx_mem_buffer *rxb;
  2805. unsigned long flags;
  2806. spin_lock_irqsave(&rxq->lock, flags);
  2807. while (!list_empty(&rxq->rx_used)) {
  2808. element = rxq->rx_used.next;
  2809. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2810. /* Alloc a new receive buffer */
  2811. rxb->skb =
  2812. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2813. if (!rxb->skb) {
  2814. if (net_ratelimit())
  2815. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2816. /* We don't reschedule replenish work here -- we will
  2817. * call the restock method and if it still needs
  2818. * more buffers it will schedule replenish */
  2819. break;
  2820. }
  2821. /* If radiotap head is required, reserve some headroom here.
  2822. * The physical head count is a variable rx_stats->phy_count.
  2823. * We reserve 4 bytes here. Plus these extra bytes, the
  2824. * headroom of the physical head should be enough for the
  2825. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2826. */
  2827. skb_reserve(rxb->skb, 4);
  2828. priv->alloc_rxb_skb++;
  2829. list_del(element);
  2830. /* Get physical address of RB/SKB */
  2831. rxb->real_dma_addr =
  2832. pci_map_single(priv->pci_dev, rxb->skb->data,
  2833. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2834. list_add_tail(&rxb->list, &rxq->rx_free);
  2835. rxq->free_count++;
  2836. }
  2837. spin_unlock_irqrestore(&rxq->lock, flags);
  2838. }
  2839. /*
  2840. * this should be called while priv->lock is locked
  2841. */
  2842. static void __iwl3945_rx_replenish(void *data)
  2843. {
  2844. struct iwl_priv *priv = data;
  2845. iwl3945_rx_allocate(priv);
  2846. iwl3945_rx_queue_restock(priv);
  2847. }
  2848. void iwl3945_rx_replenish(void *data)
  2849. {
  2850. struct iwl_priv *priv = data;
  2851. unsigned long flags;
  2852. iwl3945_rx_allocate(priv);
  2853. spin_lock_irqsave(&priv->lock, flags);
  2854. iwl3945_rx_queue_restock(priv);
  2855. spin_unlock_irqrestore(&priv->lock, flags);
  2856. }
  2857. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  2858. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  2859. * This free routine walks the list of POOL entries and if SKB is set to
  2860. * non NULL it is unmapped and freed
  2861. */
  2862. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2863. {
  2864. int i;
  2865. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  2866. if (rxq->pool[i].skb != NULL) {
  2867. pci_unmap_single(priv->pci_dev,
  2868. rxq->pool[i].real_dma_addr,
  2869. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2870. dev_kfree_skb(rxq->pool[i].skb);
  2871. }
  2872. }
  2873. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2874. rxq->dma_addr);
  2875. rxq->bd = NULL;
  2876. }
  2877. int iwl3945_rx_queue_alloc(struct iwl_priv *priv)
  2878. {
  2879. struct iwl_rx_queue *rxq = &priv->rxq;
  2880. struct pci_dev *dev = priv->pci_dev;
  2881. int i;
  2882. spin_lock_init(&rxq->lock);
  2883. INIT_LIST_HEAD(&rxq->rx_free);
  2884. INIT_LIST_HEAD(&rxq->rx_used);
  2885. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2886. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  2887. if (!rxq->bd)
  2888. return -ENOMEM;
  2889. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2890. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2891. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2892. /* Set us so that we have processed and used all buffers, but have
  2893. * not restocked the Rx queue with fresh buffers */
  2894. rxq->read = rxq->write = 0;
  2895. rxq->free_count = 0;
  2896. rxq->need_update = 0;
  2897. return 0;
  2898. }
  2899. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2900. {
  2901. unsigned long flags;
  2902. int i;
  2903. spin_lock_irqsave(&rxq->lock, flags);
  2904. INIT_LIST_HEAD(&rxq->rx_free);
  2905. INIT_LIST_HEAD(&rxq->rx_used);
  2906. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2907. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  2908. /* In the reset function, these buffers may have been allocated
  2909. * to an SKB, so we need to unmap and free potential storage */
  2910. if (rxq->pool[i].skb != NULL) {
  2911. pci_unmap_single(priv->pci_dev,
  2912. rxq->pool[i].real_dma_addr,
  2913. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2914. priv->alloc_rxb_skb--;
  2915. dev_kfree_skb(rxq->pool[i].skb);
  2916. rxq->pool[i].skb = NULL;
  2917. }
  2918. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2919. }
  2920. /* Set us so that we have processed and used all buffers, but have
  2921. * not restocked the Rx queue with fresh buffers */
  2922. rxq->read = rxq->write = 0;
  2923. rxq->free_count = 0;
  2924. spin_unlock_irqrestore(&rxq->lock, flags);
  2925. }
  2926. /* Convert linear signal-to-noise ratio into dB */
  2927. static u8 ratio2dB[100] = {
  2928. /* 0 1 2 3 4 5 6 7 8 9 */
  2929. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2930. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2931. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2932. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2933. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2934. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2935. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2936. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2937. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2938. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2939. };
  2940. /* Calculates a relative dB value from a ratio of linear
  2941. * (i.e. not dB) signal levels.
  2942. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2943. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2944. {
  2945. /* 1000:1 or higher just report as 60 dB */
  2946. if (sig_ratio >= 1000)
  2947. return 60;
  2948. /* 100:1 or higher, divide by 10 and use table,
  2949. * add 20 dB to make up for divide by 10 */
  2950. if (sig_ratio >= 100)
  2951. return 20 + (int)ratio2dB[sig_ratio/10];
  2952. /* We shouldn't see this */
  2953. if (sig_ratio < 1)
  2954. return 0;
  2955. /* Use table for ratios 1:1 - 99:1 */
  2956. return (int)ratio2dB[sig_ratio];
  2957. }
  2958. #define PERFECT_RSSI (-20) /* dBm */
  2959. #define WORST_RSSI (-95) /* dBm */
  2960. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2961. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2962. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2963. * about formulas used below. */
  2964. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2965. {
  2966. int sig_qual;
  2967. int degradation = PERFECT_RSSI - rssi_dbm;
  2968. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2969. * as indicator; formula is (signal dbm - noise dbm).
  2970. * SNR at or above 40 is a great signal (100%).
  2971. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2972. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2973. if (noise_dbm) {
  2974. if (rssi_dbm - noise_dbm >= 40)
  2975. return 100;
  2976. else if (rssi_dbm < noise_dbm)
  2977. return 0;
  2978. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2979. /* Else use just the signal level.
  2980. * This formula is a least squares fit of data points collected and
  2981. * compared with a reference system that had a percentage (%) display
  2982. * for signal quality. */
  2983. } else
  2984. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2985. (15 * RSSI_RANGE + 62 * degradation)) /
  2986. (RSSI_RANGE * RSSI_RANGE);
  2987. if (sig_qual > 100)
  2988. sig_qual = 100;
  2989. else if (sig_qual < 1)
  2990. sig_qual = 0;
  2991. return sig_qual;
  2992. }
  2993. /**
  2994. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2995. *
  2996. * Uses the priv->rx_handlers callback function array to invoke
  2997. * the appropriate handlers, including command responses,
  2998. * frame-received notifications, and other notifications.
  2999. */
  3000. static void iwl3945_rx_handle(struct iwl_priv *priv)
  3001. {
  3002. struct iwl_rx_mem_buffer *rxb;
  3003. struct iwl_rx_packet *pkt;
  3004. struct iwl_rx_queue *rxq = &priv->rxq;
  3005. u32 r, i;
  3006. int reclaim;
  3007. unsigned long flags;
  3008. u8 fill_rx = 0;
  3009. u32 count = 8;
  3010. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3011. * buffer that the driver may process (last buffer filled by ucode). */
  3012. r = iwl3945_hw_get_rx_read(priv);
  3013. i = rxq->read;
  3014. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3015. fill_rx = 1;
  3016. /* Rx interrupt, but nothing sent from uCode */
  3017. if (i == r)
  3018. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3019. while (i != r) {
  3020. rxb = rxq->queue[i];
  3021. /* If an RXB doesn't have a Rx queue slot associated with it,
  3022. * then a bug has been introduced in the queue refilling
  3023. * routines -- catch it here */
  3024. BUG_ON(rxb == NULL);
  3025. rxq->queue[i] = NULL;
  3026. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  3027. IWL_RX_BUF_SIZE,
  3028. PCI_DMA_FROMDEVICE);
  3029. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  3030. /* Reclaim a command buffer only if this packet is a response
  3031. * to a (driver-originated) command.
  3032. * If the packet (e.g. Rx frame) originated from uCode,
  3033. * there is no command buffer to reclaim.
  3034. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3035. * but apparently a few don't get set; catch them here. */
  3036. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3037. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3038. (pkt->hdr.cmd != REPLY_TX);
  3039. /* Based on type of command response or notification,
  3040. * handle those that need handling via function in
  3041. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3042. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3043. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3044. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3045. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3046. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3047. } else {
  3048. /* No handling needed */
  3049. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3050. "r %d i %d No handler needed for %s, 0x%02x\n",
  3051. r, i, get_cmd_string(pkt->hdr.cmd),
  3052. pkt->hdr.cmd);
  3053. }
  3054. if (reclaim) {
  3055. /* Invoke any callbacks, transfer the skb to caller, and
  3056. * fire off the (possibly) blocking iwl3945_send_cmd()
  3057. * as we reclaim the driver command queue */
  3058. if (rxb && rxb->skb)
  3059. iwl3945_tx_cmd_complete(priv, rxb);
  3060. else
  3061. IWL_WARN(priv, "Claim null rxb?\n");
  3062. }
  3063. /* For now we just don't re-use anything. We can tweak this
  3064. * later to try and re-use notification packets and SKBs that
  3065. * fail to Rx correctly */
  3066. if (rxb->skb != NULL) {
  3067. priv->alloc_rxb_skb--;
  3068. dev_kfree_skb_any(rxb->skb);
  3069. rxb->skb = NULL;
  3070. }
  3071. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  3072. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3073. spin_lock_irqsave(&rxq->lock, flags);
  3074. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3075. spin_unlock_irqrestore(&rxq->lock, flags);
  3076. i = (i + 1) & RX_QUEUE_MASK;
  3077. /* If there are a lot of unused frames,
  3078. * restock the Rx queue so ucode won't assert. */
  3079. if (fill_rx) {
  3080. count++;
  3081. if (count >= 8) {
  3082. priv->rxq.read = i;
  3083. __iwl3945_rx_replenish(priv);
  3084. count = 0;
  3085. }
  3086. }
  3087. }
  3088. /* Backtrack one entry */
  3089. priv->rxq.read = i;
  3090. iwl3945_rx_queue_restock(priv);
  3091. }
  3092. /**
  3093. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3094. */
  3095. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  3096. struct iwl3945_tx_queue *txq)
  3097. {
  3098. u32 reg = 0;
  3099. int rc = 0;
  3100. int txq_id = txq->q.id;
  3101. if (txq->need_update == 0)
  3102. return rc;
  3103. /* if we're trying to save power */
  3104. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3105. /* wake up nic if it's powered down ...
  3106. * uCode will wake up, and interrupt us again, so next
  3107. * time we'll skip this part. */
  3108. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  3109. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3110. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3111. iwl_set_bit(priv, CSR_GP_CNTRL,
  3112. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3113. return rc;
  3114. }
  3115. /* restore this queue's parameters in nic hardware. */
  3116. rc = iwl_grab_nic_access(priv);
  3117. if (rc)
  3118. return rc;
  3119. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  3120. txq->q.write_ptr | (txq_id << 8));
  3121. iwl_release_nic_access(priv);
  3122. /* else not in power-save mode, uCode will never sleep when we're
  3123. * trying to tx (during RFKILL, we're not trying to tx). */
  3124. } else
  3125. iwl_write32(priv, HBUS_TARG_WRPTR,
  3126. txq->q.write_ptr | (txq_id << 8));
  3127. txq->need_update = 0;
  3128. return rc;
  3129. }
  3130. #ifdef CONFIG_IWL3945_DEBUG
  3131. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  3132. struct iwl3945_rxon_cmd *rxon)
  3133. {
  3134. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3135. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3136. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3137. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3138. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3139. le32_to_cpu(rxon->filter_flags));
  3140. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3141. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3142. rxon->ofdm_basic_rates);
  3143. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3144. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3145. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3146. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3147. }
  3148. #endif
  3149. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3150. {
  3151. IWL_DEBUG_ISR("Enabling interrupts\n");
  3152. set_bit(STATUS_INT_ENABLED, &priv->status);
  3153. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3154. }
  3155. /* call this function to flush any scheduled tasklet */
  3156. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3157. {
  3158. /* wait to make sure we flush pending tasklet*/
  3159. synchronize_irq(priv->pci_dev->irq);
  3160. tasklet_kill(&priv->irq_tasklet);
  3161. }
  3162. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3163. {
  3164. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3165. /* disable interrupts from uCode/NIC to host */
  3166. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3167. /* acknowledge/clear/reset any interrupts still pending
  3168. * from uCode or flow handler (Rx/Tx DMA) */
  3169. iwl_write32(priv, CSR_INT, 0xffffffff);
  3170. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3171. IWL_DEBUG_ISR("Disabled interrupts\n");
  3172. }
  3173. static const char *desc_lookup(int i)
  3174. {
  3175. switch (i) {
  3176. case 1:
  3177. return "FAIL";
  3178. case 2:
  3179. return "BAD_PARAM";
  3180. case 3:
  3181. return "BAD_CHECKSUM";
  3182. case 4:
  3183. return "NMI_INTERRUPT";
  3184. case 5:
  3185. return "SYSASSERT";
  3186. case 6:
  3187. return "FATAL_ERROR";
  3188. }
  3189. return "UNKNOWN";
  3190. }
  3191. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3192. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3193. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3194. {
  3195. u32 i;
  3196. u32 desc, time, count, base, data1;
  3197. u32 blink1, blink2, ilink1, ilink2;
  3198. int rc;
  3199. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3200. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3201. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  3202. return;
  3203. }
  3204. rc = iwl_grab_nic_access(priv);
  3205. if (rc) {
  3206. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3207. return;
  3208. }
  3209. count = iwl_read_targ_mem(priv, base);
  3210. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3211. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  3212. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  3213. priv->status, count);
  3214. }
  3215. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  3216. "ilink1 nmiPC Line\n");
  3217. for (i = ERROR_START_OFFSET;
  3218. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3219. i += ERROR_ELEM_SIZE) {
  3220. desc = iwl_read_targ_mem(priv, base + i);
  3221. time =
  3222. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3223. blink1 =
  3224. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3225. blink2 =
  3226. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3227. ilink1 =
  3228. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3229. ilink2 =
  3230. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3231. data1 =
  3232. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3233. IWL_ERR(priv,
  3234. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3235. desc_lookup(desc), desc, time, blink1, blink2,
  3236. ilink1, ilink2, data1);
  3237. }
  3238. iwl_release_nic_access(priv);
  3239. }
  3240. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3241. /**
  3242. * iwl3945_print_event_log - Dump error event log to syslog
  3243. *
  3244. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3245. */
  3246. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3247. u32 num_events, u32 mode)
  3248. {
  3249. u32 i;
  3250. u32 base; /* SRAM byte address of event log header */
  3251. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3252. u32 ptr; /* SRAM byte address of log data */
  3253. u32 ev, time, data; /* event log data */
  3254. if (num_events == 0)
  3255. return;
  3256. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3257. if (mode == 0)
  3258. event_size = 2 * sizeof(u32);
  3259. else
  3260. event_size = 3 * sizeof(u32);
  3261. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3262. /* "time" is actually "data" for mode 0 (no timestamp).
  3263. * place event id # at far right for easier visual parsing. */
  3264. for (i = 0; i < num_events; i++) {
  3265. ev = iwl_read_targ_mem(priv, ptr);
  3266. ptr += sizeof(u32);
  3267. time = iwl_read_targ_mem(priv, ptr);
  3268. ptr += sizeof(u32);
  3269. if (mode == 0) {
  3270. /* data, ev */
  3271. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  3272. } else {
  3273. data = iwl_read_targ_mem(priv, ptr);
  3274. ptr += sizeof(u32);
  3275. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  3276. }
  3277. }
  3278. }
  3279. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3280. {
  3281. int rc;
  3282. u32 base; /* SRAM byte address of event log header */
  3283. u32 capacity; /* event log capacity in # entries */
  3284. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3285. u32 num_wraps; /* # times uCode wrapped to top of log */
  3286. u32 next_entry; /* index of next entry to be written by uCode */
  3287. u32 size; /* # entries that we'll print */
  3288. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3289. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3290. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  3291. return;
  3292. }
  3293. rc = iwl_grab_nic_access(priv);
  3294. if (rc) {
  3295. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3296. return;
  3297. }
  3298. /* event log header */
  3299. capacity = iwl_read_targ_mem(priv, base);
  3300. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3301. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3302. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3303. size = num_wraps ? capacity : next_entry;
  3304. /* bail out if nothing in log */
  3305. if (size == 0) {
  3306. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  3307. iwl_release_nic_access(priv);
  3308. return;
  3309. }
  3310. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  3311. size, num_wraps);
  3312. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3313. * i.e the next one that uCode would fill. */
  3314. if (num_wraps)
  3315. iwl3945_print_event_log(priv, next_entry,
  3316. capacity - next_entry, mode);
  3317. /* (then/else) start at top of log */
  3318. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3319. iwl_release_nic_access(priv);
  3320. }
  3321. /**
  3322. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3323. */
  3324. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3325. {
  3326. /* Set the FW error flag -- cleared on iwl3945_down */
  3327. set_bit(STATUS_FW_ERROR, &priv->status);
  3328. /* Cancel currently queued command. */
  3329. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3330. #ifdef CONFIG_IWL3945_DEBUG
  3331. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3332. iwl3945_dump_nic_error_log(priv);
  3333. iwl3945_dump_nic_event_log(priv);
  3334. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3335. }
  3336. #endif
  3337. wake_up_interruptible(&priv->wait_command_queue);
  3338. /* Keep the restart process from trying to send host
  3339. * commands by clearing the INIT status bit */
  3340. clear_bit(STATUS_READY, &priv->status);
  3341. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3342. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3343. "Restarting adapter due to uCode error.\n");
  3344. if (iwl3945_is_associated(priv)) {
  3345. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3346. sizeof(priv->recovery39_rxon));
  3347. priv->error_recovering = 1;
  3348. }
  3349. queue_work(priv->workqueue, &priv->restart);
  3350. }
  3351. }
  3352. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3353. {
  3354. unsigned long flags;
  3355. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3356. sizeof(priv->staging39_rxon));
  3357. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3358. iwl3945_commit_rxon(priv);
  3359. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3360. spin_lock_irqsave(&priv->lock, flags);
  3361. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3362. priv->error_recovering = 0;
  3363. spin_unlock_irqrestore(&priv->lock, flags);
  3364. }
  3365. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3366. {
  3367. u32 inta, handled = 0;
  3368. u32 inta_fh;
  3369. unsigned long flags;
  3370. #ifdef CONFIG_IWL3945_DEBUG
  3371. u32 inta_mask;
  3372. #endif
  3373. spin_lock_irqsave(&priv->lock, flags);
  3374. /* Ack/clear/reset pending uCode interrupts.
  3375. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3376. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3377. inta = iwl_read32(priv, CSR_INT);
  3378. iwl_write32(priv, CSR_INT, inta);
  3379. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3380. * Any new interrupts that happen after this, either while we're
  3381. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3382. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3383. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3384. #ifdef CONFIG_IWL3945_DEBUG
  3385. if (priv->debug_level & IWL_DL_ISR) {
  3386. /* just for debug */
  3387. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3388. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3389. inta, inta_mask, inta_fh);
  3390. }
  3391. #endif
  3392. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3393. * atomic, make sure that inta covers all the interrupts that
  3394. * we've discovered, even if FH interrupt came in just after
  3395. * reading CSR_INT. */
  3396. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3397. inta |= CSR_INT_BIT_FH_RX;
  3398. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3399. inta |= CSR_INT_BIT_FH_TX;
  3400. /* Now service all interrupt bits discovered above. */
  3401. if (inta & CSR_INT_BIT_HW_ERR) {
  3402. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  3403. /* Tell the device to stop sending interrupts */
  3404. iwl3945_disable_interrupts(priv);
  3405. iwl3945_irq_handle_error(priv);
  3406. handled |= CSR_INT_BIT_HW_ERR;
  3407. spin_unlock_irqrestore(&priv->lock, flags);
  3408. return;
  3409. }
  3410. #ifdef CONFIG_IWL3945_DEBUG
  3411. if (priv->debug_level & (IWL_DL_ISR)) {
  3412. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3413. if (inta & CSR_INT_BIT_SCD)
  3414. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3415. "the frame/frames.\n");
  3416. /* Alive notification via Rx interrupt will do the real work */
  3417. if (inta & CSR_INT_BIT_ALIVE)
  3418. IWL_DEBUG_ISR("Alive interrupt\n");
  3419. }
  3420. #endif
  3421. /* Safely ignore these bits for debug checks below */
  3422. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3423. /* Error detected by uCode */
  3424. if (inta & CSR_INT_BIT_SW_ERR) {
  3425. IWL_ERR(priv, "Microcode SW error detected. "
  3426. "Restarting 0x%X.\n", inta);
  3427. iwl3945_irq_handle_error(priv);
  3428. handled |= CSR_INT_BIT_SW_ERR;
  3429. }
  3430. /* uCode wakes up after power-down sleep */
  3431. if (inta & CSR_INT_BIT_WAKEUP) {
  3432. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3433. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3434. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[0]);
  3435. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[1]);
  3436. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[2]);
  3437. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[3]);
  3438. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[4]);
  3439. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[5]);
  3440. handled |= CSR_INT_BIT_WAKEUP;
  3441. }
  3442. /* All uCode command responses, including Tx command responses,
  3443. * Rx "responses" (frame-received notification), and other
  3444. * notifications from uCode come through here*/
  3445. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3446. iwl3945_rx_handle(priv);
  3447. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3448. }
  3449. if (inta & CSR_INT_BIT_FH_TX) {
  3450. IWL_DEBUG_ISR("Tx interrupt\n");
  3451. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3452. if (!iwl_grab_nic_access(priv)) {
  3453. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3454. (FH39_SRVC_CHNL), 0x0);
  3455. iwl_release_nic_access(priv);
  3456. }
  3457. handled |= CSR_INT_BIT_FH_TX;
  3458. }
  3459. if (inta & ~handled)
  3460. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3461. if (inta & ~CSR_INI_SET_MASK) {
  3462. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  3463. inta & ~CSR_INI_SET_MASK);
  3464. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  3465. }
  3466. /* Re-enable all interrupts */
  3467. /* only Re-enable if disabled by irq */
  3468. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3469. iwl3945_enable_interrupts(priv);
  3470. #ifdef CONFIG_IWL3945_DEBUG
  3471. if (priv->debug_level & (IWL_DL_ISR)) {
  3472. inta = iwl_read32(priv, CSR_INT);
  3473. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3474. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3475. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3476. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3477. }
  3478. #endif
  3479. spin_unlock_irqrestore(&priv->lock, flags);
  3480. }
  3481. static irqreturn_t iwl3945_isr(int irq, void *data)
  3482. {
  3483. struct iwl_priv *priv = data;
  3484. u32 inta, inta_mask;
  3485. u32 inta_fh;
  3486. if (!priv)
  3487. return IRQ_NONE;
  3488. spin_lock(&priv->lock);
  3489. /* Disable (but don't clear!) interrupts here to avoid
  3490. * back-to-back ISRs and sporadic interrupts from our NIC.
  3491. * If we have something to service, the tasklet will re-enable ints.
  3492. * If we *don't* have something, we'll re-enable before leaving here. */
  3493. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3494. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3495. /* Discover which interrupts are active/pending */
  3496. inta = iwl_read32(priv, CSR_INT);
  3497. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3498. /* Ignore interrupt if there's nothing in NIC to service.
  3499. * This may be due to IRQ shared with another device,
  3500. * or due to sporadic interrupts thrown from our NIC. */
  3501. if (!inta && !inta_fh) {
  3502. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3503. goto none;
  3504. }
  3505. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3506. /* Hardware disappeared */
  3507. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3508. goto unplugged;
  3509. }
  3510. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3511. inta, inta_mask, inta_fh);
  3512. inta &= ~CSR_INT_BIT_SCD;
  3513. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3514. if (likely(inta || inta_fh))
  3515. tasklet_schedule(&priv->irq_tasklet);
  3516. unplugged:
  3517. spin_unlock(&priv->lock);
  3518. return IRQ_HANDLED;
  3519. none:
  3520. /* re-enable interrupts here since we don't have anything to service. */
  3521. /* only Re-enable if disabled by irq */
  3522. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3523. iwl3945_enable_interrupts(priv);
  3524. spin_unlock(&priv->lock);
  3525. return IRQ_NONE;
  3526. }
  3527. /************************** EEPROM BANDS ****************************
  3528. *
  3529. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3530. * EEPROM contents to the specific channel number supported for each
  3531. * band.
  3532. *
  3533. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3534. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3535. * The specific geography and calibration information for that channel
  3536. * is contained in the eeprom map itself.
  3537. *
  3538. * During init, we copy the eeprom information and channel map
  3539. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3540. *
  3541. * channel_map_24/52 provides the index in the channel_info array for a
  3542. * given channel. We have to have two separate maps as there is channel
  3543. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3544. * band_2
  3545. *
  3546. * A value of 0xff stored in the channel_map indicates that the channel
  3547. * is not supported by the hardware at all.
  3548. *
  3549. * A value of 0xfe in the channel_map indicates that the channel is not
  3550. * valid for Tx with the current hardware. This means that
  3551. * while the system can tune and receive on a given channel, it may not
  3552. * be able to associate or transmit any frames on that
  3553. * channel. There is no corresponding channel information for that
  3554. * entry.
  3555. *
  3556. *********************************************************************/
  3557. /* 2.4 GHz */
  3558. static const u8 iwl3945_eeprom_band_1[14] = {
  3559. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3560. };
  3561. /* 5.2 GHz bands */
  3562. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3563. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3564. };
  3565. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3566. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3567. };
  3568. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3569. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3570. };
  3571. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3572. 145, 149, 153, 157, 161, 165
  3573. };
  3574. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3575. int *eeprom_ch_count,
  3576. const struct iwl_eeprom_channel
  3577. **eeprom_ch_info,
  3578. const u8 **eeprom_ch_index)
  3579. {
  3580. switch (band) {
  3581. case 1: /* 2.4GHz band */
  3582. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3583. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3584. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3585. break;
  3586. case 2: /* 4.9GHz band */
  3587. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3588. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3589. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3590. break;
  3591. case 3: /* 5.2GHz band */
  3592. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3593. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3594. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3595. break;
  3596. case 4: /* 5.5GHz band */
  3597. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3598. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3599. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3600. break;
  3601. case 5: /* 5.7GHz band */
  3602. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3603. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3604. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3605. break;
  3606. default:
  3607. BUG();
  3608. return;
  3609. }
  3610. }
  3611. /**
  3612. * iwl3945_get_channel_info - Find driver's private channel info
  3613. *
  3614. * Based on band and channel number.
  3615. */
  3616. const struct iwl_channel_info *
  3617. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3618. enum ieee80211_band band, u16 channel)
  3619. {
  3620. int i;
  3621. switch (band) {
  3622. case IEEE80211_BAND_5GHZ:
  3623. for (i = 14; i < priv->channel_count; i++) {
  3624. if (priv->channel_info[i].channel == channel)
  3625. return &priv->channel_info[i];
  3626. }
  3627. break;
  3628. case IEEE80211_BAND_2GHZ:
  3629. if (channel >= 1 && channel <= 14)
  3630. return &priv->channel_info[channel - 1];
  3631. break;
  3632. case IEEE80211_NUM_BANDS:
  3633. WARN_ON(1);
  3634. }
  3635. return NULL;
  3636. }
  3637. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3638. ? # x " " : "")
  3639. /**
  3640. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3641. */
  3642. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3643. {
  3644. int eeprom_ch_count = 0;
  3645. const u8 *eeprom_ch_index = NULL;
  3646. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3647. int band, ch;
  3648. struct iwl_channel_info *ch_info;
  3649. if (priv->channel_count) {
  3650. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3651. return 0;
  3652. }
  3653. if (priv->eeprom39.version < 0x2f) {
  3654. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3655. priv->eeprom39.version);
  3656. return -EINVAL;
  3657. }
  3658. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3659. priv->channel_count =
  3660. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3661. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3662. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3663. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3664. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3665. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3666. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3667. priv->channel_count, GFP_KERNEL);
  3668. if (!priv->channel_info) {
  3669. IWL_ERR(priv, "Could not allocate channel_info\n");
  3670. priv->channel_count = 0;
  3671. return -ENOMEM;
  3672. }
  3673. ch_info = priv->channel_info;
  3674. /* Loop through the 5 EEPROM bands adding them in order to the
  3675. * channel map we maintain (that contains additional information than
  3676. * what just in the EEPROM) */
  3677. for (band = 1; band <= 5; band++) {
  3678. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3679. &eeprom_ch_info, &eeprom_ch_index);
  3680. /* Loop through each band adding each of the channels */
  3681. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3682. ch_info->channel = eeprom_ch_index[ch];
  3683. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3684. IEEE80211_BAND_5GHZ;
  3685. /* permanently store EEPROM's channel regulatory flags
  3686. * and max power in channel info database. */
  3687. ch_info->eeprom = eeprom_ch_info[ch];
  3688. /* Copy the run-time flags so they are there even on
  3689. * invalid channels */
  3690. ch_info->flags = eeprom_ch_info[ch].flags;
  3691. if (!(is_channel_valid(ch_info))) {
  3692. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3693. "No traffic\n",
  3694. ch_info->channel,
  3695. ch_info->flags,
  3696. is_channel_a_band(ch_info) ?
  3697. "5.2" : "2.4");
  3698. ch_info++;
  3699. continue;
  3700. }
  3701. /* Initialize regulatory-based run-time data */
  3702. ch_info->max_power_avg = ch_info->curr_txpow =
  3703. eeprom_ch_info[ch].max_power_avg;
  3704. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3705. ch_info->min_power = 0;
  3706. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3707. " %ddBm): Ad-Hoc %ssupported\n",
  3708. ch_info->channel,
  3709. is_channel_a_band(ch_info) ?
  3710. "5.2" : "2.4",
  3711. CHECK_AND_PRINT(VALID),
  3712. CHECK_AND_PRINT(IBSS),
  3713. CHECK_AND_PRINT(ACTIVE),
  3714. CHECK_AND_PRINT(RADAR),
  3715. CHECK_AND_PRINT(WIDE),
  3716. CHECK_AND_PRINT(DFS),
  3717. eeprom_ch_info[ch].flags,
  3718. eeprom_ch_info[ch].max_power_avg,
  3719. ((eeprom_ch_info[ch].
  3720. flags & EEPROM_CHANNEL_IBSS)
  3721. && !(eeprom_ch_info[ch].
  3722. flags & EEPROM_CHANNEL_RADAR))
  3723. ? "" : "not ");
  3724. /* Set the user_txpower_limit to the highest power
  3725. * supported by any channel */
  3726. if (eeprom_ch_info[ch].max_power_avg >
  3727. priv->user_txpower_limit)
  3728. priv->user_txpower_limit =
  3729. eeprom_ch_info[ch].max_power_avg;
  3730. ch_info++;
  3731. }
  3732. }
  3733. /* Set up txpower settings in driver for all channels */
  3734. if (iwl3945_txpower_set_from_eeprom(priv))
  3735. return -EIO;
  3736. return 0;
  3737. }
  3738. /*
  3739. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3740. */
  3741. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3742. {
  3743. kfree(priv->channel_info);
  3744. priv->channel_count = 0;
  3745. }
  3746. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3747. * sending probe req. This should be set long enough to hear probe responses
  3748. * from more than one AP. */
  3749. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3750. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3751. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3752. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3753. /* For faster active scanning, scan will move to the next channel if fewer than
  3754. * PLCP_QUIET_THRESH packets are heard on this channel within
  3755. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3756. * time if it's a quiet channel (nothing responded to our probe, and there's
  3757. * no other traffic).
  3758. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3759. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3760. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3761. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3762. * Must be set longer than active dwell time.
  3763. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3764. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3765. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3766. #define IWL_PASSIVE_DWELL_BASE (100)
  3767. #define IWL_CHANNEL_TUNE_TIME 5
  3768. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3769. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3770. enum ieee80211_band band,
  3771. u8 n_probes)
  3772. {
  3773. if (band == IEEE80211_BAND_5GHZ)
  3774. return IWL_ACTIVE_DWELL_TIME_52 +
  3775. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3776. else
  3777. return IWL_ACTIVE_DWELL_TIME_24 +
  3778. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3779. }
  3780. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3781. enum ieee80211_band band)
  3782. {
  3783. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3784. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3785. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3786. if (iwl3945_is_associated(priv)) {
  3787. /* If we're associated, we clamp the maximum passive
  3788. * dwell time to be 98% of the beacon interval (minus
  3789. * 2 * channel tune time) */
  3790. passive = priv->beacon_int;
  3791. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3792. passive = IWL_PASSIVE_DWELL_BASE;
  3793. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3794. }
  3795. return passive;
  3796. }
  3797. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3798. enum ieee80211_band band,
  3799. u8 is_active, u8 n_probes,
  3800. struct iwl3945_scan_channel *scan_ch)
  3801. {
  3802. const struct ieee80211_channel *channels = NULL;
  3803. const struct ieee80211_supported_band *sband;
  3804. const struct iwl_channel_info *ch_info;
  3805. u16 passive_dwell = 0;
  3806. u16 active_dwell = 0;
  3807. int added, i;
  3808. sband = iwl3945_get_band(priv, band);
  3809. if (!sband)
  3810. return 0;
  3811. channels = sband->channels;
  3812. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3813. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3814. if (passive_dwell <= active_dwell)
  3815. passive_dwell = active_dwell + 1;
  3816. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3817. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3818. continue;
  3819. scan_ch->channel = channels[i].hw_value;
  3820. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3821. if (!is_channel_valid(ch_info)) {
  3822. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3823. scan_ch->channel);
  3824. continue;
  3825. }
  3826. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3827. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3828. /* If passive , set up for auto-switch
  3829. * and use long active_dwell time.
  3830. */
  3831. if (!is_active || is_channel_passive(ch_info) ||
  3832. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3833. scan_ch->type = 0; /* passive */
  3834. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3835. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3836. } else {
  3837. scan_ch->type = 1; /* active */
  3838. }
  3839. /* Set direct probe bits. These may be used both for active
  3840. * scan channels (probes gets sent right away),
  3841. * or for passive channels (probes get se sent only after
  3842. * hearing clear Rx packet).*/
  3843. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3844. if (n_probes)
  3845. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3846. } else {
  3847. /* uCode v1 does not allow setting direct probe bits on
  3848. * passive channel. */
  3849. if ((scan_ch->type & 1) && n_probes)
  3850. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3851. }
  3852. /* Set txpower levels to defaults */
  3853. scan_ch->tpc.dsp_atten = 110;
  3854. /* scan_pwr_info->tpc.dsp_atten; */
  3855. /*scan_pwr_info->tpc.tx_gain; */
  3856. if (band == IEEE80211_BAND_5GHZ)
  3857. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3858. else {
  3859. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3860. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3861. * power level:
  3862. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3863. */
  3864. }
  3865. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3866. scan_ch->channel,
  3867. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3868. (scan_ch->type & 1) ?
  3869. active_dwell : passive_dwell);
  3870. scan_ch++;
  3871. added++;
  3872. }
  3873. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3874. return added;
  3875. }
  3876. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3877. struct ieee80211_rate *rates)
  3878. {
  3879. int i;
  3880. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3881. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3882. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3883. rates[i].hw_value_short = i;
  3884. rates[i].flags = 0;
  3885. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3886. /*
  3887. * If CCK != 1M then set short preamble rate flag.
  3888. */
  3889. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3890. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3891. }
  3892. }
  3893. }
  3894. /**
  3895. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3896. */
  3897. static int iwl3945_init_geos(struct iwl_priv *priv)
  3898. {
  3899. struct iwl_channel_info *ch;
  3900. struct ieee80211_supported_band *sband;
  3901. struct ieee80211_channel *channels;
  3902. struct ieee80211_channel *geo_ch;
  3903. struct ieee80211_rate *rates;
  3904. int i = 0;
  3905. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3906. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3907. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3908. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3909. return 0;
  3910. }
  3911. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3912. priv->channel_count, GFP_KERNEL);
  3913. if (!channels)
  3914. return -ENOMEM;
  3915. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3916. GFP_KERNEL);
  3917. if (!rates) {
  3918. kfree(channels);
  3919. return -ENOMEM;
  3920. }
  3921. /* 5.2GHz channels start after the 2.4GHz channels */
  3922. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3923. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3924. /* just OFDM */
  3925. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3926. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3927. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3928. sband->channels = channels;
  3929. /* OFDM & CCK */
  3930. sband->bitrates = rates;
  3931. sband->n_bitrates = IWL_RATE_COUNT;
  3932. priv->ieee_channels = channels;
  3933. priv->ieee_rates = rates;
  3934. iwl3945_init_hw_rates(priv, rates);
  3935. for (i = 0; i < priv->channel_count; i++) {
  3936. ch = &priv->channel_info[i];
  3937. /* FIXME: might be removed if scan is OK*/
  3938. if (!is_channel_valid(ch))
  3939. continue;
  3940. if (is_channel_a_band(ch))
  3941. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3942. else
  3943. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3944. geo_ch = &sband->channels[sband->n_channels++];
  3945. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3946. geo_ch->max_power = ch->max_power_avg;
  3947. geo_ch->max_antenna_gain = 0xff;
  3948. geo_ch->hw_value = ch->channel;
  3949. if (is_channel_valid(ch)) {
  3950. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3951. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3952. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3953. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3954. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3955. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3956. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  3957. priv->max_channel_txpower_limit =
  3958. ch->max_power_avg;
  3959. } else {
  3960. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3961. }
  3962. /* Save flags for reg domain usage */
  3963. geo_ch->orig_flags = geo_ch->flags;
  3964. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3965. ch->channel, geo_ch->center_freq,
  3966. is_channel_a_band(ch) ? "5.2" : "2.4",
  3967. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3968. "restricted" : "valid",
  3969. geo_ch->flags);
  3970. }
  3971. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3972. priv->cfg->sku & IWL_SKU_A) {
  3973. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3974. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3975. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3976. priv->cfg->sku &= ~IWL_SKU_A;
  3977. }
  3978. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3979. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3980. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3981. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3982. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3983. &priv->bands[IEEE80211_BAND_2GHZ];
  3984. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3985. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3986. &priv->bands[IEEE80211_BAND_5GHZ];
  3987. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3988. return 0;
  3989. }
  3990. /*
  3991. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3992. */
  3993. static void iwl3945_free_geos(struct iwl_priv *priv)
  3994. {
  3995. kfree(priv->ieee_channels);
  3996. kfree(priv->ieee_rates);
  3997. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3998. }
  3999. /******************************************************************************
  4000. *
  4001. * uCode download functions
  4002. *
  4003. ******************************************************************************/
  4004. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  4005. {
  4006. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4007. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4008. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4009. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4010. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4011. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4012. }
  4013. /**
  4014. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4015. * looking at all data.
  4016. */
  4017. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  4018. {
  4019. u32 val;
  4020. u32 save_len = len;
  4021. int rc = 0;
  4022. u32 errcnt;
  4023. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4024. rc = iwl_grab_nic_access(priv);
  4025. if (rc)
  4026. return rc;
  4027. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4028. IWL39_RTC_INST_LOWER_BOUND);
  4029. errcnt = 0;
  4030. for (; len > 0; len -= sizeof(u32), image++) {
  4031. /* read data comes through single port, auto-incr addr */
  4032. /* NOTE: Use the debugless read so we don't flood kernel log
  4033. * if IWL_DL_IO is set */
  4034. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4035. if (val != le32_to_cpu(*image)) {
  4036. IWL_ERR(priv, "uCode INST section is invalid at "
  4037. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4038. save_len - len, val, le32_to_cpu(*image));
  4039. rc = -EIO;
  4040. errcnt++;
  4041. if (errcnt >= 20)
  4042. break;
  4043. }
  4044. }
  4045. iwl_release_nic_access(priv);
  4046. if (!errcnt)
  4047. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4048. return rc;
  4049. }
  4050. /**
  4051. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4052. * using sample data 100 bytes apart. If these sample points are good,
  4053. * it's a pretty good bet that everything between them is good, too.
  4054. */
  4055. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  4056. {
  4057. u32 val;
  4058. int rc = 0;
  4059. u32 errcnt = 0;
  4060. u32 i;
  4061. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4062. rc = iwl_grab_nic_access(priv);
  4063. if (rc)
  4064. return rc;
  4065. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4066. /* read data comes through single port, auto-incr addr */
  4067. /* NOTE: Use the debugless read so we don't flood kernel log
  4068. * if IWL_DL_IO is set */
  4069. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4070. i + IWL39_RTC_INST_LOWER_BOUND);
  4071. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4072. if (val != le32_to_cpu(*image)) {
  4073. #if 0 /* Enable this if you want to see details */
  4074. IWL_ERR(priv, "uCode INST section is invalid at "
  4075. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4076. i, val, *image);
  4077. #endif
  4078. rc = -EIO;
  4079. errcnt++;
  4080. if (errcnt >= 3)
  4081. break;
  4082. }
  4083. }
  4084. iwl_release_nic_access(priv);
  4085. return rc;
  4086. }
  4087. /**
  4088. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4089. * and verify its contents
  4090. */
  4091. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  4092. {
  4093. __le32 *image;
  4094. u32 len;
  4095. int rc = 0;
  4096. /* Try bootstrap */
  4097. image = (__le32 *)priv->ucode_boot.v_addr;
  4098. len = priv->ucode_boot.len;
  4099. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4100. if (rc == 0) {
  4101. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4102. return 0;
  4103. }
  4104. /* Try initialize */
  4105. image = (__le32 *)priv->ucode_init.v_addr;
  4106. len = priv->ucode_init.len;
  4107. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4108. if (rc == 0) {
  4109. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4110. return 0;
  4111. }
  4112. /* Try runtime/protocol */
  4113. image = (__le32 *)priv->ucode_code.v_addr;
  4114. len = priv->ucode_code.len;
  4115. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4116. if (rc == 0) {
  4117. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4118. return 0;
  4119. }
  4120. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4121. /* Since nothing seems to match, show first several data entries in
  4122. * instruction SRAM, so maybe visual inspection will give a clue.
  4123. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4124. image = (__le32 *)priv->ucode_boot.v_addr;
  4125. len = priv->ucode_boot.len;
  4126. rc = iwl3945_verify_inst_full(priv, image, len);
  4127. return rc;
  4128. }
  4129. static void iwl3945_nic_start(struct iwl_priv *priv)
  4130. {
  4131. /* Remove all resets to allow NIC to operate */
  4132. iwl_write32(priv, CSR_RESET, 0);
  4133. }
  4134. /**
  4135. * iwl3945_read_ucode - Read uCode images from disk file.
  4136. *
  4137. * Copy into buffers for card to fetch via bus-mastering
  4138. */
  4139. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4140. {
  4141. struct iwl_ucode *ucode;
  4142. int ret = -EINVAL, index;
  4143. const struct firmware *ucode_raw;
  4144. /* firmware file name contains uCode/driver compatibility version */
  4145. const char *name_pre = priv->cfg->fw_name_pre;
  4146. const unsigned int api_max = priv->cfg->ucode_api_max;
  4147. const unsigned int api_min = priv->cfg->ucode_api_min;
  4148. char buf[25];
  4149. u8 *src;
  4150. size_t len;
  4151. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4152. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4153. * request_firmware() is synchronous, file is in memory on return. */
  4154. for (index = api_max; index >= api_min; index--) {
  4155. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4156. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4157. if (ret < 0) {
  4158. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  4159. buf, ret);
  4160. if (ret == -ENOENT)
  4161. continue;
  4162. else
  4163. goto error;
  4164. } else {
  4165. if (index < api_max)
  4166. IWL_ERR(priv, "Loaded firmware %s, "
  4167. "which is deprecated. "
  4168. " Please use API v%u instead.\n",
  4169. buf, api_max);
  4170. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4171. buf, ucode_raw->size);
  4172. break;
  4173. }
  4174. }
  4175. if (ret < 0)
  4176. goto error;
  4177. /* Make sure that we got at least our header! */
  4178. if (ucode_raw->size < sizeof(*ucode)) {
  4179. IWL_ERR(priv, "File size way too small!\n");
  4180. ret = -EINVAL;
  4181. goto err_release;
  4182. }
  4183. /* Data from ucode file: header followed by uCode images */
  4184. ucode = (void *)ucode_raw->data;
  4185. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4186. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4187. inst_size = le32_to_cpu(ucode->inst_size);
  4188. data_size = le32_to_cpu(ucode->data_size);
  4189. init_size = le32_to_cpu(ucode->init_size);
  4190. init_data_size = le32_to_cpu(ucode->init_data_size);
  4191. boot_size = le32_to_cpu(ucode->boot_size);
  4192. /* api_ver should match the api version forming part of the
  4193. * firmware filename ... but we don't check for that and only rely
  4194. * on the API version read from firware header from here on forward */
  4195. if (api_ver < api_min || api_ver > api_max) {
  4196. IWL_ERR(priv, "Driver unable to support your firmware API. "
  4197. "Driver supports v%u, firmware is v%u.\n",
  4198. api_max, api_ver);
  4199. priv->ucode_ver = 0;
  4200. ret = -EINVAL;
  4201. goto err_release;
  4202. }
  4203. if (api_ver != api_max)
  4204. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  4205. "got %u. New firmware can be obtained "
  4206. "from http://www.intellinuxwireless.org.\n",
  4207. api_max, api_ver);
  4208. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4209. IWL_UCODE_MAJOR(priv->ucode_ver),
  4210. IWL_UCODE_MINOR(priv->ucode_ver),
  4211. IWL_UCODE_API(priv->ucode_ver),
  4212. IWL_UCODE_SERIAL(priv->ucode_ver));
  4213. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4214. priv->ucode_ver);
  4215. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4216. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4217. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4218. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4219. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4220. /* Verify size of file vs. image size info in file's header */
  4221. if (ucode_raw->size < sizeof(*ucode) +
  4222. inst_size + data_size + init_size +
  4223. init_data_size + boot_size) {
  4224. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4225. (int)ucode_raw->size);
  4226. ret = -EINVAL;
  4227. goto err_release;
  4228. }
  4229. /* Verify that uCode images will fit in card's SRAM */
  4230. if (inst_size > IWL39_MAX_INST_SIZE) {
  4231. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4232. inst_size);
  4233. ret = -EINVAL;
  4234. goto err_release;
  4235. }
  4236. if (data_size > IWL39_MAX_DATA_SIZE) {
  4237. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4238. data_size);
  4239. ret = -EINVAL;
  4240. goto err_release;
  4241. }
  4242. if (init_size > IWL39_MAX_INST_SIZE) {
  4243. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4244. init_size);
  4245. ret = -EINVAL;
  4246. goto err_release;
  4247. }
  4248. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4249. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4250. init_data_size);
  4251. ret = -EINVAL;
  4252. goto err_release;
  4253. }
  4254. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4255. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4256. boot_size);
  4257. ret = -EINVAL;
  4258. goto err_release;
  4259. }
  4260. /* Allocate ucode buffers for card's bus-master loading ... */
  4261. /* Runtime instructions and 2 copies of data:
  4262. * 1) unmodified from disk
  4263. * 2) backup cache for save/restore during power-downs */
  4264. priv->ucode_code.len = inst_size;
  4265. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4266. priv->ucode_data.len = data_size;
  4267. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4268. priv->ucode_data_backup.len = data_size;
  4269. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4270. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4271. !priv->ucode_data_backup.v_addr)
  4272. goto err_pci_alloc;
  4273. /* Initialization instructions and data */
  4274. if (init_size && init_data_size) {
  4275. priv->ucode_init.len = init_size;
  4276. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4277. priv->ucode_init_data.len = init_data_size;
  4278. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4279. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4280. goto err_pci_alloc;
  4281. }
  4282. /* Bootstrap (instructions only, no data) */
  4283. if (boot_size) {
  4284. priv->ucode_boot.len = boot_size;
  4285. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4286. if (!priv->ucode_boot.v_addr)
  4287. goto err_pci_alloc;
  4288. }
  4289. /* Copy images into buffers for card's bus-master reads ... */
  4290. /* Runtime instructions (first block of data in file) */
  4291. src = &ucode->data[0];
  4292. len = priv->ucode_code.len;
  4293. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4294. memcpy(priv->ucode_code.v_addr, src, len);
  4295. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4296. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4297. /* Runtime data (2nd block)
  4298. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4299. src = &ucode->data[inst_size];
  4300. len = priv->ucode_data.len;
  4301. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4302. memcpy(priv->ucode_data.v_addr, src, len);
  4303. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4304. /* Initialization instructions (3rd block) */
  4305. if (init_size) {
  4306. src = &ucode->data[inst_size + data_size];
  4307. len = priv->ucode_init.len;
  4308. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4309. len);
  4310. memcpy(priv->ucode_init.v_addr, src, len);
  4311. }
  4312. /* Initialization data (4th block) */
  4313. if (init_data_size) {
  4314. src = &ucode->data[inst_size + data_size + init_size];
  4315. len = priv->ucode_init_data.len;
  4316. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4317. (int)len);
  4318. memcpy(priv->ucode_init_data.v_addr, src, len);
  4319. }
  4320. /* Bootstrap instructions (5th block) */
  4321. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4322. len = priv->ucode_boot.len;
  4323. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4324. (int)len);
  4325. memcpy(priv->ucode_boot.v_addr, src, len);
  4326. /* We have our copies now, allow OS release its copies */
  4327. release_firmware(ucode_raw);
  4328. return 0;
  4329. err_pci_alloc:
  4330. IWL_ERR(priv, "failed to allocate pci memory\n");
  4331. ret = -ENOMEM;
  4332. iwl3945_dealloc_ucode_pci(priv);
  4333. err_release:
  4334. release_firmware(ucode_raw);
  4335. error:
  4336. return ret;
  4337. }
  4338. /**
  4339. * iwl3945_set_ucode_ptrs - Set uCode address location
  4340. *
  4341. * Tell initialization uCode where to find runtime uCode.
  4342. *
  4343. * BSM registers initially contain pointers to initialization uCode.
  4344. * We need to replace them to load runtime uCode inst and data,
  4345. * and to save runtime data when powering down.
  4346. */
  4347. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4348. {
  4349. dma_addr_t pinst;
  4350. dma_addr_t pdata;
  4351. int rc = 0;
  4352. unsigned long flags;
  4353. /* bits 31:0 for 3945 */
  4354. pinst = priv->ucode_code.p_addr;
  4355. pdata = priv->ucode_data_backup.p_addr;
  4356. spin_lock_irqsave(&priv->lock, flags);
  4357. rc = iwl_grab_nic_access(priv);
  4358. if (rc) {
  4359. spin_unlock_irqrestore(&priv->lock, flags);
  4360. return rc;
  4361. }
  4362. /* Tell bootstrap uCode where to find image to load */
  4363. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4364. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4365. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4366. priv->ucode_data.len);
  4367. /* Inst byte count must be last to set up, bit 31 signals uCode
  4368. * that all new ptr/size info is in place */
  4369. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4370. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4371. iwl_release_nic_access(priv);
  4372. spin_unlock_irqrestore(&priv->lock, flags);
  4373. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4374. return rc;
  4375. }
  4376. /**
  4377. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4378. *
  4379. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4380. *
  4381. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4382. */
  4383. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4384. {
  4385. /* Check alive response for "valid" sign from uCode */
  4386. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4387. /* We had an error bringing up the hardware, so take it
  4388. * all the way back down so we can try again */
  4389. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4390. goto restart;
  4391. }
  4392. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4393. * This is a paranoid check, because we would not have gotten the
  4394. * "initialize" alive if code weren't properly loaded. */
  4395. if (iwl3945_verify_ucode(priv)) {
  4396. /* Runtime instruction load was bad;
  4397. * take it all the way back down so we can try again */
  4398. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4399. goto restart;
  4400. }
  4401. /* Send pointers to protocol/runtime uCode image ... init code will
  4402. * load and launch runtime uCode, which will send us another "Alive"
  4403. * notification. */
  4404. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4405. if (iwl3945_set_ucode_ptrs(priv)) {
  4406. /* Runtime instruction load won't happen;
  4407. * take it all the way back down so we can try again */
  4408. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4409. goto restart;
  4410. }
  4411. return;
  4412. restart:
  4413. queue_work(priv->workqueue, &priv->restart);
  4414. }
  4415. /* temporary */
  4416. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4417. struct sk_buff *skb);
  4418. /**
  4419. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4420. * from protocol/runtime uCode (initialization uCode's
  4421. * Alive gets handled by iwl3945_init_alive_start()).
  4422. */
  4423. static void iwl3945_alive_start(struct iwl_priv *priv)
  4424. {
  4425. int rc = 0;
  4426. int thermal_spin = 0;
  4427. u32 rfkill;
  4428. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4429. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4430. /* We had an error bringing up the hardware, so take it
  4431. * all the way back down so we can try again */
  4432. IWL_DEBUG_INFO("Alive failed.\n");
  4433. goto restart;
  4434. }
  4435. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4436. * This is a paranoid check, because we would not have gotten the
  4437. * "runtime" alive if code weren't properly loaded. */
  4438. if (iwl3945_verify_ucode(priv)) {
  4439. /* Runtime instruction load was bad;
  4440. * take it all the way back down so we can try again */
  4441. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4442. goto restart;
  4443. }
  4444. iwl3945_clear_stations_table(priv);
  4445. rc = iwl_grab_nic_access(priv);
  4446. if (rc) {
  4447. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  4448. return;
  4449. }
  4450. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4451. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4452. iwl_release_nic_access(priv);
  4453. if (rfkill & 0x1) {
  4454. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4455. /* if RFKILL is not on, then wait for thermal
  4456. * sensor in adapter to kick in */
  4457. while (iwl3945_hw_get_temperature(priv) == 0) {
  4458. thermal_spin++;
  4459. udelay(10);
  4460. }
  4461. if (thermal_spin)
  4462. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4463. thermal_spin * 10);
  4464. } else
  4465. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4466. /* After the ALIVE response, we can send commands to 3945 uCode */
  4467. set_bit(STATUS_ALIVE, &priv->status);
  4468. /* Clear out the uCode error bit if it is set */
  4469. clear_bit(STATUS_FW_ERROR, &priv->status);
  4470. if (iwl_is_rfkill(priv))
  4471. return;
  4472. ieee80211_wake_queues(priv->hw);
  4473. priv->active_rate = priv->rates_mask;
  4474. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4475. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4476. if (iwl3945_is_associated(priv)) {
  4477. struct iwl3945_rxon_cmd *active_rxon =
  4478. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4479. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4480. sizeof(priv->staging39_rxon));
  4481. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4482. } else {
  4483. /* Initialize our rx_config data */
  4484. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4485. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4486. }
  4487. /* Configure Bluetooth device coexistence support */
  4488. iwl3945_send_bt_config(priv);
  4489. /* Configure the adapter for unassociated operation */
  4490. iwl3945_commit_rxon(priv);
  4491. iwl3945_reg_txpower_periodic(priv);
  4492. iwl3945_led_register(priv);
  4493. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4494. set_bit(STATUS_READY, &priv->status);
  4495. wake_up_interruptible(&priv->wait_command_queue);
  4496. if (priv->error_recovering)
  4497. iwl3945_error_recovery(priv);
  4498. /* reassociate for ADHOC mode */
  4499. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4500. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4501. priv->vif);
  4502. if (beacon)
  4503. iwl3945_mac_beacon_update(priv->hw, beacon);
  4504. }
  4505. return;
  4506. restart:
  4507. queue_work(priv->workqueue, &priv->restart);
  4508. }
  4509. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4510. static void __iwl3945_down(struct iwl_priv *priv)
  4511. {
  4512. unsigned long flags;
  4513. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4514. struct ieee80211_conf *conf = NULL;
  4515. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4516. conf = ieee80211_get_hw_conf(priv->hw);
  4517. if (!exit_pending)
  4518. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4519. iwl3945_led_unregister(priv);
  4520. iwl3945_clear_stations_table(priv);
  4521. /* Unblock any waiting calls */
  4522. wake_up_interruptible_all(&priv->wait_command_queue);
  4523. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4524. * exiting the module */
  4525. if (!exit_pending)
  4526. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4527. /* stop and reset the on-board processor */
  4528. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4529. /* tell the device to stop sending interrupts */
  4530. spin_lock_irqsave(&priv->lock, flags);
  4531. iwl3945_disable_interrupts(priv);
  4532. spin_unlock_irqrestore(&priv->lock, flags);
  4533. iwl_synchronize_irq(priv);
  4534. if (priv->mac80211_registered)
  4535. ieee80211_stop_queues(priv->hw);
  4536. /* If we have not previously called iwl3945_init() then
  4537. * clear all bits but the RF Kill and SUSPEND bits and return */
  4538. if (!iwl_is_init(priv)) {
  4539. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4540. STATUS_RF_KILL_HW |
  4541. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4542. STATUS_RF_KILL_SW |
  4543. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4544. STATUS_GEO_CONFIGURED |
  4545. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4546. STATUS_IN_SUSPEND |
  4547. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4548. STATUS_EXIT_PENDING;
  4549. goto exit;
  4550. }
  4551. /* ...otherwise clear out all the status bits but the RF Kill and
  4552. * SUSPEND bits and continue taking the NIC down. */
  4553. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4554. STATUS_RF_KILL_HW |
  4555. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4556. STATUS_RF_KILL_SW |
  4557. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4558. STATUS_GEO_CONFIGURED |
  4559. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4560. STATUS_IN_SUSPEND |
  4561. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4562. STATUS_FW_ERROR |
  4563. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4564. STATUS_EXIT_PENDING;
  4565. spin_lock_irqsave(&priv->lock, flags);
  4566. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4567. spin_unlock_irqrestore(&priv->lock, flags);
  4568. iwl3945_hw_txq_ctx_stop(priv);
  4569. iwl3945_hw_rxq_stop(priv);
  4570. spin_lock_irqsave(&priv->lock, flags);
  4571. if (!iwl_grab_nic_access(priv)) {
  4572. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4573. APMG_CLK_VAL_DMA_CLK_RQT);
  4574. iwl_release_nic_access(priv);
  4575. }
  4576. spin_unlock_irqrestore(&priv->lock, flags);
  4577. udelay(5);
  4578. priv->cfg->ops->lib->apm_ops.reset(priv);
  4579. exit:
  4580. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4581. if (priv->ibss_beacon)
  4582. dev_kfree_skb(priv->ibss_beacon);
  4583. priv->ibss_beacon = NULL;
  4584. /* clear out any free frames */
  4585. iwl3945_clear_free_frames(priv);
  4586. }
  4587. static void iwl3945_down(struct iwl_priv *priv)
  4588. {
  4589. mutex_lock(&priv->mutex);
  4590. __iwl3945_down(priv);
  4591. mutex_unlock(&priv->mutex);
  4592. iwl3945_cancel_deferred_work(priv);
  4593. }
  4594. #define MAX_HW_RESTARTS 5
  4595. static int __iwl3945_up(struct iwl_priv *priv)
  4596. {
  4597. int rc, i;
  4598. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4599. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4600. return -EIO;
  4601. }
  4602. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4603. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4604. "parameter)\n");
  4605. return -ENODEV;
  4606. }
  4607. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4608. IWL_ERR(priv, "ucode not available for device bring up\n");
  4609. return -EIO;
  4610. }
  4611. /* If platform's RF_KILL switch is NOT set to KILL */
  4612. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4613. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4614. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4615. else {
  4616. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4617. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4618. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4619. return -ENODEV;
  4620. }
  4621. }
  4622. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4623. rc = iwl3945_hw_nic_init(priv);
  4624. if (rc) {
  4625. IWL_ERR(priv, "Unable to int nic\n");
  4626. return rc;
  4627. }
  4628. /* make sure rfkill handshake bits are cleared */
  4629. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4630. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4631. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4632. /* clear (again), then enable host interrupts */
  4633. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4634. iwl3945_enable_interrupts(priv);
  4635. /* really make sure rfkill handshake bits are cleared */
  4636. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4637. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4638. /* Copy original ucode data image from disk into backup cache.
  4639. * This will be used to initialize the on-board processor's
  4640. * data SRAM for a clean start when the runtime program first loads. */
  4641. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4642. priv->ucode_data.len);
  4643. /* We return success when we resume from suspend and rf_kill is on. */
  4644. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4645. return 0;
  4646. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4647. iwl3945_clear_stations_table(priv);
  4648. /* load bootstrap state machine,
  4649. * load bootstrap program into processor's memory,
  4650. * prepare to load the "initialize" uCode */
  4651. priv->cfg->ops->lib->load_ucode(priv);
  4652. if (rc) {
  4653. IWL_ERR(priv,
  4654. "Unable to set up bootstrap uCode: %d\n", rc);
  4655. continue;
  4656. }
  4657. /* start card; "initialize" will load runtime ucode */
  4658. iwl3945_nic_start(priv);
  4659. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4660. return 0;
  4661. }
  4662. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4663. __iwl3945_down(priv);
  4664. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4665. /* tried to restart and config the device for as long as our
  4666. * patience could withstand */
  4667. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4668. return -EIO;
  4669. }
  4670. /*****************************************************************************
  4671. *
  4672. * Workqueue callbacks
  4673. *
  4674. *****************************************************************************/
  4675. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4676. {
  4677. struct iwl_priv *priv =
  4678. container_of(data, struct iwl_priv, init_alive_start.work);
  4679. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4680. return;
  4681. mutex_lock(&priv->mutex);
  4682. iwl3945_init_alive_start(priv);
  4683. mutex_unlock(&priv->mutex);
  4684. }
  4685. static void iwl3945_bg_alive_start(struct work_struct *data)
  4686. {
  4687. struct iwl_priv *priv =
  4688. container_of(data, struct iwl_priv, alive_start.work);
  4689. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4690. return;
  4691. mutex_lock(&priv->mutex);
  4692. iwl3945_alive_start(priv);
  4693. mutex_unlock(&priv->mutex);
  4694. }
  4695. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4696. {
  4697. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4698. wake_up_interruptible(&priv->wait_command_queue);
  4699. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4700. return;
  4701. mutex_lock(&priv->mutex);
  4702. if (!iwl_is_rfkill(priv)) {
  4703. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4704. "HW and/or SW RF Kill no longer active, restarting "
  4705. "device\n");
  4706. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4707. queue_work(priv->workqueue, &priv->restart);
  4708. } else {
  4709. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4710. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4711. "disabled by SW switch\n");
  4712. else
  4713. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  4714. "Kill switch must be turned off for "
  4715. "wireless networking to work.\n");
  4716. }
  4717. mutex_unlock(&priv->mutex);
  4718. iwl3945_rfkill_set_hw_state(priv);
  4719. }
  4720. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4721. static void iwl3945_bg_scan_check(struct work_struct *data)
  4722. {
  4723. struct iwl_priv *priv =
  4724. container_of(data, struct iwl_priv, scan_check.work);
  4725. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4726. return;
  4727. mutex_lock(&priv->mutex);
  4728. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4729. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4730. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4731. "Scan completion watchdog resetting adapter (%dms)\n",
  4732. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4733. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4734. iwl3945_send_scan_abort(priv);
  4735. }
  4736. mutex_unlock(&priv->mutex);
  4737. }
  4738. static void iwl3945_bg_request_scan(struct work_struct *data)
  4739. {
  4740. struct iwl_priv *priv =
  4741. container_of(data, struct iwl_priv, request_scan);
  4742. struct iwl_host_cmd cmd = {
  4743. .id = REPLY_SCAN_CMD,
  4744. .len = sizeof(struct iwl3945_scan_cmd),
  4745. .meta.flags = CMD_SIZE_HUGE,
  4746. };
  4747. int rc = 0;
  4748. struct iwl3945_scan_cmd *scan;
  4749. struct ieee80211_conf *conf = NULL;
  4750. u8 n_probes = 2;
  4751. enum ieee80211_band band;
  4752. DECLARE_SSID_BUF(ssid);
  4753. conf = ieee80211_get_hw_conf(priv->hw);
  4754. mutex_lock(&priv->mutex);
  4755. if (!iwl_is_ready(priv)) {
  4756. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4757. goto done;
  4758. }
  4759. /* Make sure the scan wasn't canceled before this queued work
  4760. * was given the chance to run... */
  4761. if (!test_bit(STATUS_SCANNING, &priv->status))
  4762. goto done;
  4763. /* This should never be called or scheduled if there is currently
  4764. * a scan active in the hardware. */
  4765. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4766. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4767. "Ignoring second request.\n");
  4768. rc = -EIO;
  4769. goto done;
  4770. }
  4771. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4772. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4773. goto done;
  4774. }
  4775. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4776. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4777. goto done;
  4778. }
  4779. if (iwl_is_rfkill(priv)) {
  4780. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4781. goto done;
  4782. }
  4783. if (!test_bit(STATUS_READY, &priv->status)) {
  4784. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4785. goto done;
  4786. }
  4787. if (!priv->scan_bands) {
  4788. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4789. goto done;
  4790. }
  4791. if (!priv->scan39) {
  4792. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4793. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4794. if (!priv->scan39) {
  4795. rc = -ENOMEM;
  4796. goto done;
  4797. }
  4798. }
  4799. scan = priv->scan39;
  4800. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4801. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4802. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4803. if (iwl3945_is_associated(priv)) {
  4804. u16 interval = 0;
  4805. u32 extra;
  4806. u32 suspend_time = 100;
  4807. u32 scan_suspend_time = 100;
  4808. unsigned long flags;
  4809. IWL_DEBUG_INFO("Scanning while associated...\n");
  4810. spin_lock_irqsave(&priv->lock, flags);
  4811. interval = priv->beacon_int;
  4812. spin_unlock_irqrestore(&priv->lock, flags);
  4813. scan->suspend_time = 0;
  4814. scan->max_out_time = cpu_to_le32(200 * 1024);
  4815. if (!interval)
  4816. interval = suspend_time;
  4817. /*
  4818. * suspend time format:
  4819. * 0-19: beacon interval in usec (time before exec.)
  4820. * 20-23: 0
  4821. * 24-31: number of beacons (suspend between channels)
  4822. */
  4823. extra = (suspend_time / interval) << 24;
  4824. scan_suspend_time = 0xFF0FFFFF &
  4825. (extra | ((suspend_time % interval) * 1024));
  4826. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4827. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4828. scan_suspend_time, interval);
  4829. }
  4830. /* We should add the ability for user to lock to PASSIVE ONLY */
  4831. if (priv->one_direct_scan) {
  4832. IWL_DEBUG_SCAN
  4833. ("Kicking off one direct scan for '%s'\n",
  4834. print_ssid(ssid, priv->direct_ssid,
  4835. priv->direct_ssid_len));
  4836. scan->direct_scan[0].id = WLAN_EID_SSID;
  4837. scan->direct_scan[0].len = priv->direct_ssid_len;
  4838. memcpy(scan->direct_scan[0].ssid,
  4839. priv->direct_ssid, priv->direct_ssid_len);
  4840. n_probes++;
  4841. } else
  4842. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4843. /* We don't build a direct scan probe request; the uCode will do
  4844. * that based on the direct_mask added to each channel entry */
  4845. scan->tx_cmd.len = cpu_to_le16(
  4846. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  4847. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4848. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4849. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4850. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4851. /* flags + rate selection */
  4852. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4853. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4854. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4855. scan->good_CRC_th = 0;
  4856. band = IEEE80211_BAND_2GHZ;
  4857. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4858. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4859. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4860. band = IEEE80211_BAND_5GHZ;
  4861. } else {
  4862. IWL_WARN(priv, "Invalid scan band count\n");
  4863. goto done;
  4864. }
  4865. /* select Rx antennas */
  4866. scan->flags |= iwl3945_get_antenna_flags(priv);
  4867. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4868. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4869. scan->channel_count =
  4870. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4871. n_probes,
  4872. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4873. if (scan->channel_count == 0) {
  4874. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4875. goto done;
  4876. }
  4877. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4878. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4879. cmd.data = scan;
  4880. scan->len = cpu_to_le16(cmd.len);
  4881. set_bit(STATUS_SCAN_HW, &priv->status);
  4882. rc = iwl3945_send_cmd_sync(priv, &cmd);
  4883. if (rc)
  4884. goto done;
  4885. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4886. IWL_SCAN_CHECK_WATCHDOG);
  4887. mutex_unlock(&priv->mutex);
  4888. return;
  4889. done:
  4890. /* can not perform scan make sure we clear scanning
  4891. * bits from status so next scan request can be performed.
  4892. * if we dont clear scanning status bit here all next scan
  4893. * will fail
  4894. */
  4895. clear_bit(STATUS_SCAN_HW, &priv->status);
  4896. clear_bit(STATUS_SCANNING, &priv->status);
  4897. /* inform mac80211 scan aborted */
  4898. queue_work(priv->workqueue, &priv->scan_completed);
  4899. mutex_unlock(&priv->mutex);
  4900. }
  4901. static void iwl3945_bg_up(struct work_struct *data)
  4902. {
  4903. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4904. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4905. return;
  4906. mutex_lock(&priv->mutex);
  4907. __iwl3945_up(priv);
  4908. mutex_unlock(&priv->mutex);
  4909. iwl3945_rfkill_set_hw_state(priv);
  4910. }
  4911. static void iwl3945_bg_restart(struct work_struct *data)
  4912. {
  4913. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4914. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4915. return;
  4916. iwl3945_down(priv);
  4917. queue_work(priv->workqueue, &priv->up);
  4918. }
  4919. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4920. {
  4921. struct iwl_priv *priv =
  4922. container_of(data, struct iwl_priv, rx_replenish);
  4923. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4924. return;
  4925. mutex_lock(&priv->mutex);
  4926. iwl3945_rx_replenish(priv);
  4927. mutex_unlock(&priv->mutex);
  4928. }
  4929. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4930. static void iwl3945_post_associate(struct iwl_priv *priv)
  4931. {
  4932. int rc = 0;
  4933. struct ieee80211_conf *conf = NULL;
  4934. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4935. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4936. return;
  4937. }
  4938. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4939. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4940. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4941. return;
  4942. if (!priv->vif || !priv->is_open)
  4943. return;
  4944. iwl3945_scan_cancel_timeout(priv, 200);
  4945. conf = ieee80211_get_hw_conf(priv->hw);
  4946. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4947. iwl3945_commit_rxon(priv);
  4948. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4949. iwl3945_setup_rxon_timing(priv);
  4950. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4951. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4952. if (rc)
  4953. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4954. "Attempting to continue.\n");
  4955. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4956. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4957. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4958. priv->assoc_id, priv->beacon_int);
  4959. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4960. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4961. else
  4962. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4963. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4964. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4965. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4966. else
  4967. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4968. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4969. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4970. }
  4971. iwl3945_commit_rxon(priv);
  4972. switch (priv->iw_mode) {
  4973. case NL80211_IFTYPE_STATION:
  4974. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4975. break;
  4976. case NL80211_IFTYPE_ADHOC:
  4977. priv->assoc_id = 1;
  4978. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4979. iwl3945_sync_sta(priv, IWL_STA_ID,
  4980. (priv->band == IEEE80211_BAND_5GHZ) ?
  4981. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4982. CMD_ASYNC);
  4983. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4984. iwl3945_send_beacon_cmd(priv);
  4985. break;
  4986. default:
  4987. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4988. __func__, priv->iw_mode);
  4989. break;
  4990. }
  4991. iwl3945_activate_qos(priv, 0);
  4992. /* we have just associated, don't start scan too early */
  4993. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4994. }
  4995. static void iwl3945_bg_abort_scan(struct work_struct *work)
  4996. {
  4997. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  4998. if (!iwl_is_ready(priv))
  4999. return;
  5000. mutex_lock(&priv->mutex);
  5001. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5002. iwl3945_send_scan_abort(priv);
  5003. mutex_unlock(&priv->mutex);
  5004. }
  5005. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5006. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5007. {
  5008. struct iwl_priv *priv =
  5009. container_of(work, struct iwl_priv, scan_completed);
  5010. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5011. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5012. return;
  5013. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5014. iwl3945_mac_config(priv->hw, 0);
  5015. ieee80211_scan_completed(priv->hw);
  5016. /* Since setting the TXPOWER may have been deferred while
  5017. * performing the scan, fire one off */
  5018. mutex_lock(&priv->mutex);
  5019. iwl3945_hw_reg_send_txpower(priv);
  5020. mutex_unlock(&priv->mutex);
  5021. }
  5022. /*****************************************************************************
  5023. *
  5024. * mac80211 entry point functions
  5025. *
  5026. *****************************************************************************/
  5027. #define UCODE_READY_TIMEOUT (2 * HZ)
  5028. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5029. {
  5030. struct iwl_priv *priv = hw->priv;
  5031. int ret;
  5032. IWL_DEBUG_MAC80211("enter\n");
  5033. if (pci_enable_device(priv->pci_dev)) {
  5034. IWL_ERR(priv, "Fail to pci_enable_device\n");
  5035. return -ENODEV;
  5036. }
  5037. pci_restore_state(priv->pci_dev);
  5038. pci_enable_msi(priv->pci_dev);
  5039. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5040. DRV_NAME, priv);
  5041. if (ret) {
  5042. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  5043. goto out_disable_msi;
  5044. }
  5045. /* we should be verifying the device is ready to be opened */
  5046. mutex_lock(&priv->mutex);
  5047. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5048. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5049. * ucode filename and max sizes are card-specific. */
  5050. if (!priv->ucode_code.len) {
  5051. ret = iwl3945_read_ucode(priv);
  5052. if (ret) {
  5053. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  5054. mutex_unlock(&priv->mutex);
  5055. goto out_release_irq;
  5056. }
  5057. }
  5058. ret = __iwl3945_up(priv);
  5059. mutex_unlock(&priv->mutex);
  5060. iwl3945_rfkill_set_hw_state(priv);
  5061. if (ret)
  5062. goto out_release_irq;
  5063. IWL_DEBUG_INFO("Start UP work.\n");
  5064. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5065. return 0;
  5066. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5067. * mac80211 will not be run successfully. */
  5068. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5069. test_bit(STATUS_READY, &priv->status),
  5070. UCODE_READY_TIMEOUT);
  5071. if (!ret) {
  5072. if (!test_bit(STATUS_READY, &priv->status)) {
  5073. IWL_ERR(priv,
  5074. "Wait for START_ALIVE timeout after %dms.\n",
  5075. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5076. ret = -ETIMEDOUT;
  5077. goto out_release_irq;
  5078. }
  5079. }
  5080. priv->is_open = 1;
  5081. IWL_DEBUG_MAC80211("leave\n");
  5082. return 0;
  5083. out_release_irq:
  5084. free_irq(priv->pci_dev->irq, priv);
  5085. out_disable_msi:
  5086. pci_disable_msi(priv->pci_dev);
  5087. pci_disable_device(priv->pci_dev);
  5088. priv->is_open = 0;
  5089. IWL_DEBUG_MAC80211("leave - failed\n");
  5090. return ret;
  5091. }
  5092. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5093. {
  5094. struct iwl_priv *priv = hw->priv;
  5095. IWL_DEBUG_MAC80211("enter\n");
  5096. if (!priv->is_open) {
  5097. IWL_DEBUG_MAC80211("leave - skip\n");
  5098. return;
  5099. }
  5100. priv->is_open = 0;
  5101. if (iwl_is_ready_rf(priv)) {
  5102. /* stop mac, cancel any scan request and clear
  5103. * RXON_FILTER_ASSOC_MSK BIT
  5104. */
  5105. mutex_lock(&priv->mutex);
  5106. iwl3945_scan_cancel_timeout(priv, 100);
  5107. mutex_unlock(&priv->mutex);
  5108. }
  5109. iwl3945_down(priv);
  5110. flush_workqueue(priv->workqueue);
  5111. free_irq(priv->pci_dev->irq, priv);
  5112. pci_disable_msi(priv->pci_dev);
  5113. pci_save_state(priv->pci_dev);
  5114. pci_disable_device(priv->pci_dev);
  5115. IWL_DEBUG_MAC80211("leave\n");
  5116. }
  5117. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5118. {
  5119. struct iwl_priv *priv = hw->priv;
  5120. IWL_DEBUG_MAC80211("enter\n");
  5121. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5122. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5123. if (iwl3945_tx_skb(priv, skb))
  5124. dev_kfree_skb_any(skb);
  5125. IWL_DEBUG_MAC80211("leave\n");
  5126. return NETDEV_TX_OK;
  5127. }
  5128. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5129. struct ieee80211_if_init_conf *conf)
  5130. {
  5131. struct iwl_priv *priv = hw->priv;
  5132. unsigned long flags;
  5133. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5134. if (priv->vif) {
  5135. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5136. return -EOPNOTSUPP;
  5137. }
  5138. spin_lock_irqsave(&priv->lock, flags);
  5139. priv->vif = conf->vif;
  5140. priv->iw_mode = conf->type;
  5141. spin_unlock_irqrestore(&priv->lock, flags);
  5142. mutex_lock(&priv->mutex);
  5143. if (conf->mac_addr) {
  5144. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5145. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5146. }
  5147. if (iwl_is_ready(priv))
  5148. iwl3945_set_mode(priv, conf->type);
  5149. mutex_unlock(&priv->mutex);
  5150. IWL_DEBUG_MAC80211("leave\n");
  5151. return 0;
  5152. }
  5153. /**
  5154. * iwl3945_mac_config - mac80211 config callback
  5155. *
  5156. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5157. * be set inappropriately and the driver currently sets the hardware up to
  5158. * use it whenever needed.
  5159. */
  5160. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5161. {
  5162. struct iwl_priv *priv = hw->priv;
  5163. const struct iwl_channel_info *ch_info;
  5164. struct ieee80211_conf *conf = &hw->conf;
  5165. unsigned long flags;
  5166. int ret = 0;
  5167. mutex_lock(&priv->mutex);
  5168. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5169. if (!iwl_is_ready(priv)) {
  5170. IWL_DEBUG_MAC80211("leave - not ready\n");
  5171. ret = -EIO;
  5172. goto out;
  5173. }
  5174. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  5175. test_bit(STATUS_SCANNING, &priv->status))) {
  5176. IWL_DEBUG_MAC80211("leave - scanning\n");
  5177. set_bit(STATUS_CONF_PENDING, &priv->status);
  5178. mutex_unlock(&priv->mutex);
  5179. return 0;
  5180. }
  5181. spin_lock_irqsave(&priv->lock, flags);
  5182. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5183. conf->channel->hw_value);
  5184. if (!is_channel_valid(ch_info)) {
  5185. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5186. conf->channel->hw_value, conf->channel->band);
  5187. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5188. spin_unlock_irqrestore(&priv->lock, flags);
  5189. ret = -EINVAL;
  5190. goto out;
  5191. }
  5192. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5193. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5194. /* The list of supported rates and rate mask can be different
  5195. * for each phymode; since the phymode may have changed, reset
  5196. * the rate mask to what mac80211 lists */
  5197. iwl3945_set_rate(priv);
  5198. spin_unlock_irqrestore(&priv->lock, flags);
  5199. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5200. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5201. iwl3945_hw_channel_switch(priv, conf->channel);
  5202. goto out;
  5203. }
  5204. #endif
  5205. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5206. if (!conf->radio_enabled) {
  5207. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5208. goto out;
  5209. }
  5210. if (iwl_is_rfkill(priv)) {
  5211. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5212. ret = -EIO;
  5213. goto out;
  5214. }
  5215. iwl3945_set_rate(priv);
  5216. if (memcmp(&priv->active39_rxon,
  5217. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5218. iwl3945_commit_rxon(priv);
  5219. else
  5220. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5221. IWL_DEBUG_MAC80211("leave\n");
  5222. out:
  5223. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5224. mutex_unlock(&priv->mutex);
  5225. return ret;
  5226. }
  5227. static void iwl3945_config_ap(struct iwl_priv *priv)
  5228. {
  5229. int rc = 0;
  5230. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5231. return;
  5232. /* The following should be done only at AP bring up */
  5233. if (!(iwl3945_is_associated(priv))) {
  5234. /* RXON - unassoc (to set timing command) */
  5235. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5236. iwl3945_commit_rxon(priv);
  5237. /* RXON Timing */
  5238. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5239. iwl3945_setup_rxon_timing(priv);
  5240. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5241. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5242. if (rc)
  5243. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  5244. "Attempting to continue.\n");
  5245. /* FIXME: what should be the assoc_id for AP? */
  5246. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5247. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5248. priv->staging39_rxon.flags |=
  5249. RXON_FLG_SHORT_PREAMBLE_MSK;
  5250. else
  5251. priv->staging39_rxon.flags &=
  5252. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5253. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5254. if (priv->assoc_capability &
  5255. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5256. priv->staging39_rxon.flags |=
  5257. RXON_FLG_SHORT_SLOT_MSK;
  5258. else
  5259. priv->staging39_rxon.flags &=
  5260. ~RXON_FLG_SHORT_SLOT_MSK;
  5261. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5262. priv->staging39_rxon.flags &=
  5263. ~RXON_FLG_SHORT_SLOT_MSK;
  5264. }
  5265. /* restore RXON assoc */
  5266. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5267. iwl3945_commit_rxon(priv);
  5268. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5269. }
  5270. iwl3945_send_beacon_cmd(priv);
  5271. /* FIXME - we need to add code here to detect a totally new
  5272. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5273. * clear sta table, add BCAST sta... */
  5274. }
  5275. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5276. struct ieee80211_vif *vif,
  5277. struct ieee80211_if_conf *conf)
  5278. {
  5279. struct iwl_priv *priv = hw->priv;
  5280. int rc;
  5281. if (conf == NULL)
  5282. return -EIO;
  5283. if (priv->vif != vif) {
  5284. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5285. return 0;
  5286. }
  5287. /* handle this temporarily here */
  5288. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5289. conf->changed & IEEE80211_IFCC_BEACON) {
  5290. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5291. if (!beacon)
  5292. return -ENOMEM;
  5293. mutex_lock(&priv->mutex);
  5294. rc = iwl3945_mac_beacon_update(hw, beacon);
  5295. mutex_unlock(&priv->mutex);
  5296. if (rc)
  5297. return rc;
  5298. }
  5299. if (!iwl_is_alive(priv))
  5300. return -EAGAIN;
  5301. mutex_lock(&priv->mutex);
  5302. if (conf->bssid)
  5303. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5304. /*
  5305. * very dubious code was here; the probe filtering flag is never set:
  5306. *
  5307. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5308. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5309. */
  5310. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5311. if (!conf->bssid) {
  5312. conf->bssid = priv->mac_addr;
  5313. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5314. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5315. conf->bssid);
  5316. }
  5317. if (priv->ibss_beacon)
  5318. dev_kfree_skb(priv->ibss_beacon);
  5319. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5320. }
  5321. if (iwl_is_rfkill(priv))
  5322. goto done;
  5323. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5324. !is_multicast_ether_addr(conf->bssid)) {
  5325. /* If there is currently a HW scan going on in the background
  5326. * then we need to cancel it else the RXON below will fail. */
  5327. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5328. IWL_WARN(priv, "Aborted scan still in progress "
  5329. "after 100ms\n");
  5330. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5331. mutex_unlock(&priv->mutex);
  5332. return -EAGAIN;
  5333. }
  5334. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5335. /* TODO: Audit driver for usage of these members and see
  5336. * if mac80211 deprecates them (priv->bssid looks like it
  5337. * shouldn't be there, but I haven't scanned the IBSS code
  5338. * to verify) - jpk */
  5339. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5340. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5341. iwl3945_config_ap(priv);
  5342. else {
  5343. rc = iwl3945_commit_rxon(priv);
  5344. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5345. iwl3945_add_station(priv,
  5346. priv->active39_rxon.bssid_addr, 1, 0);
  5347. }
  5348. } else {
  5349. iwl3945_scan_cancel_timeout(priv, 100);
  5350. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5351. iwl3945_commit_rxon(priv);
  5352. }
  5353. done:
  5354. IWL_DEBUG_MAC80211("leave\n");
  5355. mutex_unlock(&priv->mutex);
  5356. return 0;
  5357. }
  5358. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5359. unsigned int changed_flags,
  5360. unsigned int *total_flags,
  5361. int mc_count, struct dev_addr_list *mc_list)
  5362. {
  5363. struct iwl_priv *priv = hw->priv;
  5364. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5365. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5366. changed_flags, *total_flags);
  5367. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5368. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5369. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5370. else
  5371. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5372. }
  5373. if (changed_flags & FIF_ALLMULTI) {
  5374. if (*total_flags & FIF_ALLMULTI)
  5375. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5376. else
  5377. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5378. }
  5379. if (changed_flags & FIF_CONTROL) {
  5380. if (*total_flags & FIF_CONTROL)
  5381. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5382. else
  5383. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5384. }
  5385. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5386. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5387. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5388. else
  5389. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5390. }
  5391. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5392. * since mac80211 will call ieee80211_hw_config immediately.
  5393. * (mc_list is not supported at this time). Otherwise, we need to
  5394. * queue a background iwl_commit_rxon work.
  5395. */
  5396. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5397. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5398. }
  5399. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5400. struct ieee80211_if_init_conf *conf)
  5401. {
  5402. struct iwl_priv *priv = hw->priv;
  5403. IWL_DEBUG_MAC80211("enter\n");
  5404. mutex_lock(&priv->mutex);
  5405. if (iwl_is_ready_rf(priv)) {
  5406. iwl3945_scan_cancel_timeout(priv, 100);
  5407. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5408. iwl3945_commit_rxon(priv);
  5409. }
  5410. if (priv->vif == conf->vif) {
  5411. priv->vif = NULL;
  5412. memset(priv->bssid, 0, ETH_ALEN);
  5413. }
  5414. mutex_unlock(&priv->mutex);
  5415. IWL_DEBUG_MAC80211("leave\n");
  5416. }
  5417. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5418. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5419. struct ieee80211_vif *vif,
  5420. struct ieee80211_bss_conf *bss_conf,
  5421. u32 changes)
  5422. {
  5423. struct iwl_priv *priv = hw->priv;
  5424. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5425. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5426. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5427. bss_conf->use_short_preamble);
  5428. if (bss_conf->use_short_preamble)
  5429. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5430. else
  5431. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5432. }
  5433. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5434. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5435. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5436. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5437. else
  5438. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5439. }
  5440. if (changes & BSS_CHANGED_ASSOC) {
  5441. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5442. /* This should never happen as this function should
  5443. * never be called from interrupt context. */
  5444. if (WARN_ON_ONCE(in_interrupt()))
  5445. return;
  5446. if (bss_conf->assoc) {
  5447. priv->assoc_id = bss_conf->aid;
  5448. priv->beacon_int = bss_conf->beacon_int;
  5449. priv->timestamp = bss_conf->timestamp;
  5450. priv->assoc_capability = bss_conf->assoc_capability;
  5451. priv->next_scan_jiffies = jiffies +
  5452. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5453. mutex_lock(&priv->mutex);
  5454. iwl3945_post_associate(priv);
  5455. mutex_unlock(&priv->mutex);
  5456. } else {
  5457. priv->assoc_id = 0;
  5458. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5459. }
  5460. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5461. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5462. iwl3945_send_rxon_assoc(priv);
  5463. }
  5464. }
  5465. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5466. {
  5467. int rc = 0;
  5468. unsigned long flags;
  5469. struct iwl_priv *priv = hw->priv;
  5470. DECLARE_SSID_BUF(ssid_buf);
  5471. IWL_DEBUG_MAC80211("enter\n");
  5472. mutex_lock(&priv->mutex);
  5473. spin_lock_irqsave(&priv->lock, flags);
  5474. if (!iwl_is_ready_rf(priv)) {
  5475. rc = -EIO;
  5476. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5477. goto out_unlock;
  5478. }
  5479. /* we don't schedule scan within next_scan_jiffies period */
  5480. if (priv->next_scan_jiffies &&
  5481. time_after(priv->next_scan_jiffies, jiffies)) {
  5482. rc = -EAGAIN;
  5483. goto out_unlock;
  5484. }
  5485. /* if we just finished scan ask for delay for a broadcast scan */
  5486. if ((len == 0) && priv->last_scan_jiffies &&
  5487. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5488. jiffies)) {
  5489. rc = -EAGAIN;
  5490. goto out_unlock;
  5491. }
  5492. if (len) {
  5493. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5494. print_ssid(ssid_buf, ssid, len), (int)len);
  5495. priv->one_direct_scan = 1;
  5496. priv->direct_ssid_len = (u8)
  5497. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5498. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5499. } else
  5500. priv->one_direct_scan = 0;
  5501. rc = iwl3945_scan_initiate(priv);
  5502. IWL_DEBUG_MAC80211("leave\n");
  5503. out_unlock:
  5504. spin_unlock_irqrestore(&priv->lock, flags);
  5505. mutex_unlock(&priv->mutex);
  5506. return rc;
  5507. }
  5508. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5509. const u8 *local_addr, const u8 *addr,
  5510. struct ieee80211_key_conf *key)
  5511. {
  5512. struct iwl_priv *priv = hw->priv;
  5513. int rc = 0;
  5514. u8 sta_id;
  5515. IWL_DEBUG_MAC80211("enter\n");
  5516. if (iwl3945_mod_params.sw_crypto) {
  5517. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5518. return -EOPNOTSUPP;
  5519. }
  5520. if (is_zero_ether_addr(addr))
  5521. /* only support pairwise keys */
  5522. return -EOPNOTSUPP;
  5523. sta_id = iwl3945_hw_find_station(priv, addr);
  5524. if (sta_id == IWL_INVALID_STATION) {
  5525. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5526. addr);
  5527. return -EINVAL;
  5528. }
  5529. mutex_lock(&priv->mutex);
  5530. iwl3945_scan_cancel_timeout(priv, 100);
  5531. switch (cmd) {
  5532. case SET_KEY:
  5533. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5534. if (!rc) {
  5535. iwl3945_set_rxon_hwcrypto(priv, 1);
  5536. iwl3945_commit_rxon(priv);
  5537. key->hw_key_idx = sta_id;
  5538. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5539. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5540. }
  5541. break;
  5542. case DISABLE_KEY:
  5543. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5544. if (!rc) {
  5545. iwl3945_set_rxon_hwcrypto(priv, 0);
  5546. iwl3945_commit_rxon(priv);
  5547. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5548. }
  5549. break;
  5550. default:
  5551. rc = -EINVAL;
  5552. }
  5553. IWL_DEBUG_MAC80211("leave\n");
  5554. mutex_unlock(&priv->mutex);
  5555. return rc;
  5556. }
  5557. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5558. const struct ieee80211_tx_queue_params *params)
  5559. {
  5560. struct iwl_priv *priv = hw->priv;
  5561. unsigned long flags;
  5562. int q;
  5563. IWL_DEBUG_MAC80211("enter\n");
  5564. if (!iwl_is_ready_rf(priv)) {
  5565. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5566. return -EIO;
  5567. }
  5568. if (queue >= AC_NUM) {
  5569. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5570. return 0;
  5571. }
  5572. q = AC_NUM - 1 - queue;
  5573. spin_lock_irqsave(&priv->lock, flags);
  5574. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5575. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5576. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5577. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5578. cpu_to_le16((params->txop * 32));
  5579. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5580. priv->qos_data.qos_active = 1;
  5581. spin_unlock_irqrestore(&priv->lock, flags);
  5582. mutex_lock(&priv->mutex);
  5583. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5584. iwl3945_activate_qos(priv, 1);
  5585. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5586. iwl3945_activate_qos(priv, 0);
  5587. mutex_unlock(&priv->mutex);
  5588. IWL_DEBUG_MAC80211("leave\n");
  5589. return 0;
  5590. }
  5591. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5592. struct ieee80211_tx_queue_stats *stats)
  5593. {
  5594. struct iwl_priv *priv = hw->priv;
  5595. int i, avail;
  5596. struct iwl3945_tx_queue *txq;
  5597. struct iwl_queue *q;
  5598. unsigned long flags;
  5599. IWL_DEBUG_MAC80211("enter\n");
  5600. if (!iwl_is_ready_rf(priv)) {
  5601. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5602. return -EIO;
  5603. }
  5604. spin_lock_irqsave(&priv->lock, flags);
  5605. for (i = 0; i < AC_NUM; i++) {
  5606. txq = &priv->txq39[i];
  5607. q = &txq->q;
  5608. avail = iwl_queue_space(q);
  5609. stats[i].len = q->n_window - avail;
  5610. stats[i].limit = q->n_window - q->high_mark;
  5611. stats[i].count = q->n_window;
  5612. }
  5613. spin_unlock_irqrestore(&priv->lock, flags);
  5614. IWL_DEBUG_MAC80211("leave\n");
  5615. return 0;
  5616. }
  5617. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5618. {
  5619. struct iwl_priv *priv = hw->priv;
  5620. unsigned long flags;
  5621. mutex_lock(&priv->mutex);
  5622. IWL_DEBUG_MAC80211("enter\n");
  5623. iwl_reset_qos(priv);
  5624. spin_lock_irqsave(&priv->lock, flags);
  5625. priv->assoc_id = 0;
  5626. priv->assoc_capability = 0;
  5627. priv->call_post_assoc_from_beacon = 0;
  5628. /* new association get rid of ibss beacon skb */
  5629. if (priv->ibss_beacon)
  5630. dev_kfree_skb(priv->ibss_beacon);
  5631. priv->ibss_beacon = NULL;
  5632. priv->beacon_int = priv->hw->conf.beacon_int;
  5633. priv->timestamp = 0;
  5634. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5635. priv->beacon_int = 0;
  5636. spin_unlock_irqrestore(&priv->lock, flags);
  5637. if (!iwl_is_ready_rf(priv)) {
  5638. IWL_DEBUG_MAC80211("leave - not ready\n");
  5639. mutex_unlock(&priv->mutex);
  5640. return;
  5641. }
  5642. /* we are restarting association process
  5643. * clear RXON_FILTER_ASSOC_MSK bit
  5644. */
  5645. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5646. iwl3945_scan_cancel_timeout(priv, 100);
  5647. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5648. iwl3945_commit_rxon(priv);
  5649. }
  5650. /* Per mac80211.h: This is only used in IBSS mode... */
  5651. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5652. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5653. mutex_unlock(&priv->mutex);
  5654. return;
  5655. }
  5656. iwl3945_set_rate(priv);
  5657. mutex_unlock(&priv->mutex);
  5658. IWL_DEBUG_MAC80211("leave\n");
  5659. }
  5660. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5661. {
  5662. struct iwl_priv *priv = hw->priv;
  5663. unsigned long flags;
  5664. IWL_DEBUG_MAC80211("enter\n");
  5665. if (!iwl_is_ready_rf(priv)) {
  5666. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5667. return -EIO;
  5668. }
  5669. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5670. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5671. return -EIO;
  5672. }
  5673. spin_lock_irqsave(&priv->lock, flags);
  5674. if (priv->ibss_beacon)
  5675. dev_kfree_skb(priv->ibss_beacon);
  5676. priv->ibss_beacon = skb;
  5677. priv->assoc_id = 0;
  5678. IWL_DEBUG_MAC80211("leave\n");
  5679. spin_unlock_irqrestore(&priv->lock, flags);
  5680. iwl_reset_qos(priv);
  5681. iwl3945_post_associate(priv);
  5682. return 0;
  5683. }
  5684. /*****************************************************************************
  5685. *
  5686. * sysfs attributes
  5687. *
  5688. *****************************************************************************/
  5689. #ifdef CONFIG_IWL3945_DEBUG
  5690. /*
  5691. * The following adds a new attribute to the sysfs representation
  5692. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5693. * used for controlling the debug level.
  5694. *
  5695. * See the level definitions in iwl for details.
  5696. */
  5697. static ssize_t show_debug_level(struct device *d,
  5698. struct device_attribute *attr, char *buf)
  5699. {
  5700. struct iwl_priv *priv = d->driver_data;
  5701. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5702. }
  5703. static ssize_t store_debug_level(struct device *d,
  5704. struct device_attribute *attr,
  5705. const char *buf, size_t count)
  5706. {
  5707. struct iwl_priv *priv = d->driver_data;
  5708. unsigned long val;
  5709. int ret;
  5710. ret = strict_strtoul(buf, 0, &val);
  5711. if (ret)
  5712. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5713. else
  5714. priv->debug_level = val;
  5715. return strnlen(buf, count);
  5716. }
  5717. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5718. show_debug_level, store_debug_level);
  5719. #endif /* CONFIG_IWL3945_DEBUG */
  5720. static ssize_t show_temperature(struct device *d,
  5721. struct device_attribute *attr, char *buf)
  5722. {
  5723. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5724. if (!iwl_is_alive(priv))
  5725. return -EAGAIN;
  5726. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5727. }
  5728. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5729. static ssize_t show_tx_power(struct device *d,
  5730. struct device_attribute *attr, char *buf)
  5731. {
  5732. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5733. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5734. }
  5735. static ssize_t store_tx_power(struct device *d,
  5736. struct device_attribute *attr,
  5737. const char *buf, size_t count)
  5738. {
  5739. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5740. char *p = (char *)buf;
  5741. u32 val;
  5742. val = simple_strtoul(p, &p, 10);
  5743. if (p == buf)
  5744. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5745. else
  5746. iwl3945_hw_reg_set_txpower(priv, val);
  5747. return count;
  5748. }
  5749. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5750. static ssize_t show_flags(struct device *d,
  5751. struct device_attribute *attr, char *buf)
  5752. {
  5753. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5754. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5755. }
  5756. static ssize_t store_flags(struct device *d,
  5757. struct device_attribute *attr,
  5758. const char *buf, size_t count)
  5759. {
  5760. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5761. u32 flags = simple_strtoul(buf, NULL, 0);
  5762. mutex_lock(&priv->mutex);
  5763. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5764. /* Cancel any currently running scans... */
  5765. if (iwl3945_scan_cancel_timeout(priv, 100))
  5766. IWL_WARN(priv, "Could not cancel scan.\n");
  5767. else {
  5768. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5769. flags);
  5770. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5771. iwl3945_commit_rxon(priv);
  5772. }
  5773. }
  5774. mutex_unlock(&priv->mutex);
  5775. return count;
  5776. }
  5777. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5778. static ssize_t show_filter_flags(struct device *d,
  5779. struct device_attribute *attr, char *buf)
  5780. {
  5781. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5782. return sprintf(buf, "0x%04X\n",
  5783. le32_to_cpu(priv->active39_rxon.filter_flags));
  5784. }
  5785. static ssize_t store_filter_flags(struct device *d,
  5786. struct device_attribute *attr,
  5787. const char *buf, size_t count)
  5788. {
  5789. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5790. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5791. mutex_lock(&priv->mutex);
  5792. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5793. /* Cancel any currently running scans... */
  5794. if (iwl3945_scan_cancel_timeout(priv, 100))
  5795. IWL_WARN(priv, "Could not cancel scan.\n");
  5796. else {
  5797. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5798. "0x%04X\n", filter_flags);
  5799. priv->staging39_rxon.filter_flags =
  5800. cpu_to_le32(filter_flags);
  5801. iwl3945_commit_rxon(priv);
  5802. }
  5803. }
  5804. mutex_unlock(&priv->mutex);
  5805. return count;
  5806. }
  5807. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5808. store_filter_flags);
  5809. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5810. static ssize_t show_measurement(struct device *d,
  5811. struct device_attribute *attr, char *buf)
  5812. {
  5813. struct iwl_priv *priv = dev_get_drvdata(d);
  5814. struct iwl_spectrum_notification measure_report;
  5815. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5816. u8 *data = (u8 *)&measure_report;
  5817. unsigned long flags;
  5818. spin_lock_irqsave(&priv->lock, flags);
  5819. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5820. spin_unlock_irqrestore(&priv->lock, flags);
  5821. return 0;
  5822. }
  5823. memcpy(&measure_report, &priv->measure_report, size);
  5824. priv->measurement_status = 0;
  5825. spin_unlock_irqrestore(&priv->lock, flags);
  5826. while (size && (PAGE_SIZE - len)) {
  5827. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5828. PAGE_SIZE - len, 1);
  5829. len = strlen(buf);
  5830. if (PAGE_SIZE - len)
  5831. buf[len++] = '\n';
  5832. ofs += 16;
  5833. size -= min(size, 16U);
  5834. }
  5835. return len;
  5836. }
  5837. static ssize_t store_measurement(struct device *d,
  5838. struct device_attribute *attr,
  5839. const char *buf, size_t count)
  5840. {
  5841. struct iwl_priv *priv = dev_get_drvdata(d);
  5842. struct ieee80211_measurement_params params = {
  5843. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5844. .start_time = cpu_to_le64(priv->last_tsf),
  5845. .duration = cpu_to_le16(1),
  5846. };
  5847. u8 type = IWL_MEASURE_BASIC;
  5848. u8 buffer[32];
  5849. u8 channel;
  5850. if (count) {
  5851. char *p = buffer;
  5852. strncpy(buffer, buf, min(sizeof(buffer), count));
  5853. channel = simple_strtoul(p, NULL, 0);
  5854. if (channel)
  5855. params.channel = channel;
  5856. p = buffer;
  5857. while (*p && *p != ' ')
  5858. p++;
  5859. if (*p)
  5860. type = simple_strtoul(p + 1, NULL, 0);
  5861. }
  5862. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5863. "channel %d (for '%s')\n", type, params.channel, buf);
  5864. iwl3945_get_measurement(priv, &params, type);
  5865. return count;
  5866. }
  5867. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5868. show_measurement, store_measurement);
  5869. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5870. static ssize_t store_retry_rate(struct device *d,
  5871. struct device_attribute *attr,
  5872. const char *buf, size_t count)
  5873. {
  5874. struct iwl_priv *priv = dev_get_drvdata(d);
  5875. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5876. if (priv->retry_rate <= 0)
  5877. priv->retry_rate = 1;
  5878. return count;
  5879. }
  5880. static ssize_t show_retry_rate(struct device *d,
  5881. struct device_attribute *attr, char *buf)
  5882. {
  5883. struct iwl_priv *priv = dev_get_drvdata(d);
  5884. return sprintf(buf, "%d", priv->retry_rate);
  5885. }
  5886. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5887. store_retry_rate);
  5888. static ssize_t store_power_level(struct device *d,
  5889. struct device_attribute *attr,
  5890. const char *buf, size_t count)
  5891. {
  5892. struct iwl_priv *priv = dev_get_drvdata(d);
  5893. int rc;
  5894. int mode;
  5895. mode = simple_strtoul(buf, NULL, 0);
  5896. mutex_lock(&priv->mutex);
  5897. if (!iwl_is_ready(priv)) {
  5898. rc = -EAGAIN;
  5899. goto out;
  5900. }
  5901. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5902. (mode == IWL39_POWER_AC))
  5903. mode = IWL39_POWER_AC;
  5904. else
  5905. mode |= IWL_POWER_ENABLED;
  5906. if (mode != priv->power_mode) {
  5907. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5908. if (rc) {
  5909. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5910. goto out;
  5911. }
  5912. priv->power_mode = mode;
  5913. }
  5914. rc = count;
  5915. out:
  5916. mutex_unlock(&priv->mutex);
  5917. return rc;
  5918. }
  5919. #define MAX_WX_STRING 80
  5920. /* Values are in microsecond */
  5921. static const s32 timeout_duration[] = {
  5922. 350000,
  5923. 250000,
  5924. 75000,
  5925. 37000,
  5926. 25000,
  5927. };
  5928. static const s32 period_duration[] = {
  5929. 400000,
  5930. 700000,
  5931. 1000000,
  5932. 1000000,
  5933. 1000000
  5934. };
  5935. static ssize_t show_power_level(struct device *d,
  5936. struct device_attribute *attr, char *buf)
  5937. {
  5938. struct iwl_priv *priv = dev_get_drvdata(d);
  5939. int level = IWL_POWER_LEVEL(priv->power_mode);
  5940. char *p = buf;
  5941. p += sprintf(p, "%d ", level);
  5942. switch (level) {
  5943. case IWL_POWER_MODE_CAM:
  5944. case IWL39_POWER_AC:
  5945. p += sprintf(p, "(AC)");
  5946. break;
  5947. case IWL39_POWER_BATTERY:
  5948. p += sprintf(p, "(BATTERY)");
  5949. break;
  5950. default:
  5951. p += sprintf(p,
  5952. "(Timeout %dms, Period %dms)",
  5953. timeout_duration[level - 1] / 1000,
  5954. period_duration[level - 1] / 1000);
  5955. }
  5956. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5957. p += sprintf(p, " OFF\n");
  5958. else
  5959. p += sprintf(p, " \n");
  5960. return p - buf + 1;
  5961. }
  5962. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5963. store_power_level);
  5964. static ssize_t show_channels(struct device *d,
  5965. struct device_attribute *attr, char *buf)
  5966. {
  5967. /* all this shit doesn't belong into sysfs anyway */
  5968. return 0;
  5969. }
  5970. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5971. static ssize_t show_statistics(struct device *d,
  5972. struct device_attribute *attr, char *buf)
  5973. {
  5974. struct iwl_priv *priv = dev_get_drvdata(d);
  5975. u32 size = sizeof(struct iwl3945_notif_statistics);
  5976. u32 len = 0, ofs = 0;
  5977. u8 *data = (u8 *)&priv->statistics_39;
  5978. int rc = 0;
  5979. if (!iwl_is_alive(priv))
  5980. return -EAGAIN;
  5981. mutex_lock(&priv->mutex);
  5982. rc = iwl3945_send_statistics_request(priv);
  5983. mutex_unlock(&priv->mutex);
  5984. if (rc) {
  5985. len = sprintf(buf,
  5986. "Error sending statistics request: 0x%08X\n", rc);
  5987. return len;
  5988. }
  5989. while (size && (PAGE_SIZE - len)) {
  5990. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5991. PAGE_SIZE - len, 1);
  5992. len = strlen(buf);
  5993. if (PAGE_SIZE - len)
  5994. buf[len++] = '\n';
  5995. ofs += 16;
  5996. size -= min(size, 16U);
  5997. }
  5998. return len;
  5999. }
  6000. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6001. static ssize_t show_antenna(struct device *d,
  6002. struct device_attribute *attr, char *buf)
  6003. {
  6004. struct iwl_priv *priv = dev_get_drvdata(d);
  6005. if (!iwl_is_alive(priv))
  6006. return -EAGAIN;
  6007. return sprintf(buf, "%d\n", priv->antenna);
  6008. }
  6009. static ssize_t store_antenna(struct device *d,
  6010. struct device_attribute *attr,
  6011. const char *buf, size_t count)
  6012. {
  6013. int ant;
  6014. struct iwl_priv *priv = dev_get_drvdata(d);
  6015. if (count == 0)
  6016. return 0;
  6017. if (sscanf(buf, "%1i", &ant) != 1) {
  6018. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6019. return count;
  6020. }
  6021. if ((ant >= 0) && (ant <= 2)) {
  6022. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6023. priv->antenna = (enum iwl3945_antenna)ant;
  6024. } else
  6025. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6026. return count;
  6027. }
  6028. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6029. static ssize_t show_status(struct device *d,
  6030. struct device_attribute *attr, char *buf)
  6031. {
  6032. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6033. if (!iwl_is_alive(priv))
  6034. return -EAGAIN;
  6035. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6036. }
  6037. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6038. static ssize_t dump_error_log(struct device *d,
  6039. struct device_attribute *attr,
  6040. const char *buf, size_t count)
  6041. {
  6042. char *p = (char *)buf;
  6043. if (p[0] == '1')
  6044. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  6045. return strnlen(buf, count);
  6046. }
  6047. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6048. static ssize_t dump_event_log(struct device *d,
  6049. struct device_attribute *attr,
  6050. const char *buf, size_t count)
  6051. {
  6052. char *p = (char *)buf;
  6053. if (p[0] == '1')
  6054. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  6055. return strnlen(buf, count);
  6056. }
  6057. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6058. /*****************************************************************************
  6059. *
  6060. * driver setup and tear down
  6061. *
  6062. *****************************************************************************/
  6063. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  6064. {
  6065. priv->workqueue = create_workqueue(DRV_NAME);
  6066. init_waitqueue_head(&priv->wait_command_queue);
  6067. INIT_WORK(&priv->up, iwl3945_bg_up);
  6068. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6069. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6070. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6071. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6072. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6073. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6074. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6075. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6076. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6077. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6078. iwl3945_hw_setup_deferred_work(priv);
  6079. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6080. iwl3945_irq_tasklet, (unsigned long)priv);
  6081. }
  6082. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  6083. {
  6084. iwl3945_hw_cancel_deferred_work(priv);
  6085. cancel_delayed_work_sync(&priv->init_alive_start);
  6086. cancel_delayed_work(&priv->scan_check);
  6087. cancel_delayed_work(&priv->alive_start);
  6088. cancel_work_sync(&priv->beacon_update);
  6089. }
  6090. static struct attribute *iwl3945_sysfs_entries[] = {
  6091. &dev_attr_antenna.attr,
  6092. &dev_attr_channels.attr,
  6093. &dev_attr_dump_errors.attr,
  6094. &dev_attr_dump_events.attr,
  6095. &dev_attr_flags.attr,
  6096. &dev_attr_filter_flags.attr,
  6097. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6098. &dev_attr_measurement.attr,
  6099. #endif
  6100. &dev_attr_power_level.attr,
  6101. &dev_attr_retry_rate.attr,
  6102. &dev_attr_statistics.attr,
  6103. &dev_attr_status.attr,
  6104. &dev_attr_temperature.attr,
  6105. &dev_attr_tx_power.attr,
  6106. #ifdef CONFIG_IWL3945_DEBUG
  6107. &dev_attr_debug_level.attr,
  6108. #endif
  6109. NULL
  6110. };
  6111. static struct attribute_group iwl3945_attribute_group = {
  6112. .name = NULL, /* put in device directory */
  6113. .attrs = iwl3945_sysfs_entries,
  6114. };
  6115. static struct ieee80211_ops iwl3945_hw_ops = {
  6116. .tx = iwl3945_mac_tx,
  6117. .start = iwl3945_mac_start,
  6118. .stop = iwl3945_mac_stop,
  6119. .add_interface = iwl3945_mac_add_interface,
  6120. .remove_interface = iwl3945_mac_remove_interface,
  6121. .config = iwl3945_mac_config,
  6122. .config_interface = iwl3945_mac_config_interface,
  6123. .configure_filter = iwl3945_configure_filter,
  6124. .set_key = iwl3945_mac_set_key,
  6125. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6126. .conf_tx = iwl3945_mac_conf_tx,
  6127. .reset_tsf = iwl3945_mac_reset_tsf,
  6128. .bss_info_changed = iwl3945_bss_info_changed,
  6129. .hw_scan = iwl3945_mac_hw_scan
  6130. };
  6131. int iwl3945_init_drv(struct iwl_priv *priv)
  6132. {
  6133. int ret;
  6134. priv->retry_rate = 1;
  6135. priv->ibss_beacon = NULL;
  6136. spin_lock_init(&priv->lock);
  6137. spin_lock_init(&priv->power_data.lock);
  6138. spin_lock_init(&priv->sta_lock);
  6139. spin_lock_init(&priv->hcmd_lock);
  6140. INIT_LIST_HEAD(&priv->free_frames);
  6141. mutex_init(&priv->mutex);
  6142. /* Clear the driver's (not device's) station table */
  6143. iwl3945_clear_stations_table(priv);
  6144. priv->data_retry_limit = -1;
  6145. priv->ieee_channels = NULL;
  6146. priv->ieee_rates = NULL;
  6147. priv->band = IEEE80211_BAND_2GHZ;
  6148. priv->iw_mode = NL80211_IFTYPE_STATION;
  6149. iwl_reset_qos(priv);
  6150. priv->qos_data.qos_active = 0;
  6151. priv->qos_data.qos_cap.val = 0;
  6152. priv->rates_mask = IWL_RATES_MASK;
  6153. /* If power management is turned on, default to AC mode */
  6154. priv->power_mode = IWL_POWER_AC;
  6155. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6156. ret = iwl3945_init_channel_map(priv);
  6157. if (ret) {
  6158. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  6159. goto err;
  6160. }
  6161. ret = iwl3945_init_geos(priv);
  6162. if (ret) {
  6163. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  6164. goto err_free_channel_map;
  6165. }
  6166. return 0;
  6167. err_free_channel_map:
  6168. iwl3945_free_channel_map(priv);
  6169. err:
  6170. return ret;
  6171. }
  6172. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6173. {
  6174. int err = 0;
  6175. struct iwl_priv *priv;
  6176. struct ieee80211_hw *hw;
  6177. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6178. unsigned long flags;
  6179. /***********************
  6180. * 1. Allocating HW data
  6181. * ********************/
  6182. /* mac80211 allocates memory for this device instance, including
  6183. * space for this driver's private structure */
  6184. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  6185. if (hw == NULL) {
  6186. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6187. err = -ENOMEM;
  6188. goto out;
  6189. }
  6190. priv = hw->priv;
  6191. SET_IEEE80211_DEV(hw, &pdev->dev);
  6192. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  6193. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  6194. IWL_ERR(priv,
  6195. "invalid queues_num, should be between %d and %d\n",
  6196. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6197. err = -EINVAL;
  6198. goto out;
  6199. }
  6200. /*
  6201. * Disabling hardware scan means that mac80211 will perform scans
  6202. * "the hard way", rather than using device's scan.
  6203. */
  6204. if (iwl3945_mod_params.disable_hw_scan) {
  6205. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6206. iwl3945_hw_ops.hw_scan = NULL;
  6207. }
  6208. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6209. priv->cfg = cfg;
  6210. priv->pci_dev = pdev;
  6211. #ifdef CONFIG_IWL3945_DEBUG
  6212. priv->debug_level = iwl3945_mod_params.debug;
  6213. atomic_set(&priv->restrict_refcnt, 0);
  6214. #endif
  6215. hw->rate_control_algorithm = "iwl-3945-rs";
  6216. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6217. /* Select antenna (may be helpful if only one antenna is connected) */
  6218. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  6219. /* Tell mac80211 our characteristics */
  6220. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6221. IEEE80211_HW_NOISE_DBM;
  6222. hw->wiphy->interface_modes =
  6223. BIT(NL80211_IFTYPE_STATION) |
  6224. BIT(NL80211_IFTYPE_ADHOC);
  6225. hw->wiphy->fw_handles_regulatory = true;
  6226. /* 4 EDCA QOS priorities */
  6227. hw->queues = 4;
  6228. /***************************
  6229. * 2. Initializing PCI bus
  6230. * *************************/
  6231. if (pci_enable_device(pdev)) {
  6232. err = -ENODEV;
  6233. goto out_ieee80211_free_hw;
  6234. }
  6235. pci_set_master(pdev);
  6236. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6237. if (!err)
  6238. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6239. if (err) {
  6240. IWL_WARN(priv, "No suitable DMA available.\n");
  6241. goto out_pci_disable_device;
  6242. }
  6243. pci_set_drvdata(pdev, priv);
  6244. err = pci_request_regions(pdev, DRV_NAME);
  6245. if (err)
  6246. goto out_pci_disable_device;
  6247. /***********************
  6248. * 3. Read REV Register
  6249. * ********************/
  6250. priv->hw_base = pci_iomap(pdev, 0, 0);
  6251. if (!priv->hw_base) {
  6252. err = -ENODEV;
  6253. goto out_pci_release_regions;
  6254. }
  6255. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6256. (unsigned long long) pci_resource_len(pdev, 0));
  6257. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6258. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6259. * PCI Tx retries from interfering with C3 CPU state */
  6260. pci_write_config_byte(pdev, 0x41, 0x00);
  6261. /* amp init */
  6262. err = priv->cfg->ops->lib->apm_ops.init(priv);
  6263. if (err < 0) {
  6264. IWL_DEBUG_INFO("Failed to init APMG\n");
  6265. goto out_iounmap;
  6266. }
  6267. /***********************
  6268. * 4. Read EEPROM
  6269. * ********************/
  6270. /* Read the EEPROM */
  6271. err = iwl3945_eeprom_init(priv);
  6272. if (err) {
  6273. IWL_ERR(priv, "Unable to init EEPROM\n");
  6274. goto out_remove_sysfs;
  6275. }
  6276. /* MAC Address location in EEPROM same for 3945/4965 */
  6277. get_eeprom_mac(priv, priv->mac_addr);
  6278. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6279. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6280. /***********************
  6281. * 5. Setup HW Constants
  6282. * ********************/
  6283. /* Device-specific setup */
  6284. if (iwl3945_hw_set_hw_params(priv)) {
  6285. IWL_ERR(priv, "failed to set hw settings\n");
  6286. goto out_iounmap;
  6287. }
  6288. /***********************
  6289. * 6. Setup priv
  6290. * ********************/
  6291. err = iwl3945_init_drv(priv);
  6292. if (err) {
  6293. IWL_ERR(priv, "initializing driver failed\n");
  6294. goto out_free_geos;
  6295. }
  6296. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6297. priv->cfg->name);
  6298. /***********************************
  6299. * 7. Initialize Module Parameters
  6300. * **********************************/
  6301. /* Initialize module parameter values here */
  6302. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6303. if (iwl3945_mod_params.disable) {
  6304. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6305. IWL_DEBUG_INFO("Radio disabled.\n");
  6306. }
  6307. /***********************
  6308. * 8. Setup Services
  6309. * ********************/
  6310. spin_lock_irqsave(&priv->lock, flags);
  6311. iwl3945_disable_interrupts(priv);
  6312. spin_unlock_irqrestore(&priv->lock, flags);
  6313. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6314. if (err) {
  6315. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  6316. goto out_release_irq;
  6317. }
  6318. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6319. iwl3945_setup_deferred_work(priv);
  6320. iwl3945_setup_rx_handlers(priv);
  6321. /***********************
  6322. * 9. Conclude
  6323. * ********************/
  6324. pci_save_state(pdev);
  6325. pci_disable_device(pdev);
  6326. /*********************************
  6327. * 10. Setup and Register mac80211
  6328. * *******************************/
  6329. err = ieee80211_register_hw(priv->hw);
  6330. if (err) {
  6331. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  6332. goto out_remove_sysfs;
  6333. }
  6334. priv->hw->conf.beacon_int = 100;
  6335. priv->mac80211_registered = 1;
  6336. err = iwl3945_rfkill_init(priv);
  6337. if (err)
  6338. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  6339. "Ignoring error: %d\n", err);
  6340. return 0;
  6341. out_remove_sysfs:
  6342. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6343. out_free_geos:
  6344. iwl3945_free_geos(priv);
  6345. out_release_irq:
  6346. destroy_workqueue(priv->workqueue);
  6347. priv->workqueue = NULL;
  6348. iwl3945_unset_hw_params(priv);
  6349. out_iounmap:
  6350. pci_iounmap(pdev, priv->hw_base);
  6351. out_pci_release_regions:
  6352. pci_release_regions(pdev);
  6353. out_pci_disable_device:
  6354. pci_disable_device(pdev);
  6355. pci_set_drvdata(pdev, NULL);
  6356. out_ieee80211_free_hw:
  6357. ieee80211_free_hw(priv->hw);
  6358. out:
  6359. return err;
  6360. }
  6361. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6362. {
  6363. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6364. unsigned long flags;
  6365. if (!priv)
  6366. return;
  6367. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6368. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6369. if (priv->mac80211_registered) {
  6370. ieee80211_unregister_hw(priv->hw);
  6371. priv->mac80211_registered = 0;
  6372. } else {
  6373. iwl3945_down(priv);
  6374. }
  6375. /* make sure we flush any pending irq or
  6376. * tasklet for the driver
  6377. */
  6378. spin_lock_irqsave(&priv->lock, flags);
  6379. iwl3945_disable_interrupts(priv);
  6380. spin_unlock_irqrestore(&priv->lock, flags);
  6381. iwl_synchronize_irq(priv);
  6382. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6383. iwl3945_rfkill_unregister(priv);
  6384. iwl3945_dealloc_ucode_pci(priv);
  6385. if (priv->rxq.bd)
  6386. iwl3945_rx_queue_free(priv, &priv->rxq);
  6387. iwl3945_hw_txq_ctx_free(priv);
  6388. iwl3945_unset_hw_params(priv);
  6389. iwl3945_clear_stations_table(priv);
  6390. /*netif_stop_queue(dev); */
  6391. flush_workqueue(priv->workqueue);
  6392. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6393. * priv->workqueue... so we can't take down the workqueue
  6394. * until now... */
  6395. destroy_workqueue(priv->workqueue);
  6396. priv->workqueue = NULL;
  6397. pci_iounmap(pdev, priv->hw_base);
  6398. pci_release_regions(pdev);
  6399. pci_disable_device(pdev);
  6400. pci_set_drvdata(pdev, NULL);
  6401. iwl3945_free_channel_map(priv);
  6402. iwl3945_free_geos(priv);
  6403. kfree(priv->scan39);
  6404. if (priv->ibss_beacon)
  6405. dev_kfree_skb(priv->ibss_beacon);
  6406. ieee80211_free_hw(priv->hw);
  6407. }
  6408. #ifdef CONFIG_PM
  6409. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6410. {
  6411. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6412. if (priv->is_open) {
  6413. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6414. iwl3945_mac_stop(priv->hw);
  6415. priv->is_open = 1;
  6416. }
  6417. pci_set_power_state(pdev, PCI_D3hot);
  6418. return 0;
  6419. }
  6420. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6421. {
  6422. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6423. pci_set_power_state(pdev, PCI_D0);
  6424. if (priv->is_open)
  6425. iwl3945_mac_start(priv->hw);
  6426. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6427. return 0;
  6428. }
  6429. #endif /* CONFIG_PM */
  6430. /*************** RFKILL FUNCTIONS **********/
  6431. #ifdef CONFIG_IWL3945_RFKILL
  6432. /* software rf-kill from user */
  6433. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6434. {
  6435. struct iwl_priv *priv = data;
  6436. int err = 0;
  6437. if (!priv->rfkill)
  6438. return 0;
  6439. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6440. return 0;
  6441. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6442. mutex_lock(&priv->mutex);
  6443. switch (state) {
  6444. case RFKILL_STATE_UNBLOCKED:
  6445. if (iwl_is_rfkill_hw(priv)) {
  6446. err = -EBUSY;
  6447. goto out_unlock;
  6448. }
  6449. iwl3945_radio_kill_sw(priv, 0);
  6450. break;
  6451. case RFKILL_STATE_SOFT_BLOCKED:
  6452. iwl3945_radio_kill_sw(priv, 1);
  6453. break;
  6454. default:
  6455. IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
  6456. break;
  6457. }
  6458. out_unlock:
  6459. mutex_unlock(&priv->mutex);
  6460. return err;
  6461. }
  6462. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6463. {
  6464. struct device *device = wiphy_dev(priv->hw->wiphy);
  6465. int ret = 0;
  6466. BUG_ON(device == NULL);
  6467. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6468. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6469. if (!priv->rfkill) {
  6470. IWL_ERR(priv, "Unable to allocate rfkill device.\n");
  6471. ret = -ENOMEM;
  6472. goto error;
  6473. }
  6474. priv->rfkill->name = priv->cfg->name;
  6475. priv->rfkill->data = priv;
  6476. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6477. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6478. priv->rfkill->user_claim_unsupported = 1;
  6479. priv->rfkill->dev.class->suspend = NULL;
  6480. priv->rfkill->dev.class->resume = NULL;
  6481. ret = rfkill_register(priv->rfkill);
  6482. if (ret) {
  6483. IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
  6484. goto freed_rfkill;
  6485. }
  6486. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6487. return ret;
  6488. freed_rfkill:
  6489. if (priv->rfkill != NULL)
  6490. rfkill_free(priv->rfkill);
  6491. priv->rfkill = NULL;
  6492. error:
  6493. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6494. return ret;
  6495. }
  6496. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6497. {
  6498. if (priv->rfkill)
  6499. rfkill_unregister(priv->rfkill);
  6500. priv->rfkill = NULL;
  6501. }
  6502. /* set rf-kill to the right state. */
  6503. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6504. {
  6505. if (!priv->rfkill)
  6506. return;
  6507. if (iwl_is_rfkill_hw(priv)) {
  6508. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6509. return;
  6510. }
  6511. if (!iwl_is_rfkill_sw(priv))
  6512. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6513. else
  6514. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6515. }
  6516. #endif
  6517. /*****************************************************************************
  6518. *
  6519. * driver and module entry point
  6520. *
  6521. *****************************************************************************/
  6522. static struct pci_driver iwl3945_driver = {
  6523. .name = DRV_NAME,
  6524. .id_table = iwl3945_hw_card_ids,
  6525. .probe = iwl3945_pci_probe,
  6526. .remove = __devexit_p(iwl3945_pci_remove),
  6527. #ifdef CONFIG_PM
  6528. .suspend = iwl3945_pci_suspend,
  6529. .resume = iwl3945_pci_resume,
  6530. #endif
  6531. };
  6532. static int __init iwl3945_init(void)
  6533. {
  6534. int ret;
  6535. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6536. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6537. ret = iwl3945_rate_control_register();
  6538. if (ret) {
  6539. printk(KERN_ERR DRV_NAME
  6540. "Unable to register rate control algorithm: %d\n", ret);
  6541. return ret;
  6542. }
  6543. ret = pci_register_driver(&iwl3945_driver);
  6544. if (ret) {
  6545. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6546. goto error_register;
  6547. }
  6548. return ret;
  6549. error_register:
  6550. iwl3945_rate_control_unregister();
  6551. return ret;
  6552. }
  6553. static void __exit iwl3945_exit(void)
  6554. {
  6555. pci_unregister_driver(&iwl3945_driver);
  6556. iwl3945_rate_control_unregister();
  6557. }
  6558. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6559. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  6560. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6561. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  6562. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6563. module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  6564. MODULE_PARM_DESC(hwcrypto,
  6565. "using hardware crypto engine (default 0 [software])\n");
  6566. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  6567. MODULE_PARM_DESC(debug, "debug output mask");
  6568. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  6569. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6570. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  6571. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6572. module_exit(iwl3945_exit);
  6573. module_init(iwl3945_init);