mpi2_ioc.h 64 KB

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  1. /*
  2. * Copyright (c) 2000-2009 LSI Corporation.
  3. *
  4. *
  5. * Name: mpi2_ioc.h
  6. * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
  7. * Creation Date: October 11, 2006
  8. *
  9. * mpi2_ioc.h Version: 02.00.10
  10. *
  11. * Version History
  12. * ---------------
  13. *
  14. * Date Version Description
  15. * -------- -------- ------------------------------------------------------
  16. * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
  17. * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
  18. * MaxTargets.
  19. * Added TotalImageSize field to FWDownload Request.
  20. * Added reserved words to FWUpload Request.
  21. * 06-26-07 02.00.02 Added IR Configuration Change List Event.
  22. * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
  23. * request and replaced it with
  24. * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  25. * Replaced the MinReplyQueueDepth field of the IOCFacts
  26. * reply with MaxReplyDescriptorPostQueueDepth.
  27. * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  28. * depth for the Reply Descriptor Post Queue.
  29. * Added SASAddress field to Initiator Device Table
  30. * Overflow Event data.
  31. * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  32. * for SAS Initiator Device Status Change Event data.
  33. * Modified Reason Code defines for SAS Topology Change
  34. * List Event data, including adding a bit for PHY Vacant
  35. * status, and adding a mask for the Reason Code.
  36. * Added define for
  37. * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  38. * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  39. * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
  40. * the IOCFacts Reply.
  41. * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  42. * Moved MPI2_VERSION_UNION to mpi2.h.
  43. * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  44. * instead of enables, and added SASBroadcastPrimitiveMasks
  45. * field.
  46. * Added Log Entry Added Event and related structure.
  47. * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  48. * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  49. * Added MaxVolumes and MaxPersistentEntries fields to
  50. * IOCFacts reply.
  51. * Added ProtocalFlags and IOCCapabilities fields to
  52. * MPI2_FW_IMAGE_HEADER.
  53. * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  54. * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  55. * a U16 (from a U32).
  56. * Removed extra 's' from EventMasks name.
  57. * 06-27-08 02.00.08 Fixed an offset in a comment.
  58. * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  59. * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  60. * renamed MinReplyFrameSize to ReplyFrameSize.
  61. * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  62. * Added two new RAIDOperation values for Integrated RAID
  63. * Operations Status Event data.
  64. * Added four new IR Configuration Change List Event data
  65. * ReasonCode values.
  66. * Added two new ReasonCode defines for SAS Device Status
  67. * Change Event data.
  68. * Added three new DiscoveryStatus bits for the SAS
  69. * Discovery event data.
  70. * Added Multiplexing Status Change bit to the PhyStatus
  71. * field of the SAS Topology Change List event data.
  72. * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  73. * BootFlags are now product-specific.
  74. * Added defines for the indivdual signature bytes
  75. * for MPI2_INIT_IMAGE_FOOTER.
  76. * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  77. * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  78. * define.
  79. * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  80. * define.
  81. * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  82. * --------------------------------------------------------------------------
  83. */
  84. #ifndef MPI2_IOC_H
  85. #define MPI2_IOC_H
  86. /*****************************************************************************
  87. *
  88. * IOC Messages
  89. *
  90. *****************************************************************************/
  91. /****************************************************************************
  92. * IOCInit message
  93. ****************************************************************************/
  94. /* IOCInit Request message */
  95. typedef struct _MPI2_IOC_INIT_REQUEST
  96. {
  97. U8 WhoInit; /* 0x00 */
  98. U8 Reserved1; /* 0x01 */
  99. U8 ChainOffset; /* 0x02 */
  100. U8 Function; /* 0x03 */
  101. U16 Reserved2; /* 0x04 */
  102. U8 Reserved3; /* 0x06 */
  103. U8 MsgFlags; /* 0x07 */
  104. U8 VP_ID; /* 0x08 */
  105. U8 VF_ID; /* 0x09 */
  106. U16 Reserved4; /* 0x0A */
  107. U16 MsgVersion; /* 0x0C */
  108. U16 HeaderVersion; /* 0x0E */
  109. U32 Reserved5; /* 0x10 */
  110. U32 Reserved6; /* 0x14 */
  111. U16 Reserved7; /* 0x18 */
  112. U16 SystemRequestFrameSize; /* 0x1A */
  113. U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
  114. U16 ReplyFreeQueueDepth; /* 0x1E */
  115. U32 SenseBufferAddressHigh; /* 0x20 */
  116. U32 SystemReplyAddressHigh; /* 0x24 */
  117. U64 SystemRequestFrameBaseAddress; /* 0x28 */
  118. U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
  119. U64 ReplyFreeQueueAddress; /* 0x38 */
  120. U64 TimeStamp; /* 0x40 */
  121. } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
  122. Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
  123. /* WhoInit values */
  124. #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
  125. #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
  126. #define MPI2_WHOINIT_ROM_BIOS (0x02)
  127. #define MPI2_WHOINIT_PCI_PEER (0x03)
  128. #define MPI2_WHOINIT_HOST_DRIVER (0x04)
  129. #define MPI2_WHOINIT_MANUFACTURER (0x05)
  130. /* MsgVersion */
  131. #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
  132. #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
  133. #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
  134. #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
  135. /* HeaderVersion */
  136. #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
  137. #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
  138. #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
  139. #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
  140. /* minimum depth for the Reply Descriptor Post Queue */
  141. #define MPI2_RDPQ_DEPTH_MIN (16)
  142. /* IOCInit Reply message */
  143. typedef struct _MPI2_IOC_INIT_REPLY
  144. {
  145. U8 WhoInit; /* 0x00 */
  146. U8 Reserved1; /* 0x01 */
  147. U8 MsgLength; /* 0x02 */
  148. U8 Function; /* 0x03 */
  149. U16 Reserved2; /* 0x04 */
  150. U8 Reserved3; /* 0x06 */
  151. U8 MsgFlags; /* 0x07 */
  152. U8 VP_ID; /* 0x08 */
  153. U8 VF_ID; /* 0x09 */
  154. U16 Reserved4; /* 0x0A */
  155. U16 Reserved5; /* 0x0C */
  156. U16 IOCStatus; /* 0x0E */
  157. U32 IOCLogInfo; /* 0x10 */
  158. } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
  159. Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
  160. /****************************************************************************
  161. * IOCFacts message
  162. ****************************************************************************/
  163. /* IOCFacts Request message */
  164. typedef struct _MPI2_IOC_FACTS_REQUEST
  165. {
  166. U16 Reserved1; /* 0x00 */
  167. U8 ChainOffset; /* 0x02 */
  168. U8 Function; /* 0x03 */
  169. U16 Reserved2; /* 0x04 */
  170. U8 Reserved3; /* 0x06 */
  171. U8 MsgFlags; /* 0x07 */
  172. U8 VP_ID; /* 0x08 */
  173. U8 VF_ID; /* 0x09 */
  174. U16 Reserved4; /* 0x0A */
  175. } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
  176. Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
  177. /* IOCFacts Reply message */
  178. typedef struct _MPI2_IOC_FACTS_REPLY
  179. {
  180. U16 MsgVersion; /* 0x00 */
  181. U8 MsgLength; /* 0x02 */
  182. U8 Function; /* 0x03 */
  183. U16 HeaderVersion; /* 0x04 */
  184. U8 IOCNumber; /* 0x06 */
  185. U8 MsgFlags; /* 0x07 */
  186. U8 VP_ID; /* 0x08 */
  187. U8 VF_ID; /* 0x09 */
  188. U16 Reserved1; /* 0x0A */
  189. U16 IOCExceptions; /* 0x0C */
  190. U16 IOCStatus; /* 0x0E */
  191. U32 IOCLogInfo; /* 0x10 */
  192. U8 MaxChainDepth; /* 0x14 */
  193. U8 WhoInit; /* 0x15 */
  194. U8 NumberOfPorts; /* 0x16 */
  195. U8 Reserved2; /* 0x17 */
  196. U16 RequestCredit; /* 0x18 */
  197. U16 ProductID; /* 0x1A */
  198. U32 IOCCapabilities; /* 0x1C */
  199. MPI2_VERSION_UNION FWVersion; /* 0x20 */
  200. U16 IOCRequestFrameSize; /* 0x24 */
  201. U16 Reserved3; /* 0x26 */
  202. U16 MaxInitiators; /* 0x28 */
  203. U16 MaxTargets; /* 0x2A */
  204. U16 MaxSasExpanders; /* 0x2C */
  205. U16 MaxEnclosures; /* 0x2E */
  206. U16 ProtocolFlags; /* 0x30 */
  207. U16 HighPriorityCredit; /* 0x32 */
  208. U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
  209. U8 ReplyFrameSize; /* 0x36 */
  210. U8 MaxVolumes; /* 0x37 */
  211. U16 MaxDevHandle; /* 0x38 */
  212. U16 MaxPersistentEntries; /* 0x3A */
  213. U32 Reserved4; /* 0x3C */
  214. } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
  215. Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
  216. /* MsgVersion */
  217. #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
  218. #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
  219. #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
  220. #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
  221. /* HeaderVersion */
  222. #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
  223. #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
  224. #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
  225. #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
  226. /* IOCExceptions */
  227. #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
  228. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
  229. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
  230. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
  231. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
  232. #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
  233. #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
  234. #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
  235. #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
  236. #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
  237. #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
  238. /* defines for WhoInit field are after the IOCInit Request */
  239. /* ProductID field uses MPI2_FW_HEADER_PID_ */
  240. /* IOCCapabilities */
  241. #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
  242. #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
  243. #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
  244. #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
  245. #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
  246. #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
  247. #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
  248. #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
  249. #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
  250. /* ProtocolFlags */
  251. #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
  252. #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
  253. /****************************************************************************
  254. * PortFacts message
  255. ****************************************************************************/
  256. /* PortFacts Request message */
  257. typedef struct _MPI2_PORT_FACTS_REQUEST
  258. {
  259. U16 Reserved1; /* 0x00 */
  260. U8 ChainOffset; /* 0x02 */
  261. U8 Function; /* 0x03 */
  262. U16 Reserved2; /* 0x04 */
  263. U8 PortNumber; /* 0x06 */
  264. U8 MsgFlags; /* 0x07 */
  265. U8 VP_ID; /* 0x08 */
  266. U8 VF_ID; /* 0x09 */
  267. U16 Reserved3; /* 0x0A */
  268. } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
  269. Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
  270. /* PortFacts Reply message */
  271. typedef struct _MPI2_PORT_FACTS_REPLY
  272. {
  273. U16 Reserved1; /* 0x00 */
  274. U8 MsgLength; /* 0x02 */
  275. U8 Function; /* 0x03 */
  276. U16 Reserved2; /* 0x04 */
  277. U8 PortNumber; /* 0x06 */
  278. U8 MsgFlags; /* 0x07 */
  279. U8 VP_ID; /* 0x08 */
  280. U8 VF_ID; /* 0x09 */
  281. U16 Reserved3; /* 0x0A */
  282. U16 Reserved4; /* 0x0C */
  283. U16 IOCStatus; /* 0x0E */
  284. U32 IOCLogInfo; /* 0x10 */
  285. U8 Reserved5; /* 0x14 */
  286. U8 PortType; /* 0x15 */
  287. U16 Reserved6; /* 0x16 */
  288. U16 MaxPostedCmdBuffers; /* 0x18 */
  289. U16 Reserved7; /* 0x1A */
  290. } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
  291. Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
  292. /* PortType values */
  293. #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
  294. #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
  295. #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
  296. #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
  297. #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
  298. /****************************************************************************
  299. * PortEnable message
  300. ****************************************************************************/
  301. /* PortEnable Request message */
  302. typedef struct _MPI2_PORT_ENABLE_REQUEST
  303. {
  304. U16 Reserved1; /* 0x00 */
  305. U8 ChainOffset; /* 0x02 */
  306. U8 Function; /* 0x03 */
  307. U8 Reserved2; /* 0x04 */
  308. U8 PortFlags; /* 0x05 */
  309. U8 Reserved3; /* 0x06 */
  310. U8 MsgFlags; /* 0x07 */
  311. U8 VP_ID; /* 0x08 */
  312. U8 VF_ID; /* 0x09 */
  313. U16 Reserved4; /* 0x0A */
  314. } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
  315. Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
  316. /* PortEnable Reply message */
  317. typedef struct _MPI2_PORT_ENABLE_REPLY
  318. {
  319. U16 Reserved1; /* 0x00 */
  320. U8 MsgLength; /* 0x02 */
  321. U8 Function; /* 0x03 */
  322. U8 Reserved2; /* 0x04 */
  323. U8 PortFlags; /* 0x05 */
  324. U8 Reserved3; /* 0x06 */
  325. U8 MsgFlags; /* 0x07 */
  326. U8 VP_ID; /* 0x08 */
  327. U8 VF_ID; /* 0x09 */
  328. U16 Reserved4; /* 0x0A */
  329. U16 Reserved5; /* 0x0C */
  330. U16 IOCStatus; /* 0x0E */
  331. U32 IOCLogInfo; /* 0x10 */
  332. } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
  333. Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
  334. /****************************************************************************
  335. * EventNotification message
  336. ****************************************************************************/
  337. /* EventNotification Request message */
  338. #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
  339. typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
  340. {
  341. U16 Reserved1; /* 0x00 */
  342. U8 ChainOffset; /* 0x02 */
  343. U8 Function; /* 0x03 */
  344. U16 Reserved2; /* 0x04 */
  345. U8 Reserved3; /* 0x06 */
  346. U8 MsgFlags; /* 0x07 */
  347. U8 VP_ID; /* 0x08 */
  348. U8 VF_ID; /* 0x09 */
  349. U16 Reserved4; /* 0x0A */
  350. U32 Reserved5; /* 0x0C */
  351. U32 Reserved6; /* 0x10 */
  352. U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
  353. U16 SASBroadcastPrimitiveMasks; /* 0x24 */
  354. U16 Reserved7; /* 0x26 */
  355. U32 Reserved8; /* 0x28 */
  356. } MPI2_EVENT_NOTIFICATION_REQUEST,
  357. MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
  358. Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
  359. /* EventNotification Reply message */
  360. typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
  361. {
  362. U16 EventDataLength; /* 0x00 */
  363. U8 MsgLength; /* 0x02 */
  364. U8 Function; /* 0x03 */
  365. U16 Reserved1; /* 0x04 */
  366. U8 AckRequired; /* 0x06 */
  367. U8 MsgFlags; /* 0x07 */
  368. U8 VP_ID; /* 0x08 */
  369. U8 VF_ID; /* 0x09 */
  370. U16 Reserved2; /* 0x0A */
  371. U16 Reserved3; /* 0x0C */
  372. U16 IOCStatus; /* 0x0E */
  373. U32 IOCLogInfo; /* 0x10 */
  374. U16 Event; /* 0x14 */
  375. U16 Reserved4; /* 0x16 */
  376. U32 EventContext; /* 0x18 */
  377. U32 EventData[1]; /* 0x1C */
  378. } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
  379. Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
  380. /* AckRequired */
  381. #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
  382. #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
  383. /* Event */
  384. #define MPI2_EVENT_LOG_DATA (0x0001)
  385. #define MPI2_EVENT_STATE_CHANGE (0x0002)
  386. #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
  387. #define MPI2_EVENT_EVENT_CHANGE (0x000A)
  388. #define MPI2_EVENT_TASK_SET_FULL (0x000E)
  389. #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
  390. #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
  391. #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
  392. #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
  393. #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
  394. #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
  395. #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
  396. #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
  397. #define MPI2_EVENT_IR_VOLUME (0x001E)
  398. #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
  399. #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
  400. #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
  401. /* Log Entry Added Event data */
  402. /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
  403. #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
  404. typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
  405. {
  406. U64 TimeStamp; /* 0x00 */
  407. U32 Reserved1; /* 0x08 */
  408. U16 LogSequence; /* 0x0C */
  409. U16 LogEntryQualifier; /* 0x0E */
  410. U8 VP_ID; /* 0x10 */
  411. U8 VF_ID; /* 0x11 */
  412. U16 Reserved2; /* 0x12 */
  413. U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
  414. } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
  415. MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
  416. Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
  417. /* Hard Reset Received Event data */
  418. typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
  419. {
  420. U8 Reserved1; /* 0x00 */
  421. U8 Port; /* 0x01 */
  422. U16 Reserved2; /* 0x02 */
  423. } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
  424. MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
  425. Mpi2EventDataHardResetReceived_t,
  426. MPI2_POINTER pMpi2EventDataHardResetReceived_t;
  427. /* Task Set Full Event data */
  428. typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
  429. {
  430. U16 DevHandle; /* 0x00 */
  431. U16 CurrentDepth; /* 0x02 */
  432. } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
  433. Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
  434. /* SAS Device Status Change Event data */
  435. typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
  436. {
  437. U16 TaskTag; /* 0x00 */
  438. U8 ReasonCode; /* 0x02 */
  439. U8 Reserved1; /* 0x03 */
  440. U8 ASC; /* 0x04 */
  441. U8 ASCQ; /* 0x05 */
  442. U16 DevHandle; /* 0x06 */
  443. U32 Reserved2; /* 0x08 */
  444. U64 SASAddress; /* 0x0C */
  445. U8 LUN[8]; /* 0x14 */
  446. } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
  447. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
  448. Mpi2EventDataSasDeviceStatusChange_t,
  449. MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
  450. /* SAS Device Status Change Event data ReasonCode values */
  451. #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
  452. #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
  453. #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
  454. #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
  455. #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
  456. #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
  457. #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
  458. #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
  459. #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
  460. #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
  461. #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
  462. /* Integrated RAID Operation Status Event data */
  463. typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
  464. {
  465. U16 VolDevHandle; /* 0x00 */
  466. U16 Reserved1; /* 0x02 */
  467. U8 RAIDOperation; /* 0x04 */
  468. U8 PercentComplete; /* 0x05 */
  469. U16 Reserved2; /* 0x06 */
  470. U32 Resereved3; /* 0x08 */
  471. } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
  472. MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
  473. Mpi2EventDataIrOperationStatus_t,
  474. MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
  475. /* Integrated RAID Operation Status Event data RAIDOperation values */
  476. #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
  477. #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
  478. #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
  479. #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
  480. #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
  481. /* Integrated RAID Volume Event data */
  482. typedef struct _MPI2_EVENT_DATA_IR_VOLUME
  483. {
  484. U16 VolDevHandle; /* 0x00 */
  485. U8 ReasonCode; /* 0x02 */
  486. U8 Reserved1; /* 0x03 */
  487. U32 NewValue; /* 0x04 */
  488. U32 PreviousValue; /* 0x08 */
  489. } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
  490. Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
  491. /* Integrated RAID Volume Event data ReasonCode values */
  492. #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
  493. #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
  494. #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
  495. /* Integrated RAID Physical Disk Event data */
  496. typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
  497. {
  498. U16 Reserved1; /* 0x00 */
  499. U8 ReasonCode; /* 0x02 */
  500. U8 PhysDiskNum; /* 0x03 */
  501. U16 PhysDiskDevHandle; /* 0x04 */
  502. U16 Reserved2; /* 0x06 */
  503. U16 Slot; /* 0x08 */
  504. U16 EnclosureHandle; /* 0x0A */
  505. U32 NewValue; /* 0x0C */
  506. U32 PreviousValue; /* 0x10 */
  507. } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
  508. MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
  509. Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
  510. /* Integrated RAID Physical Disk Event data ReasonCode values */
  511. #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
  512. #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
  513. #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
  514. /* Integrated RAID Configuration Change List Event data */
  515. /*
  516. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  517. * one and check NumElements at runtime.
  518. */
  519. #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
  520. #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
  521. #endif
  522. typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
  523. {
  524. U16 ElementFlags; /* 0x00 */
  525. U16 VolDevHandle; /* 0x02 */
  526. U8 ReasonCode; /* 0x04 */
  527. U8 PhysDiskNum; /* 0x05 */
  528. U16 PhysDiskDevHandle; /* 0x06 */
  529. } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
  530. Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
  531. /* IR Configuration Change List Event data ElementFlags values */
  532. #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
  533. #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
  534. #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
  535. #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
  536. /* IR Configuration Change List Event data ReasonCode values */
  537. #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
  538. #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
  539. #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
  540. #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
  541. #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
  542. #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
  543. #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
  544. #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
  545. #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
  546. typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
  547. {
  548. U8 NumElements; /* 0x00 */
  549. U8 Reserved1; /* 0x01 */
  550. U8 Reserved2; /* 0x02 */
  551. U8 ConfigNum; /* 0x03 */
  552. U32 Flags; /* 0x04 */
  553. MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
  554. } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
  555. MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
  556. Mpi2EventDataIrConfigChangeList_t,
  557. MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
  558. /* IR Configuration Change List Event data Flags values */
  559. #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
  560. /* SAS Discovery Event data */
  561. typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
  562. {
  563. U8 Flags; /* 0x00 */
  564. U8 ReasonCode; /* 0x01 */
  565. U8 PhysicalPort; /* 0x02 */
  566. U8 Reserved1; /* 0x03 */
  567. U32 DiscoveryStatus; /* 0x04 */
  568. } MPI2_EVENT_DATA_SAS_DISCOVERY,
  569. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
  570. Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
  571. /* SAS Discovery Event data Flags values */
  572. #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
  573. #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
  574. /* SAS Discovery Event data ReasonCode values */
  575. #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
  576. #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
  577. /* SAS Discovery Event data DiscoveryStatus values */
  578. #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
  579. #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
  580. #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
  581. #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
  582. #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
  583. #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
  584. #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
  585. #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
  586. #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
  587. #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
  588. #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
  589. #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
  590. #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
  591. #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
  592. #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
  593. #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
  594. #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
  595. #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
  596. #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
  597. #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
  598. /* SAS Broadcast Primitive Event data */
  599. typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
  600. {
  601. U8 PhyNum; /* 0x00 */
  602. U8 Port; /* 0x01 */
  603. U8 PortWidth; /* 0x02 */
  604. U8 Primitive; /* 0x03 */
  605. } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
  606. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
  607. Mpi2EventDataSasBroadcastPrimitive_t,
  608. MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
  609. /* defines for the Primitive field */
  610. #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
  611. #define MPI2_EVENT_PRIMITIVE_SES (0x02)
  612. #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
  613. #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
  614. #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
  615. #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
  616. #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
  617. #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
  618. /* SAS Initiator Device Status Change Event data */
  619. typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
  620. {
  621. U8 ReasonCode; /* 0x00 */
  622. U8 PhysicalPort; /* 0x01 */
  623. U16 DevHandle; /* 0x02 */
  624. U64 SASAddress; /* 0x04 */
  625. } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
  626. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
  627. Mpi2EventDataSasInitDevStatusChange_t,
  628. MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
  629. /* SAS Initiator Device Status Change event ReasonCode values */
  630. #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
  631. #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
  632. /* SAS Initiator Device Table Overflow Event data */
  633. typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
  634. {
  635. U16 MaxInit; /* 0x00 */
  636. U16 CurrentInit; /* 0x02 */
  637. U64 SASAddress; /* 0x04 */
  638. } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
  639. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
  640. Mpi2EventDataSasInitTableOverflow_t,
  641. MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
  642. /* SAS Topology Change List Event data */
  643. /*
  644. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  645. * one and check NumEntries at runtime.
  646. */
  647. #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
  648. #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
  649. #endif
  650. typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
  651. {
  652. U16 AttachedDevHandle; /* 0x00 */
  653. U8 LinkRate; /* 0x02 */
  654. U8 PhyStatus; /* 0x03 */
  655. } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
  656. Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
  657. typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
  658. {
  659. U16 EnclosureHandle; /* 0x00 */
  660. U16 ExpanderDevHandle; /* 0x02 */
  661. U8 NumPhys; /* 0x04 */
  662. U8 Reserved1; /* 0x05 */
  663. U16 Reserved2; /* 0x06 */
  664. U8 NumEntries; /* 0x08 */
  665. U8 StartPhyNum; /* 0x09 */
  666. U8 ExpStatus; /* 0x0A */
  667. U8 PhysicalPort; /* 0x0B */
  668. MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
  669. } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
  670. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
  671. Mpi2EventDataSasTopologyChangeList_t,
  672. MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
  673. /* values for the ExpStatus field */
  674. #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
  675. #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
  676. #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
  677. #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
  678. /* defines for the LinkRate field */
  679. #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
  680. #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
  681. #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
  682. #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
  683. #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
  684. #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
  685. #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
  686. #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
  687. #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
  688. #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
  689. #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
  690. #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
  691. #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
  692. /* values for the PhyStatus field */
  693. #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
  694. #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
  695. /* values for the PhyStatus ReasonCode sub-field */
  696. #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
  697. #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
  698. #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
  699. #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
  700. #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
  701. #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
  702. /* SAS Enclosure Device Status Change Event data */
  703. typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
  704. {
  705. U16 EnclosureHandle; /* 0x00 */
  706. U8 ReasonCode; /* 0x02 */
  707. U8 PhysicalPort; /* 0x03 */
  708. U64 EnclosureLogicalID; /* 0x04 */
  709. U16 NumSlots; /* 0x0C */
  710. U16 StartSlot; /* 0x0E */
  711. U32 PhyBits; /* 0x10 */
  712. } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
  713. MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
  714. Mpi2EventDataSasEnclDevStatusChange_t,
  715. MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
  716. /* SAS Enclosure Device Status Change event ReasonCode values */
  717. #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
  718. #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
  719. /****************************************************************************
  720. * EventAck message
  721. ****************************************************************************/
  722. /* EventAck Request message */
  723. typedef struct _MPI2_EVENT_ACK_REQUEST
  724. {
  725. U16 Reserved1; /* 0x00 */
  726. U8 ChainOffset; /* 0x02 */
  727. U8 Function; /* 0x03 */
  728. U16 Reserved2; /* 0x04 */
  729. U8 Reserved3; /* 0x06 */
  730. U8 MsgFlags; /* 0x07 */
  731. U8 VP_ID; /* 0x08 */
  732. U8 VF_ID; /* 0x09 */
  733. U16 Reserved4; /* 0x0A */
  734. U16 Event; /* 0x0C */
  735. U16 Reserved5; /* 0x0E */
  736. U32 EventContext; /* 0x10 */
  737. } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
  738. Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
  739. /* EventAck Reply message */
  740. typedef struct _MPI2_EVENT_ACK_REPLY
  741. {
  742. U16 Reserved1; /* 0x00 */
  743. U8 MsgLength; /* 0x02 */
  744. U8 Function; /* 0x03 */
  745. U16 Reserved2; /* 0x04 */
  746. U8 Reserved3; /* 0x06 */
  747. U8 MsgFlags; /* 0x07 */
  748. U8 VP_ID; /* 0x08 */
  749. U8 VF_ID; /* 0x09 */
  750. U16 Reserved4; /* 0x0A */
  751. U16 Reserved5; /* 0x0C */
  752. U16 IOCStatus; /* 0x0E */
  753. U32 IOCLogInfo; /* 0x10 */
  754. } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
  755. Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
  756. /****************************************************************************
  757. * FWDownload message
  758. ****************************************************************************/
  759. /* FWDownload Request message */
  760. typedef struct _MPI2_FW_DOWNLOAD_REQUEST
  761. {
  762. U8 ImageType; /* 0x00 */
  763. U8 Reserved1; /* 0x01 */
  764. U8 ChainOffset; /* 0x02 */
  765. U8 Function; /* 0x03 */
  766. U16 Reserved2; /* 0x04 */
  767. U8 Reserved3; /* 0x06 */
  768. U8 MsgFlags; /* 0x07 */
  769. U8 VP_ID; /* 0x08 */
  770. U8 VF_ID; /* 0x09 */
  771. U16 Reserved4; /* 0x0A */
  772. U32 TotalImageSize; /* 0x0C */
  773. U32 Reserved5; /* 0x10 */
  774. MPI2_MPI_SGE_UNION SGL; /* 0x14 */
  775. } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
  776. Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
  777. #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
  778. #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
  779. #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
  780. #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
  781. #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
  782. #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
  783. #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
  784. #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
  785. /* FWDownload TransactionContext Element */
  786. typedef struct _MPI2_FW_DOWNLOAD_TCSGE
  787. {
  788. U8 Reserved1; /* 0x00 */
  789. U8 ContextSize; /* 0x01 */
  790. U8 DetailsLength; /* 0x02 */
  791. U8 Flags; /* 0x03 */
  792. U32 Reserved2; /* 0x04 */
  793. U32 ImageOffset; /* 0x08 */
  794. U32 ImageSize; /* 0x0C */
  795. } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
  796. Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
  797. /* FWDownload Reply message */
  798. typedef struct _MPI2_FW_DOWNLOAD_REPLY
  799. {
  800. U8 ImageType; /* 0x00 */
  801. U8 Reserved1; /* 0x01 */
  802. U8 MsgLength; /* 0x02 */
  803. U8 Function; /* 0x03 */
  804. U16 Reserved2; /* 0x04 */
  805. U8 Reserved3; /* 0x06 */
  806. U8 MsgFlags; /* 0x07 */
  807. U8 VP_ID; /* 0x08 */
  808. U8 VF_ID; /* 0x09 */
  809. U16 Reserved4; /* 0x0A */
  810. U16 Reserved5; /* 0x0C */
  811. U16 IOCStatus; /* 0x0E */
  812. U32 IOCLogInfo; /* 0x10 */
  813. } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
  814. Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
  815. /****************************************************************************
  816. * FWUpload message
  817. ****************************************************************************/
  818. /* FWUpload Request message */
  819. typedef struct _MPI2_FW_UPLOAD_REQUEST
  820. {
  821. U8 ImageType; /* 0x00 */
  822. U8 Reserved1; /* 0x01 */
  823. U8 ChainOffset; /* 0x02 */
  824. U8 Function; /* 0x03 */
  825. U16 Reserved2; /* 0x04 */
  826. U8 Reserved3; /* 0x06 */
  827. U8 MsgFlags; /* 0x07 */
  828. U8 VP_ID; /* 0x08 */
  829. U8 VF_ID; /* 0x09 */
  830. U16 Reserved4; /* 0x0A */
  831. U32 Reserved5; /* 0x0C */
  832. U32 Reserved6; /* 0x10 */
  833. MPI2_MPI_SGE_UNION SGL; /* 0x14 */
  834. } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
  835. Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
  836. #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
  837. #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
  838. #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
  839. #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
  840. #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
  841. #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
  842. #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
  843. #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
  844. #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
  845. #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
  846. typedef struct _MPI2_FW_UPLOAD_TCSGE
  847. {
  848. U8 Reserved1; /* 0x00 */
  849. U8 ContextSize; /* 0x01 */
  850. U8 DetailsLength; /* 0x02 */
  851. U8 Flags; /* 0x03 */
  852. U32 Reserved2; /* 0x04 */
  853. U32 ImageOffset; /* 0x08 */
  854. U32 ImageSize; /* 0x0C */
  855. } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
  856. Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
  857. /* FWUpload Reply message */
  858. typedef struct _MPI2_FW_UPLOAD_REPLY
  859. {
  860. U8 ImageType; /* 0x00 */
  861. U8 Reserved1; /* 0x01 */
  862. U8 MsgLength; /* 0x02 */
  863. U8 Function; /* 0x03 */
  864. U16 Reserved2; /* 0x04 */
  865. U8 Reserved3; /* 0x06 */
  866. U8 MsgFlags; /* 0x07 */
  867. U8 VP_ID; /* 0x08 */
  868. U8 VF_ID; /* 0x09 */
  869. U16 Reserved4; /* 0x0A */
  870. U16 Reserved5; /* 0x0C */
  871. U16 IOCStatus; /* 0x0E */
  872. U32 IOCLogInfo; /* 0x10 */
  873. U32 ActualImageSize; /* 0x14 */
  874. } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
  875. Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
  876. /* FW Image Header */
  877. typedef struct _MPI2_FW_IMAGE_HEADER
  878. {
  879. U32 Signature; /* 0x00 */
  880. U32 Signature0; /* 0x04 */
  881. U32 Signature1; /* 0x08 */
  882. U32 Signature2; /* 0x0C */
  883. MPI2_VERSION_UNION MPIVersion; /* 0x10 */
  884. MPI2_VERSION_UNION FWVersion; /* 0x14 */
  885. MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
  886. MPI2_VERSION_UNION PackageVersion; /* 0x1C */
  887. U16 VendorID; /* 0x20 */
  888. U16 ProductID; /* 0x22 */
  889. U16 ProtocolFlags; /* 0x24 */
  890. U16 Reserved26; /* 0x26 */
  891. U32 IOCCapabilities; /* 0x28 */
  892. U32 ImageSize; /* 0x2C */
  893. U32 NextImageHeaderOffset; /* 0x30 */
  894. U32 Checksum; /* 0x34 */
  895. U32 Reserved38; /* 0x38 */
  896. U32 Reserved3C; /* 0x3C */
  897. U32 Reserved40; /* 0x40 */
  898. U32 Reserved44; /* 0x44 */
  899. U32 Reserved48; /* 0x48 */
  900. U32 Reserved4C; /* 0x4C */
  901. U32 Reserved50; /* 0x50 */
  902. U32 Reserved54; /* 0x54 */
  903. U32 Reserved58; /* 0x58 */
  904. U32 Reserved5C; /* 0x5C */
  905. U32 Reserved60; /* 0x60 */
  906. U32 FirmwareVersionNameWhat; /* 0x64 */
  907. U8 FirmwareVersionName[32]; /* 0x68 */
  908. U32 VendorNameWhat; /* 0x88 */
  909. U8 VendorName[32]; /* 0x8C */
  910. U32 PackageNameWhat; /* 0x88 */
  911. U8 PackageName[32]; /* 0x8C */
  912. U32 ReservedD0; /* 0xD0 */
  913. U32 ReservedD4; /* 0xD4 */
  914. U32 ReservedD8; /* 0xD8 */
  915. U32 ReservedDC; /* 0xDC */
  916. U32 ReservedE0; /* 0xE0 */
  917. U32 ReservedE4; /* 0xE4 */
  918. U32 ReservedE8; /* 0xE8 */
  919. U32 ReservedEC; /* 0xEC */
  920. U32 ReservedF0; /* 0xF0 */
  921. U32 ReservedF4; /* 0xF4 */
  922. U32 ReservedF8; /* 0xF8 */
  923. U32 ReservedFC; /* 0xFC */
  924. } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
  925. Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
  926. /* Signature field */
  927. #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
  928. #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
  929. #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
  930. /* Signature0 field */
  931. #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
  932. #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
  933. /* Signature1 field */
  934. #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
  935. #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
  936. /* Signature2 field */
  937. #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
  938. #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
  939. /* defines for using the ProductID field */
  940. #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
  941. #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
  942. #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
  943. #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
  944. #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
  945. /* SAS */
  946. #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
  947. /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
  948. /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
  949. #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
  950. #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
  951. #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
  952. #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
  953. #define MPI2_FW_HEADER_SIZE (0x100)
  954. /* Extended Image Header */
  955. typedef struct _MPI2_EXT_IMAGE_HEADER
  956. {
  957. U8 ImageType; /* 0x00 */
  958. U8 Reserved1; /* 0x01 */
  959. U16 Reserved2; /* 0x02 */
  960. U32 Checksum; /* 0x04 */
  961. U32 ImageSize; /* 0x08 */
  962. U32 NextImageHeaderOffset; /* 0x0C */
  963. U32 PackageVersion; /* 0x10 */
  964. U32 Reserved3; /* 0x14 */
  965. U32 Reserved4; /* 0x18 */
  966. U32 Reserved5; /* 0x1C */
  967. U8 IdentifyString[32]; /* 0x20 */
  968. } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
  969. Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
  970. /* useful offsets */
  971. #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
  972. #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
  973. #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
  974. #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
  975. /* defines for the ImageType field */
  976. #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
  977. #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
  978. #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
  979. #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
  980. #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
  981. #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
  982. #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
  983. #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
  984. #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
  985. /* FLASH Layout Extended Image Data */
  986. /*
  987. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  988. * one and check RegionsPerLayout at runtime.
  989. */
  990. #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
  991. #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
  992. #endif
  993. /*
  994. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  995. * one and check NumberOfLayouts at runtime.
  996. */
  997. #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
  998. #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
  999. #endif
  1000. typedef struct _MPI2_FLASH_REGION
  1001. {
  1002. U8 RegionType; /* 0x00 */
  1003. U8 Reserved1; /* 0x01 */
  1004. U16 Reserved2; /* 0x02 */
  1005. U32 RegionOffset; /* 0x04 */
  1006. U32 RegionSize; /* 0x08 */
  1007. U32 Reserved3; /* 0x0C */
  1008. } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
  1009. Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
  1010. typedef struct _MPI2_FLASH_LAYOUT
  1011. {
  1012. U32 FlashSize; /* 0x00 */
  1013. U32 Reserved1; /* 0x04 */
  1014. U32 Reserved2; /* 0x08 */
  1015. U32 Reserved3; /* 0x0C */
  1016. MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
  1017. } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
  1018. Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
  1019. typedef struct _MPI2_FLASH_LAYOUT_DATA
  1020. {
  1021. U8 ImageRevision; /* 0x00 */
  1022. U8 Reserved1; /* 0x01 */
  1023. U8 SizeOfRegion; /* 0x02 */
  1024. U8 Reserved2; /* 0x03 */
  1025. U16 NumberOfLayouts; /* 0x04 */
  1026. U16 RegionsPerLayout; /* 0x06 */
  1027. U16 MinimumSectorAlignment; /* 0x08 */
  1028. U16 Reserved3; /* 0x0A */
  1029. U32 Reserved4; /* 0x0C */
  1030. MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
  1031. } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
  1032. Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
  1033. /* defines for the RegionType field */
  1034. #define MPI2_FLASH_REGION_UNUSED (0x00)
  1035. #define MPI2_FLASH_REGION_FIRMWARE (0x01)
  1036. #define MPI2_FLASH_REGION_BIOS (0x02)
  1037. #define MPI2_FLASH_REGION_NVDATA (0x03)
  1038. #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
  1039. #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
  1040. #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
  1041. #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
  1042. #define MPI2_FLASH_REGION_MEGARAID (0x09)
  1043. #define MPI2_FLASH_REGION_INIT (0x0A)
  1044. /* ImageRevision */
  1045. #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
  1046. /* Supported Devices Extended Image Data */
  1047. /*
  1048. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1049. * one and check NumberOfDevices at runtime.
  1050. */
  1051. #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
  1052. #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
  1053. #endif
  1054. typedef struct _MPI2_SUPPORTED_DEVICE
  1055. {
  1056. U16 DeviceID; /* 0x00 */
  1057. U16 VendorID; /* 0x02 */
  1058. U16 DeviceIDMask; /* 0x04 */
  1059. U16 Reserved1; /* 0x06 */
  1060. U8 LowPCIRev; /* 0x08 */
  1061. U8 HighPCIRev; /* 0x09 */
  1062. U16 Reserved2; /* 0x0A */
  1063. U32 Reserved3; /* 0x0C */
  1064. } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
  1065. Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
  1066. typedef struct _MPI2_SUPPORTED_DEVICES_DATA
  1067. {
  1068. U8 ImageRevision; /* 0x00 */
  1069. U8 Reserved1; /* 0x01 */
  1070. U8 NumberOfDevices; /* 0x02 */
  1071. U8 Reserved2; /* 0x03 */
  1072. U32 Reserved3; /* 0x04 */
  1073. MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
  1074. } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
  1075. Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
  1076. /* ImageRevision */
  1077. #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
  1078. /* Init Extended Image Data */
  1079. typedef struct _MPI2_INIT_IMAGE_FOOTER
  1080. {
  1081. U32 BootFlags; /* 0x00 */
  1082. U32 ImageSize; /* 0x04 */
  1083. U32 Signature0; /* 0x08 */
  1084. U32 Signature1; /* 0x0C */
  1085. U32 Signature2; /* 0x10 */
  1086. U32 ResetVector; /* 0x14 */
  1087. } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
  1088. Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
  1089. /* defines for the BootFlags field */
  1090. #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
  1091. /* defines for the ImageSize field */
  1092. #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
  1093. /* defines for the Signature0 field */
  1094. #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
  1095. #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
  1096. /* defines for the Signature1 field */
  1097. #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
  1098. #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
  1099. /* defines for the Signature2 field */
  1100. #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
  1101. #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
  1102. /* Signature fields as individual bytes */
  1103. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
  1104. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
  1105. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
  1106. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
  1107. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
  1108. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
  1109. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
  1110. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
  1111. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
  1112. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
  1113. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
  1114. #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
  1115. /* defines for the ResetVector field */
  1116. #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
  1117. #endif