cxgb3i_ddp.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773
  1. /*
  2. * cxgb3i_ddp.c: Chelsio S3xx iSCSI DDP Manager.
  3. *
  4. * Copyright (c) 2008 Chelsio Communications, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Written by: Karen Xie (kxie@chelsio.com)
  11. */
  12. #include <linux/skbuff.h>
  13. #include <linux/scatterlist.h>
  14. /* from cxgb3 LLD */
  15. #include "common.h"
  16. #include "t3_cpl.h"
  17. #include "t3cdev.h"
  18. #include "cxgb3_ctl_defs.h"
  19. #include "cxgb3_offload.h"
  20. #include "firmware_exports.h"
  21. #include "cxgb3i_ddp.h"
  22. #define DRV_MODULE_NAME "cxgb3i_ddp"
  23. #define DRV_MODULE_VERSION "1.0.0"
  24. #define DRV_MODULE_RELDATE "Dec. 1, 2008"
  25. static char version[] =
  26. "Chelsio S3xx iSCSI DDP " DRV_MODULE_NAME
  27. " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  28. MODULE_AUTHOR("Karen Xie <kxie@chelsio.com>");
  29. MODULE_DESCRIPTION("cxgb3i ddp pagepod manager");
  30. MODULE_LICENSE("GPL");
  31. MODULE_VERSION(DRV_MODULE_VERSION);
  32. #define ddp_log_error(fmt...) printk(KERN_ERR "cxgb3i_ddp: ERR! " fmt)
  33. #define ddp_log_warn(fmt...) printk(KERN_WARNING "cxgb3i_ddp: WARN! " fmt)
  34. #define ddp_log_info(fmt...) printk(KERN_INFO "cxgb3i_ddp: " fmt)
  35. #ifdef __DEBUG_CXGB3I_DDP__
  36. #define ddp_log_debug(fmt, args...) \
  37. printk(KERN_INFO "cxgb3i_ddp: %s - " fmt, __func__ , ## args)
  38. #else
  39. #define ddp_log_debug(fmt...)
  40. #endif
  41. /*
  42. * iSCSI Direct Data Placement
  43. *
  44. * T3 h/w can directly place the iSCSI Data-In or Data-Out PDU's payload into
  45. * pre-posted final destination host-memory buffers based on the Initiator
  46. * Task Tag (ITT) in Data-In or Target Task Tag (TTT) in Data-Out PDUs.
  47. *
  48. * The host memory address is programmed into h/w in the format of pagepod
  49. * entries.
  50. * The location of the pagepod entry is encoded into ddp tag which is used or
  51. * is the base for ITT/TTT.
  52. */
  53. #define DDP_PGIDX_MAX 4
  54. #define DDP_THRESHOLD 2048
  55. static unsigned char ddp_page_order[DDP_PGIDX_MAX] = {0, 1, 2, 4};
  56. static unsigned char ddp_page_shift[DDP_PGIDX_MAX] = {12, 13, 14, 16};
  57. static unsigned char page_idx = DDP_PGIDX_MAX;
  58. static LIST_HEAD(cxgb3i_ddp_list);
  59. static DEFINE_RWLOCK(cxgb3i_ddp_rwlock);
  60. /*
  61. * functions to program the pagepod in h/w
  62. */
  63. static inline void ulp_mem_io_set_hdr(struct sk_buff *skb, unsigned int addr)
  64. {
  65. struct ulp_mem_io *req = (struct ulp_mem_io *)skb->head;
  66. req->wr.wr_lo = 0;
  67. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS));
  68. req->cmd_lock_addr = htonl(V_ULP_MEMIO_ADDR(addr >> 5) |
  69. V_ULPTX_CMD(ULP_MEM_WRITE));
  70. req->len = htonl(V_ULP_MEMIO_DATA_LEN(PPOD_SIZE >> 5) |
  71. V_ULPTX_NFLITS((PPOD_SIZE >> 3) + 1));
  72. }
  73. static int set_ddp_map(struct cxgb3i_ddp_info *ddp, struct pagepod_hdr *hdr,
  74. unsigned int idx, unsigned int npods,
  75. struct cxgb3i_gather_list *gl)
  76. {
  77. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ddp->llimit;
  78. int i;
  79. for (i = 0; i < npods; i++, idx++, pm_addr += PPOD_SIZE) {
  80. struct sk_buff *skb = ddp->gl_skb[idx];
  81. struct pagepod *ppod;
  82. int j, pidx;
  83. /* hold on to the skb until we clear the ddp mapping */
  84. skb_get(skb);
  85. ulp_mem_io_set_hdr(skb, pm_addr);
  86. ppod = (struct pagepod *)
  87. (skb->head + sizeof(struct ulp_mem_io));
  88. memcpy(&(ppod->hdr), hdr, sizeof(struct pagepod));
  89. for (pidx = 4 * i, j = 0; j < 5; ++j, ++pidx)
  90. ppod->addr[j] = pidx < gl->nelem ?
  91. cpu_to_be64(gl->phys_addr[pidx]) : 0UL;
  92. skb->priority = CPL_PRIORITY_CONTROL;
  93. cxgb3_ofld_send(ddp->tdev, skb);
  94. }
  95. return 0;
  96. }
  97. static int clear_ddp_map(struct cxgb3i_ddp_info *ddp, unsigned int idx,
  98. unsigned int npods)
  99. {
  100. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ddp->llimit;
  101. int i;
  102. for (i = 0; i < npods; i++, idx++, pm_addr += PPOD_SIZE) {
  103. struct sk_buff *skb = ddp->gl_skb[idx];
  104. ddp->gl_skb[idx] = NULL;
  105. memset((skb->head + sizeof(struct ulp_mem_io)), 0, PPOD_SIZE);
  106. ulp_mem_io_set_hdr(skb, pm_addr);
  107. skb->priority = CPL_PRIORITY_CONTROL;
  108. cxgb3_ofld_send(ddp->tdev, skb);
  109. }
  110. return 0;
  111. }
  112. static inline int ddp_find_unused_entries(struct cxgb3i_ddp_info *ddp,
  113. int start, int max, int count,
  114. struct cxgb3i_gather_list *gl)
  115. {
  116. unsigned int i, j;
  117. spin_lock(&ddp->map_lock);
  118. for (i = start; i <= max;) {
  119. for (j = 0; j < count; j++) {
  120. if (ddp->gl_map[i + j])
  121. break;
  122. }
  123. if (j == count) {
  124. for (j = 0; j < count; j++)
  125. ddp->gl_map[i + j] = gl;
  126. spin_unlock(&ddp->map_lock);
  127. return i;
  128. }
  129. i += j + 1;
  130. }
  131. spin_unlock(&ddp->map_lock);
  132. return -EBUSY;
  133. }
  134. static inline void ddp_unmark_entries(struct cxgb3i_ddp_info *ddp,
  135. int start, int count)
  136. {
  137. spin_lock(&ddp->map_lock);
  138. memset(&ddp->gl_map[start], 0,
  139. count * sizeof(struct cxgb3i_gather_list *));
  140. spin_unlock(&ddp->map_lock);
  141. }
  142. static inline void ddp_free_gl_skb(struct cxgb3i_ddp_info *ddp,
  143. int idx, int count)
  144. {
  145. int i;
  146. for (i = 0; i < count; i++, idx++)
  147. if (ddp->gl_skb[idx]) {
  148. kfree_skb(ddp->gl_skb[idx]);
  149. ddp->gl_skb[idx] = NULL;
  150. }
  151. }
  152. static inline int ddp_alloc_gl_skb(struct cxgb3i_ddp_info *ddp, int idx,
  153. int count, gfp_t gfp)
  154. {
  155. int i;
  156. for (i = 0; i < count; i++) {
  157. struct sk_buff *skb = alloc_skb(sizeof(struct ulp_mem_io) +
  158. PPOD_SIZE, gfp);
  159. if (skb) {
  160. ddp->gl_skb[idx + i] = skb;
  161. skb_put(skb, sizeof(struct ulp_mem_io) + PPOD_SIZE);
  162. } else {
  163. ddp_free_gl_skb(ddp, idx, i);
  164. return -ENOMEM;
  165. }
  166. }
  167. return 0;
  168. }
  169. /**
  170. * cxgb3i_ddp_find_page_index - return ddp page index for a given page size
  171. * @pgsz: page size
  172. * return the ddp page index, if no match is found return DDP_PGIDX_MAX.
  173. */
  174. int cxgb3i_ddp_find_page_index(unsigned long pgsz)
  175. {
  176. int i;
  177. for (i = 0; i < DDP_PGIDX_MAX; i++) {
  178. if (pgsz == (1UL << ddp_page_shift[i]))
  179. return i;
  180. }
  181. ddp_log_debug("ddp page size 0x%lx not supported.\n", pgsz);
  182. return DDP_PGIDX_MAX;
  183. }
  184. EXPORT_SYMBOL_GPL(cxgb3i_ddp_find_page_index);
  185. static inline void ddp_gl_unmap(struct pci_dev *pdev,
  186. struct cxgb3i_gather_list *gl)
  187. {
  188. int i;
  189. for (i = 0; i < gl->nelem; i++)
  190. pci_unmap_page(pdev, gl->phys_addr[i], PAGE_SIZE,
  191. PCI_DMA_FROMDEVICE);
  192. }
  193. static inline int ddp_gl_map(struct pci_dev *pdev,
  194. struct cxgb3i_gather_list *gl)
  195. {
  196. int i;
  197. for (i = 0; i < gl->nelem; i++) {
  198. gl->phys_addr[i] = pci_map_page(pdev, gl->pages[i], 0,
  199. PAGE_SIZE,
  200. PCI_DMA_FROMDEVICE);
  201. if (unlikely(pci_dma_mapping_error(pdev, gl->phys_addr[i])))
  202. goto unmap;
  203. }
  204. return i;
  205. unmap:
  206. if (i) {
  207. unsigned int nelem = gl->nelem;
  208. gl->nelem = i;
  209. ddp_gl_unmap(pdev, gl);
  210. gl->nelem = nelem;
  211. }
  212. return -ENOMEM;
  213. }
  214. /**
  215. * cxgb3i_ddp_make_gl - build ddp page buffer list
  216. * @xferlen: total buffer length
  217. * @sgl: page buffer scatter-gather list
  218. * @sgcnt: # of page buffers
  219. * @pdev: pci_dev, used for pci map
  220. * @gfp: allocation mode
  221. *
  222. * construct a ddp page buffer list from the scsi scattergather list.
  223. * coalesce buffers as much as possible, and obtain dma addresses for
  224. * each page.
  225. *
  226. * Return the cxgb3i_gather_list constructed from the page buffers if the
  227. * memory can be used for ddp. Return NULL otherwise.
  228. */
  229. struct cxgb3i_gather_list *cxgb3i_ddp_make_gl(unsigned int xferlen,
  230. struct scatterlist *sgl,
  231. unsigned int sgcnt,
  232. struct pci_dev *pdev,
  233. gfp_t gfp)
  234. {
  235. struct cxgb3i_gather_list *gl;
  236. struct scatterlist *sg = sgl;
  237. struct page *sgpage = sg_page(sg);
  238. unsigned int sglen = sg->length;
  239. unsigned int sgoffset = sg->offset;
  240. unsigned int npages = (xferlen + sgoffset + PAGE_SIZE - 1) >>
  241. PAGE_SHIFT;
  242. int i = 1, j = 0;
  243. if (xferlen < DDP_THRESHOLD) {
  244. ddp_log_debug("xfer %u < threshold %u, no ddp.\n",
  245. xferlen, DDP_THRESHOLD);
  246. return NULL;
  247. }
  248. gl = kzalloc(sizeof(struct cxgb3i_gather_list) +
  249. npages * (sizeof(dma_addr_t) + sizeof(struct page *)),
  250. gfp);
  251. if (!gl)
  252. return NULL;
  253. gl->pages = (struct page **)&gl->phys_addr[npages];
  254. gl->length = xferlen;
  255. gl->offset = sgoffset;
  256. gl->pages[0] = sgpage;
  257. sg = sg_next(sg);
  258. while (sg) {
  259. struct page *page = sg_page(sg);
  260. if (sgpage == page && sg->offset == sgoffset + sglen)
  261. sglen += sg->length;
  262. else {
  263. /* make sure the sgl is fit for ddp:
  264. * each has the same page size, and
  265. * all of the middle pages are used completely
  266. */
  267. if ((j && sgoffset) ||
  268. ((i != sgcnt - 1) &&
  269. ((sglen + sgoffset) & ~PAGE_MASK)))
  270. goto error_out;
  271. j++;
  272. if (j == gl->nelem || sg->offset)
  273. goto error_out;
  274. gl->pages[j] = page;
  275. sglen = sg->length;
  276. sgoffset = sg->offset;
  277. sgpage = page;
  278. }
  279. i++;
  280. sg = sg_next(sg);
  281. }
  282. gl->nelem = ++j;
  283. if (ddp_gl_map(pdev, gl) < 0)
  284. goto error_out;
  285. return gl;
  286. error_out:
  287. kfree(gl);
  288. return NULL;
  289. }
  290. EXPORT_SYMBOL_GPL(cxgb3i_ddp_make_gl);
  291. /**
  292. * cxgb3i_ddp_release_gl - release a page buffer list
  293. * @gl: a ddp page buffer list
  294. * @pdev: pci_dev used for pci_unmap
  295. * free a ddp page buffer list resulted from cxgb3i_ddp_make_gl().
  296. */
  297. void cxgb3i_ddp_release_gl(struct cxgb3i_gather_list *gl,
  298. struct pci_dev *pdev)
  299. {
  300. ddp_gl_unmap(pdev, gl);
  301. kfree(gl);
  302. }
  303. EXPORT_SYMBOL_GPL(cxgb3i_ddp_release_gl);
  304. /**
  305. * cxgb3i_ddp_tag_reserve - set up ddp for a data transfer
  306. * @tdev: t3cdev adapter
  307. * @tid: connection id
  308. * @tformat: tag format
  309. * @tagp: contains s/w tag initially, will be updated with ddp/hw tag
  310. * @gl: the page momory list
  311. * @gfp: allocation mode
  312. *
  313. * ddp setup for a given page buffer list and construct the ddp tag.
  314. * return 0 if success, < 0 otherwise.
  315. */
  316. int cxgb3i_ddp_tag_reserve(struct t3cdev *tdev, unsigned int tid,
  317. struct cxgb3i_tag_format *tformat, u32 *tagp,
  318. struct cxgb3i_gather_list *gl, gfp_t gfp)
  319. {
  320. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  321. struct pagepod_hdr hdr;
  322. unsigned int npods;
  323. int idx = -1, idx_max;
  324. int err = -ENOMEM;
  325. u32 sw_tag = *tagp;
  326. u32 tag;
  327. if (page_idx >= DDP_PGIDX_MAX || !ddp || !gl || !gl->nelem ||
  328. gl->length < DDP_THRESHOLD) {
  329. ddp_log_debug("pgidx %u, xfer %u/%u, NO ddp.\n",
  330. page_idx, gl->length, DDP_THRESHOLD);
  331. return -EINVAL;
  332. }
  333. npods = (gl->nelem + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
  334. idx_max = ddp->nppods - npods + 1;
  335. if (ddp->idx_last == ddp->nppods)
  336. idx = ddp_find_unused_entries(ddp, 0, idx_max, npods, gl);
  337. else {
  338. idx = ddp_find_unused_entries(ddp, ddp->idx_last + 1,
  339. idx_max, npods, gl);
  340. if (idx < 0 && ddp->idx_last >= npods)
  341. idx = ddp_find_unused_entries(ddp, 0,
  342. ddp->idx_last - npods + 1,
  343. npods, gl);
  344. }
  345. if (idx < 0) {
  346. ddp_log_debug("xferlen %u, gl %u, npods %u NO DDP.\n",
  347. gl->length, gl->nelem, npods);
  348. return idx;
  349. }
  350. err = ddp_alloc_gl_skb(ddp, idx, npods, gfp);
  351. if (err < 0)
  352. goto unmark_entries;
  353. tag = cxgb3i_ddp_tag_base(tformat, sw_tag);
  354. tag |= idx << PPOD_IDX_SHIFT;
  355. hdr.rsvd = 0;
  356. hdr.vld_tid = htonl(F_PPOD_VALID | V_PPOD_TID(tid));
  357. hdr.pgsz_tag_clr = htonl(tag & ddp->rsvd_tag_mask);
  358. hdr.maxoffset = htonl(gl->length);
  359. hdr.pgoffset = htonl(gl->offset);
  360. err = set_ddp_map(ddp, &hdr, idx, npods, gl);
  361. if (err < 0)
  362. goto free_gl_skb;
  363. ddp->idx_last = idx;
  364. ddp_log_debug("xfer %u, gl %u,%u, tid 0x%x, 0x%x -> 0x%x(%u,%u).\n",
  365. gl->length, gl->nelem, gl->offset, tid, sw_tag, tag,
  366. idx, npods);
  367. *tagp = tag;
  368. return 0;
  369. free_gl_skb:
  370. ddp_free_gl_skb(ddp, idx, npods);
  371. unmark_entries:
  372. ddp_unmark_entries(ddp, idx, npods);
  373. return err;
  374. }
  375. EXPORT_SYMBOL_GPL(cxgb3i_ddp_tag_reserve);
  376. /**
  377. * cxgb3i_ddp_tag_release - release a ddp tag
  378. * @tdev: t3cdev adapter
  379. * @tag: ddp tag
  380. * ddp cleanup for a given ddp tag and release all the resources held
  381. */
  382. void cxgb3i_ddp_tag_release(struct t3cdev *tdev, u32 tag)
  383. {
  384. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  385. u32 idx;
  386. if (!ddp) {
  387. ddp_log_error("release ddp tag 0x%x, ddp NULL.\n", tag);
  388. return;
  389. }
  390. idx = (tag >> PPOD_IDX_SHIFT) & ddp->idx_mask;
  391. if (idx < ddp->nppods) {
  392. struct cxgb3i_gather_list *gl = ddp->gl_map[idx];
  393. unsigned int npods;
  394. if (!gl) {
  395. ddp_log_error("release ddp 0x%x, idx 0x%x, gl NULL.\n",
  396. tag, idx);
  397. return;
  398. }
  399. npods = (gl->nelem + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
  400. ddp_log_debug("ddp tag 0x%x, release idx 0x%x, npods %u.\n",
  401. tag, idx, npods);
  402. clear_ddp_map(ddp, idx, npods);
  403. ddp_unmark_entries(ddp, idx, npods);
  404. cxgb3i_ddp_release_gl(gl, ddp->pdev);
  405. } else
  406. ddp_log_error("ddp tag 0x%x, idx 0x%x > max 0x%x.\n",
  407. tag, idx, ddp->nppods);
  408. }
  409. EXPORT_SYMBOL_GPL(cxgb3i_ddp_tag_release);
  410. static int setup_conn_pgidx(struct t3cdev *tdev, unsigned int tid, int pg_idx,
  411. int reply)
  412. {
  413. struct sk_buff *skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
  414. GFP_KERNEL);
  415. struct cpl_set_tcb_field *req;
  416. u64 val = pg_idx < DDP_PGIDX_MAX ? pg_idx : 0;
  417. if (!skb)
  418. return -ENOMEM;
  419. /* set up ulp submode and page size */
  420. req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req));
  421. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
  422. OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
  423. req->reply = V_NO_REPLY(reply ? 0 : 1);
  424. req->cpu_idx = 0;
  425. req->word = htons(31);
  426. req->mask = cpu_to_be64(0xF0000000);
  427. req->val = cpu_to_be64(val << 28);
  428. skb->priority = CPL_PRIORITY_CONTROL;
  429. cxgb3_ofld_send(tdev, skb);
  430. return 0;
  431. }
  432. /**
  433. * cxgb3i_setup_conn_host_pagesize - setup the conn.'s ddp page size
  434. * @tdev: t3cdev adapter
  435. * @tid: connection id
  436. * @reply: request reply from h/w
  437. * set up the ddp page size based on the host PAGE_SIZE for a connection
  438. * identified by tid
  439. */
  440. int cxgb3i_setup_conn_host_pagesize(struct t3cdev *tdev, unsigned int tid,
  441. int reply)
  442. {
  443. return setup_conn_pgidx(tdev, tid, page_idx, reply);
  444. }
  445. EXPORT_SYMBOL_GPL(cxgb3i_setup_conn_host_pagesize);
  446. /**
  447. * cxgb3i_setup_conn_pagesize - setup the conn.'s ddp page size
  448. * @tdev: t3cdev adapter
  449. * @tid: connection id
  450. * @reply: request reply from h/w
  451. * @pgsz: ddp page size
  452. * set up the ddp page size for a connection identified by tid
  453. */
  454. int cxgb3i_setup_conn_pagesize(struct t3cdev *tdev, unsigned int tid,
  455. int reply, unsigned long pgsz)
  456. {
  457. int pgidx = cxgb3i_ddp_find_page_index(pgsz);
  458. return setup_conn_pgidx(tdev, tid, pgidx, reply);
  459. }
  460. EXPORT_SYMBOL_GPL(cxgb3i_setup_conn_pagesize);
  461. /**
  462. * cxgb3i_setup_conn_digest - setup conn. digest setting
  463. * @tdev: t3cdev adapter
  464. * @tid: connection id
  465. * @hcrc: header digest enabled
  466. * @dcrc: data digest enabled
  467. * @reply: request reply from h/w
  468. * set up the iscsi digest settings for a connection identified by tid
  469. */
  470. int cxgb3i_setup_conn_digest(struct t3cdev *tdev, unsigned int tid,
  471. int hcrc, int dcrc, int reply)
  472. {
  473. struct sk_buff *skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
  474. GFP_KERNEL);
  475. struct cpl_set_tcb_field *req;
  476. u64 val = (hcrc ? 1 : 0) | (dcrc ? 2 : 0);
  477. if (!skb)
  478. return -ENOMEM;
  479. /* set up ulp submode and page size */
  480. req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req));
  481. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
  482. OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
  483. req->reply = V_NO_REPLY(reply ? 0 : 1);
  484. req->cpu_idx = 0;
  485. req->word = htons(31);
  486. req->mask = cpu_to_be64(0x0F000000);
  487. req->val = cpu_to_be64(val << 24);
  488. skb->priority = CPL_PRIORITY_CONTROL;
  489. cxgb3_ofld_send(tdev, skb);
  490. return 0;
  491. }
  492. EXPORT_SYMBOL_GPL(cxgb3i_setup_conn_digest);
  493. static int ddp_init(struct t3cdev *tdev)
  494. {
  495. struct cxgb3i_ddp_info *ddp;
  496. struct ulp_iscsi_info uinfo;
  497. unsigned int ppmax, bits;
  498. int i, err;
  499. static int vers_printed;
  500. if (!vers_printed) {
  501. printk(KERN_INFO "%s", version);
  502. vers_printed = 1;
  503. }
  504. err = tdev->ctl(tdev, ULP_ISCSI_GET_PARAMS, &uinfo);
  505. if (err < 0) {
  506. ddp_log_error("%s, failed to get iscsi param err=%d.\n",
  507. tdev->name, err);
  508. return err;
  509. }
  510. ppmax = (uinfo.ulimit - uinfo.llimit + 1) >> PPOD_SIZE_SHIFT;
  511. bits = __ilog2_u32(ppmax) + 1;
  512. if (bits > PPOD_IDX_MAX_SIZE)
  513. bits = PPOD_IDX_MAX_SIZE;
  514. ppmax = (1 << (bits - 1)) - 1;
  515. ddp = cxgb3i_alloc_big_mem(sizeof(struct cxgb3i_ddp_info) +
  516. ppmax *
  517. (sizeof(struct cxgb3i_gather_list *) +
  518. sizeof(struct sk_buff *)),
  519. GFP_KERNEL);
  520. if (!ddp) {
  521. ddp_log_warn("%s unable to alloc ddp 0x%d, ddp disabled.\n",
  522. tdev->name, ppmax);
  523. return 0;
  524. }
  525. ddp->gl_map = (struct cxgb3i_gather_list **)(ddp + 1);
  526. ddp->gl_skb = (struct sk_buff **)(((char *)ddp->gl_map) +
  527. ppmax *
  528. sizeof(struct cxgb3i_gather_list *));
  529. spin_lock_init(&ddp->map_lock);
  530. ddp->tdev = tdev;
  531. ddp->pdev = uinfo.pdev;
  532. ddp->max_txsz = min_t(unsigned int, uinfo.max_txsz, ULP2_MAX_PKT_SIZE);
  533. ddp->max_rxsz = min_t(unsigned int, uinfo.max_rxsz, ULP2_MAX_PKT_SIZE);
  534. ddp->llimit = uinfo.llimit;
  535. ddp->ulimit = uinfo.ulimit;
  536. ddp->nppods = ppmax;
  537. ddp->idx_last = ppmax;
  538. ddp->idx_bits = bits;
  539. ddp->idx_mask = (1 << bits) - 1;
  540. ddp->rsvd_tag_mask = (1 << (bits + PPOD_IDX_SHIFT)) - 1;
  541. uinfo.tagmask = ddp->idx_mask << PPOD_IDX_SHIFT;
  542. for (i = 0; i < DDP_PGIDX_MAX; i++)
  543. uinfo.pgsz_factor[i] = ddp_page_order[i];
  544. uinfo.ulimit = uinfo.llimit + (ppmax << PPOD_SIZE_SHIFT);
  545. err = tdev->ctl(tdev, ULP_ISCSI_SET_PARAMS, &uinfo);
  546. if (err < 0) {
  547. ddp_log_warn("%s unable to set iscsi param err=%d, "
  548. "ddp disabled.\n", tdev->name, err);
  549. goto free_ddp_map;
  550. }
  551. tdev->ulp_iscsi = ddp;
  552. /* add to the list */
  553. write_lock(&cxgb3i_ddp_rwlock);
  554. list_add_tail(&ddp->list, &cxgb3i_ddp_list);
  555. write_unlock(&cxgb3i_ddp_rwlock);
  556. ddp_log_info("nppods %u (0x%x ~ 0x%x), bits %u, mask 0x%x,0x%x "
  557. "pkt %u/%u, %u/%u.\n",
  558. ppmax, ddp->llimit, ddp->ulimit, ddp->idx_bits,
  559. ddp->idx_mask, ddp->rsvd_tag_mask,
  560. ddp->max_txsz, uinfo.max_txsz,
  561. ddp->max_rxsz, uinfo.max_rxsz);
  562. return 0;
  563. free_ddp_map:
  564. cxgb3i_free_big_mem(ddp);
  565. return err;
  566. }
  567. /**
  568. * cxgb3i_adapter_ddp_init - initialize the adapter's ddp resource
  569. * @tdev: t3cdev adapter
  570. * @tformat: tag format
  571. * @txsz: max tx pdu payload size, filled in by this func.
  572. * @rxsz: max rx pdu payload size, filled in by this func.
  573. * initialize the ddp pagepod manager for a given adapter if needed and
  574. * setup the tag format for a given iscsi entity
  575. */
  576. int cxgb3i_adapter_ddp_init(struct t3cdev *tdev,
  577. struct cxgb3i_tag_format *tformat,
  578. unsigned int *txsz, unsigned int *rxsz)
  579. {
  580. struct cxgb3i_ddp_info *ddp;
  581. unsigned char idx_bits;
  582. if (!tformat)
  583. return -EINVAL;
  584. if (!tdev->ulp_iscsi) {
  585. int err = ddp_init(tdev);
  586. if (err < 0)
  587. return err;
  588. }
  589. ddp = (struct cxgb3i_ddp_info *)tdev->ulp_iscsi;
  590. idx_bits = 32 - tformat->sw_bits;
  591. tformat->rsvd_bits = ddp->idx_bits;
  592. tformat->rsvd_shift = PPOD_IDX_SHIFT;
  593. tformat->rsvd_mask = (1 << tformat->rsvd_bits) - 1;
  594. ddp_log_info("tag format: sw %u, rsvd %u,%u, mask 0x%x.\n",
  595. tformat->sw_bits, tformat->rsvd_bits,
  596. tformat->rsvd_shift, tformat->rsvd_mask);
  597. *txsz = min_t(unsigned int, ULP2_MAX_PDU_PAYLOAD,
  598. ddp->max_txsz - ISCSI_PDU_NONPAYLOAD_LEN);
  599. *rxsz = min_t(unsigned int, ULP2_MAX_PDU_PAYLOAD,
  600. ddp->max_rxsz - ISCSI_PDU_NONPAYLOAD_LEN);
  601. ddp_log_info("max payload size: %u/%u, %u/%u.\n",
  602. *txsz, ddp->max_txsz, *rxsz, ddp->max_rxsz);
  603. return 0;
  604. }
  605. EXPORT_SYMBOL_GPL(cxgb3i_adapter_ddp_init);
  606. static void ddp_release(struct cxgb3i_ddp_info *ddp)
  607. {
  608. int i = 0;
  609. struct t3cdev *tdev = ddp->tdev;
  610. tdev->ulp_iscsi = NULL;
  611. while (i < ddp->nppods) {
  612. struct cxgb3i_gather_list *gl = ddp->gl_map[i];
  613. if (gl) {
  614. int npods = (gl->nelem + PPOD_PAGES_MAX - 1)
  615. >> PPOD_PAGES_SHIFT;
  616. kfree(gl);
  617. ddp_free_gl_skb(ddp, i, npods);
  618. } else
  619. i++;
  620. }
  621. cxgb3i_free_big_mem(ddp);
  622. }
  623. /**
  624. * cxgb3i_adapter_ddp_cleanup - release the adapter's ddp resource
  625. * @tdev: t3cdev adapter
  626. * release all the resource held by the ddp pagepod manager for a given
  627. * adapter if needed
  628. */
  629. void cxgb3i_adapter_ddp_cleanup(struct t3cdev *tdev)
  630. {
  631. struct cxgb3i_ddp_info *ddp;
  632. /* remove from the list */
  633. write_lock(&cxgb3i_ddp_rwlock);
  634. list_for_each_entry(ddp, &cxgb3i_ddp_list, list) {
  635. if (ddp->tdev == tdev) {
  636. list_del(&ddp->list);
  637. break;
  638. }
  639. }
  640. write_unlock(&cxgb3i_ddp_rwlock);
  641. if (ddp)
  642. ddp_release(ddp);
  643. }
  644. EXPORT_SYMBOL_GPL(cxgb3i_adapter_ddp_cleanup);
  645. /**
  646. * cxgb3i_ddp_init_module - module init entry point
  647. * initialize any driver wide global data structures
  648. */
  649. static int __init cxgb3i_ddp_init_module(void)
  650. {
  651. page_idx = cxgb3i_ddp_find_page_index(PAGE_SIZE);
  652. ddp_log_info("system PAGE_SIZE %lu, ddp idx %u.\n",
  653. PAGE_SIZE, page_idx);
  654. return 0;
  655. }
  656. /**
  657. * cxgb3i_ddp_exit_module - module cleanup/exit entry point
  658. * go through the ddp list and release any resource held.
  659. */
  660. static void __exit cxgb3i_ddp_exit_module(void)
  661. {
  662. struct cxgb3i_ddp_info *ddp;
  663. /* release all ddp manager if there is any */
  664. write_lock(&cxgb3i_ddp_rwlock);
  665. list_for_each_entry(ddp, &cxgb3i_ddp_list, list) {
  666. list_del(&ddp->list);
  667. ddp_release(ddp);
  668. }
  669. write_unlock(&cxgb3i_ddp_rwlock);
  670. }
  671. module_init(cxgb3i_ddp_init_module);
  672. module_exit(cxgb3i_ddp_exit_module);