at91sam9g45.dtsi 12 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc003ff /* pioA */
  102. 0xffffffff 0x800f8f00 /* pioB */
  103. 0xffffffff 0x00000e00 /* pioC */
  104. 0xffffffff 0xff0c1381 /* pioD */
  105. 0xffffffff 0x81ffff81 /* pioE */
  106. >;
  107. /* shared pinctrl settings */
  108. dbgu {
  109. pinctrl_dbgu: dbgu-0 {
  110. atmel,pins =
  111. <1 12 0x1 0x0 /* PB12 periph A */
  112. 1 13 0x1 0x0>; /* PB13 periph A */
  113. };
  114. };
  115. usart0 {
  116. pinctrl_usart0: usart0-0 {
  117. atmel,pins =
  118. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  119. 1 18 0x1 0x0>; /* PB18 periph A */
  120. };
  121. pinctrl_usart0_rts: usart0_rts-0 {
  122. atmel,pins =
  123. <1 17 0x2 0x0>; /* PB17 periph B */
  124. };
  125. pinctrl_usart0_cts: usart0_cts-0 {
  126. atmel,pins =
  127. <1 15 0x2 0x0>; /* PB15 periph B */
  128. };
  129. };
  130. uart1 {
  131. pinctrl_usart1: usart1-0 {
  132. atmel,pins =
  133. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  134. 1 5 0x1 0x0>; /* PB5 periph A */
  135. };
  136. pinctrl_usart1_rts: usart1_rts-0 {
  137. atmel,pins =
  138. <3 16 0x1 0x0>; /* PD16 periph A */
  139. };
  140. pinctrl_usart1_cts: usart1_cts-0 {
  141. atmel,pins =
  142. <3 17 0x1 0x0>; /* PD17 periph A */
  143. };
  144. };
  145. usart2 {
  146. pinctrl_usart2: usart2-0 {
  147. atmel,pins =
  148. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  149. 1 7 0x1 0x0>; /* PB7 periph A */
  150. };
  151. pinctrl_usart2_rts: usart2_rts-0 {
  152. atmel,pins =
  153. <2 9 0x2 0x0>; /* PC9 periph B */
  154. };
  155. pinctrl_usart2_cts: usart2_cts-0 {
  156. atmel,pins =
  157. <2 11 0x2 0x0>; /* PC11 periph B */
  158. };
  159. };
  160. usart3 {
  161. pinctrl_usart3: usart3-0 {
  162. atmel,pins =
  163. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  164. 1 9 0x1 0x0>; /* PB8 periph A */
  165. };
  166. pinctrl_usart3_rts: usart3_rts-0 {
  167. atmel,pins =
  168. <0 23 0x2 0x0>; /* PA23 periph B */
  169. };
  170. pinctrl_usart3_cts: usart3_cts-0 {
  171. atmel,pins =
  172. <0 24 0x2 0x0>; /* PA24 periph B */
  173. };
  174. };
  175. nand {
  176. pinctrl_nand: nand-0 {
  177. atmel,pins =
  178. <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
  179. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  180. };
  181. };
  182. macb {
  183. pinctrl_macb_rmii: macb_rmii-0 {
  184. atmel,pins =
  185. <0 10 0x1 0x0 /* PA10 periph A */
  186. 0 11 0x1 0x0 /* PA11 periph A */
  187. 0 12 0x1 0x0 /* PA12 periph A */
  188. 0 13 0x1 0x0 /* PA13 periph A */
  189. 0 14 0x1 0x0 /* PA14 periph A */
  190. 0 15 0x1 0x0 /* PA15 periph A */
  191. 0 16 0x1 0x0 /* PA16 periph A */
  192. 0 17 0x1 0x0 /* PA17 periph A */
  193. 0 18 0x1 0x0 /* PA18 periph A */
  194. 0 19 0x1 0x0>; /* PA19 periph A */
  195. };
  196. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  197. atmel,pins =
  198. <0 6 0x2 0x0 /* PA6 periph B */
  199. 0 7 0x2 0x0 /* PA7 periph B */
  200. 0 8 0x2 0x0 /* PA8 periph B */
  201. 0 9 0x2 0x0 /* PA9 periph B */
  202. 0 27 0x2 0x0 /* PA27 periph B */
  203. 0 28 0x2 0x0 /* PA28 periph B */
  204. 0 29 0x2 0x0 /* PA29 periph B */
  205. 0 30 0x2 0x0>; /* PA30 periph B */
  206. };
  207. };
  208. mmc0 {
  209. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  210. atmel,pins =
  211. <0 0 0x1 0x0 /* PA0 periph A */
  212. 0 1 0x1 0x1 /* PA1 periph A with pullup */
  213. 0 2 0x1 0x1>; /* PA2 periph A with pullup */
  214. };
  215. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  216. atmel,pins =
  217. <0 3 0x1 0x1 /* PA3 periph A with pullup */
  218. 0 4 0x1 0x1 /* PA4 periph A with pullup */
  219. 0 5 0x1 0x1>; /* PA5 periph A with pullup */
  220. };
  221. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  222. atmel,pins =
  223. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  224. 0 7 0x1 0x1 /* PA7 periph A with pullup */
  225. 0 8 0x1 0x1 /* PA8 periph A with pullup */
  226. 0 9 0x1 0x1>; /* PA9 periph A with pullup */
  227. };
  228. };
  229. mmc1 {
  230. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  231. atmel,pins =
  232. <0 31 0x1 0x0 /* PA31 periph A */
  233. 0 22 0x1 0x1 /* PA22 periph A with pullup */
  234. 0 23 0x1 0x1>; /* PA23 periph A with pullup */
  235. };
  236. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  237. atmel,pins =
  238. <0 24 0x1 0x1 /* PA24 periph A with pullup */
  239. 0 25 0x1 0x1 /* PA25 periph A with pullup */
  240. 0 26 0x1 0x1>; /* PA26 periph A with pullup */
  241. };
  242. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  243. atmel,pins =
  244. <0 27 0x1 0x1 /* PA27 periph A with pullup */
  245. 0 28 0x1 0x1 /* PA28 periph A with pullup */
  246. 0 29 0x1 0x1 /* PA29 periph A with pullup */
  247. 0 20 0x1 0x1>; /* PA30 periph A with pullup */
  248. };
  249. };
  250. pioA: gpio@fffff200 {
  251. compatible = "atmel,at91rm9200-gpio";
  252. reg = <0xfffff200 0x200>;
  253. interrupts = <2 4 1>;
  254. #gpio-cells = <2>;
  255. gpio-controller;
  256. interrupt-controller;
  257. #interrupt-cells = <2>;
  258. };
  259. pioB: gpio@fffff400 {
  260. compatible = "atmel,at91rm9200-gpio";
  261. reg = <0xfffff400 0x200>;
  262. interrupts = <3 4 1>;
  263. #gpio-cells = <2>;
  264. gpio-controller;
  265. interrupt-controller;
  266. #interrupt-cells = <2>;
  267. };
  268. pioC: gpio@fffff600 {
  269. compatible = "atmel,at91rm9200-gpio";
  270. reg = <0xfffff600 0x200>;
  271. interrupts = <4 4 1>;
  272. #gpio-cells = <2>;
  273. gpio-controller;
  274. interrupt-controller;
  275. #interrupt-cells = <2>;
  276. };
  277. pioD: gpio@fffff800 {
  278. compatible = "atmel,at91rm9200-gpio";
  279. reg = <0xfffff800 0x200>;
  280. interrupts = <5 4 1>;
  281. #gpio-cells = <2>;
  282. gpio-controller;
  283. interrupt-controller;
  284. #interrupt-cells = <2>;
  285. };
  286. pioE: gpio@fffffa00 {
  287. compatible = "atmel,at91rm9200-gpio";
  288. reg = <0xfffffa00 0x200>;
  289. interrupts = <5 4 1>;
  290. #gpio-cells = <2>;
  291. gpio-controller;
  292. interrupt-controller;
  293. #interrupt-cells = <2>;
  294. };
  295. };
  296. dbgu: serial@ffffee00 {
  297. compatible = "atmel,at91sam9260-usart";
  298. reg = <0xffffee00 0x200>;
  299. interrupts = <1 4 7>;
  300. pinctrl-names = "default";
  301. pinctrl-0 = <&pinctrl_dbgu>;
  302. status = "disabled";
  303. };
  304. usart0: serial@fff8c000 {
  305. compatible = "atmel,at91sam9260-usart";
  306. reg = <0xfff8c000 0x200>;
  307. interrupts = <7 4 5>;
  308. atmel,use-dma-rx;
  309. atmel,use-dma-tx;
  310. pinctrl-names = "default";
  311. pinctrl-0 = <&pinctrl_usart0>;
  312. status = "disabled";
  313. };
  314. usart1: serial@fff90000 {
  315. compatible = "atmel,at91sam9260-usart";
  316. reg = <0xfff90000 0x200>;
  317. interrupts = <8 4 5>;
  318. atmel,use-dma-rx;
  319. atmel,use-dma-tx;
  320. pinctrl-names = "default";
  321. pinctrl-0 = <&pinctrl_usart1>;
  322. status = "disabled";
  323. };
  324. usart2: serial@fff94000 {
  325. compatible = "atmel,at91sam9260-usart";
  326. reg = <0xfff94000 0x200>;
  327. interrupts = <9 4 5>;
  328. atmel,use-dma-rx;
  329. atmel,use-dma-tx;
  330. pinctrl-names = "default";
  331. pinctrl-0 = <&pinctrl_usart2>;
  332. status = "disabled";
  333. };
  334. usart3: serial@fff98000 {
  335. compatible = "atmel,at91sam9260-usart";
  336. reg = <0xfff98000 0x200>;
  337. interrupts = <10 4 5>;
  338. atmel,use-dma-rx;
  339. atmel,use-dma-tx;
  340. pinctrl-names = "default";
  341. pinctrl-0 = <&pinctrl_usart3>;
  342. status = "disabled";
  343. };
  344. macb0: ethernet@fffbc000 {
  345. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  346. reg = <0xfffbc000 0x100>;
  347. interrupts = <25 4 3>;
  348. pinctrl-names = "default";
  349. pinctrl-0 = <&pinctrl_macb_rmii>;
  350. status = "disabled";
  351. };
  352. i2c0: i2c@fff84000 {
  353. compatible = "atmel,at91sam9g10-i2c";
  354. reg = <0xfff84000 0x100>;
  355. interrupts = <12 4 6>;
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. status = "disabled";
  359. };
  360. i2c1: i2c@fff88000 {
  361. compatible = "atmel,at91sam9g10-i2c";
  362. reg = <0xfff88000 0x100>;
  363. interrupts = <13 4 6>;
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. status = "disabled";
  367. };
  368. adc0: adc@fffb0000 {
  369. compatible = "atmel,at91sam9260-adc";
  370. reg = <0xfffb0000 0x100>;
  371. interrupts = <20 4 0>;
  372. atmel,adc-use-external-triggers;
  373. atmel,adc-channels-used = <0xff>;
  374. atmel,adc-vref = <3300>;
  375. atmel,adc-num-channels = <8>;
  376. atmel,adc-startup-time = <40>;
  377. atmel,adc-channel-base = <0x30>;
  378. atmel,adc-drdy-mask = <0x10000>;
  379. atmel,adc-status-register = <0x1c>;
  380. atmel,adc-trigger-register = <0x08>;
  381. trigger@0 {
  382. trigger-name = "external-rising";
  383. trigger-value = <0x1>;
  384. trigger-external;
  385. };
  386. trigger@1 {
  387. trigger-name = "external-falling";
  388. trigger-value = <0x2>;
  389. trigger-external;
  390. };
  391. trigger@2 {
  392. trigger-name = "external-any";
  393. trigger-value = <0x3>;
  394. trigger-external;
  395. };
  396. trigger@3 {
  397. trigger-name = "continuous";
  398. trigger-value = <0x6>;
  399. };
  400. };
  401. mmc0: mmc@fff80000 {
  402. compatible = "atmel,hsmci";
  403. reg = <0xfff80000 0x600>;
  404. interrupts = <11 4 0>;
  405. #address-cells = <1>;
  406. #size-cells = <0>;
  407. status = "disabled";
  408. };
  409. mmc1: mmc@fffd0000 {
  410. compatible = "atmel,hsmci";
  411. reg = <0xfffd0000 0x600>;
  412. interrupts = <29 4 0>;
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. status = "disabled";
  416. };
  417. };
  418. nand0: nand@40000000 {
  419. compatible = "atmel,at91rm9200-nand";
  420. #address-cells = <1>;
  421. #size-cells = <1>;
  422. reg = <0x40000000 0x10000000
  423. 0xffffe200 0x200
  424. >;
  425. atmel,nand-addr-offset = <21>;
  426. atmel,nand-cmd-offset = <22>;
  427. pinctrl-names = "default";
  428. pinctrl-0 = <&pinctrl_nand>;
  429. gpios = <&pioC 8 0
  430. &pioC 14 0
  431. 0
  432. >;
  433. status = "disabled";
  434. };
  435. usb0: ohci@00700000 {
  436. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  437. reg = <0x00700000 0x100000>;
  438. interrupts = <22 4 2>;
  439. status = "disabled";
  440. };
  441. usb1: ehci@00800000 {
  442. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  443. reg = <0x00800000 0x100000>;
  444. interrupts = <22 4 2>;
  445. status = "disabled";
  446. };
  447. };
  448. i2c@0 {
  449. compatible = "i2c-gpio";
  450. gpios = <&pioA 20 0 /* sda */
  451. &pioA 21 0 /* scl */
  452. >;
  453. i2c-gpio,sda-open-drain;
  454. i2c-gpio,scl-open-drain;
  455. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  456. #address-cells = <1>;
  457. #size-cells = <0>;
  458. status = "disabled";
  459. };
  460. };