dmaengine.h 14 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. #ifndef DMAENGINE_H
  22. #define DMAENGINE_H
  23. #include <linux/device.h>
  24. #include <linux/uio.h>
  25. #include <linux/kref.h>
  26. #include <linux/completion.h>
  27. #include <linux/rcupdate.h>
  28. #include <linux/dma-mapping.h>
  29. /**
  30. * enum dma_state - resource PNP/power management state
  31. * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
  32. * @DMA_RESOURCE_RESUME: DMA device returning to full power
  33. * @DMA_RESOURCE_AVAILABLE: DMA device available to the system
  34. * @DMA_RESOURCE_REMOVED: DMA device removed from the system
  35. */
  36. enum dma_state {
  37. DMA_RESOURCE_SUSPEND,
  38. DMA_RESOURCE_RESUME,
  39. DMA_RESOURCE_AVAILABLE,
  40. DMA_RESOURCE_REMOVED,
  41. };
  42. /**
  43. * enum dma_state_client - state of the channel in the client
  44. * @DMA_ACK: client would like to use, or was using this channel
  45. * @DMA_DUP: client has already seen this channel, or is not using this channel
  46. * @DMA_NAK: client does not want to see any more channels
  47. */
  48. enum dma_state_client {
  49. DMA_ACK,
  50. DMA_DUP,
  51. DMA_NAK,
  52. };
  53. /**
  54. * typedef dma_cookie_t - an opaque DMA cookie
  55. *
  56. * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  57. */
  58. typedef s32 dma_cookie_t;
  59. #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
  60. /**
  61. * enum dma_status - DMA transaction status
  62. * @DMA_SUCCESS: transaction completed successfully
  63. * @DMA_IN_PROGRESS: transaction not yet processed
  64. * @DMA_ERROR: transaction failed
  65. */
  66. enum dma_status {
  67. DMA_SUCCESS,
  68. DMA_IN_PROGRESS,
  69. DMA_ERROR,
  70. };
  71. /**
  72. * enum dma_transaction_type - DMA transaction types/indexes
  73. */
  74. enum dma_transaction_type {
  75. DMA_MEMCPY,
  76. DMA_XOR,
  77. DMA_PQ_XOR,
  78. DMA_DUAL_XOR,
  79. DMA_PQ_UPDATE,
  80. DMA_ZERO_SUM,
  81. DMA_PQ_ZERO_SUM,
  82. DMA_MEMSET,
  83. DMA_MEMCPY_CRC32C,
  84. DMA_INTERRUPT,
  85. };
  86. /* last transaction type for creation of the capabilities mask */
  87. #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
  88. /**
  89. * enum dma_prep_flags - DMA flags to augment operation preparation
  90. * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
  91. * this transaction
  92. */
  93. enum dma_prep_flags {
  94. DMA_PREP_INTERRUPT = (1 << 0),
  95. };
  96. /**
  97. * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
  98. * See linux/cpumask.h
  99. */
  100. typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
  101. /**
  102. * struct dma_chan_percpu - the per-CPU part of struct dma_chan
  103. * @refcount: local_t used for open-coded "bigref" counting
  104. * @memcpy_count: transaction counter
  105. * @bytes_transferred: byte counter
  106. */
  107. struct dma_chan_percpu {
  108. local_t refcount;
  109. /* stats */
  110. unsigned long memcpy_count;
  111. unsigned long bytes_transferred;
  112. };
  113. /**
  114. * struct dma_chan - devices supply DMA channels, clients use them
  115. * @device: ptr to the dma device who supplies this channel, always !%NULL
  116. * @cookie: last cookie value returned to client
  117. * @chan_id: channel ID for sysfs
  118. * @class_dev: class device for sysfs
  119. * @refcount: kref, used in "bigref" slow-mode
  120. * @slow_ref: indicates that the DMA channel is free
  121. * @rcu: the DMA channel's RCU head
  122. * @device_node: used to add this to the device chan list
  123. * @local: per-cpu pointer to a struct dma_chan_percpu
  124. */
  125. struct dma_chan {
  126. struct dma_device *device;
  127. dma_cookie_t cookie;
  128. /* sysfs */
  129. int chan_id;
  130. struct device dev;
  131. struct kref refcount;
  132. int slow_ref;
  133. struct rcu_head rcu;
  134. struct list_head device_node;
  135. struct dma_chan_percpu *local;
  136. };
  137. #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
  138. void dma_chan_cleanup(struct kref *kref);
  139. static inline void dma_chan_get(struct dma_chan *chan)
  140. {
  141. if (unlikely(chan->slow_ref))
  142. kref_get(&chan->refcount);
  143. else {
  144. local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
  145. put_cpu();
  146. }
  147. }
  148. static inline void dma_chan_put(struct dma_chan *chan)
  149. {
  150. if (unlikely(chan->slow_ref))
  151. kref_put(&chan->refcount, dma_chan_cleanup);
  152. else {
  153. local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
  154. put_cpu();
  155. }
  156. }
  157. /*
  158. * typedef dma_event_callback - function pointer to a DMA event callback
  159. * For each channel added to the system this routine is called for each client.
  160. * If the client would like to use the channel it returns '1' to signal (ack)
  161. * the dmaengine core to take out a reference on the channel and its
  162. * corresponding device. A client must not 'ack' an available channel more
  163. * than once. When a channel is removed all clients are notified. If a client
  164. * is using the channel it must 'ack' the removal. A client must not 'ack' a
  165. * removed channel more than once.
  166. * @client - 'this' pointer for the client context
  167. * @chan - channel to be acted upon
  168. * @state - available or removed
  169. */
  170. struct dma_client;
  171. typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
  172. struct dma_chan *chan, enum dma_state state);
  173. /**
  174. * struct dma_client - info on the entity making use of DMA services
  175. * @event_callback: func ptr to call when something happens
  176. * @cap_mask: only return channels that satisfy the requested capabilities
  177. * a value of zero corresponds to any capability
  178. * @global_node: list_head for global dma_client_list
  179. */
  180. struct dma_client {
  181. dma_event_callback event_callback;
  182. dma_cap_mask_t cap_mask;
  183. struct list_head global_node;
  184. };
  185. typedef void (*dma_async_tx_callback)(void *dma_async_param);
  186. /**
  187. * struct dma_async_tx_descriptor - async transaction descriptor
  188. * ---dma generic offload fields---
  189. * @cookie: tracking cookie for this transaction, set to -EBUSY if
  190. * this tx is sitting on a dependency list
  191. * @ack: the descriptor can not be reused until the client acknowledges
  192. * receipt, i.e. has has a chance to establish any dependency chains
  193. * @phys: physical address of the descriptor
  194. * @tx_list: driver common field for operations that require multiple
  195. * descriptors
  196. * @chan: target channel for this operation
  197. * @tx_submit: set the prepared descriptor(s) to be executed by the engine
  198. * @callback: routine to call after this operation is complete
  199. * @callback_param: general parameter to pass to the callback routine
  200. * ---async_tx api specific fields---
  201. * @depend_list: at completion this list of transactions are submitted
  202. * @depend_node: allow this transaction to be executed after another
  203. * transaction has completed, possibly on another channel
  204. * @parent: pointer to the next level up in the dependency chain
  205. * @lock: protect the dependency list
  206. */
  207. struct dma_async_tx_descriptor {
  208. dma_cookie_t cookie;
  209. int ack;
  210. dma_addr_t phys;
  211. struct list_head tx_list;
  212. struct dma_chan *chan;
  213. dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
  214. dma_async_tx_callback callback;
  215. void *callback_param;
  216. struct list_head depend_list;
  217. struct list_head depend_node;
  218. struct dma_async_tx_descriptor *parent;
  219. spinlock_t lock;
  220. };
  221. /**
  222. * struct dma_device - info on the entity supplying DMA services
  223. * @chancnt: how many DMA channels are supported
  224. * @channels: the list of struct dma_chan
  225. * @global_node: list_head for global dma_device_list
  226. * @cap_mask: one or more dma_capability flags
  227. * @max_xor: maximum number of xor sources, 0 if no capability
  228. * @refcount: reference count
  229. * @done: IO completion struct
  230. * @dev_id: unique device ID
  231. * @dev: struct device reference for dma mapping api
  232. * @device_alloc_chan_resources: allocate resources and return the
  233. * number of allocated descriptors
  234. * @device_free_chan_resources: release DMA channel's resources
  235. * @device_prep_dma_memcpy: prepares a memcpy operation
  236. * @device_prep_dma_xor: prepares a xor operation
  237. * @device_prep_dma_zero_sum: prepares a zero_sum operation
  238. * @device_prep_dma_memset: prepares a memset operation
  239. * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
  240. * @device_dependency_added: async_tx notifies the channel about new deps
  241. * @device_issue_pending: push pending transactions to hardware
  242. */
  243. struct dma_device {
  244. unsigned int chancnt;
  245. struct list_head channels;
  246. struct list_head global_node;
  247. dma_cap_mask_t cap_mask;
  248. int max_xor;
  249. struct kref refcount;
  250. struct completion done;
  251. int dev_id;
  252. struct device *dev;
  253. int (*device_alloc_chan_resources)(struct dma_chan *chan);
  254. void (*device_free_chan_resources)(struct dma_chan *chan);
  255. struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
  256. struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  257. size_t len, unsigned long flags);
  258. struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
  259. struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
  260. unsigned int src_cnt, size_t len, unsigned long flags);
  261. struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
  262. struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
  263. size_t len, u32 *result, unsigned long flags);
  264. struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
  265. struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
  266. unsigned long flags);
  267. struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
  268. struct dma_chan *chan);
  269. void (*device_dependency_added)(struct dma_chan *chan);
  270. enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
  271. dma_cookie_t cookie, dma_cookie_t *last,
  272. dma_cookie_t *used);
  273. void (*device_issue_pending)(struct dma_chan *chan);
  274. };
  275. /* --- public DMA engine API --- */
  276. void dma_async_client_register(struct dma_client *client);
  277. void dma_async_client_unregister(struct dma_client *client);
  278. void dma_async_client_chan_request(struct dma_client *client);
  279. dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
  280. void *dest, void *src, size_t len);
  281. dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
  282. struct page *page, unsigned int offset, void *kdata, size_t len);
  283. dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
  284. struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
  285. unsigned int src_off, size_t len);
  286. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  287. struct dma_chan *chan);
  288. static inline void
  289. async_tx_ack(struct dma_async_tx_descriptor *tx)
  290. {
  291. tx->ack = 1;
  292. }
  293. #define first_dma_cap(mask) __first_dma_cap(&(mask))
  294. static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
  295. {
  296. return min_t(int, DMA_TX_TYPE_END,
  297. find_first_bit(srcp->bits, DMA_TX_TYPE_END));
  298. }
  299. #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
  300. static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
  301. {
  302. return min_t(int, DMA_TX_TYPE_END,
  303. find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
  304. }
  305. #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
  306. static inline void
  307. __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
  308. {
  309. set_bit(tx_type, dstp->bits);
  310. }
  311. #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
  312. static inline int
  313. __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
  314. {
  315. return test_bit(tx_type, srcp->bits);
  316. }
  317. #define for_each_dma_cap_mask(cap, mask) \
  318. for ((cap) = first_dma_cap(mask); \
  319. (cap) < DMA_TX_TYPE_END; \
  320. (cap) = next_dma_cap((cap), (mask)))
  321. /**
  322. * dma_async_issue_pending - flush pending transactions to HW
  323. * @chan: target DMA channel
  324. *
  325. * This allows drivers to push copies to HW in batches,
  326. * reducing MMIO writes where possible.
  327. */
  328. static inline void dma_async_issue_pending(struct dma_chan *chan)
  329. {
  330. return chan->device->device_issue_pending(chan);
  331. }
  332. #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
  333. /**
  334. * dma_async_is_tx_complete - poll for transaction completion
  335. * @chan: DMA channel
  336. * @cookie: transaction identifier to check status of
  337. * @last: returns last completed cookie, can be NULL
  338. * @used: returns last issued cookie, can be NULL
  339. *
  340. * If @last and @used are passed in, upon return they reflect the driver
  341. * internal state and can be used with dma_async_is_complete() to check
  342. * the status of multiple cookies without re-checking hardware state.
  343. */
  344. static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
  345. dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
  346. {
  347. return chan->device->device_is_tx_complete(chan, cookie, last, used);
  348. }
  349. #define dma_async_memcpy_complete(chan, cookie, last, used)\
  350. dma_async_is_tx_complete(chan, cookie, last, used)
  351. /**
  352. * dma_async_is_complete - test a cookie against chan state
  353. * @cookie: transaction identifier to test status of
  354. * @last_complete: last know completed transaction
  355. * @last_used: last cookie value handed out
  356. *
  357. * dma_async_is_complete() is used in dma_async_memcpy_complete()
  358. * the test logic is seperated for lightweight testing of multiple cookies
  359. */
  360. static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
  361. dma_cookie_t last_complete, dma_cookie_t last_used)
  362. {
  363. if (last_complete <= last_used) {
  364. if ((cookie <= last_complete) || (cookie > last_used))
  365. return DMA_SUCCESS;
  366. } else {
  367. if ((cookie <= last_complete) && (cookie > last_used))
  368. return DMA_SUCCESS;
  369. }
  370. return DMA_IN_PROGRESS;
  371. }
  372. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
  373. /* --- DMA device --- */
  374. int dma_async_device_register(struct dma_device *device);
  375. void dma_async_device_unregister(struct dma_device *device);
  376. /* --- Helper iov-locking functions --- */
  377. struct dma_page_list {
  378. char *base_address;
  379. int nr_pages;
  380. struct page **pages;
  381. };
  382. struct dma_pinned_list {
  383. int nr_iovecs;
  384. struct dma_page_list page_list[0];
  385. };
  386. struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
  387. void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
  388. dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
  389. struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
  390. dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
  391. struct dma_pinned_list *pinned_list, struct page *page,
  392. unsigned int offset, size_t len);
  393. #endif /* DMAENGINE_H */