mthca_main.c 32 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. mdev->limits.num_ports = dev_lim->num_ports;
  141. mdev->limits.vl_cap = dev_lim->max_vl;
  142. mdev->limits.mtu_cap = dev_lim->max_mtu;
  143. mdev->limits.gid_table_len = dev_lim->max_gids;
  144. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  145. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  146. mdev->limits.max_sg = dev_lim->max_sg;
  147. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  148. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  149. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  150. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  151. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  152. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  153. /*
  154. * Subtract 1 from the limit because we need to allocate a
  155. * spare CQE so the HCA HW can tell the difference between an
  156. * empty CQ and a full CQ.
  157. */
  158. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  159. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  160. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  161. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  162. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  163. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  164. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  165. mdev->limits.port_width_cap = dev_lim->max_port_width;
  166. mdev->limits.flags = dev_lim->flags;
  167. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  168. May be doable since hardware supports it for SRQ.
  169. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  170. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  171. supported by driver. */
  172. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  173. IB_DEVICE_PORT_ACTIVE_EVENT |
  174. IB_DEVICE_SYS_IMAGE_GUID |
  175. IB_DEVICE_RC_RNR_NAK_GEN;
  176. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  177. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  178. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  179. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  180. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  181. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  182. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  183. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  184. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  185. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  186. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  187. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  188. return 0;
  189. }
  190. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  191. {
  192. u8 status;
  193. int err;
  194. struct mthca_dev_lim dev_lim;
  195. struct mthca_profile profile;
  196. struct mthca_init_hca_param init_hca;
  197. err = mthca_SYS_EN(mdev, &status);
  198. if (err) {
  199. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  200. return err;
  201. }
  202. if (status) {
  203. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  204. "aborting.\n", status);
  205. return -EINVAL;
  206. }
  207. err = mthca_QUERY_FW(mdev, &status);
  208. if (err) {
  209. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  210. goto err_disable;
  211. }
  212. if (status) {
  213. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  214. "aborting.\n", status);
  215. err = -EINVAL;
  216. goto err_disable;
  217. }
  218. err = mthca_QUERY_DDR(mdev, &status);
  219. if (err) {
  220. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  221. goto err_disable;
  222. }
  223. if (status) {
  224. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  225. "aborting.\n", status);
  226. err = -EINVAL;
  227. goto err_disable;
  228. }
  229. err = mthca_dev_lim(mdev, &dev_lim);
  230. profile = default_profile;
  231. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  232. profile.uarc_size = 0;
  233. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  234. profile.num_srq = dev_lim.max_srqs;
  235. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  236. if (err < 0)
  237. goto err_disable;
  238. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  239. if (err) {
  240. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  241. goto err_disable;
  242. }
  243. if (status) {
  244. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  245. "aborting.\n", status);
  246. err = -EINVAL;
  247. goto err_disable;
  248. }
  249. return 0;
  250. err_disable:
  251. mthca_SYS_DIS(mdev, &status);
  252. return err;
  253. }
  254. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  255. {
  256. u8 status;
  257. int err;
  258. /* FIXME: use HCA-attached memory for FW if present */
  259. mdev->fw.arbel.fw_icm =
  260. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  261. GFP_HIGHUSER | __GFP_NOWARN);
  262. if (!mdev->fw.arbel.fw_icm) {
  263. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  264. return -ENOMEM;
  265. }
  266. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  267. if (err) {
  268. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  269. goto err_free;
  270. }
  271. if (status) {
  272. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  273. err = -EINVAL;
  274. goto err_free;
  275. }
  276. err = mthca_RUN_FW(mdev, &status);
  277. if (err) {
  278. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  279. goto err_unmap_fa;
  280. }
  281. if (status) {
  282. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  283. err = -EINVAL;
  284. goto err_unmap_fa;
  285. }
  286. return 0;
  287. err_unmap_fa:
  288. mthca_UNMAP_FA(mdev, &status);
  289. err_free:
  290. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  291. return err;
  292. }
  293. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  294. struct mthca_dev_lim *dev_lim,
  295. struct mthca_init_hca_param *init_hca,
  296. u64 icm_size)
  297. {
  298. u64 aux_pages;
  299. u8 status;
  300. int err;
  301. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  302. if (err) {
  303. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  304. return err;
  305. }
  306. if (status) {
  307. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  308. "aborting.\n", status);
  309. return -EINVAL;
  310. }
  311. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  312. (unsigned long long) icm_size >> 10,
  313. (unsigned long long) aux_pages << 2);
  314. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  315. GFP_HIGHUSER | __GFP_NOWARN);
  316. if (!mdev->fw.arbel.aux_icm) {
  317. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  318. return -ENOMEM;
  319. }
  320. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  321. if (err) {
  322. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  323. goto err_free_aux;
  324. }
  325. if (status) {
  326. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  327. err = -EINVAL;
  328. goto err_free_aux;
  329. }
  330. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  331. if (err) {
  332. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  333. goto err_unmap_aux;
  334. }
  335. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  336. MTHCA_MTT_SEG_SIZE,
  337. mdev->limits.num_mtt_segs,
  338. mdev->limits.reserved_mtts, 1);
  339. if (!mdev->mr_table.mtt_table) {
  340. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  341. err = -ENOMEM;
  342. goto err_unmap_eq;
  343. }
  344. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  345. dev_lim->mpt_entry_sz,
  346. mdev->limits.num_mpts,
  347. mdev->limits.reserved_mrws, 1);
  348. if (!mdev->mr_table.mpt_table) {
  349. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  350. err = -ENOMEM;
  351. goto err_unmap_mtt;
  352. }
  353. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  354. dev_lim->qpc_entry_sz,
  355. mdev->limits.num_qps,
  356. mdev->limits.reserved_qps, 0);
  357. if (!mdev->qp_table.qp_table) {
  358. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  359. err = -ENOMEM;
  360. goto err_unmap_mpt;
  361. }
  362. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  363. dev_lim->eqpc_entry_sz,
  364. mdev->limits.num_qps,
  365. mdev->limits.reserved_qps, 0);
  366. if (!mdev->qp_table.eqp_table) {
  367. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  368. err = -ENOMEM;
  369. goto err_unmap_qp;
  370. }
  371. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  372. MTHCA_RDB_ENTRY_SIZE,
  373. mdev->limits.num_qps <<
  374. mdev->qp_table.rdb_shift,
  375. 0, 0);
  376. if (!mdev->qp_table.rdb_table) {
  377. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  378. err = -ENOMEM;
  379. goto err_unmap_eqp;
  380. }
  381. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  382. dev_lim->cqc_entry_sz,
  383. mdev->limits.num_cqs,
  384. mdev->limits.reserved_cqs, 0);
  385. if (!mdev->cq_table.table) {
  386. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  387. err = -ENOMEM;
  388. goto err_unmap_rdb;
  389. }
  390. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  391. mdev->srq_table.table =
  392. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  393. dev_lim->srq_entry_sz,
  394. mdev->limits.num_srqs,
  395. mdev->limits.reserved_srqs, 0);
  396. if (!mdev->srq_table.table) {
  397. mthca_err(mdev, "Failed to map SRQ context memory, "
  398. "aborting.\n");
  399. err = -ENOMEM;
  400. goto err_unmap_cq;
  401. }
  402. }
  403. /*
  404. * It's not strictly required, but for simplicity just map the
  405. * whole multicast group table now. The table isn't very big
  406. * and it's a lot easier than trying to track ref counts.
  407. */
  408. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  409. MTHCA_MGM_ENTRY_SIZE,
  410. mdev->limits.num_mgms +
  411. mdev->limits.num_amgms,
  412. mdev->limits.num_mgms +
  413. mdev->limits.num_amgms,
  414. 0);
  415. if (!mdev->mcg_table.table) {
  416. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  417. err = -ENOMEM;
  418. goto err_unmap_srq;
  419. }
  420. return 0;
  421. err_unmap_srq:
  422. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  423. mthca_free_icm_table(mdev, mdev->srq_table.table);
  424. err_unmap_cq:
  425. mthca_free_icm_table(mdev, mdev->cq_table.table);
  426. err_unmap_rdb:
  427. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  428. err_unmap_eqp:
  429. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  430. err_unmap_qp:
  431. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  432. err_unmap_mpt:
  433. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  434. err_unmap_mtt:
  435. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  436. err_unmap_eq:
  437. mthca_unmap_eq_icm(mdev);
  438. err_unmap_aux:
  439. mthca_UNMAP_ICM_AUX(mdev, &status);
  440. err_free_aux:
  441. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  442. return err;
  443. }
  444. static void mthca_free_icms(struct mthca_dev *mdev)
  445. {
  446. u8 status;
  447. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  448. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  449. mthca_free_icm_table(mdev, mdev->srq_table.table);
  450. mthca_free_icm_table(mdev, mdev->cq_table.table);
  451. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  452. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  453. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  454. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  455. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  456. mthca_unmap_eq_icm(mdev);
  457. mthca_UNMAP_ICM_AUX(mdev, &status);
  458. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  459. }
  460. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  461. {
  462. struct mthca_dev_lim dev_lim;
  463. struct mthca_profile profile;
  464. struct mthca_init_hca_param init_hca;
  465. u64 icm_size;
  466. u8 status;
  467. int err;
  468. err = mthca_QUERY_FW(mdev, &status);
  469. if (err) {
  470. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  471. return err;
  472. }
  473. if (status) {
  474. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  475. "aborting.\n", status);
  476. return -EINVAL;
  477. }
  478. err = mthca_ENABLE_LAM(mdev, &status);
  479. if (err) {
  480. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  481. return err;
  482. }
  483. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  484. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  485. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  486. } else if (status) {
  487. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  488. "aborting.\n", status);
  489. return -EINVAL;
  490. }
  491. err = mthca_load_fw(mdev);
  492. if (err) {
  493. mthca_err(mdev, "Failed to start FW, aborting.\n");
  494. goto err_disable;
  495. }
  496. err = mthca_dev_lim(mdev, &dev_lim);
  497. if (err) {
  498. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  499. goto err_stop_fw;
  500. }
  501. profile = default_profile;
  502. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  503. profile.num_udav = 0;
  504. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  505. profile.num_srq = dev_lim.max_srqs;
  506. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  507. if ((int) icm_size < 0) {
  508. err = icm_size;
  509. goto err_stop_fw;
  510. }
  511. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  512. if (err)
  513. goto err_stop_fw;
  514. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  515. if (err) {
  516. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  517. goto err_free_icm;
  518. }
  519. if (status) {
  520. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  521. "aborting.\n", status);
  522. err = -EINVAL;
  523. goto err_free_icm;
  524. }
  525. return 0;
  526. err_free_icm:
  527. mthca_free_icms(mdev);
  528. err_stop_fw:
  529. mthca_UNMAP_FA(mdev, &status);
  530. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  531. err_disable:
  532. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  533. mthca_DISABLE_LAM(mdev, &status);
  534. return err;
  535. }
  536. static void mthca_close_hca(struct mthca_dev *mdev)
  537. {
  538. u8 status;
  539. mthca_CLOSE_HCA(mdev, 0, &status);
  540. if (mthca_is_memfree(mdev)) {
  541. mthca_free_icms(mdev);
  542. mthca_UNMAP_FA(mdev, &status);
  543. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  544. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  545. mthca_DISABLE_LAM(mdev, &status);
  546. } else
  547. mthca_SYS_DIS(mdev, &status);
  548. }
  549. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  550. {
  551. u8 status;
  552. int err;
  553. struct mthca_adapter adapter;
  554. if (mthca_is_memfree(mdev))
  555. err = mthca_init_arbel(mdev);
  556. else
  557. err = mthca_init_tavor(mdev);
  558. if (err)
  559. return err;
  560. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  561. if (err) {
  562. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  563. goto err_close;
  564. }
  565. if (status) {
  566. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  567. "aborting.\n", status);
  568. err = -EINVAL;
  569. goto err_close;
  570. }
  571. mdev->eq_table.inta_pin = adapter.inta_pin;
  572. mdev->rev_id = adapter.revision_id;
  573. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  574. return 0;
  575. err_close:
  576. mthca_close_hca(mdev);
  577. return err;
  578. }
  579. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  580. {
  581. int err;
  582. u8 status;
  583. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  584. err = mthca_init_uar_table(dev);
  585. if (err) {
  586. mthca_err(dev, "Failed to initialize "
  587. "user access region table, aborting.\n");
  588. return err;
  589. }
  590. err = mthca_uar_alloc(dev, &dev->driver_uar);
  591. if (err) {
  592. mthca_err(dev, "Failed to allocate driver access region, "
  593. "aborting.\n");
  594. goto err_uar_table_free;
  595. }
  596. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  597. if (!dev->kar) {
  598. mthca_err(dev, "Couldn't map kernel access region, "
  599. "aborting.\n");
  600. err = -ENOMEM;
  601. goto err_uar_free;
  602. }
  603. err = mthca_init_pd_table(dev);
  604. if (err) {
  605. mthca_err(dev, "Failed to initialize "
  606. "protection domain table, aborting.\n");
  607. goto err_kar_unmap;
  608. }
  609. err = mthca_init_mr_table(dev);
  610. if (err) {
  611. mthca_err(dev, "Failed to initialize "
  612. "memory region table, aborting.\n");
  613. goto err_pd_table_free;
  614. }
  615. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  616. if (err) {
  617. mthca_err(dev, "Failed to create driver PD, "
  618. "aborting.\n");
  619. goto err_mr_table_free;
  620. }
  621. err = mthca_init_eq_table(dev);
  622. if (err) {
  623. mthca_err(dev, "Failed to initialize "
  624. "event queue table, aborting.\n");
  625. goto err_pd_free;
  626. }
  627. err = mthca_cmd_use_events(dev);
  628. if (err) {
  629. mthca_err(dev, "Failed to switch to event-driven "
  630. "firmware commands, aborting.\n");
  631. goto err_eq_table_free;
  632. }
  633. err = mthca_NOP(dev, &status);
  634. if (err || status) {
  635. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  636. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  637. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  638. dev->pdev->irq);
  639. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  640. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  641. else
  642. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  643. goto err_cmd_poll;
  644. }
  645. mthca_dbg(dev, "NOP command IRQ test passed\n");
  646. err = mthca_init_cq_table(dev);
  647. if (err) {
  648. mthca_err(dev, "Failed to initialize "
  649. "completion queue table, aborting.\n");
  650. goto err_cmd_poll;
  651. }
  652. err = mthca_init_srq_table(dev);
  653. if (err) {
  654. mthca_err(dev, "Failed to initialize "
  655. "shared receive queue table, aborting.\n");
  656. goto err_cq_table_free;
  657. }
  658. err = mthca_init_qp_table(dev);
  659. if (err) {
  660. mthca_err(dev, "Failed to initialize "
  661. "queue pair table, aborting.\n");
  662. goto err_srq_table_free;
  663. }
  664. err = mthca_init_av_table(dev);
  665. if (err) {
  666. mthca_err(dev, "Failed to initialize "
  667. "address vector table, aborting.\n");
  668. goto err_qp_table_free;
  669. }
  670. err = mthca_init_mcg_table(dev);
  671. if (err) {
  672. mthca_err(dev, "Failed to initialize "
  673. "multicast group table, aborting.\n");
  674. goto err_av_table_free;
  675. }
  676. return 0;
  677. err_av_table_free:
  678. mthca_cleanup_av_table(dev);
  679. err_qp_table_free:
  680. mthca_cleanup_qp_table(dev);
  681. err_srq_table_free:
  682. mthca_cleanup_srq_table(dev);
  683. err_cq_table_free:
  684. mthca_cleanup_cq_table(dev);
  685. err_cmd_poll:
  686. mthca_cmd_use_polling(dev);
  687. err_eq_table_free:
  688. mthca_cleanup_eq_table(dev);
  689. err_pd_free:
  690. mthca_pd_free(dev, &dev->driver_pd);
  691. err_mr_table_free:
  692. mthca_cleanup_mr_table(dev);
  693. err_pd_table_free:
  694. mthca_cleanup_pd_table(dev);
  695. err_kar_unmap:
  696. iounmap(dev->kar);
  697. err_uar_free:
  698. mthca_uar_free(dev, &dev->driver_uar);
  699. err_uar_table_free:
  700. mthca_cleanup_uar_table(dev);
  701. return err;
  702. }
  703. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  704. int ddr_hidden)
  705. {
  706. int err;
  707. /*
  708. * We can't just use pci_request_regions() because the MSI-X
  709. * table is right in the middle of the first BAR. If we did
  710. * pci_request_region and grab all of the first BAR, then
  711. * setting up MSI-X would fail, since the PCI core wants to do
  712. * request_mem_region on the MSI-X vector table.
  713. *
  714. * So just request what we need right now, and request any
  715. * other regions we need when setting up EQs.
  716. */
  717. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  718. MTHCA_HCR_SIZE, DRV_NAME))
  719. return -EBUSY;
  720. err = pci_request_region(pdev, 2, DRV_NAME);
  721. if (err)
  722. goto err_bar2_failed;
  723. if (!ddr_hidden) {
  724. err = pci_request_region(pdev, 4, DRV_NAME);
  725. if (err)
  726. goto err_bar4_failed;
  727. }
  728. return 0;
  729. err_bar4_failed:
  730. pci_release_region(pdev, 2);
  731. err_bar2_failed:
  732. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  733. MTHCA_HCR_SIZE);
  734. return err;
  735. }
  736. static void mthca_release_regions(struct pci_dev *pdev,
  737. int ddr_hidden)
  738. {
  739. if (!ddr_hidden)
  740. pci_release_region(pdev, 4);
  741. pci_release_region(pdev, 2);
  742. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  743. MTHCA_HCR_SIZE);
  744. }
  745. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  746. {
  747. struct msix_entry entries[3];
  748. int err;
  749. entries[0].entry = 0;
  750. entries[1].entry = 1;
  751. entries[2].entry = 2;
  752. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  753. if (err) {
  754. if (err > 0)
  755. mthca_info(mdev, "Only %d MSI-X vectors available, "
  756. "not using MSI-X\n", err);
  757. return err;
  758. }
  759. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  760. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  761. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  762. return 0;
  763. }
  764. /* Types of supported HCA */
  765. enum {
  766. TAVOR, /* MT23108 */
  767. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  768. ARBEL_NATIVE, /* MT25208 with extended features */
  769. SINAI /* MT25204 */
  770. };
  771. #define MTHCA_FW_VER(major, minor, subminor) \
  772. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  773. static struct {
  774. u64 latest_fw;
  775. int is_memfree;
  776. int is_pcie;
  777. } mthca_hca_table[] = {
  778. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  779. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  780. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  781. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  782. };
  783. static int __devinit mthca_init_one(struct pci_dev *pdev,
  784. const struct pci_device_id *id)
  785. {
  786. static int mthca_version_printed = 0;
  787. int ddr_hidden = 0;
  788. int err;
  789. struct mthca_dev *mdev;
  790. if (!mthca_version_printed) {
  791. printk(KERN_INFO "%s", mthca_version);
  792. ++mthca_version_printed;
  793. }
  794. printk(KERN_INFO PFX "Initializing %s\n",
  795. pci_name(pdev));
  796. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  797. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  798. pci_name(pdev), id->driver_data);
  799. return -ENODEV;
  800. }
  801. err = pci_enable_device(pdev);
  802. if (err) {
  803. dev_err(&pdev->dev, "Cannot enable PCI device, "
  804. "aborting.\n");
  805. return err;
  806. }
  807. /*
  808. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  809. * be present)
  810. */
  811. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  812. pci_resource_len(pdev, 0) != 1 << 20) {
  813. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  814. err = -ENODEV;
  815. goto err_disable_pdev;
  816. }
  817. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM) ||
  818. pci_resource_len(pdev, 2) != 1 << 23) {
  819. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  820. err = -ENODEV;
  821. goto err_disable_pdev;
  822. }
  823. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  824. ddr_hidden = 1;
  825. err = mthca_request_regions(pdev, ddr_hidden);
  826. if (err) {
  827. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  828. "aborting.\n");
  829. goto err_disable_pdev;
  830. }
  831. pci_set_master(pdev);
  832. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  833. if (err) {
  834. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  835. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  836. if (err) {
  837. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  838. goto err_free_res;
  839. }
  840. }
  841. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  842. if (err) {
  843. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  844. "consistent PCI DMA mask.\n");
  845. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  846. if (err) {
  847. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  848. "aborting.\n");
  849. goto err_free_res;
  850. }
  851. }
  852. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  853. if (!mdev) {
  854. dev_err(&pdev->dev, "Device struct alloc failed, "
  855. "aborting.\n");
  856. err = -ENOMEM;
  857. goto err_free_res;
  858. }
  859. mdev->pdev = pdev;
  860. if (ddr_hidden)
  861. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  862. if (mthca_hca_table[id->driver_data].is_memfree)
  863. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  864. if (mthca_hca_table[id->driver_data].is_pcie)
  865. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  866. /*
  867. * Now reset the HCA before we touch the PCI capabilities or
  868. * attempt a firmware command, since a boot ROM may have left
  869. * the HCA in an undefined state.
  870. */
  871. err = mthca_reset(mdev);
  872. if (err) {
  873. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  874. goto err_free_dev;
  875. }
  876. if (msi_x && !mthca_enable_msi_x(mdev))
  877. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  878. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  879. !pci_enable_msi(pdev))
  880. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  881. if (mthca_cmd_init(mdev)) {
  882. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  883. goto err_free_dev;
  884. }
  885. err = mthca_tune_pci(mdev);
  886. if (err)
  887. goto err_cmd;
  888. err = mthca_init_hca(mdev);
  889. if (err)
  890. goto err_cmd;
  891. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  892. mthca_warn(mdev, "HCA FW version %x.%x.%x is old (%x.%x.%x is current).\n",
  893. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  894. (int) (mdev->fw_ver & 0xffff),
  895. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  896. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  897. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  898. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  899. }
  900. err = mthca_setup_hca(mdev);
  901. if (err)
  902. goto err_close;
  903. err = mthca_register_device(mdev);
  904. if (err)
  905. goto err_cleanup;
  906. err = mthca_create_agents(mdev);
  907. if (err)
  908. goto err_unregister;
  909. pci_set_drvdata(pdev, mdev);
  910. return 0;
  911. err_unregister:
  912. mthca_unregister_device(mdev);
  913. err_cleanup:
  914. mthca_cleanup_mcg_table(mdev);
  915. mthca_cleanup_av_table(mdev);
  916. mthca_cleanup_qp_table(mdev);
  917. mthca_cleanup_srq_table(mdev);
  918. mthca_cleanup_cq_table(mdev);
  919. mthca_cmd_use_polling(mdev);
  920. mthca_cleanup_eq_table(mdev);
  921. mthca_pd_free(mdev, &mdev->driver_pd);
  922. mthca_cleanup_mr_table(mdev);
  923. mthca_cleanup_pd_table(mdev);
  924. mthca_cleanup_uar_table(mdev);
  925. err_close:
  926. mthca_close_hca(mdev);
  927. err_cmd:
  928. mthca_cmd_cleanup(mdev);
  929. err_free_dev:
  930. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  931. pci_disable_msix(pdev);
  932. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  933. pci_disable_msi(pdev);
  934. ib_dealloc_device(&mdev->ib_dev);
  935. err_free_res:
  936. mthca_release_regions(pdev, ddr_hidden);
  937. err_disable_pdev:
  938. pci_disable_device(pdev);
  939. pci_set_drvdata(pdev, NULL);
  940. return err;
  941. }
  942. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  943. {
  944. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  945. u8 status;
  946. int p;
  947. if (mdev) {
  948. mthca_free_agents(mdev);
  949. mthca_unregister_device(mdev);
  950. for (p = 1; p <= mdev->limits.num_ports; ++p)
  951. mthca_CLOSE_IB(mdev, p, &status);
  952. mthca_cleanup_mcg_table(mdev);
  953. mthca_cleanup_av_table(mdev);
  954. mthca_cleanup_qp_table(mdev);
  955. mthca_cleanup_srq_table(mdev);
  956. mthca_cleanup_cq_table(mdev);
  957. mthca_cmd_use_polling(mdev);
  958. mthca_cleanup_eq_table(mdev);
  959. mthca_pd_free(mdev, &mdev->driver_pd);
  960. mthca_cleanup_mr_table(mdev);
  961. mthca_cleanup_pd_table(mdev);
  962. iounmap(mdev->kar);
  963. mthca_uar_free(mdev, &mdev->driver_uar);
  964. mthca_cleanup_uar_table(mdev);
  965. mthca_close_hca(mdev);
  966. mthca_cmd_cleanup(mdev);
  967. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  968. pci_disable_msix(pdev);
  969. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  970. pci_disable_msi(pdev);
  971. ib_dealloc_device(&mdev->ib_dev);
  972. mthca_release_regions(pdev, mdev->mthca_flags &
  973. MTHCA_FLAG_DDR_HIDDEN);
  974. pci_disable_device(pdev);
  975. pci_set_drvdata(pdev, NULL);
  976. }
  977. }
  978. static struct pci_device_id mthca_pci_table[] = {
  979. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  980. .driver_data = TAVOR },
  981. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  982. .driver_data = TAVOR },
  983. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  984. .driver_data = ARBEL_COMPAT },
  985. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  986. .driver_data = ARBEL_COMPAT },
  987. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  988. .driver_data = ARBEL_NATIVE },
  989. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  990. .driver_data = ARBEL_NATIVE },
  991. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  992. .driver_data = SINAI },
  993. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  994. .driver_data = SINAI },
  995. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  996. .driver_data = SINAI },
  997. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  998. .driver_data = SINAI },
  999. { 0, }
  1000. };
  1001. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1002. static struct pci_driver mthca_driver = {
  1003. .name = DRV_NAME,
  1004. .owner = THIS_MODULE,
  1005. .id_table = mthca_pci_table,
  1006. .probe = mthca_init_one,
  1007. .remove = __devexit_p(mthca_remove_one)
  1008. };
  1009. static int __init mthca_init(void)
  1010. {
  1011. int ret;
  1012. ret = pci_register_driver(&mthca_driver);
  1013. return ret < 0 ? ret : 0;
  1014. }
  1015. static void __exit mthca_cleanup(void)
  1016. {
  1017. pci_unregister_driver(&mthca_driver);
  1018. }
  1019. module_init(mthca_init);
  1020. module_exit(mthca_cleanup);