aic79xx_osm_pci.c 9.7 KB

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  1. /*
  2. * Linux driver attachment glue for PCI based U320 controllers.
  3. *
  4. * Copyright (c) 2000-2001 Adaptec Inc.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic79xx_osm_pci.c#25 $
  40. */
  41. #include "aic79xx_osm.h"
  42. #include "aic79xx_inline.h"
  43. #include "aic79xx_pci.h"
  44. static int ahd_linux_pci_dev_probe(struct pci_dev *pdev,
  45. const struct pci_device_id *ent);
  46. static int ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd,
  47. u_long *base, u_long *base2);
  48. static int ahd_linux_pci_reserve_mem_region(struct ahd_softc *ahd,
  49. u_long *bus_addr,
  50. uint8_t __iomem **maddr);
  51. static void ahd_linux_pci_dev_remove(struct pci_dev *pdev);
  52. /* Define the macro locally since it's different for different class of chips.
  53. */
  54. #define ID(x) \
  55. ID2C(x), \
  56. ID2C(IDIROC(x))
  57. static struct pci_device_id ahd_linux_pci_id_table[] = {
  58. /* aic7901 based controllers */
  59. ID(ID_AHA_29320A),
  60. ID(ID_AHA_29320ALP),
  61. /* aic7902 based controllers */
  62. ID(ID_AHA_29320),
  63. ID(ID_AHA_29320B),
  64. ID(ID_AHA_29320LP),
  65. ID(ID_AHA_39320),
  66. ID(ID_AHA_39320_B),
  67. ID(ID_AHA_39320A),
  68. ID(ID_AHA_39320D),
  69. ID(ID_AHA_39320D_HP),
  70. ID(ID_AHA_39320D_B),
  71. ID(ID_AHA_39320D_B_HP),
  72. /* Generic chip probes for devices we don't know exactly. */
  73. ID16(ID_AIC7901 & ID_9005_GENERIC_MASK),
  74. ID(ID_AIC7901A & ID_DEV_VENDOR_MASK),
  75. ID16(ID_AIC7902 & ID_9005_GENERIC_MASK),
  76. { 0 }
  77. };
  78. MODULE_DEVICE_TABLE(pci, ahd_linux_pci_id_table);
  79. struct pci_driver aic79xx_pci_driver = {
  80. .name = "aic79xx",
  81. .probe = ahd_linux_pci_dev_probe,
  82. .remove = ahd_linux_pci_dev_remove,
  83. .id_table = ahd_linux_pci_id_table
  84. };
  85. static void
  86. ahd_linux_pci_dev_remove(struct pci_dev *pdev)
  87. {
  88. struct ahd_softc *ahd;
  89. u_long l;
  90. /*
  91. * We should be able to just perform
  92. * the free directly, but check our
  93. * list for extra sanity.
  94. */
  95. ahd_list_lock(&l);
  96. ahd = ahd_find_softc((struct ahd_softc *)pci_get_drvdata(pdev));
  97. if (ahd != NULL) {
  98. u_long s;
  99. TAILQ_REMOVE(&ahd_tailq, ahd, links);
  100. ahd_list_unlock(&l);
  101. ahd_lock(ahd, &s);
  102. ahd_intr_enable(ahd, FALSE);
  103. ahd_unlock(ahd, &s);
  104. ahd_free(ahd);
  105. } else
  106. ahd_list_unlock(&l);
  107. }
  108. static int
  109. ahd_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  110. {
  111. char buf[80];
  112. struct ahd_softc *ahd;
  113. ahd_dev_softc_t pci;
  114. struct ahd_pci_identity *entry;
  115. char *name;
  116. int error;
  117. /*
  118. * Some BIOSen report the same device multiple times.
  119. */
  120. TAILQ_FOREACH(ahd, &ahd_tailq, links) {
  121. struct pci_dev *probed_pdev;
  122. probed_pdev = ahd->dev_softc;
  123. if (probed_pdev->bus->number == pdev->bus->number
  124. && probed_pdev->devfn == pdev->devfn)
  125. break;
  126. }
  127. if (ahd != NULL) {
  128. /* Skip duplicate. */
  129. return (-ENODEV);
  130. }
  131. pci = pdev;
  132. entry = ahd_find_pci_device(pci);
  133. if (entry == NULL)
  134. return (-ENODEV);
  135. /*
  136. * Allocate a softc for this card and
  137. * set it up for attachment by our
  138. * common detect routine.
  139. */
  140. sprintf(buf, "ahd_pci:%d:%d:%d",
  141. ahd_get_pci_bus(pci),
  142. ahd_get_pci_slot(pci),
  143. ahd_get_pci_function(pci));
  144. name = malloc(strlen(buf) + 1, M_DEVBUF, M_NOWAIT);
  145. if (name == NULL)
  146. return (-ENOMEM);
  147. strcpy(name, buf);
  148. ahd = ahd_alloc(NULL, name);
  149. if (ahd == NULL)
  150. return (-ENOMEM);
  151. if (pci_enable_device(pdev)) {
  152. ahd_free(ahd);
  153. return (-ENODEV);
  154. }
  155. pci_set_master(pdev);
  156. if (sizeof(dma_addr_t) > 4) {
  157. uint64_t memsize;
  158. const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
  159. memsize = ahd_linux_get_memsize();
  160. if (memsize >= 0x8000000000ULL
  161. && pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
  162. ahd->flags |= AHD_64BIT_ADDRESSING;
  163. } else if (memsize > 0x80000000
  164. && pci_set_dma_mask(pdev, mask_39bit) == 0) {
  165. ahd->flags |= AHD_39BIT_ADDRESSING;
  166. }
  167. } else {
  168. pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  169. }
  170. ahd->dev_softc = pci;
  171. error = ahd_pci_config(ahd, entry);
  172. if (error != 0) {
  173. ahd_free(ahd);
  174. return (-error);
  175. }
  176. pci_set_drvdata(pdev, ahd);
  177. if (aic79xx_detect_complete) {
  178. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
  179. ahd_linux_register_host(ahd, &aic79xx_driver_template);
  180. #else
  181. printf("aic79xx: ignoring PCI device found after "
  182. "initialization\n");
  183. return (-ENODEV);
  184. #endif
  185. }
  186. return (0);
  187. }
  188. int
  189. ahd_linux_pci_init(void)
  190. {
  191. return (pci_module_init(&aic79xx_pci_driver));
  192. }
  193. void
  194. ahd_linux_pci_exit(void)
  195. {
  196. pci_unregister_driver(&aic79xx_pci_driver);
  197. }
  198. static int
  199. ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, u_long *base,
  200. u_long *base2)
  201. {
  202. *base = pci_resource_start(ahd->dev_softc, 0);
  203. /*
  204. * This is really the 3rd bar and should be at index 2,
  205. * but the Linux PCI code doesn't know how to "count" 64bit
  206. * bars.
  207. */
  208. *base2 = pci_resource_start(ahd->dev_softc, 3);
  209. if (*base == 0 || *base2 == 0)
  210. return (ENOMEM);
  211. if (request_region(*base, 256, "aic79xx") == 0)
  212. return (ENOMEM);
  213. if (request_region(*base2, 256, "aic79xx") == 0) {
  214. release_region(*base2, 256);
  215. return (ENOMEM);
  216. }
  217. return (0);
  218. }
  219. static int
  220. ahd_linux_pci_reserve_mem_region(struct ahd_softc *ahd,
  221. u_long *bus_addr,
  222. uint8_t __iomem **maddr)
  223. {
  224. u_long start;
  225. u_long base_page;
  226. u_long base_offset;
  227. int error;
  228. if (aic79xx_allow_memio == 0)
  229. return (ENOMEM);
  230. if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) != 0)
  231. return (ENOMEM);
  232. error = 0;
  233. start = pci_resource_start(ahd->dev_softc, 1);
  234. base_page = start & PAGE_MASK;
  235. base_offset = start - base_page;
  236. if (start != 0) {
  237. *bus_addr = start;
  238. if (request_mem_region(start, 0x1000, "aic79xx") == 0)
  239. error = ENOMEM;
  240. if (error == 0) {
  241. *maddr = ioremap_nocache(base_page, base_offset + 256);
  242. if (*maddr == NULL) {
  243. error = ENOMEM;
  244. release_mem_region(start, 0x1000);
  245. } else
  246. *maddr += base_offset;
  247. }
  248. } else
  249. error = ENOMEM;
  250. return (error);
  251. }
  252. int
  253. ahd_pci_map_registers(struct ahd_softc *ahd)
  254. {
  255. uint32_t command;
  256. u_long base;
  257. uint8_t __iomem *maddr;
  258. int error;
  259. /*
  260. * If its allowed, we prefer memory mapped access.
  261. */
  262. command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, 4);
  263. command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
  264. base = 0;
  265. maddr = NULL;
  266. error = ahd_linux_pci_reserve_mem_region(ahd, &base, &maddr);
  267. if (error == 0) {
  268. ahd->platform_data->mem_busaddr = base;
  269. ahd->tags[0] = BUS_SPACE_MEMIO;
  270. ahd->bshs[0].maddr = maddr;
  271. ahd->tags[1] = BUS_SPACE_MEMIO;
  272. ahd->bshs[1].maddr = maddr + 0x100;
  273. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
  274. command | PCIM_CMD_MEMEN, 4);
  275. if (ahd_pci_test_register_access(ahd) != 0) {
  276. printf("aic79xx: PCI Device %d:%d:%d "
  277. "failed memory mapped test. Using PIO.\n",
  278. ahd_get_pci_bus(ahd->dev_softc),
  279. ahd_get_pci_slot(ahd->dev_softc),
  280. ahd_get_pci_function(ahd->dev_softc));
  281. iounmap(maddr);
  282. release_mem_region(ahd->platform_data->mem_busaddr,
  283. 0x1000);
  284. ahd->bshs[0].maddr = NULL;
  285. maddr = NULL;
  286. } else
  287. command |= PCIM_CMD_MEMEN;
  288. } else if (bootverbose) {
  289. printf("aic79xx: PCI%d:%d:%d MEM region 0x%lx "
  290. "unavailable. Cannot memory map device.\n",
  291. ahd_get_pci_bus(ahd->dev_softc),
  292. ahd_get_pci_slot(ahd->dev_softc),
  293. ahd_get_pci_function(ahd->dev_softc),
  294. base);
  295. }
  296. if (maddr == NULL) {
  297. u_long base2;
  298. error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2);
  299. if (error == 0) {
  300. ahd->tags[0] = BUS_SPACE_PIO;
  301. ahd->tags[1] = BUS_SPACE_PIO;
  302. ahd->bshs[0].ioport = base;
  303. ahd->bshs[1].ioport = base2;
  304. command |= PCIM_CMD_PORTEN;
  305. } else {
  306. printf("aic79xx: PCI%d:%d:%d IO regions 0x%lx and 0x%lx"
  307. "unavailable. Cannot map device.\n",
  308. ahd_get_pci_bus(ahd->dev_softc),
  309. ahd_get_pci_slot(ahd->dev_softc),
  310. ahd_get_pci_function(ahd->dev_softc),
  311. base, base2);
  312. }
  313. }
  314. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 4);
  315. return (error);
  316. }
  317. int
  318. ahd_pci_map_int(struct ahd_softc *ahd)
  319. {
  320. int error;
  321. error = request_irq(ahd->dev_softc->irq, ahd_linux_isr,
  322. SA_SHIRQ, "aic79xx", ahd);
  323. if (error == 0)
  324. ahd->platform_data->irq = ahd->dev_softc->irq;
  325. return (-error);
  326. }
  327. void
  328. ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state)
  329. {
  330. pci_set_power_state(ahd->dev_softc, new_state);
  331. }