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mxc-ssi.h

mxc-ssi.h 9.1 KB
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  1. /*
    2. 

  2.  * This program is free software; you can redistribute it and/or modify
    3. 

  3.  * it under the terms of the GNU General Public License version 2 as
    4. 

  4.  * published by the Free Software Foundation.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _IMX_SSI_H
    8. 

  8. #define _IMX_SSI_H
    9. 

  9. 

  10. #include <mach/hardware.h>
    11. 

  11. 

  12. /* SSI regs definition - MOVE to /arch/arm/plat-mxc/include/mach/ when stable */
    13. 

  13. #define SSI1_IO_BASE_ADDR	IO_ADDRESS(SSI1_BASE_ADDR)
    14. 

  14. #define SSI2_IO_BASE_ADDR	IO_ADDRESS(SSI2_BASE_ADDR)
    15. 

  15. 

  16. #define STX0   0x00
    17. 

  17. #define STX1   0x04
    18. 

  18. #define SRX0   0x08
    19. 

  19. #define SRX1   0x0c
    20. 

  20. #define SCR    0x10
    21. 

  21. #define SISR   0x14
    22. 

  22. #define SIER   0x18
    23. 

  23. #define STCR   0x1c
    24. 

  24. #define SRCR   0x20
    25. 

  25. #define STCCR  0x24
    26. 

  26. #define SRCCR  0x28
    27. 

  27. #define SFCSR  0x2c
    28. 

  28. #define STR    0x30
    29. 

  29. #define SOR    0x34
    30. 

  30. #define SACNT  0x38
    31. 

  31. #define SACADD 0x3c
    32. 

  32. #define SACDAT 0x40
    33. 

  33. #define SATAG  0x44
    34. 

  34. #define STMSK  0x48
    35. 

  35. #define SRMSK  0x4c
    36. 

  36. 

  37. #define SSI1_STX0	(*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX0)))
    38. 

  38. #define SSI1_STX1   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX1)))
    39. 

  39. #define SSI1_SRX0   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX0)))
    40. 

  40. #define SSI1_SRX1   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX1)))
    41. 

  41. #define SSI1_SCR    (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SCR)))
    42. 

  42. #define SSI1_SISR   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SISR)))
    43. 

  43. #define SSI1_SIER   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SIER)))
    44. 

  44. #define SSI1_STCR   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCR)))
    45. 

  45. #define SSI1_SRCR   (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCR)))
    46. 

  46. #define SSI1_STCCR  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCCR)))
    47. 

  47. #define SSI1_SRCCR  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCCR)))
    48. 

  48. #define SSI1_SFCSR  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SFCSR)))
    49. 

  49. #define SSI1_STR    (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STR)))
    50. 

  50. #define SSI1_SOR    (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SOR)))
    51. 

  51. #define SSI1_SACNT  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACNT)))
    52. 

  52. #define SSI1_SACADD (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACADD)))
    53. 

  53. #define SSI1_SACDAT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACDAT)))
    54. 

  54. #define SSI1_SATAG  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SATAG)))
    55. 

  55. #define SSI1_STMSK  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STMSK)))
    56. 

  56. #define SSI1_SRMSK  (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRMSK)))
    57. 

  57. 

  58. 

  59. #define SSI2_STX0	(*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX0)))
    60. 

  60. #define SSI2_STX1   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX1)))
    61. 

  61. #define SSI2_SRX0   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX0)))
    62. 

  62. #define SSI2_SRX1   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX1)))
    63. 

  63. #define SSI2_SCR    (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SCR)))
    64. 

  64. #define SSI2_SISR   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SISR)))
    65. 

  65. #define SSI2_SIER   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SIER)))
    66. 

  66. #define SSI2_STCR   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCR)))
    67. 

  67. #define SSI2_SRCR   (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCR)))
    68. 

  68. #define SSI2_STCCR  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCCR)))
    69. 

  69. #define SSI2_SRCCR  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCCR)))
    70. 

  70. #define SSI2_SFCSR  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SFCSR)))
    71. 

  71. #define SSI2_STR    (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STR)))
    72. 

  72. #define SSI2_SOR    (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SOR)))
    73. 

  73. #define SSI2_SACNT  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACNT)))
    74. 

  74. #define SSI2_SACADD (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACADD)))
    75. 

  75. #define SSI2_SACDAT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACDAT)))
    76. 

  76. #define SSI2_SATAG  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SATAG)))
    77. 

  77. #define SSI2_STMSK  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STMSK)))
    78. 

  78. #define SSI2_SRMSK  (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRMSK)))
    79. 

  79. 

  80. #define SSI_SCR_CLK_IST        (1 << 9)
    81. 

  81. #define SSI_SCR_TCH_EN         (1 << 8)
    82. 

  82. #define SSI_SCR_SYS_CLK_EN     (1 << 7)
    83. 

  83. #define SSI_SCR_I2S_MODE_NORM  (0 << 5)
    84. 

  84. #define SSI_SCR_I2S_MODE_MSTR  (1 << 5)
    85. 

  85. #define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
    86. 

  86. #define SSI_SCR_SYN            (1 << 4)
    87. 

  87. #define SSI_SCR_NET            (1 << 3)
    88. 

  88. #define SSI_SCR_RE             (1 << 2)
    89. 

  89. #define SSI_SCR_TE             (1 << 1)
    90. 

  90. #define SSI_SCR_SSIEN          (1 << 0)
    91. 

  91. 

  92. #define SSI_SISR_CMDAU         (1 << 18)
    93. 

  93. #define SSI_SISR_CMDDU         (1 << 17)
    94. 

  94. #define SSI_SISR_RXT           (1 << 16)
    95. 

  95. #define SSI_SISR_RDR1          (1 << 15)
    96. 

  96. #define SSI_SISR_RDR0          (1 << 14)
    97. 

  97. #define SSI_SISR_TDE1          (1 << 13)
    98. 

  98. #define SSI_SISR_TDE0          (1 << 12)
    99. 

  99. #define SSI_SISR_ROE1          (1 << 11)
    100. 

  100. #define SSI_SISR_ROE0          (1 << 10)
    101. 

  101. #define SSI_SISR_TUE1          (1 << 9)
    102. 

  102. #define SSI_SISR_TUE0          (1 << 8)
    103. 

  103. #define SSI_SISR_TFS           (1 << 7)
    104. 

  104. #define SSI_SISR_RFS           (1 << 6)
    105. 

  105. #define SSI_SISR_TLS           (1 << 5)
    106. 

  106. #define SSI_SISR_RLS           (1 << 4)
    107. 

  107. #define SSI_SISR_RFF1          (1 << 3)
    108. 

  108. #define SSI_SISR_RFF0          (1 << 2)
    109. 

  109. #define SSI_SISR_TFE1          (1 << 1)
    110. 

  110. #define SSI_SISR_TFE0          (1 << 0)
    111. 

  111. 

  112. #define SSI_SIER_RDMAE         (1 << 22)
    113. 

  113. #define SSI_SIER_RIE           (1 << 21)
    114. 

  114. #define SSI_SIER_TDMAE         (1 << 20)
    115. 

  115. #define SSI_SIER_TIE           (1 << 19)
    116. 

  116. #define SSI_SIER_CMDAU_EN      (1 << 18)
    117. 

  117. #define SSI_SIER_CMDDU_EN      (1 << 17)
    118. 

  118. #define SSI_SIER_RXT_EN        (1 << 16)
    119. 

  119. #define SSI_SIER_RDR1_EN       (1 << 15)
    120. 

  120. #define SSI_SIER_RDR0_EN       (1 << 14)
    121. 

  121. #define SSI_SIER_TDE1_EN       (1 << 13)
    122. 

  122. #define SSI_SIER_TDE0_EN       (1 << 12)
    123. 

  123. #define SSI_SIER_ROE1_EN       (1 << 11)
    124. 

  124. #define SSI_SIER_ROE0_EN       (1 << 10)
    125. 

  125. #define SSI_SIER_TUE1_EN       (1 << 9)
    126. 

  126. #define SSI_SIER_TUE0_EN       (1 << 8)
    127. 

  127. #define SSI_SIER_TFS_EN        (1 << 7)
    128. 

  128. #define SSI_SIER_RFS_EN        (1 << 6)
    129. 

  129. #define SSI_SIER_TLS_EN        (1 << 5)
    130. 

  130. #define SSI_SIER_RLS_EN        (1 << 4)
    131. 

  131. #define SSI_SIER_RFF1_EN       (1 << 3)
    132. 

  132. #define SSI_SIER_RFF0_EN       (1 << 2)
    133. 

  133. #define SSI_SIER_TFE1_EN       (1 << 1)
    134. 

  134. #define SSI_SIER_TFE0_EN       (1 << 0)
    135. 

  135. 

  136. #define SSI_STCR_TXBIT0        (1 << 9)
    137. 

  137. #define SSI_STCR_TFEN1         (1 << 8)
    138. 

  138. #define SSI_STCR_TFEN0         (1 << 7)
    139. 

  139. #define SSI_STCR_TFDIR         (1 << 6)
    140. 

  140. #define SSI_STCR_TXDIR         (1 << 5)
    141. 

  141. #define SSI_STCR_TSHFD         (1 << 4)
    142. 

  142. #define SSI_STCR_TSCKP         (1 << 3)
    143. 

  143. #define SSI_STCR_TFSI          (1 << 2)
    144. 

  144. #define SSI_STCR_TFSL          (1 << 1)
    145. 

  145. #define SSI_STCR_TEFS          (1 << 0)
    146. 

  146. 

  147. #define SSI_SRCR_RXBIT0        (1 << 9)
    148. 

  148. #define SSI_SRCR_RFEN1         (1 << 8)
    149. 

  149. #define SSI_SRCR_RFEN0         (1 << 7)
    150. 

  150. #define SSI_SRCR_RFDIR         (1 << 6)
    151. 

  151. #define SSI_SRCR_RXDIR         (1 << 5)
    152. 

  152. #define SSI_SRCR_RSHFD         (1 << 4)
    153. 

  153. #define SSI_SRCR_RSCKP         (1 << 3)
    154. 

  154. #define SSI_SRCR_RFSI          (1 << 2)
    155. 

  155. #define SSI_SRCR_RFSL          (1 << 1)
    156. 

  156. #define SSI_SRCR_REFS          (1 << 0)
    157. 

  157. 

  158. #define SSI_STCCR_DIV2         (1 << 18)
    159. 

  159. #define SSI_STCCR_PSR          (1 << 15)
    160. 

  160. #define SSI_STCCR_WL(x)        ((((x) - 2) >> 1) << 13)
    161. 

  161. #define SSI_STCCR_DC(x)        (((x) & 0x1f) << 8)
    162. 

  162. #define SSI_STCCR_PM(x)        (((x) & 0xff) << 0)
    163. 

  163. #define SSI_STCCR_WL_MASK        (0xf << 13)
    164. 

  164. #define SSI_STCCR_DC_MASK        (0x1f << 8)
    165. 

  165. #define SSI_STCCR_PM_MASK        (0xff << 0)
    166. 

  166. 

  167. #define SSI_SRCCR_DIV2         (1 << 18)
    168. 

  168. #define SSI_SRCCR_PSR          (1 << 15)
    169. 

  169. #define SSI_SRCCR_WL(x)        ((((x) - 2) >> 1) << 13)
    170. 

  170. #define SSI_SRCCR_DC(x)        (((x) & 0x1f) << 8)
    171. 

  171. #define SSI_SRCCR_PM(x)        (((x) & 0xff) << 0)
    172. 

  172. #define SSI_SRCCR_WL_MASK        (0xf << 13)
    173. 

  173. #define SSI_SRCCR_DC_MASK        (0x1f << 8)
    174. 

  174. #define SSI_SRCCR_PM_MASK        (0xff << 0)
    175. 

  175. 

  176. 

  177. #define SSI_SFCSR_RFCNT1(x)   (((x) & 0xf) << 28)
    178. 

  178. #define SSI_SFCSR_TFCNT1(x)   (((x) & 0xf) << 24)
    179. 

  179. #define SSI_SFCSR_RFWM1(x)    (((x) & 0xf) << 20)
    180. 

  180. #define SSI_SFCSR_TFWM1(x)    (((x) & 0xf) << 16)
    181. 

  181. #define SSI_SFCSR_RFCNT0(x)   (((x) & 0xf) << 12)
    182. 

  182. #define SSI_SFCSR_TFCNT0(x)   (((x) & 0xf) <<  8)
    183. 

  183. #define SSI_SFCSR_RFWM0(x)    (((x) & 0xf) <<  4)
    184. 

  184. #define SSI_SFCSR_TFWM0(x)    (((x) & 0xf) <<  0)
    185. 

  185. 

  186. #define SSI_STR_TEST          (1 << 15)
    187. 

  187. #define SSI_STR_RCK2TCK       (1 << 14)
    188. 

  188. #define SSI_STR_RFS2TFS       (1 << 13)
    189. 

  189. #define SSI_STR_RXSTATE(x)    (((x) & 0xf) << 8)
    190. 

  190. #define SSI_STR_TXD2RXD       (1 <<  7)
    191. 

  191. #define SSI_STR_TCK2RCK       (1 <<  6)
    192. 

  192. #define SSI_STR_TFS2RFS       (1 <<  5)
    193. 

  193. #define SSI_STR_TXSTATE(x)    (((x) & 0xf) << 0)
    194. 

  194. 

  195. #define SSI_SOR_CLKOFF        (1 << 6)
    196. 

  196. #define SSI_SOR_RX_CLR        (1 << 5)
    197. 

  197. #define SSI_SOR_TX_CLR        (1 << 4)
    198. 

  198. #define SSI_SOR_INIT          (1 << 3)
    199. 

  199. #define SSI_SOR_WAIT(x)       (((x) & 0x3) << 1)
    200. 

  200. #define SSI_SOR_SYNRST        (1 << 0)
    201. 

  201. 

  202. #define SSI_SACNT_FRDIV(x)    (((x) & 0x3f) << 5)
    203. 

  203. #define SSI_SACNT_WR          (x << 4)
    204. 

  204. #define SSI_SACNT_RD          (x << 3)
    205. 

  205. #define SSI_SACNT_TIF         (x << 2)
    206. 

  206. #define SSI_SACNT_FV          (x << 1)
    207. 

  207. #define SSI_SACNT_AC97EN      (x << 0)
    208. 

  208. 

  209. /* Watermarks for FIFO's */
    210. 

  210. #define TXFIFO_WATERMARK				0x4
    211. 

  211. #define RXFIFO_WATERMARK				0x4
    212. 

  212. 

  213. /* i.MX DAI SSP ID's */
    214. 

  214. #define IMX_DAI_SSI0			0 /* SSI1 FIFO 0 */
    215. 

  215. #define IMX_DAI_SSI1			1 /* SSI1 FIFO 1 */
    216. 

  216. #define IMX_DAI_SSI2			2 /* SSI2 FIFO 0 */
    217. 

  217. #define IMX_DAI_SSI3			3 /* SSI2 FIFO 1 */
    218. 

  218. 

  219. /* SSI clock sources */
    220. 

  220. #define IMX_SSP_SYS_CLK		0
    221. 

  221. 

  222. /* SSI audio dividers */
    223. 

  223. #define IMX_SSI_TX_DIV_2			0
    224. 

  224. #define IMX_SSI_TX_DIV_PSR			1
    225. 

  225. #define IMX_SSI_TX_DIV_PM			2
    226. 

  226. #define IMX_SSI_RX_DIV_2			3
    227. 

  227. #define IMX_SSI_RX_DIV_PSR			4
    228. 

  228. #define IMX_SSI_RX_DIV_PM			5
    229. 

  229. 

  230. 

  231. /* SSI Div 2 */
    232. 

  232. #define IMX_SSI_DIV_2_OFF		(~SSI_STCCR_DIV2)
    233. 

  233. #define IMX_SSI_DIV_2_ON		SSI_STCCR_DIV2
    234. 

  234. 

  235. extern struct snd_soc_dai imx_ssi_pcm_dai[4];
    236. 

  236. extern int get_ssi_clk(int ssi, struct device *dev);
    237. 

  237. extern void put_ssi_clk(int ssi);
    238. 

  238. #endif
    239.