twl4030.c 69 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. unsigned int bypass_state;
  120. unsigned int codec_powered;
  121. unsigned int codec_muted;
  122. struct snd_pcm_substream *master_substream;
  123. struct snd_pcm_substream *slave_substream;
  124. unsigned int configured;
  125. unsigned int rate;
  126. unsigned int sample_bits;
  127. unsigned int channels;
  128. unsigned int sysclk;
  129. /* Headset output state handling */
  130. unsigned int hsl_enabled;
  131. unsigned int hsr_enabled;
  132. };
  133. /*
  134. * read twl4030 register cache
  135. */
  136. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  137. unsigned int reg)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return -EIO;
  142. return cache[reg];
  143. }
  144. /*
  145. * write twl4030 register cache
  146. */
  147. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  148. u8 reg, u8 value)
  149. {
  150. u8 *cache = codec->reg_cache;
  151. if (reg >= TWL4030_CACHEREGNUM)
  152. return;
  153. cache[reg] = value;
  154. }
  155. /*
  156. * write to the twl4030 register space
  157. */
  158. static int twl4030_write(struct snd_soc_codec *codec,
  159. unsigned int reg, unsigned int value)
  160. {
  161. twl4030_write_reg_cache(codec, reg, value);
  162. if (likely(reg < TWL4030_REG_SW_SHADOW))
  163. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  164. reg);
  165. else
  166. return 0;
  167. }
  168. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  169. {
  170. struct twl4030_priv *twl4030 = codec->private_data;
  171. u8 mode;
  172. if (enable == twl4030->codec_powered)
  173. return;
  174. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  175. if (enable)
  176. mode |= TWL4030_CODECPDZ;
  177. else
  178. mode &= ~TWL4030_CODECPDZ;
  179. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  180. twl4030->codec_powered = enable;
  181. /* REVISIT: this delay is present in TI sample drivers */
  182. /* but there seems to be no TRM requirement for it */
  183. udelay(10);
  184. }
  185. static void twl4030_init_chip(struct snd_soc_codec *codec)
  186. {
  187. u8 *cache = codec->reg_cache;
  188. int i;
  189. /* clear CODECPDZ prior to setting register defaults */
  190. twl4030_codec_enable(codec, 0);
  191. /* set all audio section registers to reasonable defaults */
  192. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  193. twl4030_write(codec, i, cache[i]);
  194. }
  195. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  196. {
  197. struct twl4030_priv *twl4030 = codec->private_data;
  198. u8 reg_val;
  199. if (mute == twl4030->codec_muted)
  200. return;
  201. if (mute) {
  202. /* Disable PLL */
  203. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  204. reg_val &= ~TWL4030_APLL_EN;
  205. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  206. } else {
  207. /* Enable PLL */
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  209. reg_val |= TWL4030_APLL_EN;
  210. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  211. }
  212. twl4030->codec_muted = mute;
  213. }
  214. static void twl4030_power_up(struct snd_soc_codec *codec)
  215. {
  216. struct twl4030_priv *twl4030 = codec->private_data;
  217. u8 anamicl, regmisc1, byte;
  218. int i = 0;
  219. if (twl4030->codec_powered)
  220. return;
  221. /* set CODECPDZ to turn on codec */
  222. twl4030_codec_enable(codec, 1);
  223. /* initiate offset cancellation */
  224. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  225. twl4030_write(codec, TWL4030_REG_ANAMICL,
  226. anamicl | TWL4030_CNCL_OFFSET_START);
  227. /* wait for offset cancellation to complete */
  228. do {
  229. /* this takes a little while, so don't slam i2c */
  230. udelay(2000);
  231. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  232. TWL4030_REG_ANAMICL);
  233. } while ((i++ < 100) &&
  234. ((byte & TWL4030_CNCL_OFFSET_START) ==
  235. TWL4030_CNCL_OFFSET_START));
  236. /* Make sure that the reg_cache has the same value as the HW */
  237. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  238. /* anti-pop when changing analog gain */
  239. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  240. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  241. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  242. /* toggle CODECPDZ as per TRM */
  243. twl4030_codec_enable(codec, 0);
  244. twl4030_codec_enable(codec, 1);
  245. }
  246. /*
  247. * Unconditional power down
  248. */
  249. static void twl4030_power_down(struct snd_soc_codec *codec)
  250. {
  251. /* power down */
  252. twl4030_codec_enable(codec, 0);
  253. }
  254. /* Earpiece */
  255. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  256. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  257. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  258. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  259. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  260. };
  261. /* PreDrive Left */
  262. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  263. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  264. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  265. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  266. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  267. };
  268. /* PreDrive Right */
  269. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  270. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  271. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  272. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  273. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  274. };
  275. /* Headset Left */
  276. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  277. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  278. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  279. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  280. };
  281. /* Headset Right */
  282. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  283. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  284. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  285. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  286. };
  287. /* Carkit Left */
  288. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  289. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  290. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  291. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  292. };
  293. /* Carkit Right */
  294. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  295. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  296. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  297. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  298. };
  299. /* Handsfree Left */
  300. static const char *twl4030_handsfreel_texts[] =
  301. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  302. static const struct soc_enum twl4030_handsfreel_enum =
  303. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  304. ARRAY_SIZE(twl4030_handsfreel_texts),
  305. twl4030_handsfreel_texts);
  306. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  307. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  308. /* Handsfree Left virtual mute */
  309. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  310. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  311. /* Handsfree Right */
  312. static const char *twl4030_handsfreer_texts[] =
  313. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  314. static const struct soc_enum twl4030_handsfreer_enum =
  315. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  316. ARRAY_SIZE(twl4030_handsfreer_texts),
  317. twl4030_handsfreer_texts);
  318. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  319. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  320. /* Handsfree Right virtual mute */
  321. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  322. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  323. /* Vibra */
  324. /* Vibra audio path selection */
  325. static const char *twl4030_vibra_texts[] =
  326. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  327. static const struct soc_enum twl4030_vibra_enum =
  328. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  329. ARRAY_SIZE(twl4030_vibra_texts),
  330. twl4030_vibra_texts);
  331. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  332. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  333. /* Vibra path selection: local vibrator (PWM) or audio driven */
  334. static const char *twl4030_vibrapath_texts[] =
  335. {"Local vibrator", "Audio"};
  336. static const struct soc_enum twl4030_vibrapath_enum =
  337. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  338. ARRAY_SIZE(twl4030_vibrapath_texts),
  339. twl4030_vibrapath_texts);
  340. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  341. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  342. /* Left analog microphone selection */
  343. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  344. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  345. TWL4030_REG_ANAMICL, 0, 1, 0),
  346. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  347. TWL4030_REG_ANAMICL, 1, 1, 0),
  348. SOC_DAPM_SINGLE("AUXL Capture Switch",
  349. TWL4030_REG_ANAMICL, 2, 1, 0),
  350. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  351. TWL4030_REG_ANAMICL, 3, 1, 0),
  352. };
  353. /* Right analog microphone selection */
  354. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  355. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  356. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  357. };
  358. /* TX1 L/R Analog/Digital microphone selection */
  359. static const char *twl4030_micpathtx1_texts[] =
  360. {"Analog", "Digimic0"};
  361. static const struct soc_enum twl4030_micpathtx1_enum =
  362. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  363. ARRAY_SIZE(twl4030_micpathtx1_texts),
  364. twl4030_micpathtx1_texts);
  365. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  366. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  367. /* TX2 L/R Analog/Digital microphone selection */
  368. static const char *twl4030_micpathtx2_texts[] =
  369. {"Analog", "Digimic1"};
  370. static const struct soc_enum twl4030_micpathtx2_enum =
  371. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  372. ARRAY_SIZE(twl4030_micpathtx2_texts),
  373. twl4030_micpathtx2_texts);
  374. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  375. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  376. /* Analog bypass for AudioR1 */
  377. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  378. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  379. /* Analog bypass for AudioL1 */
  380. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  381. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  382. /* Analog bypass for AudioR2 */
  383. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  384. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  385. /* Analog bypass for AudioL2 */
  386. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  387. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  388. /* Analog bypass for Voice */
  389. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  390. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  391. /* Digital bypass gain, 0 mutes the bypass */
  392. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  393. TLV_DB_RANGE_HEAD(2),
  394. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  395. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  396. };
  397. /* Digital bypass left (TX1L -> RX2L) */
  398. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  399. SOC_DAPM_SINGLE_TLV("Volume",
  400. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  401. twl4030_dapm_dbypass_tlv);
  402. /* Digital bypass right (TX1R -> RX2R) */
  403. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  404. SOC_DAPM_SINGLE_TLV("Volume",
  405. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  406. twl4030_dapm_dbypass_tlv);
  407. /*
  408. * Voice Sidetone GAIN volume control:
  409. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  410. */
  411. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  412. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  413. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  414. SOC_DAPM_SINGLE_TLV("Volume",
  415. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  416. twl4030_dapm_dbypassv_tlv);
  417. static int micpath_event(struct snd_soc_dapm_widget *w,
  418. struct snd_kcontrol *kcontrol, int event)
  419. {
  420. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  421. unsigned char adcmicsel, micbias_ctl;
  422. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  423. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  424. /* Prepare the bits for the given TX path:
  425. * shift_l == 0: TX1 microphone path
  426. * shift_l == 2: TX2 microphone path */
  427. if (e->shift_l) {
  428. /* TX2 microphone path */
  429. if (adcmicsel & TWL4030_TX2IN_SEL)
  430. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  431. else
  432. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  433. } else {
  434. /* TX1 microphone path */
  435. if (adcmicsel & TWL4030_TX1IN_SEL)
  436. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  437. else
  438. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  439. }
  440. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  441. return 0;
  442. }
  443. /*
  444. * Output PGA builder:
  445. * Handle the muting and unmuting of the given output (turning off the
  446. * amplifier associated with the output pin)
  447. * On mute bypass the reg_cache and mute the volume
  448. * On unmute: restore the register content
  449. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  450. */
  451. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  452. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  453. struct snd_kcontrol *kcontrol, int event) \
  454. { \
  455. u8 reg_val; \
  456. \
  457. switch (event) { \
  458. case SND_SOC_DAPM_POST_PMU: \
  459. twl4030_write(w->codec, reg, \
  460. twl4030_read_reg_cache(w->codec, reg)); \
  461. break; \
  462. case SND_SOC_DAPM_POST_PMD: \
  463. reg_val = twl4030_read_reg_cache(w->codec, reg); \
  464. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  465. reg_val & (~mask), \
  466. reg); \
  467. break; \
  468. } \
  469. return 0; \
  470. }
  471. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  472. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  473. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  474. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  475. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  476. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  477. {
  478. unsigned char hs_ctl;
  479. hs_ctl = twl4030_read_reg_cache(codec, reg);
  480. if (ramp) {
  481. /* HF ramp-up */
  482. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  483. twl4030_write(codec, reg, hs_ctl);
  484. udelay(10);
  485. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  486. twl4030_write(codec, reg, hs_ctl);
  487. udelay(40);
  488. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  489. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  490. twl4030_write(codec, reg, hs_ctl);
  491. } else {
  492. /* HF ramp-down */
  493. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  494. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  495. twl4030_write(codec, reg, hs_ctl);
  496. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  497. twl4030_write(codec, reg, hs_ctl);
  498. udelay(40);
  499. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  500. twl4030_write(codec, reg, hs_ctl);
  501. }
  502. }
  503. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  504. struct snd_kcontrol *kcontrol, int event)
  505. {
  506. switch (event) {
  507. case SND_SOC_DAPM_POST_PMU:
  508. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  509. break;
  510. case SND_SOC_DAPM_POST_PMD:
  511. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  512. break;
  513. }
  514. return 0;
  515. }
  516. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  517. struct snd_kcontrol *kcontrol, int event)
  518. {
  519. switch (event) {
  520. case SND_SOC_DAPM_POST_PMU:
  521. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  525. break;
  526. }
  527. return 0;
  528. }
  529. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  530. {
  531. struct snd_soc_device *socdev = codec->socdev;
  532. struct twl4030_setup_data *setup = socdev->codec_data;
  533. unsigned char hs_gain, hs_pop;
  534. struct twl4030_priv *twl4030 = codec->private_data;
  535. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  536. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  537. 8388608, 16777216, 33554432, 67108864};
  538. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  539. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  540. /* Enable external mute control, this dramatically reduces
  541. * the pop-noise */
  542. if (setup && setup->hs_extmute) {
  543. if (setup->set_hs_extmute) {
  544. setup->set_hs_extmute(1);
  545. } else {
  546. hs_pop |= TWL4030_EXTMUTE;
  547. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  548. }
  549. }
  550. if (ramp) {
  551. /* Headset ramp-up according to the TRM */
  552. hs_pop |= TWL4030_VMID_EN;
  553. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  554. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  555. hs_pop |= TWL4030_RAMP_EN;
  556. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  557. /* Wait ramp delay time + 1, so the VMID can settle */
  558. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  559. twl4030->sysclk) + 1);
  560. } else {
  561. /* Headset ramp-down _not_ according to
  562. * the TRM, but in a way that it is working */
  563. hs_pop &= ~TWL4030_RAMP_EN;
  564. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  565. /* Wait ramp delay time + 1, so the VMID can settle */
  566. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  567. twl4030->sysclk) + 1);
  568. /* Bypass the reg_cache to mute the headset */
  569. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  570. hs_gain & (~0x0f),
  571. TWL4030_REG_HS_GAIN_SET);
  572. hs_pop &= ~TWL4030_VMID_EN;
  573. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  574. }
  575. /* Disable external mute */
  576. if (setup && setup->hs_extmute) {
  577. if (setup->set_hs_extmute) {
  578. setup->set_hs_extmute(0);
  579. } else {
  580. hs_pop &= ~TWL4030_EXTMUTE;
  581. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  582. }
  583. }
  584. }
  585. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  586. struct snd_kcontrol *kcontrol, int event)
  587. {
  588. struct twl4030_priv *twl4030 = w->codec->private_data;
  589. switch (event) {
  590. case SND_SOC_DAPM_POST_PMU:
  591. /* Do the ramp-up only once */
  592. if (!twl4030->hsr_enabled)
  593. headset_ramp(w->codec, 1);
  594. twl4030->hsl_enabled = 1;
  595. break;
  596. case SND_SOC_DAPM_POST_PMD:
  597. /* Do the ramp-down only if both headsetL/R is disabled */
  598. if (!twl4030->hsr_enabled)
  599. headset_ramp(w->codec, 0);
  600. twl4030->hsl_enabled = 0;
  601. break;
  602. }
  603. return 0;
  604. }
  605. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  606. struct snd_kcontrol *kcontrol, int event)
  607. {
  608. struct twl4030_priv *twl4030 = w->codec->private_data;
  609. switch (event) {
  610. case SND_SOC_DAPM_POST_PMU:
  611. /* Do the ramp-up only once */
  612. if (!twl4030->hsl_enabled)
  613. headset_ramp(w->codec, 1);
  614. twl4030->hsr_enabled = 1;
  615. break;
  616. case SND_SOC_DAPM_POST_PMD:
  617. /* Do the ramp-down only if both headsetL/R is disabled */
  618. if (!twl4030->hsl_enabled)
  619. headset_ramp(w->codec, 0);
  620. twl4030->hsr_enabled = 0;
  621. break;
  622. }
  623. return 0;
  624. }
  625. static int bypass_event(struct snd_soc_dapm_widget *w,
  626. struct snd_kcontrol *kcontrol, int event)
  627. {
  628. struct soc_mixer_control *m =
  629. (struct soc_mixer_control *)w->kcontrols->private_value;
  630. struct twl4030_priv *twl4030 = w->codec->private_data;
  631. unsigned char reg, misc;
  632. reg = twl4030_read_reg_cache(w->codec, m->reg);
  633. /*
  634. * bypass_state[0:3] - analog HiFi bypass
  635. * bypass_state[4] - analog voice bypass
  636. * bypass_state[5] - digital voice bypass
  637. * bypass_state[6:7] - digital HiFi bypass
  638. */
  639. if (m->reg == TWL4030_REG_VSTPGA) {
  640. /* Voice digital bypass */
  641. if (reg)
  642. twl4030->bypass_state |= (1 << 5);
  643. else
  644. twl4030->bypass_state &= ~(1 << 5);
  645. } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  646. /* Analog bypass */
  647. if (reg & (1 << m->shift))
  648. twl4030->bypass_state |=
  649. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  650. else
  651. twl4030->bypass_state &=
  652. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  653. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  654. /* Analog voice bypass */
  655. if (reg & (1 << m->shift))
  656. twl4030->bypass_state |= (1 << 4);
  657. else
  658. twl4030->bypass_state &= ~(1 << 4);
  659. } else {
  660. /* Digital bypass */
  661. if (reg & (0x7 << m->shift))
  662. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  663. else
  664. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  665. }
  666. /* Enable master analog loopback mode if any analog switch is enabled*/
  667. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  668. if (twl4030->bypass_state & 0x1F)
  669. misc |= TWL4030_FMLOOP_EN;
  670. else
  671. misc &= ~TWL4030_FMLOOP_EN;
  672. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  673. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  674. if (twl4030->bypass_state)
  675. twl4030_codec_mute(w->codec, 0);
  676. else
  677. twl4030_codec_mute(w->codec, 1);
  678. }
  679. return 0;
  680. }
  681. /*
  682. * Some of the gain controls in TWL (mostly those which are associated with
  683. * the outputs) are implemented in an interesting way:
  684. * 0x0 : Power down (mute)
  685. * 0x1 : 6dB
  686. * 0x2 : 0 dB
  687. * 0x3 : -6 dB
  688. * Inverting not going to help with these.
  689. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  690. */
  691. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  692. xinvert, tlv_array) \
  693. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  694. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  695. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  696. .tlv.p = (tlv_array), \
  697. .info = snd_soc_info_volsw, \
  698. .get = snd_soc_get_volsw_twl4030, \
  699. .put = snd_soc_put_volsw_twl4030, \
  700. .private_value = (unsigned long)&(struct soc_mixer_control) \
  701. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  702. .max = xmax, .invert = xinvert} }
  703. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  704. xinvert, tlv_array) \
  705. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  706. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  707. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  708. .tlv.p = (tlv_array), \
  709. .info = snd_soc_info_volsw_2r, \
  710. .get = snd_soc_get_volsw_r2_twl4030,\
  711. .put = snd_soc_put_volsw_r2_twl4030, \
  712. .private_value = (unsigned long)&(struct soc_mixer_control) \
  713. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  714. .rshift = xshift, .max = xmax, .invert = xinvert} }
  715. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  716. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  717. xinvert, tlv_array)
  718. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  719. struct snd_ctl_elem_value *ucontrol)
  720. {
  721. struct soc_mixer_control *mc =
  722. (struct soc_mixer_control *)kcontrol->private_value;
  723. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  724. unsigned int reg = mc->reg;
  725. unsigned int shift = mc->shift;
  726. unsigned int rshift = mc->rshift;
  727. int max = mc->max;
  728. int mask = (1 << fls(max)) - 1;
  729. ucontrol->value.integer.value[0] =
  730. (snd_soc_read(codec, reg) >> shift) & mask;
  731. if (ucontrol->value.integer.value[0])
  732. ucontrol->value.integer.value[0] =
  733. max + 1 - ucontrol->value.integer.value[0];
  734. if (shift != rshift) {
  735. ucontrol->value.integer.value[1] =
  736. (snd_soc_read(codec, reg) >> rshift) & mask;
  737. if (ucontrol->value.integer.value[1])
  738. ucontrol->value.integer.value[1] =
  739. max + 1 - ucontrol->value.integer.value[1];
  740. }
  741. return 0;
  742. }
  743. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  744. struct snd_ctl_elem_value *ucontrol)
  745. {
  746. struct soc_mixer_control *mc =
  747. (struct soc_mixer_control *)kcontrol->private_value;
  748. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  749. unsigned int reg = mc->reg;
  750. unsigned int shift = mc->shift;
  751. unsigned int rshift = mc->rshift;
  752. int max = mc->max;
  753. int mask = (1 << fls(max)) - 1;
  754. unsigned short val, val2, val_mask;
  755. val = (ucontrol->value.integer.value[0] & mask);
  756. val_mask = mask << shift;
  757. if (val)
  758. val = max + 1 - val;
  759. val = val << shift;
  760. if (shift != rshift) {
  761. val2 = (ucontrol->value.integer.value[1] & mask);
  762. val_mask |= mask << rshift;
  763. if (val2)
  764. val2 = max + 1 - val2;
  765. val |= val2 << rshift;
  766. }
  767. return snd_soc_update_bits(codec, reg, val_mask, val);
  768. }
  769. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  770. struct snd_ctl_elem_value *ucontrol)
  771. {
  772. struct soc_mixer_control *mc =
  773. (struct soc_mixer_control *)kcontrol->private_value;
  774. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  775. unsigned int reg = mc->reg;
  776. unsigned int reg2 = mc->rreg;
  777. unsigned int shift = mc->shift;
  778. int max = mc->max;
  779. int mask = (1<<fls(max))-1;
  780. ucontrol->value.integer.value[0] =
  781. (snd_soc_read(codec, reg) >> shift) & mask;
  782. ucontrol->value.integer.value[1] =
  783. (snd_soc_read(codec, reg2) >> shift) & mask;
  784. if (ucontrol->value.integer.value[0])
  785. ucontrol->value.integer.value[0] =
  786. max + 1 - ucontrol->value.integer.value[0];
  787. if (ucontrol->value.integer.value[1])
  788. ucontrol->value.integer.value[1] =
  789. max + 1 - ucontrol->value.integer.value[1];
  790. return 0;
  791. }
  792. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  793. struct snd_ctl_elem_value *ucontrol)
  794. {
  795. struct soc_mixer_control *mc =
  796. (struct soc_mixer_control *)kcontrol->private_value;
  797. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  798. unsigned int reg = mc->reg;
  799. unsigned int reg2 = mc->rreg;
  800. unsigned int shift = mc->shift;
  801. int max = mc->max;
  802. int mask = (1 << fls(max)) - 1;
  803. int err;
  804. unsigned short val, val2, val_mask;
  805. val_mask = mask << shift;
  806. val = (ucontrol->value.integer.value[0] & mask);
  807. val2 = (ucontrol->value.integer.value[1] & mask);
  808. if (val)
  809. val = max + 1 - val;
  810. if (val2)
  811. val2 = max + 1 - val2;
  812. val = val << shift;
  813. val2 = val2 << shift;
  814. err = snd_soc_update_bits(codec, reg, val_mask, val);
  815. if (err < 0)
  816. return err;
  817. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  818. return err;
  819. }
  820. /* Codec operation modes */
  821. static const char *twl4030_op_modes_texts[] = {
  822. "Option 2 (voice/audio)", "Option 1 (audio)"
  823. };
  824. static const struct soc_enum twl4030_op_modes_enum =
  825. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  826. ARRAY_SIZE(twl4030_op_modes_texts),
  827. twl4030_op_modes_texts);
  828. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  832. struct twl4030_priv *twl4030 = codec->private_data;
  833. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  834. unsigned short val;
  835. unsigned short mask, bitmask;
  836. if (twl4030->configured) {
  837. printk(KERN_ERR "twl4030 operation mode cannot be "
  838. "changed on-the-fly\n");
  839. return -EBUSY;
  840. }
  841. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  842. ;
  843. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  844. return -EINVAL;
  845. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  846. mask = (bitmask - 1) << e->shift_l;
  847. if (e->shift_l != e->shift_r) {
  848. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  849. return -EINVAL;
  850. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  851. mask |= (bitmask - 1) << e->shift_r;
  852. }
  853. return snd_soc_update_bits(codec, e->reg, mask, val);
  854. }
  855. /*
  856. * FGAIN volume control:
  857. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  858. */
  859. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  860. /*
  861. * CGAIN volume control:
  862. * 0 dB to 12 dB in 6 dB steps
  863. * value 2 and 3 means 12 dB
  864. */
  865. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  866. /*
  867. * Voice Downlink GAIN volume control:
  868. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  869. */
  870. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  871. /*
  872. * Analog playback gain
  873. * -24 dB to 12 dB in 2 dB steps
  874. */
  875. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  876. /*
  877. * Gain controls tied to outputs
  878. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  879. */
  880. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  881. /*
  882. * Gain control for earpiece amplifier
  883. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  884. */
  885. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  886. /*
  887. * Capture gain after the ADCs
  888. * from 0 dB to 31 dB in 1 dB steps
  889. */
  890. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  891. /*
  892. * Gain control for input amplifiers
  893. * 0 dB to 30 dB in 6 dB steps
  894. */
  895. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  896. /* AVADC clock priority */
  897. static const char *twl4030_avadc_clk_priority_texts[] = {
  898. "Voice high priority", "HiFi high priority"
  899. };
  900. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  901. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  902. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  903. twl4030_avadc_clk_priority_texts);
  904. static const char *twl4030_rampdelay_texts[] = {
  905. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  906. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  907. "3495/2581/1748 ms"
  908. };
  909. static const struct soc_enum twl4030_rampdelay_enum =
  910. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  911. ARRAY_SIZE(twl4030_rampdelay_texts),
  912. twl4030_rampdelay_texts);
  913. /* Vibra H-bridge direction mode */
  914. static const char *twl4030_vibradirmode_texts[] = {
  915. "Vibra H-bridge direction", "Audio data MSB",
  916. };
  917. static const struct soc_enum twl4030_vibradirmode_enum =
  918. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  919. ARRAY_SIZE(twl4030_vibradirmode_texts),
  920. twl4030_vibradirmode_texts);
  921. /* Vibra H-bridge direction */
  922. static const char *twl4030_vibradir_texts[] = {
  923. "Positive polarity", "Negative polarity",
  924. };
  925. static const struct soc_enum twl4030_vibradir_enum =
  926. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  927. ARRAY_SIZE(twl4030_vibradir_texts),
  928. twl4030_vibradir_texts);
  929. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  930. /* Codec operation mode control */
  931. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  932. snd_soc_get_enum_double,
  933. snd_soc_put_twl4030_opmode_enum_double),
  934. /* Common playback gain controls */
  935. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  936. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  937. 0, 0x3f, 0, digital_fine_tlv),
  938. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  939. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  940. 0, 0x3f, 0, digital_fine_tlv),
  941. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  942. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  943. 6, 0x2, 0, digital_coarse_tlv),
  944. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  945. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  946. 6, 0x2, 0, digital_coarse_tlv),
  947. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  948. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  949. 3, 0x12, 1, analog_tlv),
  950. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  951. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  952. 3, 0x12, 1, analog_tlv),
  953. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  954. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  955. 1, 1, 0),
  956. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  957. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  958. 1, 1, 0),
  959. /* Common voice downlink gain controls */
  960. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  961. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  962. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  963. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  964. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  965. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  966. /* Separate output gain controls */
  967. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  968. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  969. 4, 3, 0, output_tvl),
  970. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  971. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  972. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  973. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  974. 4, 3, 0, output_tvl),
  975. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  976. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  977. /* Common capture gain controls */
  978. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  979. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  980. 0, 0x1f, 0, digital_capture_tlv),
  981. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  982. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  983. 0, 0x1f, 0, digital_capture_tlv),
  984. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  985. 0, 3, 5, 0, input_gain_tlv),
  986. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  987. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  988. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  989. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  990. };
  991. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  992. /* Left channel inputs */
  993. SND_SOC_DAPM_INPUT("MAINMIC"),
  994. SND_SOC_DAPM_INPUT("HSMIC"),
  995. SND_SOC_DAPM_INPUT("AUXL"),
  996. SND_SOC_DAPM_INPUT("CARKITMIC"),
  997. /* Right channel inputs */
  998. SND_SOC_DAPM_INPUT("SUBMIC"),
  999. SND_SOC_DAPM_INPUT("AUXR"),
  1000. /* Digital microphones (Stereo) */
  1001. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1002. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1003. /* Outputs */
  1004. SND_SOC_DAPM_OUTPUT("OUTL"),
  1005. SND_SOC_DAPM_OUTPUT("OUTR"),
  1006. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1007. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1008. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1009. SND_SOC_DAPM_OUTPUT("HSOL"),
  1010. SND_SOC_DAPM_OUTPUT("HSOR"),
  1011. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1012. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1013. SND_SOC_DAPM_OUTPUT("HFL"),
  1014. SND_SOC_DAPM_OUTPUT("HFR"),
  1015. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1016. /* DACs */
  1017. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1018. SND_SOC_NOPM, 0, 0),
  1019. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1020. SND_SOC_NOPM, 0, 0),
  1021. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1022. SND_SOC_NOPM, 0, 0),
  1023. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1024. SND_SOC_NOPM, 0, 0),
  1025. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1026. SND_SOC_NOPM, 0, 0),
  1027. /* Analog bypasses */
  1028. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1029. &twl4030_dapm_abypassr1_control, bypass_event,
  1030. SND_SOC_DAPM_POST_REG),
  1031. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1032. &twl4030_dapm_abypassl1_control,
  1033. bypass_event, SND_SOC_DAPM_POST_REG),
  1034. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1035. &twl4030_dapm_abypassr2_control,
  1036. bypass_event, SND_SOC_DAPM_POST_REG),
  1037. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1038. &twl4030_dapm_abypassl2_control,
  1039. bypass_event, SND_SOC_DAPM_POST_REG),
  1040. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1041. &twl4030_dapm_abypassv_control,
  1042. bypass_event, SND_SOC_DAPM_POST_REG),
  1043. /* Digital bypasses */
  1044. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1045. &twl4030_dapm_dbypassl_control, bypass_event,
  1046. SND_SOC_DAPM_POST_REG),
  1047. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1048. &twl4030_dapm_dbypassr_control, bypass_event,
  1049. SND_SOC_DAPM_POST_REG),
  1050. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1051. &twl4030_dapm_dbypassv_control, bypass_event,
  1052. SND_SOC_DAPM_POST_REG),
  1053. /* Digital mixers, power control for the physical DACs */
  1054. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1055. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1056. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1057. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1058. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1059. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1060. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1061. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1062. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1063. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1064. /* Analog mixers, power control for the physical PGAs */
  1065. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1066. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1067. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1068. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1069. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1070. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1071. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1072. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1073. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1074. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1075. /* Output MIXER controls */
  1076. /* Earpiece */
  1077. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1078. &twl4030_dapm_earpiece_controls[0],
  1079. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1080. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1081. 0, 0, NULL, 0, earpiecepga_event,
  1082. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1083. /* PreDrivL/R */
  1084. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1085. &twl4030_dapm_predrivel_controls[0],
  1086. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1087. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1088. 0, 0, NULL, 0, predrivelpga_event,
  1089. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1090. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1091. &twl4030_dapm_predriver_controls[0],
  1092. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1093. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1094. 0, 0, NULL, 0, predriverpga_event,
  1095. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1096. /* HeadsetL/R */
  1097. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1098. &twl4030_dapm_hsol_controls[0],
  1099. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1100. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1101. 0, 0, NULL, 0, headsetlpga_event,
  1102. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1103. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1104. &twl4030_dapm_hsor_controls[0],
  1105. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1106. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1107. 0, 0, NULL, 0, headsetrpga_event,
  1108. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1109. /* CarkitL/R */
  1110. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1111. &twl4030_dapm_carkitl_controls[0],
  1112. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1113. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1114. 0, 0, NULL, 0, carkitlpga_event,
  1115. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1116. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1117. &twl4030_dapm_carkitr_controls[0],
  1118. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1119. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1120. 0, 0, NULL, 0, carkitrpga_event,
  1121. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1122. /* Output MUX controls */
  1123. /* HandsfreeL/R */
  1124. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1125. &twl4030_dapm_handsfreel_control),
  1126. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1127. &twl4030_dapm_handsfreelmute_control),
  1128. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1129. 0, 0, NULL, 0, handsfreelpga_event,
  1130. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1131. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1132. &twl4030_dapm_handsfreer_control),
  1133. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1134. &twl4030_dapm_handsfreermute_control),
  1135. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1136. 0, 0, NULL, 0, handsfreerpga_event,
  1137. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1138. /* Vibra */
  1139. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1140. &twl4030_dapm_vibra_control),
  1141. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1142. &twl4030_dapm_vibrapath_control),
  1143. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1144. capture */
  1145. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1146. SND_SOC_NOPM, 0, 0),
  1147. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1148. SND_SOC_NOPM, 0, 0),
  1149. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1150. SND_SOC_NOPM, 0, 0),
  1151. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1152. SND_SOC_NOPM, 0, 0),
  1153. /* Analog/Digital mic path selection.
  1154. TX1 Left/Right: either analog Left/Right or Digimic0
  1155. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1156. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1157. &twl4030_dapm_micpathtx1_control, micpath_event,
  1158. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1159. SND_SOC_DAPM_POST_REG),
  1160. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1161. &twl4030_dapm_micpathtx2_control, micpath_event,
  1162. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1163. SND_SOC_DAPM_POST_REG),
  1164. /* Analog input mixers for the capture amplifiers */
  1165. SND_SOC_DAPM_MIXER("Analog Left",
  1166. TWL4030_REG_ANAMICL, 4, 0,
  1167. &twl4030_dapm_analoglmic_controls[0],
  1168. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1169. SND_SOC_DAPM_MIXER("Analog Right",
  1170. TWL4030_REG_ANAMICR, 4, 0,
  1171. &twl4030_dapm_analogrmic_controls[0],
  1172. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1173. SND_SOC_DAPM_PGA("ADC Physical Left",
  1174. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1175. SND_SOC_DAPM_PGA("ADC Physical Right",
  1176. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1177. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1178. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1179. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1180. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1181. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1182. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1183. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1184. };
  1185. static const struct snd_soc_dapm_route intercon[] = {
  1186. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1187. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1188. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1189. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1190. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1191. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1192. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1193. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1194. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1195. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1196. /* Internal playback routings */
  1197. /* Earpiece */
  1198. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1199. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1200. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1201. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1202. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1203. /* PreDrivL */
  1204. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1205. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1206. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1207. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1208. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1209. /* PreDrivR */
  1210. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1211. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1212. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1213. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1214. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1215. /* HeadsetL */
  1216. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1217. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1218. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1219. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1220. /* HeadsetR */
  1221. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1222. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1223. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1224. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1225. /* CarkitL */
  1226. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1227. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1228. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1229. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1230. /* CarkitR */
  1231. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1232. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1233. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1234. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1235. /* HandsfreeL */
  1236. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1237. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1238. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1239. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1240. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1241. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1242. /* HandsfreeR */
  1243. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1244. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1245. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1246. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1247. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1248. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1249. /* Vibra */
  1250. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1251. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1252. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1253. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1254. /* outputs */
  1255. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1256. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1257. {"EARPIECE", NULL, "Earpiece PGA"},
  1258. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1259. {"PREDRIVER", NULL, "PredriveR PGA"},
  1260. {"HSOL", NULL, "HeadsetL PGA"},
  1261. {"HSOR", NULL, "HeadsetR PGA"},
  1262. {"CARKITL", NULL, "CarkitL PGA"},
  1263. {"CARKITR", NULL, "CarkitR PGA"},
  1264. {"HFL", NULL, "HandsfreeL PGA"},
  1265. {"HFR", NULL, "HandsfreeR PGA"},
  1266. {"Vibra Route", "Audio", "Vibra Mux"},
  1267. {"VIBRA", NULL, "Vibra Route"},
  1268. /* Capture path */
  1269. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1270. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1271. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1272. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1273. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1274. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1275. {"ADC Physical Left", NULL, "Analog Left"},
  1276. {"ADC Physical Right", NULL, "Analog Right"},
  1277. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1278. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1279. /* TX1 Left capture path */
  1280. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1281. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1282. /* TX1 Right capture path */
  1283. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1284. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1285. /* TX2 Left capture path */
  1286. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1287. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1288. /* TX2 Right capture path */
  1289. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1290. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1291. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1292. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1293. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1294. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1295. /* Analog bypass routes */
  1296. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1297. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1298. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1299. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1300. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1301. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1302. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1303. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1304. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1305. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1306. /* Digital bypass routes */
  1307. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1308. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1309. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1310. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1311. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1312. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1313. };
  1314. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1315. {
  1316. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1317. ARRAY_SIZE(twl4030_dapm_widgets));
  1318. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1319. snd_soc_dapm_new_widgets(codec);
  1320. return 0;
  1321. }
  1322. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1323. enum snd_soc_bias_level level)
  1324. {
  1325. struct twl4030_priv *twl4030 = codec->private_data;
  1326. switch (level) {
  1327. case SND_SOC_BIAS_ON:
  1328. twl4030_codec_mute(codec, 0);
  1329. break;
  1330. case SND_SOC_BIAS_PREPARE:
  1331. twl4030_power_up(codec);
  1332. if (twl4030->bypass_state)
  1333. twl4030_codec_mute(codec, 0);
  1334. else
  1335. twl4030_codec_mute(codec, 1);
  1336. break;
  1337. case SND_SOC_BIAS_STANDBY:
  1338. twl4030_power_up(codec);
  1339. if (twl4030->bypass_state)
  1340. twl4030_codec_mute(codec, 0);
  1341. else
  1342. twl4030_codec_mute(codec, 1);
  1343. break;
  1344. case SND_SOC_BIAS_OFF:
  1345. twl4030_power_down(codec);
  1346. break;
  1347. }
  1348. codec->bias_level = level;
  1349. return 0;
  1350. }
  1351. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1352. struct snd_pcm_substream *mst_substream)
  1353. {
  1354. struct snd_pcm_substream *slv_substream;
  1355. /* Pick the stream, which need to be constrained */
  1356. if (mst_substream == twl4030->master_substream)
  1357. slv_substream = twl4030->slave_substream;
  1358. else if (mst_substream == twl4030->slave_substream)
  1359. slv_substream = twl4030->master_substream;
  1360. else /* This should not happen.. */
  1361. return;
  1362. /* Set the constraints according to the already configured stream */
  1363. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1364. SNDRV_PCM_HW_PARAM_RATE,
  1365. twl4030->rate,
  1366. twl4030->rate);
  1367. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1368. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1369. twl4030->sample_bits,
  1370. twl4030->sample_bits);
  1371. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1372. SNDRV_PCM_HW_PARAM_CHANNELS,
  1373. twl4030->channels,
  1374. twl4030->channels);
  1375. }
  1376. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1377. * capture has to be enabled/disabled. */
  1378. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1379. int enable)
  1380. {
  1381. u8 reg, mask;
  1382. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1383. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1384. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1385. else
  1386. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1387. if (enable)
  1388. reg |= mask;
  1389. else
  1390. reg &= ~mask;
  1391. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1392. }
  1393. static int twl4030_startup(struct snd_pcm_substream *substream,
  1394. struct snd_soc_dai *dai)
  1395. {
  1396. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1397. struct snd_soc_device *socdev = rtd->socdev;
  1398. struct snd_soc_codec *codec = socdev->card->codec;
  1399. struct twl4030_priv *twl4030 = codec->private_data;
  1400. if (twl4030->master_substream) {
  1401. twl4030->slave_substream = substream;
  1402. /* The DAI has one configuration for playback and capture, so
  1403. * if the DAI has been already configured then constrain this
  1404. * substream to match it. */
  1405. if (twl4030->configured)
  1406. twl4030_constraints(twl4030, twl4030->master_substream);
  1407. } else {
  1408. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1409. TWL4030_OPTION_1)) {
  1410. /* In option2 4 channel is not supported, set the
  1411. * constraint for the first stream for channels, the
  1412. * second stream will 'inherit' this cosntraint */
  1413. snd_pcm_hw_constraint_minmax(substream->runtime,
  1414. SNDRV_PCM_HW_PARAM_CHANNELS,
  1415. 2, 2);
  1416. }
  1417. twl4030->master_substream = substream;
  1418. }
  1419. return 0;
  1420. }
  1421. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1422. struct snd_soc_dai *dai)
  1423. {
  1424. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1425. struct snd_soc_device *socdev = rtd->socdev;
  1426. struct snd_soc_codec *codec = socdev->card->codec;
  1427. struct twl4030_priv *twl4030 = codec->private_data;
  1428. if (twl4030->master_substream == substream)
  1429. twl4030->master_substream = twl4030->slave_substream;
  1430. twl4030->slave_substream = NULL;
  1431. /* If all streams are closed, or the remaining stream has not yet
  1432. * been configured than set the DAI as not configured. */
  1433. if (!twl4030->master_substream)
  1434. twl4030->configured = 0;
  1435. else if (!twl4030->master_substream->runtime->channels)
  1436. twl4030->configured = 0;
  1437. /* If the closing substream had 4 channel, do the necessary cleanup */
  1438. if (substream->runtime->channels == 4)
  1439. twl4030_tdm_enable(codec, substream->stream, 0);
  1440. }
  1441. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1442. struct snd_pcm_hw_params *params,
  1443. struct snd_soc_dai *dai)
  1444. {
  1445. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1446. struct snd_soc_device *socdev = rtd->socdev;
  1447. struct snd_soc_codec *codec = socdev->card->codec;
  1448. struct twl4030_priv *twl4030 = codec->private_data;
  1449. u8 mode, old_mode, format, old_format;
  1450. /* If the substream has 4 channel, do the necessary setup */
  1451. if (params_channels(params) == 4) {
  1452. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1453. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1454. /* Safety check: are we in the correct operating mode and
  1455. * the interface is in TDM mode? */
  1456. if ((mode & TWL4030_OPTION_1) &&
  1457. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1458. twl4030_tdm_enable(codec, substream->stream, 1);
  1459. else
  1460. return -EINVAL;
  1461. }
  1462. if (twl4030->configured)
  1463. /* Ignoring hw_params for already configured DAI */
  1464. return 0;
  1465. /* bit rate */
  1466. old_mode = twl4030_read_reg_cache(codec,
  1467. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1468. mode = old_mode & ~TWL4030_APLL_RATE;
  1469. switch (params_rate(params)) {
  1470. case 8000:
  1471. mode |= TWL4030_APLL_RATE_8000;
  1472. break;
  1473. case 11025:
  1474. mode |= TWL4030_APLL_RATE_11025;
  1475. break;
  1476. case 12000:
  1477. mode |= TWL4030_APLL_RATE_12000;
  1478. break;
  1479. case 16000:
  1480. mode |= TWL4030_APLL_RATE_16000;
  1481. break;
  1482. case 22050:
  1483. mode |= TWL4030_APLL_RATE_22050;
  1484. break;
  1485. case 24000:
  1486. mode |= TWL4030_APLL_RATE_24000;
  1487. break;
  1488. case 32000:
  1489. mode |= TWL4030_APLL_RATE_32000;
  1490. break;
  1491. case 44100:
  1492. mode |= TWL4030_APLL_RATE_44100;
  1493. break;
  1494. case 48000:
  1495. mode |= TWL4030_APLL_RATE_48000;
  1496. break;
  1497. case 96000:
  1498. mode |= TWL4030_APLL_RATE_96000;
  1499. break;
  1500. default:
  1501. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1502. params_rate(params));
  1503. return -EINVAL;
  1504. }
  1505. if (mode != old_mode) {
  1506. /* change rate and set CODECPDZ */
  1507. twl4030_codec_enable(codec, 0);
  1508. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1509. twl4030_codec_enable(codec, 1);
  1510. }
  1511. /* sample size */
  1512. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1513. format = old_format;
  1514. format &= ~TWL4030_DATA_WIDTH;
  1515. switch (params_format(params)) {
  1516. case SNDRV_PCM_FORMAT_S16_LE:
  1517. format |= TWL4030_DATA_WIDTH_16S_16W;
  1518. break;
  1519. case SNDRV_PCM_FORMAT_S24_LE:
  1520. format |= TWL4030_DATA_WIDTH_32S_24W;
  1521. break;
  1522. default:
  1523. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1524. params_format(params));
  1525. return -EINVAL;
  1526. }
  1527. if (format != old_format) {
  1528. /* clear CODECPDZ before changing format (codec requirement) */
  1529. twl4030_codec_enable(codec, 0);
  1530. /* change format */
  1531. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1532. /* set CODECPDZ afterwards */
  1533. twl4030_codec_enable(codec, 1);
  1534. }
  1535. /* Store the important parameters for the DAI configuration and set
  1536. * the DAI as configured */
  1537. twl4030->configured = 1;
  1538. twl4030->rate = params_rate(params);
  1539. twl4030->sample_bits = hw_param_interval(params,
  1540. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1541. twl4030->channels = params_channels(params);
  1542. /* If both playback and capture streams are open, and one of them
  1543. * is setting the hw parameters right now (since we are here), set
  1544. * constraints to the other stream to match the current one. */
  1545. if (twl4030->slave_substream)
  1546. twl4030_constraints(twl4030, substream);
  1547. return 0;
  1548. }
  1549. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1550. int clk_id, unsigned int freq, int dir)
  1551. {
  1552. struct snd_soc_codec *codec = codec_dai->codec;
  1553. struct twl4030_priv *twl4030 = codec->private_data;
  1554. u8 infreq;
  1555. switch (freq) {
  1556. case 19200000:
  1557. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1558. twl4030->sysclk = 19200;
  1559. break;
  1560. case 26000000:
  1561. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1562. twl4030->sysclk = 26000;
  1563. break;
  1564. case 38400000:
  1565. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1566. twl4030->sysclk = 38400;
  1567. break;
  1568. default:
  1569. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1570. freq);
  1571. return -EINVAL;
  1572. }
  1573. infreq |= TWL4030_APLL_EN;
  1574. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1575. return 0;
  1576. }
  1577. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1578. unsigned int fmt)
  1579. {
  1580. struct snd_soc_codec *codec = codec_dai->codec;
  1581. u8 old_format, format;
  1582. /* get format */
  1583. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1584. format = old_format;
  1585. /* set master/slave audio interface */
  1586. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1587. case SND_SOC_DAIFMT_CBM_CFM:
  1588. format &= ~(TWL4030_AIF_SLAVE_EN);
  1589. format &= ~(TWL4030_CLK256FS_EN);
  1590. break;
  1591. case SND_SOC_DAIFMT_CBS_CFS:
  1592. format |= TWL4030_AIF_SLAVE_EN;
  1593. format |= TWL4030_CLK256FS_EN;
  1594. break;
  1595. default:
  1596. return -EINVAL;
  1597. }
  1598. /* interface format */
  1599. format &= ~TWL4030_AIF_FORMAT;
  1600. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1601. case SND_SOC_DAIFMT_I2S:
  1602. format |= TWL4030_AIF_FORMAT_CODEC;
  1603. break;
  1604. case SND_SOC_DAIFMT_DSP_A:
  1605. format |= TWL4030_AIF_FORMAT_TDM;
  1606. break;
  1607. default:
  1608. return -EINVAL;
  1609. }
  1610. if (format != old_format) {
  1611. /* clear CODECPDZ before changing format (codec requirement) */
  1612. twl4030_codec_enable(codec, 0);
  1613. /* change format */
  1614. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1615. /* set CODECPDZ afterwards */
  1616. twl4030_codec_enable(codec, 1);
  1617. }
  1618. return 0;
  1619. }
  1620. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1621. {
  1622. struct snd_soc_codec *codec = dai->codec;
  1623. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1624. if (tristate)
  1625. reg |= TWL4030_AIF_TRI_EN;
  1626. else
  1627. reg &= ~TWL4030_AIF_TRI_EN;
  1628. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1629. }
  1630. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1631. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1632. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1633. int enable)
  1634. {
  1635. u8 reg, mask;
  1636. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1637. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1638. mask = TWL4030_ARXL1_VRX_EN;
  1639. else
  1640. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1641. if (enable)
  1642. reg |= mask;
  1643. else
  1644. reg &= ~mask;
  1645. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1646. }
  1647. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1648. struct snd_soc_dai *dai)
  1649. {
  1650. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1651. struct snd_soc_device *socdev = rtd->socdev;
  1652. struct snd_soc_codec *codec = socdev->card->codec;
  1653. u8 infreq;
  1654. u8 mode;
  1655. /* If the system master clock is not 26MHz, the voice PCM interface is
  1656. * not avilable.
  1657. */
  1658. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1659. & TWL4030_APLL_INFREQ;
  1660. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1661. printk(KERN_ERR "TWL4030 voice startup: "
  1662. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1663. return -EINVAL;
  1664. }
  1665. /* If the codec mode is not option2, the voice PCM interface is not
  1666. * avilable.
  1667. */
  1668. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1669. & TWL4030_OPT_MODE;
  1670. if (mode != TWL4030_OPTION_2) {
  1671. printk(KERN_ERR "TWL4030 voice startup: "
  1672. "the codec mode is not option2\n");
  1673. return -EINVAL;
  1674. }
  1675. return 0;
  1676. }
  1677. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1678. struct snd_soc_dai *dai)
  1679. {
  1680. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1681. struct snd_soc_device *socdev = rtd->socdev;
  1682. struct snd_soc_codec *codec = socdev->card->codec;
  1683. /* Enable voice digital filters */
  1684. twl4030_voice_enable(codec, substream->stream, 0);
  1685. }
  1686. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1687. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1688. {
  1689. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1690. struct snd_soc_device *socdev = rtd->socdev;
  1691. struct snd_soc_codec *codec = socdev->card->codec;
  1692. u8 old_mode, mode;
  1693. /* Enable voice digital filters */
  1694. twl4030_voice_enable(codec, substream->stream, 1);
  1695. /* bit rate */
  1696. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1697. & ~(TWL4030_CODECPDZ);
  1698. mode = old_mode;
  1699. switch (params_rate(params)) {
  1700. case 8000:
  1701. mode &= ~(TWL4030_SEL_16K);
  1702. break;
  1703. case 16000:
  1704. mode |= TWL4030_SEL_16K;
  1705. break;
  1706. default:
  1707. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1708. params_rate(params));
  1709. return -EINVAL;
  1710. }
  1711. if (mode != old_mode) {
  1712. /* change rate and set CODECPDZ */
  1713. twl4030_codec_enable(codec, 0);
  1714. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1715. twl4030_codec_enable(codec, 1);
  1716. }
  1717. return 0;
  1718. }
  1719. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1720. int clk_id, unsigned int freq, int dir)
  1721. {
  1722. struct snd_soc_codec *codec = codec_dai->codec;
  1723. u8 infreq;
  1724. switch (freq) {
  1725. case 26000000:
  1726. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1727. break;
  1728. default:
  1729. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1730. freq);
  1731. return -EINVAL;
  1732. }
  1733. infreq |= TWL4030_APLL_EN;
  1734. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1735. return 0;
  1736. }
  1737. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1738. unsigned int fmt)
  1739. {
  1740. struct snd_soc_codec *codec = codec_dai->codec;
  1741. u8 old_format, format;
  1742. /* get format */
  1743. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1744. format = old_format;
  1745. /* set master/slave audio interface */
  1746. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1747. case SND_SOC_DAIFMT_CBM_CFM:
  1748. format &= ~(TWL4030_VIF_SLAVE_EN);
  1749. break;
  1750. case SND_SOC_DAIFMT_CBS_CFS:
  1751. format |= TWL4030_VIF_SLAVE_EN;
  1752. break;
  1753. default:
  1754. return -EINVAL;
  1755. }
  1756. /* clock inversion */
  1757. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1758. case SND_SOC_DAIFMT_IB_NF:
  1759. format &= ~(TWL4030_VIF_FORMAT);
  1760. break;
  1761. case SND_SOC_DAIFMT_NB_IF:
  1762. format |= TWL4030_VIF_FORMAT;
  1763. break;
  1764. default:
  1765. return -EINVAL;
  1766. }
  1767. if (format != old_format) {
  1768. /* change format and set CODECPDZ */
  1769. twl4030_codec_enable(codec, 0);
  1770. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1771. twl4030_codec_enable(codec, 1);
  1772. }
  1773. return 0;
  1774. }
  1775. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1776. {
  1777. struct snd_soc_codec *codec = dai->codec;
  1778. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1779. if (tristate)
  1780. reg |= TWL4030_VIF_TRI_EN;
  1781. else
  1782. reg &= ~TWL4030_VIF_TRI_EN;
  1783. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1784. }
  1785. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1786. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1787. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1788. .startup = twl4030_startup,
  1789. .shutdown = twl4030_shutdown,
  1790. .hw_params = twl4030_hw_params,
  1791. .set_sysclk = twl4030_set_dai_sysclk,
  1792. .set_fmt = twl4030_set_dai_fmt,
  1793. .set_tristate = twl4030_set_tristate,
  1794. };
  1795. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1796. .startup = twl4030_voice_startup,
  1797. .shutdown = twl4030_voice_shutdown,
  1798. .hw_params = twl4030_voice_hw_params,
  1799. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1800. .set_fmt = twl4030_voice_set_dai_fmt,
  1801. .set_tristate = twl4030_voice_set_tristate,
  1802. };
  1803. struct snd_soc_dai twl4030_dai[] = {
  1804. {
  1805. .name = "twl4030",
  1806. .playback = {
  1807. .stream_name = "HiFi Playback",
  1808. .channels_min = 2,
  1809. .channels_max = 4,
  1810. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1811. .formats = TWL4030_FORMATS,},
  1812. .capture = {
  1813. .stream_name = "Capture",
  1814. .channels_min = 2,
  1815. .channels_max = 4,
  1816. .rates = TWL4030_RATES,
  1817. .formats = TWL4030_FORMATS,},
  1818. .ops = &twl4030_dai_ops,
  1819. },
  1820. {
  1821. .name = "twl4030 Voice",
  1822. .playback = {
  1823. .stream_name = "Voice Playback",
  1824. .channels_min = 1,
  1825. .channels_max = 1,
  1826. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1827. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1828. .capture = {
  1829. .stream_name = "Capture",
  1830. .channels_min = 1,
  1831. .channels_max = 2,
  1832. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1833. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1834. .ops = &twl4030_dai_voice_ops,
  1835. },
  1836. };
  1837. EXPORT_SYMBOL_GPL(twl4030_dai);
  1838. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1839. {
  1840. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1841. struct snd_soc_codec *codec = socdev->card->codec;
  1842. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1843. return 0;
  1844. }
  1845. static int twl4030_resume(struct platform_device *pdev)
  1846. {
  1847. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1848. struct snd_soc_codec *codec = socdev->card->codec;
  1849. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1850. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1851. return 0;
  1852. }
  1853. /*
  1854. * initialize the driver
  1855. * register the mixer and dsp interfaces with the kernel
  1856. */
  1857. static int twl4030_init(struct snd_soc_device *socdev)
  1858. {
  1859. struct snd_soc_codec *codec = socdev->card->codec;
  1860. struct twl4030_setup_data *setup = socdev->codec_data;
  1861. struct twl4030_priv *twl4030 = codec->private_data;
  1862. int ret = 0;
  1863. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1864. codec->name = "twl4030";
  1865. codec->owner = THIS_MODULE;
  1866. codec->read = twl4030_read_reg_cache;
  1867. codec->write = twl4030_write;
  1868. codec->set_bias_level = twl4030_set_bias_level;
  1869. codec->dai = twl4030_dai;
  1870. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1871. codec->reg_cache_size = sizeof(twl4030_reg);
  1872. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1873. GFP_KERNEL);
  1874. if (codec->reg_cache == NULL)
  1875. return -ENOMEM;
  1876. /* Configuration for headset ramp delay from setup data */
  1877. if (setup) {
  1878. unsigned char hs_pop;
  1879. if (setup->sysclk)
  1880. twl4030->sysclk = setup->sysclk;
  1881. else
  1882. twl4030->sysclk = 26000;
  1883. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1884. hs_pop &= ~TWL4030_RAMP_DELAY;
  1885. hs_pop |= (setup->ramp_delay_value << 2);
  1886. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1887. } else {
  1888. twl4030->sysclk = 26000;
  1889. }
  1890. /* register pcms */
  1891. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1892. if (ret < 0) {
  1893. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1894. goto pcm_err;
  1895. }
  1896. twl4030_init_chip(codec);
  1897. /* power on device */
  1898. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1899. snd_soc_add_controls(codec, twl4030_snd_controls,
  1900. ARRAY_SIZE(twl4030_snd_controls));
  1901. twl4030_add_widgets(codec);
  1902. ret = snd_soc_init_card(socdev);
  1903. if (ret < 0) {
  1904. printk(KERN_ERR "twl4030: failed to register card\n");
  1905. goto card_err;
  1906. }
  1907. return ret;
  1908. card_err:
  1909. snd_soc_free_pcms(socdev);
  1910. snd_soc_dapm_free(socdev);
  1911. pcm_err:
  1912. kfree(codec->reg_cache);
  1913. return ret;
  1914. }
  1915. static struct snd_soc_device *twl4030_socdev;
  1916. static int twl4030_probe(struct platform_device *pdev)
  1917. {
  1918. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1919. struct snd_soc_codec *codec;
  1920. struct twl4030_priv *twl4030;
  1921. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1922. if (codec == NULL)
  1923. return -ENOMEM;
  1924. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1925. if (twl4030 == NULL) {
  1926. kfree(codec);
  1927. return -ENOMEM;
  1928. }
  1929. codec->private_data = twl4030;
  1930. socdev->card->codec = codec;
  1931. mutex_init(&codec->mutex);
  1932. INIT_LIST_HEAD(&codec->dapm_widgets);
  1933. INIT_LIST_HEAD(&codec->dapm_paths);
  1934. twl4030_socdev = socdev;
  1935. twl4030_init(socdev);
  1936. return 0;
  1937. }
  1938. static int twl4030_remove(struct platform_device *pdev)
  1939. {
  1940. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1941. struct snd_soc_codec *codec = socdev->card->codec;
  1942. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1943. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1944. snd_soc_free_pcms(socdev);
  1945. snd_soc_dapm_free(socdev);
  1946. kfree(codec->private_data);
  1947. kfree(codec);
  1948. return 0;
  1949. }
  1950. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1951. .probe = twl4030_probe,
  1952. .remove = twl4030_remove,
  1953. .suspend = twl4030_suspend,
  1954. .resume = twl4030_resume,
  1955. };
  1956. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1957. static int __init twl4030_modinit(void)
  1958. {
  1959. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1960. }
  1961. module_init(twl4030_modinit);
  1962. static void __exit twl4030_exit(void)
  1963. {
  1964. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1965. }
  1966. module_exit(twl4030_exit);
  1967. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1968. MODULE_AUTHOR("Steve Sakoman");
  1969. MODULE_LICENSE("GPL");