patch_nvhdmi.c 11 KB

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  1. /*
  2. * Universal Interface for Intel High Definition Audio Codec
  3. *
  4. * HD audio interface patch for NVIDIA HDMI codecs
  5. *
  6. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  7. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  8. *
  9. *
  10. * This driver is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This driver is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. */
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <sound/core.h>
  28. #include "hda_codec.h"
  29. #include "hda_local.h"
  30. /* define below to restrict the supported rates and formats */
  31. /* #define LIMITED_RATE_FMT_SUPPORT */
  32. struct nvhdmi_spec {
  33. struct hda_multi_out multiout;
  34. struct hda_pcm pcm_rec;
  35. };
  36. #define Nv_VERB_SET_Channel_Allocation 0xF79
  37. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  38. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  39. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  40. #define Nv_Master_Convert_nid 0x04
  41. #define Nv_Master_Pin_nid 0x05
  42. static hda_nid_t nvhdmi_convert_nids[4] = {
  43. /*front, rear, clfe, rear_surr */
  44. 0x6, 0x8, 0xa, 0xc,
  45. };
  46. static struct hda_verb nvhdmi_basic_init[] = {
  47. /* set audio protect on */
  48. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  49. /* enable digital output on pin widget */
  50. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  51. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  52. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  53. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  54. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  55. {} /* terminator */
  56. };
  57. #ifdef LIMITED_RATE_FMT_SUPPORT
  58. /* support only the safe format and rate */
  59. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  60. #define SUPPORTED_MAXBPS 16
  61. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  62. #else
  63. /* support all rates and formats */
  64. #define SUPPORTED_RATES \
  65. (SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  66. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  67. SNDRV_PCM_RATE_192000)
  68. #define SUPPORTED_MAXBPS 24
  69. #define SUPPORTED_FORMATS \
  70. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  71. #endif
  72. /*
  73. * Controls
  74. */
  75. static int nvhdmi_build_controls(struct hda_codec *codec)
  76. {
  77. struct nvhdmi_spec *spec = codec->spec;
  78. int err;
  79. err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid);
  80. if (err < 0)
  81. return err;
  82. return 0;
  83. }
  84. static int nvhdmi_init(struct hda_codec *codec)
  85. {
  86. snd_hda_sequence_write(codec, nvhdmi_basic_init);
  87. return 0;
  88. }
  89. /*
  90. * Digital out
  91. */
  92. static int nvhdmi_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
  93. struct hda_codec *codec,
  94. struct snd_pcm_substream *substream)
  95. {
  96. struct nvhdmi_spec *spec = codec->spec;
  97. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  98. }
  99. static int nvhdmi_dig_playback_pcm_close_8ch(struct hda_pcm_stream *hinfo,
  100. struct hda_codec *codec,
  101. struct snd_pcm_substream *substream)
  102. {
  103. struct nvhdmi_spec *spec = codec->spec;
  104. int i;
  105. snd_hda_codec_write(codec, Nv_Master_Convert_nid,
  106. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  107. for (i = 0; i < 4; i++) {
  108. /* set the stream id */
  109. snd_hda_codec_write(codec, nvhdmi_convert_nids[i], 0,
  110. AC_VERB_SET_CHANNEL_STREAMID, 0);
  111. /* set the stream format */
  112. snd_hda_codec_write(codec, nvhdmi_convert_nids[i], 0,
  113. AC_VERB_SET_STREAM_FORMAT, 0);
  114. }
  115. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  116. }
  117. static int nvhdmi_dig_playback_pcm_close_2ch(struct hda_pcm_stream *hinfo,
  118. struct hda_codec *codec,
  119. struct snd_pcm_substream *substream)
  120. {
  121. struct nvhdmi_spec *spec = codec->spec;
  122. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  123. }
  124. static int nvhdmi_dig_playback_pcm_prepare_8ch(struct hda_pcm_stream *hinfo,
  125. struct hda_codec *codec,
  126. unsigned int stream_tag,
  127. unsigned int format,
  128. struct snd_pcm_substream *substream)
  129. {
  130. int chs;
  131. unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
  132. int i;
  133. mutex_lock(&codec->spdif_mutex);
  134. chs = substream->runtime->channels;
  135. chan = chs ? (chs - 1) : 1;
  136. switch (chs) {
  137. default:
  138. case 0:
  139. case 2:
  140. chanmask = 0x00;
  141. break;
  142. case 4:
  143. chanmask = 0x08;
  144. break;
  145. case 6:
  146. chanmask = 0x0b;
  147. break;
  148. case 8:
  149. chanmask = 0x13;
  150. break;
  151. }
  152. dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
  153. dataDCC2 = 0x2;
  154. /* set the Audio InforFrame Channel Allocation */
  155. snd_hda_codec_write(codec, 0x1, 0,
  156. Nv_VERB_SET_Channel_Allocation, chanmask);
  157. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  158. if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
  159. snd_hda_codec_write(codec,
  160. Nv_Master_Convert_nid,
  161. 0,
  162. AC_VERB_SET_DIGI_CONVERT_1,
  163. codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
  164. /* set the stream id */
  165. snd_hda_codec_write(codec, Nv_Master_Convert_nid, 0,
  166. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  167. /* set the stream format */
  168. snd_hda_codec_write(codec, Nv_Master_Convert_nid, 0,
  169. AC_VERB_SET_STREAM_FORMAT, format);
  170. /* turn on again (if needed) */
  171. /* enable and set the channel status audio/data flag */
  172. if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
  173. snd_hda_codec_write(codec,
  174. Nv_Master_Convert_nid,
  175. 0,
  176. AC_VERB_SET_DIGI_CONVERT_1,
  177. codec->spdif_ctls & 0xff);
  178. snd_hda_codec_write(codec,
  179. Nv_Master_Convert_nid,
  180. 0,
  181. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  182. }
  183. for (i = 0; i < 4; i++) {
  184. if (chs == 2)
  185. channel_id = 0;
  186. else
  187. channel_id = i * 2;
  188. /* turn off SPDIF once;
  189. *otherwise the IEC958 bits won't be updated
  190. */
  191. if (codec->spdif_status_reset &&
  192. (codec->spdif_ctls & AC_DIG1_ENABLE))
  193. snd_hda_codec_write(codec,
  194. nvhdmi_convert_nids[i],
  195. 0,
  196. AC_VERB_SET_DIGI_CONVERT_1,
  197. codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
  198. /* set the stream id */
  199. snd_hda_codec_write(codec,
  200. nvhdmi_convert_nids[i],
  201. 0,
  202. AC_VERB_SET_CHANNEL_STREAMID,
  203. (stream_tag << 4) | channel_id);
  204. /* set the stream format */
  205. snd_hda_codec_write(codec,
  206. nvhdmi_convert_nids[i],
  207. 0,
  208. AC_VERB_SET_STREAM_FORMAT,
  209. format);
  210. /* turn on again (if needed) */
  211. /* enable and set the channel status audio/data flag */
  212. if (codec->spdif_status_reset &&
  213. (codec->spdif_ctls & AC_DIG1_ENABLE)) {
  214. snd_hda_codec_write(codec,
  215. nvhdmi_convert_nids[i],
  216. 0,
  217. AC_VERB_SET_DIGI_CONVERT_1,
  218. codec->spdif_ctls & 0xff);
  219. snd_hda_codec_write(codec,
  220. nvhdmi_convert_nids[i],
  221. 0,
  222. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  223. }
  224. }
  225. /* set the Audio Info Frame Checksum */
  226. snd_hda_codec_write(codec, 0x1, 0,
  227. Nv_VERB_SET_Info_Frame_Checksum,
  228. (0x71 - chan - chanmask));
  229. mutex_unlock(&codec->spdif_mutex);
  230. return 0;
  231. }
  232. static int nvhdmi_dig_playback_pcm_prepare_2ch(struct hda_pcm_stream *hinfo,
  233. struct hda_codec *codec,
  234. unsigned int stream_tag,
  235. unsigned int format,
  236. struct snd_pcm_substream *substream)
  237. {
  238. struct nvhdmi_spec *spec = codec->spec;
  239. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, stream_tag,
  240. format, substream);
  241. }
  242. static struct hda_pcm_stream nvhdmi_pcm_digital_playback_8ch = {
  243. .substreams = 1,
  244. .channels_min = 2,
  245. .channels_max = 8,
  246. .nid = Nv_Master_Convert_nid,
  247. .rates = SUPPORTED_RATES,
  248. .maxbps = SUPPORTED_MAXBPS,
  249. .formats = SUPPORTED_FORMATS,
  250. .ops = {
  251. .open = nvhdmi_dig_playback_pcm_open,
  252. .close = nvhdmi_dig_playback_pcm_close_8ch,
  253. .prepare = nvhdmi_dig_playback_pcm_prepare_8ch
  254. },
  255. };
  256. static struct hda_pcm_stream nvhdmi_pcm_digital_playback_2ch = {
  257. .substreams = 1,
  258. .channels_min = 2,
  259. .channels_max = 2,
  260. .nid = Nv_Master_Convert_nid,
  261. .rates = SUPPORTED_RATES,
  262. .maxbps = SUPPORTED_MAXBPS,
  263. .formats = SUPPORTED_FORMATS,
  264. .ops = {
  265. .open = nvhdmi_dig_playback_pcm_open,
  266. .close = nvhdmi_dig_playback_pcm_close_2ch,
  267. .prepare = nvhdmi_dig_playback_pcm_prepare_2ch
  268. },
  269. };
  270. static int nvhdmi_build_pcms_8ch(struct hda_codec *codec)
  271. {
  272. struct nvhdmi_spec *spec = codec->spec;
  273. struct hda_pcm *info = &spec->pcm_rec;
  274. codec->num_pcms = 1;
  275. codec->pcm_info = info;
  276. info->name = "NVIDIA HDMI";
  277. info->pcm_type = HDA_PCM_TYPE_HDMI;
  278. info->stream[SNDRV_PCM_STREAM_PLAYBACK]
  279. = nvhdmi_pcm_digital_playback_8ch;
  280. return 0;
  281. }
  282. static int nvhdmi_build_pcms_2ch(struct hda_codec *codec)
  283. {
  284. struct nvhdmi_spec *spec = codec->spec;
  285. struct hda_pcm *info = &spec->pcm_rec;
  286. codec->num_pcms = 1;
  287. codec->pcm_info = info;
  288. info->name = "NVIDIA HDMI";
  289. info->pcm_type = HDA_PCM_TYPE_HDMI;
  290. info->stream[SNDRV_PCM_STREAM_PLAYBACK]
  291. = nvhdmi_pcm_digital_playback_2ch;
  292. return 0;
  293. }
  294. static void nvhdmi_free(struct hda_codec *codec)
  295. {
  296. kfree(codec->spec);
  297. }
  298. static struct hda_codec_ops nvhdmi_patch_ops_8ch = {
  299. .build_controls = nvhdmi_build_controls,
  300. .build_pcms = nvhdmi_build_pcms_8ch,
  301. .init = nvhdmi_init,
  302. .free = nvhdmi_free,
  303. };
  304. static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
  305. .build_controls = nvhdmi_build_controls,
  306. .build_pcms = nvhdmi_build_pcms_2ch,
  307. .init = nvhdmi_init,
  308. .free = nvhdmi_free,
  309. };
  310. static int patch_nvhdmi_8ch(struct hda_codec *codec)
  311. {
  312. struct nvhdmi_spec *spec;
  313. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  314. if (spec == NULL)
  315. return -ENOMEM;
  316. codec->spec = spec;
  317. spec->multiout.num_dacs = 0; /* no analog */
  318. spec->multiout.max_channels = 8;
  319. spec->multiout.dig_out_nid = Nv_Master_Convert_nid;
  320. codec->patch_ops = nvhdmi_patch_ops_8ch;
  321. return 0;
  322. }
  323. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  324. {
  325. struct nvhdmi_spec *spec;
  326. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  327. if (spec == NULL)
  328. return -ENOMEM;
  329. codec->spec = spec;
  330. spec->multiout.num_dacs = 0; /* no analog */
  331. spec->multiout.max_channels = 2;
  332. spec->multiout.dig_out_nid = Nv_Master_Convert_nid;
  333. codec->patch_ops = nvhdmi_patch_ops_2ch;
  334. return 0;
  335. }
  336. /*
  337. * patch entries
  338. */
  339. static struct hda_codec_preset snd_hda_preset_nvhdmi[] = {
  340. { .id = 0x10de0002, .name = "MCP78 HDMI", .patch = patch_nvhdmi_8ch },
  341. { .id = 0x10de0003, .name = "MCP78 HDMI", .patch = patch_nvhdmi_8ch },
  342. { .id = 0x10de0005, .name = "MCP78 HDMI", .patch = patch_nvhdmi_8ch },
  343. { .id = 0x10de0006, .name = "MCP78 HDMI", .patch = patch_nvhdmi_8ch },
  344. { .id = 0x10de0007, .name = "MCP7A HDMI", .patch = patch_nvhdmi_8ch },
  345. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  346. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  347. {} /* terminator */
  348. };
  349. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  350. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  351. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  352. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  353. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  354. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  355. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  356. MODULE_LICENSE("GPL");
  357. MODULE_DESCRIPTION("Nvidia HDMI HD-audio codec");
  358. static struct hda_codec_preset_list nvhdmi_list = {
  359. .preset = snd_hda_preset_nvhdmi,
  360. .owner = THIS_MODULE,
  361. };
  362. static int __init patch_nvhdmi_init(void)
  363. {
  364. return snd_hda_add_codec_preset(&nvhdmi_list);
  365. }
  366. static void __exit patch_nvhdmi_exit(void)
  367. {
  368. snd_hda_delete_codec_preset(&nvhdmi_list);
  369. }
  370. module_init(patch_nvhdmi_init)
  371. module_exit(patch_nvhdmi_exit)