s3c2410_wdt.c 13 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/types.h>
  28. #include <linux/timer.h>
  29. #include <linux/miscdevice.h>
  30. #include <linux/watchdog.h>
  31. #include <linux/fs.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <mach/map.h>
  39. #undef S3C_VA_WATCHDOG
  40. #define S3C_VA_WATCHDOG (0)
  41. #include <plat/regs-watchdog.h>
  42. #define PFX "s3c2410-wdt: "
  43. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  44. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  45. static int nowayout = WATCHDOG_NOWAYOUT;
  46. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  47. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  48. static int soft_noboot;
  49. static int debug;
  50. module_param(tmr_margin, int, 0);
  51. module_param(tmr_atboot, int, 0);
  52. module_param(nowayout, int, 0);
  53. module_param(soft_noboot, int, 0);
  54. module_param(debug, int, 0);
  55. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
  56. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  57. MODULE_PARM_DESC(tmr_atboot,
  58. "Watchdog is started at boot time if set to 1, default="
  59. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  60. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  61. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  62. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  63. "0 to reboot (default depends on ONLY_TESTING)");
  64. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
  65. static unsigned long open_lock;
  66. static struct device *wdt_dev; /* platform device attached to */
  67. static struct resource *wdt_mem;
  68. static struct resource *wdt_irq;
  69. static struct clk *wdt_clock;
  70. static void __iomem *wdt_base;
  71. static unsigned int wdt_count;
  72. static char expect_close;
  73. static DEFINE_SPINLOCK(wdt_lock);
  74. /* watchdog control routines */
  75. #define DBG(msg...) do { \
  76. if (debug) \
  77. printk(KERN_INFO msg); \
  78. } while (0)
  79. /* functions */
  80. static void s3c2410wdt_keepalive(void)
  81. {
  82. spin_lock(&wdt_lock);
  83. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  84. spin_unlock(&wdt_lock);
  85. }
  86. static void __s3c2410wdt_stop(void)
  87. {
  88. unsigned long wtcon;
  89. wtcon = readl(wdt_base + S3C2410_WTCON);
  90. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  91. writel(wtcon, wdt_base + S3C2410_WTCON);
  92. }
  93. static void s3c2410wdt_stop(void)
  94. {
  95. spin_lock(&wdt_lock);
  96. __s3c2410wdt_stop();
  97. spin_unlock(&wdt_lock);
  98. }
  99. static void s3c2410wdt_start(void)
  100. {
  101. unsigned long wtcon;
  102. spin_lock(&wdt_lock);
  103. __s3c2410wdt_stop();
  104. wtcon = readl(wdt_base + S3C2410_WTCON);
  105. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  106. if (soft_noboot) {
  107. wtcon |= S3C2410_WTCON_INTEN;
  108. wtcon &= ~S3C2410_WTCON_RSTEN;
  109. } else {
  110. wtcon &= ~S3C2410_WTCON_INTEN;
  111. wtcon |= S3C2410_WTCON_RSTEN;
  112. }
  113. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  114. __func__, wdt_count, wtcon);
  115. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  116. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  117. writel(wtcon, wdt_base + S3C2410_WTCON);
  118. spin_unlock(&wdt_lock);
  119. }
  120. static int s3c2410wdt_set_heartbeat(int timeout)
  121. {
  122. unsigned int freq = clk_get_rate(wdt_clock);
  123. unsigned int count;
  124. unsigned int divisor = 1;
  125. unsigned long wtcon;
  126. if (timeout < 1)
  127. return -EINVAL;
  128. freq /= 128;
  129. count = timeout * freq;
  130. DBG("%s: count=%d, timeout=%d, freq=%d\n",
  131. __func__, count, timeout, freq);
  132. /* if the count is bigger than the watchdog register,
  133. then work out what we need to do (and if) we can
  134. actually make this value
  135. */
  136. if (count >= 0x10000) {
  137. for (divisor = 1; divisor <= 0x100; divisor++) {
  138. if ((count / divisor) < 0x10000)
  139. break;
  140. }
  141. if ((count / divisor) >= 0x10000) {
  142. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  143. return -EINVAL;
  144. }
  145. }
  146. tmr_margin = timeout;
  147. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  148. __func__, timeout, divisor, count, count/divisor);
  149. count /= divisor;
  150. wdt_count = count;
  151. /* update the pre-scaler */
  152. wtcon = readl(wdt_base + S3C2410_WTCON);
  153. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  154. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  155. writel(count, wdt_base + S3C2410_WTDAT);
  156. writel(wtcon, wdt_base + S3C2410_WTCON);
  157. return 0;
  158. }
  159. /*
  160. * /dev/watchdog handling
  161. */
  162. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  163. {
  164. if (test_and_set_bit(0, &open_lock))
  165. return -EBUSY;
  166. if (nowayout)
  167. __module_get(THIS_MODULE);
  168. expect_close = 0;
  169. /* start the timer */
  170. s3c2410wdt_start();
  171. return nonseekable_open(inode, file);
  172. }
  173. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  174. {
  175. /*
  176. * Shut off the timer.
  177. * Lock it in if it's a module and we set nowayout
  178. */
  179. if (expect_close == 42)
  180. s3c2410wdt_stop();
  181. else {
  182. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  183. s3c2410wdt_keepalive();
  184. }
  185. expect_close = 0;
  186. clear_bit(0, &open_lock);
  187. return 0;
  188. }
  189. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  190. size_t len, loff_t *ppos)
  191. {
  192. /*
  193. * Refresh the timer.
  194. */
  195. if (len) {
  196. if (!nowayout) {
  197. size_t i;
  198. /* In case it was set long ago */
  199. expect_close = 0;
  200. for (i = 0; i != len; i++) {
  201. char c;
  202. if (get_user(c, data + i))
  203. return -EFAULT;
  204. if (c == 'V')
  205. expect_close = 42;
  206. }
  207. }
  208. s3c2410wdt_keepalive();
  209. }
  210. return len;
  211. }
  212. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  213. static const struct watchdog_info s3c2410_wdt_ident = {
  214. .options = OPTIONS,
  215. .firmware_version = 0,
  216. .identity = "S3C2410 Watchdog",
  217. };
  218. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  219. unsigned long arg)
  220. {
  221. void __user *argp = (void __user *)arg;
  222. int __user *p = argp;
  223. int new_margin;
  224. switch (cmd) {
  225. case WDIOC_GETSUPPORT:
  226. return copy_to_user(argp, &s3c2410_wdt_ident,
  227. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  228. case WDIOC_GETSTATUS:
  229. case WDIOC_GETBOOTSTATUS:
  230. return put_user(0, p);
  231. case WDIOC_KEEPALIVE:
  232. s3c2410wdt_keepalive();
  233. return 0;
  234. case WDIOC_SETTIMEOUT:
  235. if (get_user(new_margin, p))
  236. return -EFAULT;
  237. if (s3c2410wdt_set_heartbeat(new_margin))
  238. return -EINVAL;
  239. s3c2410wdt_keepalive();
  240. return put_user(tmr_margin, p);
  241. case WDIOC_GETTIMEOUT:
  242. return put_user(tmr_margin, p);
  243. default:
  244. return -ENOTTY;
  245. }
  246. }
  247. /* kernel interface */
  248. static const struct file_operations s3c2410wdt_fops = {
  249. .owner = THIS_MODULE,
  250. .llseek = no_llseek,
  251. .write = s3c2410wdt_write,
  252. .unlocked_ioctl = s3c2410wdt_ioctl,
  253. .open = s3c2410wdt_open,
  254. .release = s3c2410wdt_release,
  255. };
  256. static struct miscdevice s3c2410wdt_miscdev = {
  257. .minor = WATCHDOG_MINOR,
  258. .name = "watchdog",
  259. .fops = &s3c2410wdt_fops,
  260. };
  261. /* interrupt handler code */
  262. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  263. {
  264. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  265. s3c2410wdt_keepalive();
  266. return IRQ_HANDLED;
  267. }
  268. /* device interface */
  269. static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
  270. {
  271. struct resource *res;
  272. struct device *dev;
  273. unsigned int wtcon;
  274. int started = 0;
  275. int ret;
  276. int size;
  277. DBG("%s: probe=%p\n", __func__, pdev);
  278. dev = &pdev->dev;
  279. wdt_dev = &pdev->dev;
  280. /* get the memory region for the watchdog timer */
  281. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  282. if (res == NULL) {
  283. dev_err(dev, "no memory resource specified\n");
  284. return -ENOENT;
  285. }
  286. size = (res->end - res->start) + 1;
  287. wdt_mem = request_mem_region(res->start, size, pdev->name);
  288. if (wdt_mem == NULL) {
  289. dev_err(dev, "failed to get memory region\n");
  290. ret = -ENOENT;
  291. goto err_req;
  292. }
  293. wdt_base = ioremap(res->start, size);
  294. if (wdt_base == NULL) {
  295. dev_err(dev, "failed to ioremap() region\n");
  296. ret = -EINVAL;
  297. goto err_req;
  298. }
  299. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  300. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  301. if (wdt_irq == NULL) {
  302. dev_err(dev, "no irq resource specified\n");
  303. ret = -ENOENT;
  304. goto err_map;
  305. }
  306. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  307. if (ret != 0) {
  308. dev_err(dev, "failed to install irq (%d)\n", ret);
  309. goto err_map;
  310. }
  311. wdt_clock = clk_get(&pdev->dev, "watchdog");
  312. if (IS_ERR(wdt_clock)) {
  313. dev_err(dev, "failed to find watchdog clock source\n");
  314. ret = PTR_ERR(wdt_clock);
  315. goto err_irq;
  316. }
  317. clk_enable(wdt_clock);
  318. /* see if we can actually set the requested timer margin, and if
  319. * not, try the default value */
  320. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  321. started = s3c2410wdt_set_heartbeat(
  322. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  323. if (started == 0)
  324. dev_info(dev,
  325. "tmr_margin value out of range, default %d used\n",
  326. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  327. else
  328. dev_info(dev, "default timer value is out of range, "
  329. "cannot start\n");
  330. }
  331. ret = misc_register(&s3c2410wdt_miscdev);
  332. if (ret) {
  333. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  334. WATCHDOG_MINOR, ret);
  335. goto err_clk;
  336. }
  337. if (tmr_atboot && started == 0) {
  338. dev_info(dev, "starting watchdog timer\n");
  339. s3c2410wdt_start();
  340. } else if (!tmr_atboot) {
  341. /* if we're not enabling the watchdog, then ensure it is
  342. * disabled if it has been left running from the bootloader
  343. * or other source */
  344. s3c2410wdt_stop();
  345. }
  346. /* print out a statement of readiness */
  347. wtcon = readl(wdt_base + S3C2410_WTCON);
  348. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  349. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  350. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  351. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  352. return 0;
  353. err_clk:
  354. clk_disable(wdt_clock);
  355. clk_put(wdt_clock);
  356. err_irq:
  357. free_irq(wdt_irq->start, pdev);
  358. err_map:
  359. iounmap(wdt_base);
  360. err_req:
  361. release_resource(wdt_mem);
  362. kfree(wdt_mem);
  363. return ret;
  364. }
  365. static int __devexit s3c2410wdt_remove(struct platform_device *dev)
  366. {
  367. release_resource(wdt_mem);
  368. kfree(wdt_mem);
  369. wdt_mem = NULL;
  370. free_irq(wdt_irq->start, dev);
  371. wdt_irq = NULL;
  372. clk_disable(wdt_clock);
  373. clk_put(wdt_clock);
  374. wdt_clock = NULL;
  375. iounmap(wdt_base);
  376. misc_deregister(&s3c2410wdt_miscdev);
  377. return 0;
  378. }
  379. static void s3c2410wdt_shutdown(struct platform_device *dev)
  380. {
  381. s3c2410wdt_stop();
  382. }
  383. #ifdef CONFIG_PM
  384. static unsigned long wtcon_save;
  385. static unsigned long wtdat_save;
  386. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  387. {
  388. /* Save watchdog state, and turn it off. */
  389. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  390. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  391. /* Note that WTCNT doesn't need to be saved. */
  392. s3c2410wdt_stop();
  393. return 0;
  394. }
  395. static int s3c2410wdt_resume(struct platform_device *dev)
  396. {
  397. /* Restore watchdog state. */
  398. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  399. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  400. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  401. printk(KERN_INFO PFX "watchdog %sabled\n",
  402. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  403. return 0;
  404. }
  405. #else
  406. #define s3c2410wdt_suspend NULL
  407. #define s3c2410wdt_resume NULL
  408. #endif /* CONFIG_PM */
  409. static struct platform_driver s3c2410wdt_driver = {
  410. .probe = s3c2410wdt_probe,
  411. .remove = __devexit_p(s3c2410wdt_remove),
  412. .shutdown = s3c2410wdt_shutdown,
  413. .suspend = s3c2410wdt_suspend,
  414. .resume = s3c2410wdt_resume,
  415. .driver = {
  416. .owner = THIS_MODULE,
  417. .name = "s3c2410-wdt",
  418. },
  419. };
  420. static char banner[] __initdata =
  421. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  422. static int __init watchdog_init(void)
  423. {
  424. printk(banner);
  425. return platform_driver_register(&s3c2410wdt_driver);
  426. }
  427. static void __exit watchdog_exit(void)
  428. {
  429. platform_driver_unregister(&s3c2410wdt_driver);
  430. }
  431. module_init(watchdog_init);
  432. module_exit(watchdog_exit);
  433. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  434. "Dimitry Andric <dimitry.andric@tomtom.com>");
  435. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  436. MODULE_LICENSE("GPL");
  437. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  438. MODULE_ALIAS("platform:s3c2410-wdt");