xhci-mem.c 29 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/usb.h>
  23. #include <linux/pci.h>
  24. #include <linux/dmapool.h>
  25. #include "xhci.h"
  26. /*
  27. * Allocates a generic ring segment from the ring pool, sets the dma address,
  28. * initializes the segment to zero, and sets the private next pointer to NULL.
  29. *
  30. * Section 4.11.1.1:
  31. * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  32. */
  33. static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  34. {
  35. struct xhci_segment *seg;
  36. dma_addr_t dma;
  37. seg = kzalloc(sizeof *seg, flags);
  38. if (!seg)
  39. return 0;
  40. xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  41. seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  42. if (!seg->trbs) {
  43. kfree(seg);
  44. return 0;
  45. }
  46. xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  47. seg->trbs, (unsigned long long)dma);
  48. memset(seg->trbs, 0, SEGMENT_SIZE);
  49. seg->dma = dma;
  50. seg->next = NULL;
  51. return seg;
  52. }
  53. static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  54. {
  55. if (!seg)
  56. return;
  57. if (seg->trbs) {
  58. xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  59. seg->trbs, (unsigned long long)seg->dma);
  60. dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  61. seg->trbs = NULL;
  62. }
  63. xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  64. kfree(seg);
  65. }
  66. /*
  67. * Make the prev segment point to the next segment.
  68. *
  69. * Change the last TRB in the prev segment to be a Link TRB which points to the
  70. * DMA address of the next segment. The caller needs to set any Link TRB
  71. * related flags, such as End TRB, Toggle Cycle, and no snoop.
  72. */
  73. static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  74. struct xhci_segment *next, bool link_trbs)
  75. {
  76. u32 val;
  77. if (!prev || !next)
  78. return;
  79. prev->next = next;
  80. if (link_trbs) {
  81. prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
  82. /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  83. val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
  84. val &= ~TRB_TYPE_BITMASK;
  85. val |= TRB_TYPE(TRB_LINK);
  86. /* Always set the chain bit with 0.95 hardware */
  87. if (xhci_link_trb_quirk(xhci))
  88. val |= TRB_CHAIN;
  89. prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
  90. }
  91. xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
  92. (unsigned long long)prev->dma,
  93. (unsigned long long)next->dma);
  94. }
  95. /* XXX: Do we need the hcd structure in all these functions? */
  96. void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
  97. {
  98. struct xhci_segment *seg;
  99. struct xhci_segment *first_seg;
  100. if (!ring || !ring->first_seg)
  101. return;
  102. first_seg = ring->first_seg;
  103. seg = first_seg->next;
  104. xhci_dbg(xhci, "Freeing ring at %p\n", ring);
  105. while (seg != first_seg) {
  106. struct xhci_segment *next = seg->next;
  107. xhci_segment_free(xhci, seg);
  108. seg = next;
  109. }
  110. xhci_segment_free(xhci, first_seg);
  111. ring->first_seg = NULL;
  112. kfree(ring);
  113. }
  114. /**
  115. * Create a new ring with zero or more segments.
  116. *
  117. * Link each segment together into a ring.
  118. * Set the end flag and the cycle toggle bit on the last segment.
  119. * See section 4.9.1 and figures 15 and 16.
  120. */
  121. static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
  122. unsigned int num_segs, bool link_trbs, gfp_t flags)
  123. {
  124. struct xhci_ring *ring;
  125. struct xhci_segment *prev;
  126. ring = kzalloc(sizeof *(ring), flags);
  127. xhci_dbg(xhci, "Allocating ring at %p\n", ring);
  128. if (!ring)
  129. return 0;
  130. INIT_LIST_HEAD(&ring->td_list);
  131. if (num_segs == 0)
  132. return ring;
  133. ring->first_seg = xhci_segment_alloc(xhci, flags);
  134. if (!ring->first_seg)
  135. goto fail;
  136. num_segs--;
  137. prev = ring->first_seg;
  138. while (num_segs > 0) {
  139. struct xhci_segment *next;
  140. next = xhci_segment_alloc(xhci, flags);
  141. if (!next)
  142. goto fail;
  143. xhci_link_segments(xhci, prev, next, link_trbs);
  144. prev = next;
  145. num_segs--;
  146. }
  147. xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
  148. if (link_trbs) {
  149. /* See section 4.9.2.1 and 6.4.4.1 */
  150. prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
  151. xhci_dbg(xhci, "Wrote link toggle flag to"
  152. " segment %p (virtual), 0x%llx (DMA)\n",
  153. prev, (unsigned long long)prev->dma);
  154. }
  155. /* The ring is empty, so the enqueue pointer == dequeue pointer */
  156. ring->enqueue = ring->first_seg->trbs;
  157. ring->enq_seg = ring->first_seg;
  158. ring->dequeue = ring->enqueue;
  159. ring->deq_seg = ring->first_seg;
  160. /* The ring is initialized to 0. The producer must write 1 to the cycle
  161. * bit to handover ownership of the TRB, so PCS = 1. The consumer must
  162. * compare CCS to the cycle bit to check ownership, so CCS = 1.
  163. */
  164. ring->cycle_state = 1;
  165. return ring;
  166. fail:
  167. xhci_ring_free(xhci, ring);
  168. return 0;
  169. }
  170. #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
  171. struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
  172. int type, gfp_t flags)
  173. {
  174. struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
  175. if (!ctx)
  176. return NULL;
  177. BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
  178. ctx->type = type;
  179. ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
  180. if (type == XHCI_CTX_TYPE_INPUT)
  181. ctx->size += CTX_SIZE(xhci->hcc_params);
  182. ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
  183. memset(ctx->bytes, 0, ctx->size);
  184. return ctx;
  185. }
  186. void xhci_free_container_ctx(struct xhci_hcd *xhci,
  187. struct xhci_container_ctx *ctx)
  188. {
  189. dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
  190. kfree(ctx);
  191. }
  192. struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
  193. struct xhci_container_ctx *ctx)
  194. {
  195. BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
  196. return (struct xhci_input_control_ctx *)ctx->bytes;
  197. }
  198. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
  199. struct xhci_container_ctx *ctx)
  200. {
  201. if (ctx->type == XHCI_CTX_TYPE_DEVICE)
  202. return (struct xhci_slot_ctx *)ctx->bytes;
  203. return (struct xhci_slot_ctx *)
  204. (ctx->bytes + CTX_SIZE(xhci->hcc_params));
  205. }
  206. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
  207. struct xhci_container_ctx *ctx,
  208. unsigned int ep_index)
  209. {
  210. /* increment ep index by offset of start of ep ctx array */
  211. ep_index++;
  212. if (ctx->type == XHCI_CTX_TYPE_INPUT)
  213. ep_index++;
  214. return (struct xhci_ep_ctx *)
  215. (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
  216. }
  217. /* All the xhci_tds in the ring's TD list should be freed at this point */
  218. void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
  219. {
  220. struct xhci_virt_device *dev;
  221. int i;
  222. /* Slot ID 0 is reserved */
  223. if (slot_id == 0 || !xhci->devs[slot_id])
  224. return;
  225. dev = xhci->devs[slot_id];
  226. xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
  227. if (!dev)
  228. return;
  229. for (i = 0; i < 31; ++i)
  230. if (dev->eps[i].ring)
  231. xhci_ring_free(xhci, dev->eps[i].ring);
  232. if (dev->in_ctx)
  233. xhci_free_container_ctx(xhci, dev->in_ctx);
  234. if (dev->out_ctx)
  235. xhci_free_container_ctx(xhci, dev->out_ctx);
  236. kfree(xhci->devs[slot_id]);
  237. xhci->devs[slot_id] = 0;
  238. }
  239. int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
  240. struct usb_device *udev, gfp_t flags)
  241. {
  242. struct xhci_virt_device *dev;
  243. int i;
  244. /* Slot ID 0 is reserved */
  245. if (slot_id == 0 || xhci->devs[slot_id]) {
  246. xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
  247. return 0;
  248. }
  249. xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
  250. if (!xhci->devs[slot_id])
  251. return 0;
  252. dev = xhci->devs[slot_id];
  253. /* Allocate the (output) device context that will be used in the HC. */
  254. dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
  255. if (!dev->out_ctx)
  256. goto fail;
  257. xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
  258. (unsigned long long)dev->out_ctx->dma);
  259. /* Allocate the (input) device context for address device command */
  260. dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
  261. if (!dev->in_ctx)
  262. goto fail;
  263. xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
  264. (unsigned long long)dev->in_ctx->dma);
  265. /* Initialize the cancellation list for each endpoint */
  266. for (i = 0; i < 31; i++)
  267. INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
  268. /* Allocate endpoint 0 ring */
  269. dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
  270. if (!dev->eps[0].ring)
  271. goto fail;
  272. init_completion(&dev->cmd_completion);
  273. INIT_LIST_HEAD(&dev->cmd_list);
  274. /* Point to output device context in dcbaa. */
  275. xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
  276. xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
  277. slot_id,
  278. &xhci->dcbaa->dev_context_ptrs[slot_id],
  279. (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
  280. return 1;
  281. fail:
  282. xhci_free_virt_device(xhci, slot_id);
  283. return 0;
  284. }
  285. /* Setup an xHCI virtual device for a Set Address command */
  286. int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
  287. {
  288. struct xhci_virt_device *dev;
  289. struct xhci_ep_ctx *ep0_ctx;
  290. struct usb_device *top_dev;
  291. struct xhci_slot_ctx *slot_ctx;
  292. struct xhci_input_control_ctx *ctrl_ctx;
  293. dev = xhci->devs[udev->slot_id];
  294. /* Slot ID 0 is reserved */
  295. if (udev->slot_id == 0 || !dev) {
  296. xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
  297. udev->slot_id);
  298. return -EINVAL;
  299. }
  300. ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
  301. ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
  302. slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
  303. /* 2) New slot context and endpoint 0 context are valid*/
  304. ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
  305. /* 3) Only the control endpoint is valid - one endpoint context */
  306. slot_ctx->dev_info |= LAST_CTX(1);
  307. slot_ctx->dev_info |= (u32) udev->route;
  308. switch (udev->speed) {
  309. case USB_SPEED_SUPER:
  310. slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
  311. break;
  312. case USB_SPEED_HIGH:
  313. slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
  314. break;
  315. case USB_SPEED_FULL:
  316. slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
  317. break;
  318. case USB_SPEED_LOW:
  319. slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
  320. break;
  321. case USB_SPEED_VARIABLE:
  322. xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
  323. return -EINVAL;
  324. break;
  325. default:
  326. /* Speed was set earlier, this shouldn't happen. */
  327. BUG();
  328. }
  329. /* Find the root hub port this device is under */
  330. for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
  331. top_dev = top_dev->parent)
  332. /* Found device below root hub */;
  333. slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
  334. xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
  335. /* Is this a LS/FS device under a HS hub? */
  336. if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
  337. udev->tt) {
  338. slot_ctx->tt_info = udev->tt->hub->slot_id;
  339. slot_ctx->tt_info |= udev->ttport << 8;
  340. if (udev->tt->multi)
  341. slot_ctx->dev_info |= DEV_MTT;
  342. }
  343. xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
  344. xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
  345. /* Step 4 - ring already allocated */
  346. /* Step 5 */
  347. ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
  348. /*
  349. * XXX: Not sure about wireless USB devices.
  350. */
  351. switch (udev->speed) {
  352. case USB_SPEED_SUPER:
  353. ep0_ctx->ep_info2 |= MAX_PACKET(512);
  354. break;
  355. case USB_SPEED_HIGH:
  356. /* USB core guesses at a 64-byte max packet first for FS devices */
  357. case USB_SPEED_FULL:
  358. ep0_ctx->ep_info2 |= MAX_PACKET(64);
  359. break;
  360. case USB_SPEED_LOW:
  361. ep0_ctx->ep_info2 |= MAX_PACKET(8);
  362. break;
  363. case USB_SPEED_VARIABLE:
  364. xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
  365. return -EINVAL;
  366. break;
  367. default:
  368. /* New speed? */
  369. BUG();
  370. }
  371. /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
  372. ep0_ctx->ep_info2 |= MAX_BURST(0);
  373. ep0_ctx->ep_info2 |= ERROR_COUNT(3);
  374. ep0_ctx->deq =
  375. dev->eps[0].ring->first_seg->dma;
  376. ep0_ctx->deq |= dev->eps[0].ring->cycle_state;
  377. /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
  378. return 0;
  379. }
  380. /* Return the polling or NAK interval.
  381. *
  382. * The polling interval is expressed in "microframes". If xHCI's Interval field
  383. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  384. *
  385. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  386. * is set to 0.
  387. */
  388. static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  389. struct usb_host_endpoint *ep)
  390. {
  391. unsigned int interval = 0;
  392. switch (udev->speed) {
  393. case USB_SPEED_HIGH:
  394. /* Max NAK rate */
  395. if (usb_endpoint_xfer_control(&ep->desc) ||
  396. usb_endpoint_xfer_bulk(&ep->desc))
  397. interval = ep->desc.bInterval;
  398. /* Fall through - SS and HS isoc/int have same decoding */
  399. case USB_SPEED_SUPER:
  400. if (usb_endpoint_xfer_int(&ep->desc) ||
  401. usb_endpoint_xfer_isoc(&ep->desc)) {
  402. if (ep->desc.bInterval == 0)
  403. interval = 0;
  404. else
  405. interval = ep->desc.bInterval - 1;
  406. if (interval > 15)
  407. interval = 15;
  408. if (interval != ep->desc.bInterval + 1)
  409. dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
  410. ep->desc.bEndpointAddress, 1 << interval);
  411. }
  412. break;
  413. /* Convert bInterval (in 1-255 frames) to microframes and round down to
  414. * nearest power of 2.
  415. */
  416. case USB_SPEED_FULL:
  417. case USB_SPEED_LOW:
  418. if (usb_endpoint_xfer_int(&ep->desc) ||
  419. usb_endpoint_xfer_isoc(&ep->desc)) {
  420. interval = fls(8*ep->desc.bInterval) - 1;
  421. if (interval > 10)
  422. interval = 10;
  423. if (interval < 3)
  424. interval = 3;
  425. if ((1 << interval) != 8*ep->desc.bInterval)
  426. dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
  427. ep->desc.bEndpointAddress, 1 << interval);
  428. }
  429. break;
  430. default:
  431. BUG();
  432. }
  433. return EP_INTERVAL(interval);
  434. }
  435. static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
  436. struct usb_host_endpoint *ep)
  437. {
  438. int in;
  439. u32 type;
  440. in = usb_endpoint_dir_in(&ep->desc);
  441. if (usb_endpoint_xfer_control(&ep->desc)) {
  442. type = EP_TYPE(CTRL_EP);
  443. } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
  444. if (in)
  445. type = EP_TYPE(BULK_IN_EP);
  446. else
  447. type = EP_TYPE(BULK_OUT_EP);
  448. } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
  449. if (in)
  450. type = EP_TYPE(ISOC_IN_EP);
  451. else
  452. type = EP_TYPE(ISOC_OUT_EP);
  453. } else if (usb_endpoint_xfer_int(&ep->desc)) {
  454. if (in)
  455. type = EP_TYPE(INT_IN_EP);
  456. else
  457. type = EP_TYPE(INT_OUT_EP);
  458. } else {
  459. BUG();
  460. }
  461. return type;
  462. }
  463. int xhci_endpoint_init(struct xhci_hcd *xhci,
  464. struct xhci_virt_device *virt_dev,
  465. struct usb_device *udev,
  466. struct usb_host_endpoint *ep,
  467. gfp_t mem_flags)
  468. {
  469. unsigned int ep_index;
  470. struct xhci_ep_ctx *ep_ctx;
  471. struct xhci_ring *ep_ring;
  472. unsigned int max_packet;
  473. unsigned int max_burst;
  474. ep_index = xhci_get_endpoint_index(&ep->desc);
  475. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  476. /* Set up the endpoint ring */
  477. virt_dev->eps[ep_index].new_ring =
  478. xhci_ring_alloc(xhci, 1, true, mem_flags);
  479. if (!virt_dev->eps[ep_index].new_ring)
  480. return -ENOMEM;
  481. ep_ring = virt_dev->eps[ep_index].new_ring;
  482. ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
  483. ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
  484. /* FIXME dig Mult and streams info out of ep companion desc */
  485. /* Allow 3 retries for everything but isoc;
  486. * error count = 0 means infinite retries.
  487. */
  488. if (!usb_endpoint_xfer_isoc(&ep->desc))
  489. ep_ctx->ep_info2 = ERROR_COUNT(3);
  490. else
  491. ep_ctx->ep_info2 = ERROR_COUNT(1);
  492. ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
  493. /* Set the max packet size and max burst */
  494. switch (udev->speed) {
  495. case USB_SPEED_SUPER:
  496. max_packet = ep->desc.wMaxPacketSize;
  497. ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
  498. /* dig out max burst from ep companion desc */
  499. if (!ep->ss_ep_comp) {
  500. xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n");
  501. max_packet = 0;
  502. } else {
  503. max_packet = ep->ss_ep_comp->desc.bMaxBurst;
  504. }
  505. ep_ctx->ep_info2 |= MAX_BURST(max_packet);
  506. break;
  507. case USB_SPEED_HIGH:
  508. /* bits 11:12 specify the number of additional transaction
  509. * opportunities per microframe (USB 2.0, section 9.6.6)
  510. */
  511. if (usb_endpoint_xfer_isoc(&ep->desc) ||
  512. usb_endpoint_xfer_int(&ep->desc)) {
  513. max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
  514. ep_ctx->ep_info2 |= MAX_BURST(max_burst);
  515. }
  516. /* Fall through */
  517. case USB_SPEED_FULL:
  518. case USB_SPEED_LOW:
  519. max_packet = ep->desc.wMaxPacketSize & 0x3ff;
  520. ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
  521. break;
  522. default:
  523. BUG();
  524. }
  525. /* FIXME Debug endpoint context */
  526. return 0;
  527. }
  528. void xhci_endpoint_zero(struct xhci_hcd *xhci,
  529. struct xhci_virt_device *virt_dev,
  530. struct usb_host_endpoint *ep)
  531. {
  532. unsigned int ep_index;
  533. struct xhci_ep_ctx *ep_ctx;
  534. ep_index = xhci_get_endpoint_index(&ep->desc);
  535. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  536. ep_ctx->ep_info = 0;
  537. ep_ctx->ep_info2 = 0;
  538. ep_ctx->deq = 0;
  539. ep_ctx->tx_info = 0;
  540. /* Don't free the endpoint ring until the set interface or configuration
  541. * request succeeds.
  542. */
  543. }
  544. /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
  545. * Useful when you want to change one particular aspect of the endpoint and then
  546. * issue a configure endpoint command.
  547. */
  548. void xhci_endpoint_copy(struct xhci_hcd *xhci,
  549. struct xhci_container_ctx *in_ctx,
  550. struct xhci_container_ctx *out_ctx,
  551. unsigned int ep_index)
  552. {
  553. struct xhci_ep_ctx *out_ep_ctx;
  554. struct xhci_ep_ctx *in_ep_ctx;
  555. out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  556. in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  557. in_ep_ctx->ep_info = out_ep_ctx->ep_info;
  558. in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
  559. in_ep_ctx->deq = out_ep_ctx->deq;
  560. in_ep_ctx->tx_info = out_ep_ctx->tx_info;
  561. }
  562. /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
  563. * Useful when you want to change one particular aspect of the endpoint and then
  564. * issue a configure endpoint command. Only the context entries field matters,
  565. * but we'll copy the whole thing anyway.
  566. */
  567. void xhci_slot_copy(struct xhci_hcd *xhci,
  568. struct xhci_container_ctx *in_ctx,
  569. struct xhci_container_ctx *out_ctx)
  570. {
  571. struct xhci_slot_ctx *in_slot_ctx;
  572. struct xhci_slot_ctx *out_slot_ctx;
  573. in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  574. out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
  575. in_slot_ctx->dev_info = out_slot_ctx->dev_info;
  576. in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
  577. in_slot_ctx->tt_info = out_slot_ctx->tt_info;
  578. in_slot_ctx->dev_state = out_slot_ctx->dev_state;
  579. }
  580. /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
  581. static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
  582. {
  583. int i;
  584. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  585. int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
  586. xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
  587. if (!num_sp)
  588. return 0;
  589. xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
  590. if (!xhci->scratchpad)
  591. goto fail_sp;
  592. xhci->scratchpad->sp_array =
  593. pci_alloc_consistent(to_pci_dev(dev),
  594. num_sp * sizeof(u64),
  595. &xhci->scratchpad->sp_dma);
  596. if (!xhci->scratchpad->sp_array)
  597. goto fail_sp2;
  598. xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
  599. if (!xhci->scratchpad->sp_buffers)
  600. goto fail_sp3;
  601. xhci->scratchpad->sp_dma_buffers =
  602. kzalloc(sizeof(dma_addr_t) * num_sp, flags);
  603. if (!xhci->scratchpad->sp_dma_buffers)
  604. goto fail_sp4;
  605. xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
  606. for (i = 0; i < num_sp; i++) {
  607. dma_addr_t dma;
  608. void *buf = pci_alloc_consistent(to_pci_dev(dev),
  609. xhci->page_size, &dma);
  610. if (!buf)
  611. goto fail_sp5;
  612. xhci->scratchpad->sp_array[i] = dma;
  613. xhci->scratchpad->sp_buffers[i] = buf;
  614. xhci->scratchpad->sp_dma_buffers[i] = dma;
  615. }
  616. return 0;
  617. fail_sp5:
  618. for (i = i - 1; i >= 0; i--) {
  619. pci_free_consistent(to_pci_dev(dev), xhci->page_size,
  620. xhci->scratchpad->sp_buffers[i],
  621. xhci->scratchpad->sp_dma_buffers[i]);
  622. }
  623. kfree(xhci->scratchpad->sp_dma_buffers);
  624. fail_sp4:
  625. kfree(xhci->scratchpad->sp_buffers);
  626. fail_sp3:
  627. pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
  628. xhci->scratchpad->sp_array,
  629. xhci->scratchpad->sp_dma);
  630. fail_sp2:
  631. kfree(xhci->scratchpad);
  632. xhci->scratchpad = NULL;
  633. fail_sp:
  634. return -ENOMEM;
  635. }
  636. static void scratchpad_free(struct xhci_hcd *xhci)
  637. {
  638. int num_sp;
  639. int i;
  640. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  641. if (!xhci->scratchpad)
  642. return;
  643. num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
  644. for (i = 0; i < num_sp; i++) {
  645. pci_free_consistent(pdev, xhci->page_size,
  646. xhci->scratchpad->sp_buffers[i],
  647. xhci->scratchpad->sp_dma_buffers[i]);
  648. }
  649. kfree(xhci->scratchpad->sp_dma_buffers);
  650. kfree(xhci->scratchpad->sp_buffers);
  651. pci_free_consistent(pdev, num_sp * sizeof(u64),
  652. xhci->scratchpad->sp_array,
  653. xhci->scratchpad->sp_dma);
  654. kfree(xhci->scratchpad);
  655. xhci->scratchpad = NULL;
  656. }
  657. struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
  658. bool allocate_completion, gfp_t mem_flags)
  659. {
  660. struct xhci_command *command;
  661. command = kzalloc(sizeof(*command), mem_flags);
  662. if (!command)
  663. return NULL;
  664. command->in_ctx =
  665. xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, mem_flags);
  666. if (!command->in_ctx)
  667. return NULL;
  668. if (allocate_completion) {
  669. command->completion =
  670. kzalloc(sizeof(struct completion), mem_flags);
  671. if (!command->completion) {
  672. xhci_free_container_ctx(xhci, command->in_ctx);
  673. return NULL;
  674. }
  675. init_completion(command->completion);
  676. }
  677. command->status = 0;
  678. INIT_LIST_HEAD(&command->cmd_list);
  679. return command;
  680. }
  681. void xhci_free_command(struct xhci_hcd *xhci,
  682. struct xhci_command *command)
  683. {
  684. xhci_free_container_ctx(xhci,
  685. command->in_ctx);
  686. kfree(command->completion);
  687. kfree(command);
  688. }
  689. void xhci_mem_cleanup(struct xhci_hcd *xhci)
  690. {
  691. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  692. int size;
  693. int i;
  694. /* Free the Event Ring Segment Table and the actual Event Ring */
  695. if (xhci->ir_set) {
  696. xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
  697. xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
  698. xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
  699. }
  700. size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
  701. if (xhci->erst.entries)
  702. pci_free_consistent(pdev, size,
  703. xhci->erst.entries, xhci->erst.erst_dma_addr);
  704. xhci->erst.entries = NULL;
  705. xhci_dbg(xhci, "Freed ERST\n");
  706. if (xhci->event_ring)
  707. xhci_ring_free(xhci, xhci->event_ring);
  708. xhci->event_ring = NULL;
  709. xhci_dbg(xhci, "Freed event ring\n");
  710. xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
  711. if (xhci->cmd_ring)
  712. xhci_ring_free(xhci, xhci->cmd_ring);
  713. xhci->cmd_ring = NULL;
  714. xhci_dbg(xhci, "Freed command ring\n");
  715. for (i = 1; i < MAX_HC_SLOTS; ++i)
  716. xhci_free_virt_device(xhci, i);
  717. if (xhci->segment_pool)
  718. dma_pool_destroy(xhci->segment_pool);
  719. xhci->segment_pool = NULL;
  720. xhci_dbg(xhci, "Freed segment pool\n");
  721. if (xhci->device_pool)
  722. dma_pool_destroy(xhci->device_pool);
  723. xhci->device_pool = NULL;
  724. xhci_dbg(xhci, "Freed device context pool\n");
  725. xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
  726. if (xhci->dcbaa)
  727. pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
  728. xhci->dcbaa, xhci->dcbaa->dma);
  729. xhci->dcbaa = NULL;
  730. scratchpad_free(xhci);
  731. xhci->page_size = 0;
  732. xhci->page_shift = 0;
  733. }
  734. int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
  735. {
  736. dma_addr_t dma;
  737. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  738. unsigned int val, val2;
  739. u64 val_64;
  740. struct xhci_segment *seg;
  741. u32 page_size;
  742. int i;
  743. page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
  744. xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
  745. for (i = 0; i < 16; i++) {
  746. if ((0x1 & page_size) != 0)
  747. break;
  748. page_size = page_size >> 1;
  749. }
  750. if (i < 16)
  751. xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
  752. else
  753. xhci_warn(xhci, "WARN: no supported page size\n");
  754. /* Use 4K pages, since that's common and the minimum the HC supports */
  755. xhci->page_shift = 12;
  756. xhci->page_size = 1 << xhci->page_shift;
  757. xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
  758. /*
  759. * Program the Number of Device Slots Enabled field in the CONFIG
  760. * register with the max value of slots the HC can handle.
  761. */
  762. val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
  763. xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
  764. (unsigned int) val);
  765. val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
  766. val |= (val2 & ~HCS_SLOTS_MASK);
  767. xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
  768. (unsigned int) val);
  769. xhci_writel(xhci, val, &xhci->op_regs->config_reg);
  770. /*
  771. * Section 5.4.8 - doorbell array must be
  772. * "physically contiguous and 64-byte (cache line) aligned".
  773. */
  774. xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
  775. sizeof(*xhci->dcbaa), &dma);
  776. if (!xhci->dcbaa)
  777. goto fail;
  778. memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
  779. xhci->dcbaa->dma = dma;
  780. xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
  781. (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
  782. xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
  783. /*
  784. * Initialize the ring segment pool. The ring must be a contiguous
  785. * structure comprised of TRBs. The TRBs must be 16 byte aligned,
  786. * however, the command ring segment needs 64-byte aligned segments,
  787. * so we pick the greater alignment need.
  788. */
  789. xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
  790. SEGMENT_SIZE, 64, xhci->page_size);
  791. /* See Table 46 and Note on Figure 55 */
  792. xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
  793. 2112, 64, xhci->page_size);
  794. if (!xhci->segment_pool || !xhci->device_pool)
  795. goto fail;
  796. /* Set up the command ring to have one segments for now. */
  797. xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
  798. if (!xhci->cmd_ring)
  799. goto fail;
  800. xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
  801. xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
  802. (unsigned long long)xhci->cmd_ring->first_seg->dma);
  803. /* Set the address in the Command Ring Control register */
  804. val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
  805. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  806. (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
  807. xhci->cmd_ring->cycle_state;
  808. xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
  809. xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
  810. xhci_dbg_cmd_ptrs(xhci);
  811. val = xhci_readl(xhci, &xhci->cap_regs->db_off);
  812. val &= DBOFF_MASK;
  813. xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
  814. " from cap regs base addr\n", val);
  815. xhci->dba = (void *) xhci->cap_regs + val;
  816. xhci_dbg_regs(xhci);
  817. xhci_print_run_regs(xhci);
  818. /* Set ir_set to interrupt register set 0 */
  819. xhci->ir_set = (void *) xhci->run_regs->ir_set;
  820. /*
  821. * Event ring setup: Allocate a normal ring, but also setup
  822. * the event ring segment table (ERST). Section 4.9.3.
  823. */
  824. xhci_dbg(xhci, "// Allocating event ring\n");
  825. xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
  826. if (!xhci->event_ring)
  827. goto fail;
  828. xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
  829. sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
  830. if (!xhci->erst.entries)
  831. goto fail;
  832. xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
  833. (unsigned long long)dma);
  834. memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
  835. xhci->erst.num_entries = ERST_NUM_SEGS;
  836. xhci->erst.erst_dma_addr = dma;
  837. xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
  838. xhci->erst.num_entries,
  839. xhci->erst.entries,
  840. (unsigned long long)xhci->erst.erst_dma_addr);
  841. /* set ring base address and size for each segment table entry */
  842. for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
  843. struct xhci_erst_entry *entry = &xhci->erst.entries[val];
  844. entry->seg_addr = seg->dma;
  845. entry->seg_size = TRBS_PER_SEGMENT;
  846. entry->rsvd = 0;
  847. seg = seg->next;
  848. }
  849. /* set ERST count with the number of entries in the segment table */
  850. val = xhci_readl(xhci, &xhci->ir_set->erst_size);
  851. val &= ERST_SIZE_MASK;
  852. val |= ERST_NUM_SEGS;
  853. xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
  854. val);
  855. xhci_writel(xhci, val, &xhci->ir_set->erst_size);
  856. xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
  857. /* set the segment table base address */
  858. xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
  859. (unsigned long long)xhci->erst.erst_dma_addr);
  860. val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
  861. val_64 &= ERST_PTR_MASK;
  862. val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
  863. xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
  864. /* Set the event ring dequeue address */
  865. xhci_set_hc_event_deq(xhci);
  866. xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
  867. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  868. /*
  869. * XXX: Might need to set the Interrupter Moderation Register to
  870. * something other than the default (~1ms minimum between interrupts).
  871. * See section 5.5.1.2.
  872. */
  873. init_completion(&xhci->addr_dev);
  874. for (i = 0; i < MAX_HC_SLOTS; ++i)
  875. xhci->devs[i] = 0;
  876. if (scratchpad_alloc(xhci, flags))
  877. goto fail;
  878. return 0;
  879. fail:
  880. xhci_warn(xhci, "Couldn't initialize memory\n");
  881. xhci_mem_cleanup(xhci);
  882. return -ENOMEM;
  883. }