cxgb3i_ddp.c 20 KB

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  1. /*
  2. * cxgb3i_ddp.c: Chelsio S3xx iSCSI DDP Manager.
  3. *
  4. * Copyright (c) 2008 Chelsio Communications, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Written by: Karen Xie (kxie@chelsio.com)
  11. */
  12. #include <linux/skbuff.h>
  13. #include <linux/scatterlist.h>
  14. /* from cxgb3 LLD */
  15. #include "common.h"
  16. #include "t3_cpl.h"
  17. #include "t3cdev.h"
  18. #include "cxgb3_ctl_defs.h"
  19. #include "cxgb3_offload.h"
  20. #include "firmware_exports.h"
  21. #include "cxgb3i_ddp.h"
  22. #define ddp_log_error(fmt...) printk(KERN_ERR "cxgb3i_ddp: ERR! " fmt)
  23. #define ddp_log_warn(fmt...) printk(KERN_WARNING "cxgb3i_ddp: WARN! " fmt)
  24. #define ddp_log_info(fmt...) printk(KERN_INFO "cxgb3i_ddp: " fmt)
  25. #ifdef __DEBUG_CXGB3I_DDP__
  26. #define ddp_log_debug(fmt, args...) \
  27. printk(KERN_INFO "cxgb3i_ddp: %s - " fmt, __func__ , ## args)
  28. #else
  29. #define ddp_log_debug(fmt...)
  30. #endif
  31. /*
  32. * iSCSI Direct Data Placement
  33. *
  34. * T3 h/w can directly place the iSCSI Data-In or Data-Out PDU's payload into
  35. * pre-posted final destination host-memory buffers based on the Initiator
  36. * Task Tag (ITT) in Data-In or Target Task Tag (TTT) in Data-Out PDUs.
  37. *
  38. * The host memory address is programmed into h/w in the format of pagepod
  39. * entries.
  40. * The location of the pagepod entry is encoded into ddp tag which is used or
  41. * is the base for ITT/TTT.
  42. */
  43. #define DDP_PGIDX_MAX 4
  44. #define DDP_THRESHOLD 2048
  45. static unsigned char ddp_page_order[DDP_PGIDX_MAX] = {0, 1, 2, 4};
  46. static unsigned char ddp_page_shift[DDP_PGIDX_MAX] = {12, 13, 14, 16};
  47. static unsigned char page_idx = DDP_PGIDX_MAX;
  48. /*
  49. * functions to program the pagepod in h/w
  50. */
  51. static inline void ulp_mem_io_set_hdr(struct sk_buff *skb, unsigned int addr)
  52. {
  53. struct ulp_mem_io *req = (struct ulp_mem_io *)skb->head;
  54. req->wr.wr_lo = 0;
  55. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS));
  56. req->cmd_lock_addr = htonl(V_ULP_MEMIO_ADDR(addr >> 5) |
  57. V_ULPTX_CMD(ULP_MEM_WRITE));
  58. req->len = htonl(V_ULP_MEMIO_DATA_LEN(PPOD_SIZE >> 5) |
  59. V_ULPTX_NFLITS((PPOD_SIZE >> 3) + 1));
  60. }
  61. static int set_ddp_map(struct cxgb3i_ddp_info *ddp, struct pagepod_hdr *hdr,
  62. unsigned int idx, unsigned int npods,
  63. struct cxgb3i_gather_list *gl)
  64. {
  65. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ddp->llimit;
  66. int i;
  67. for (i = 0; i < npods; i++, idx++, pm_addr += PPOD_SIZE) {
  68. struct sk_buff *skb = ddp->gl_skb[idx];
  69. struct pagepod *ppod;
  70. int j, pidx;
  71. /* hold on to the skb until we clear the ddp mapping */
  72. skb_get(skb);
  73. ulp_mem_io_set_hdr(skb, pm_addr);
  74. ppod = (struct pagepod *)
  75. (skb->head + sizeof(struct ulp_mem_io));
  76. memcpy(&(ppod->hdr), hdr, sizeof(struct pagepod));
  77. for (pidx = 4 * i, j = 0; j < 5; ++j, ++pidx)
  78. ppod->addr[j] = pidx < gl->nelem ?
  79. cpu_to_be64(gl->phys_addr[pidx]) : 0UL;
  80. skb->priority = CPL_PRIORITY_CONTROL;
  81. cxgb3_ofld_send(ddp->tdev, skb);
  82. }
  83. return 0;
  84. }
  85. static void clear_ddp_map(struct cxgb3i_ddp_info *ddp, unsigned int tag,
  86. unsigned int idx, unsigned int npods)
  87. {
  88. unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ddp->llimit;
  89. int i;
  90. for (i = 0; i < npods; i++, idx++, pm_addr += PPOD_SIZE) {
  91. struct sk_buff *skb = ddp->gl_skb[idx];
  92. if (!skb) {
  93. ddp_log_error("ddp tag 0x%x, 0x%x, %d/%u, skb NULL.\n",
  94. tag, idx, i, npods);
  95. continue;
  96. }
  97. ddp->gl_skb[idx] = NULL;
  98. memset((skb->head + sizeof(struct ulp_mem_io)), 0, PPOD_SIZE);
  99. ulp_mem_io_set_hdr(skb, pm_addr);
  100. skb->priority = CPL_PRIORITY_CONTROL;
  101. cxgb3_ofld_send(ddp->tdev, skb);
  102. }
  103. }
  104. static inline int ddp_find_unused_entries(struct cxgb3i_ddp_info *ddp,
  105. unsigned int start, unsigned int max,
  106. unsigned int count,
  107. struct cxgb3i_gather_list *gl)
  108. {
  109. unsigned int i, j, k;
  110. /* not enough entries */
  111. if ((max - start) < count)
  112. return -EBUSY;
  113. max -= count;
  114. spin_lock(&ddp->map_lock);
  115. for (i = start; i < max;) {
  116. for (j = 0, k = i; j < count; j++, k++) {
  117. if (ddp->gl_map[k])
  118. break;
  119. }
  120. if (j == count) {
  121. for (j = 0, k = i; j < count; j++, k++)
  122. ddp->gl_map[k] = gl;
  123. spin_unlock(&ddp->map_lock);
  124. return i;
  125. }
  126. i += j + 1;
  127. }
  128. spin_unlock(&ddp->map_lock);
  129. return -EBUSY;
  130. }
  131. static inline void ddp_unmark_entries(struct cxgb3i_ddp_info *ddp,
  132. int start, int count)
  133. {
  134. spin_lock(&ddp->map_lock);
  135. memset(&ddp->gl_map[start], 0,
  136. count * sizeof(struct cxgb3i_gather_list *));
  137. spin_unlock(&ddp->map_lock);
  138. }
  139. static inline void ddp_free_gl_skb(struct cxgb3i_ddp_info *ddp,
  140. int idx, int count)
  141. {
  142. int i;
  143. for (i = 0; i < count; i++, idx++)
  144. if (ddp->gl_skb[idx]) {
  145. kfree_skb(ddp->gl_skb[idx]);
  146. ddp->gl_skb[idx] = NULL;
  147. }
  148. }
  149. static inline int ddp_alloc_gl_skb(struct cxgb3i_ddp_info *ddp, int idx,
  150. int count, gfp_t gfp)
  151. {
  152. int i;
  153. for (i = 0; i < count; i++) {
  154. struct sk_buff *skb = alloc_skb(sizeof(struct ulp_mem_io) +
  155. PPOD_SIZE, gfp);
  156. if (skb) {
  157. ddp->gl_skb[idx + i] = skb;
  158. skb_put(skb, sizeof(struct ulp_mem_io) + PPOD_SIZE);
  159. } else {
  160. ddp_free_gl_skb(ddp, idx, i);
  161. return -ENOMEM;
  162. }
  163. }
  164. return 0;
  165. }
  166. /**
  167. * cxgb3i_ddp_find_page_index - return ddp page index for a given page size
  168. * @pgsz: page size
  169. * return the ddp page index, if no match is found return DDP_PGIDX_MAX.
  170. */
  171. int cxgb3i_ddp_find_page_index(unsigned long pgsz)
  172. {
  173. int i;
  174. for (i = 0; i < DDP_PGIDX_MAX; i++) {
  175. if (pgsz == (1UL << ddp_page_shift[i]))
  176. return i;
  177. }
  178. ddp_log_debug("ddp page size 0x%lx not supported.\n", pgsz);
  179. return DDP_PGIDX_MAX;
  180. }
  181. /**
  182. * cxgb3i_ddp_adjust_page_table - adjust page table with PAGE_SIZE
  183. * return the ddp page index, if no match is found return DDP_PGIDX_MAX.
  184. */
  185. int cxgb3i_ddp_adjust_page_table(void)
  186. {
  187. int i;
  188. unsigned int base_order, order;
  189. if (PAGE_SIZE < (1UL << ddp_page_shift[0])) {
  190. ddp_log_info("PAGE_SIZE 0x%lx too small, min. 0x%lx.\n",
  191. PAGE_SIZE, 1UL << ddp_page_shift[0]);
  192. return -EINVAL;
  193. }
  194. base_order = get_order(1UL << ddp_page_shift[0]);
  195. order = get_order(1 << PAGE_SHIFT);
  196. for (i = 0; i < DDP_PGIDX_MAX; i++) {
  197. /* first is the kernel page size, then just doubling the size */
  198. ddp_page_order[i] = order - base_order + i;
  199. ddp_page_shift[i] = PAGE_SHIFT + i;
  200. }
  201. return 0;
  202. }
  203. static inline void ddp_gl_unmap(struct pci_dev *pdev,
  204. struct cxgb3i_gather_list *gl)
  205. {
  206. int i;
  207. for (i = 0; i < gl->nelem; i++)
  208. pci_unmap_page(pdev, gl->phys_addr[i], PAGE_SIZE,
  209. PCI_DMA_FROMDEVICE);
  210. }
  211. static inline int ddp_gl_map(struct pci_dev *pdev,
  212. struct cxgb3i_gather_list *gl)
  213. {
  214. int i;
  215. for (i = 0; i < gl->nelem; i++) {
  216. gl->phys_addr[i] = pci_map_page(pdev, gl->pages[i], 0,
  217. PAGE_SIZE,
  218. PCI_DMA_FROMDEVICE);
  219. if (unlikely(pci_dma_mapping_error(pdev, gl->phys_addr[i])))
  220. goto unmap;
  221. }
  222. return i;
  223. unmap:
  224. if (i) {
  225. unsigned int nelem = gl->nelem;
  226. gl->nelem = i;
  227. ddp_gl_unmap(pdev, gl);
  228. gl->nelem = nelem;
  229. }
  230. return -ENOMEM;
  231. }
  232. /**
  233. * cxgb3i_ddp_make_gl - build ddp page buffer list
  234. * @xferlen: total buffer length
  235. * @sgl: page buffer scatter-gather list
  236. * @sgcnt: # of page buffers
  237. * @pdev: pci_dev, used for pci map
  238. * @gfp: allocation mode
  239. *
  240. * construct a ddp page buffer list from the scsi scattergather list.
  241. * coalesce buffers as much as possible, and obtain dma addresses for
  242. * each page.
  243. *
  244. * Return the cxgb3i_gather_list constructed from the page buffers if the
  245. * memory can be used for ddp. Return NULL otherwise.
  246. */
  247. struct cxgb3i_gather_list *cxgb3i_ddp_make_gl(unsigned int xferlen,
  248. struct scatterlist *sgl,
  249. unsigned int sgcnt,
  250. struct pci_dev *pdev,
  251. gfp_t gfp)
  252. {
  253. struct cxgb3i_gather_list *gl;
  254. struct scatterlist *sg = sgl;
  255. struct page *sgpage = sg_page(sg);
  256. unsigned int sglen = sg->length;
  257. unsigned int sgoffset = sg->offset;
  258. unsigned int npages = (xferlen + sgoffset + PAGE_SIZE - 1) >>
  259. PAGE_SHIFT;
  260. int i = 1, j = 0;
  261. if (xferlen < DDP_THRESHOLD) {
  262. ddp_log_debug("xfer %u < threshold %u, no ddp.\n",
  263. xferlen, DDP_THRESHOLD);
  264. return NULL;
  265. }
  266. gl = kzalloc(sizeof(struct cxgb3i_gather_list) +
  267. npages * (sizeof(dma_addr_t) + sizeof(struct page *)),
  268. gfp);
  269. if (!gl)
  270. return NULL;
  271. gl->pages = (struct page **)&gl->phys_addr[npages];
  272. gl->length = xferlen;
  273. gl->offset = sgoffset;
  274. gl->pages[0] = sgpage;
  275. sg = sg_next(sg);
  276. while (sg) {
  277. struct page *page = sg_page(sg);
  278. if (sgpage == page && sg->offset == sgoffset + sglen)
  279. sglen += sg->length;
  280. else {
  281. /* make sure the sgl is fit for ddp:
  282. * each has the same page size, and
  283. * all of the middle pages are used completely
  284. */
  285. if ((j && sgoffset) ||
  286. ((i != sgcnt - 1) &&
  287. ((sglen + sgoffset) & ~PAGE_MASK)))
  288. goto error_out;
  289. j++;
  290. if (j == gl->nelem || sg->offset)
  291. goto error_out;
  292. gl->pages[j] = page;
  293. sglen = sg->length;
  294. sgoffset = sg->offset;
  295. sgpage = page;
  296. }
  297. i++;
  298. sg = sg_next(sg);
  299. }
  300. gl->nelem = ++j;
  301. if (ddp_gl_map(pdev, gl) < 0)
  302. goto error_out;
  303. return gl;
  304. error_out:
  305. kfree(gl);
  306. return NULL;
  307. }
  308. /**
  309. * cxgb3i_ddp_release_gl - release a page buffer list
  310. * @gl: a ddp page buffer list
  311. * @pdev: pci_dev used for pci_unmap
  312. * free a ddp page buffer list resulted from cxgb3i_ddp_make_gl().
  313. */
  314. void cxgb3i_ddp_release_gl(struct cxgb3i_gather_list *gl,
  315. struct pci_dev *pdev)
  316. {
  317. ddp_gl_unmap(pdev, gl);
  318. kfree(gl);
  319. }
  320. /**
  321. * cxgb3i_ddp_tag_reserve - set up ddp for a data transfer
  322. * @tdev: t3cdev adapter
  323. * @tid: connection id
  324. * @tformat: tag format
  325. * @tagp: contains s/w tag initially, will be updated with ddp/hw tag
  326. * @gl: the page momory list
  327. * @gfp: allocation mode
  328. *
  329. * ddp setup for a given page buffer list and construct the ddp tag.
  330. * return 0 if success, < 0 otherwise.
  331. */
  332. int cxgb3i_ddp_tag_reserve(struct t3cdev *tdev, unsigned int tid,
  333. struct cxgb3i_tag_format *tformat, u32 *tagp,
  334. struct cxgb3i_gather_list *gl, gfp_t gfp)
  335. {
  336. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  337. struct pagepod_hdr hdr;
  338. unsigned int npods;
  339. int idx = -1;
  340. int err = -ENOMEM;
  341. u32 sw_tag = *tagp;
  342. u32 tag;
  343. if (page_idx >= DDP_PGIDX_MAX || !ddp || !gl || !gl->nelem ||
  344. gl->length < DDP_THRESHOLD) {
  345. ddp_log_debug("pgidx %u, xfer %u/%u, NO ddp.\n",
  346. page_idx, gl->length, DDP_THRESHOLD);
  347. return -EINVAL;
  348. }
  349. npods = (gl->nelem + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
  350. if (ddp->idx_last == ddp->nppods)
  351. idx = ddp_find_unused_entries(ddp, 0, ddp->nppods, npods, gl);
  352. else {
  353. idx = ddp_find_unused_entries(ddp, ddp->idx_last + 1,
  354. ddp->nppods, npods, gl);
  355. if (idx < 0 && ddp->idx_last >= npods) {
  356. idx = ddp_find_unused_entries(ddp, 0,
  357. min(ddp->idx_last + npods, ddp->nppods),
  358. npods, gl);
  359. }
  360. }
  361. if (idx < 0) {
  362. ddp_log_debug("xferlen %u, gl %u, npods %u NO DDP.\n",
  363. gl->length, gl->nelem, npods);
  364. return idx;
  365. }
  366. err = ddp_alloc_gl_skb(ddp, idx, npods, gfp);
  367. if (err < 0)
  368. goto unmark_entries;
  369. tag = cxgb3i_ddp_tag_base(tformat, sw_tag);
  370. tag |= idx << PPOD_IDX_SHIFT;
  371. hdr.rsvd = 0;
  372. hdr.vld_tid = htonl(F_PPOD_VALID | V_PPOD_TID(tid));
  373. hdr.pgsz_tag_clr = htonl(tag & ddp->rsvd_tag_mask);
  374. hdr.maxoffset = htonl(gl->length);
  375. hdr.pgoffset = htonl(gl->offset);
  376. err = set_ddp_map(ddp, &hdr, idx, npods, gl);
  377. if (err < 0)
  378. goto free_gl_skb;
  379. ddp->idx_last = idx;
  380. ddp_log_debug("xfer %u, gl %u,%u, tid 0x%x, 0x%x -> 0x%x(%u,%u).\n",
  381. gl->length, gl->nelem, gl->offset, tid, sw_tag, tag,
  382. idx, npods);
  383. *tagp = tag;
  384. return 0;
  385. free_gl_skb:
  386. ddp_free_gl_skb(ddp, idx, npods);
  387. unmark_entries:
  388. ddp_unmark_entries(ddp, idx, npods);
  389. return err;
  390. }
  391. /**
  392. * cxgb3i_ddp_tag_release - release a ddp tag
  393. * @tdev: t3cdev adapter
  394. * @tag: ddp tag
  395. * ddp cleanup for a given ddp tag and release all the resources held
  396. */
  397. void cxgb3i_ddp_tag_release(struct t3cdev *tdev, u32 tag)
  398. {
  399. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  400. u32 idx;
  401. if (!ddp) {
  402. ddp_log_error("release ddp tag 0x%x, ddp NULL.\n", tag);
  403. return;
  404. }
  405. idx = (tag >> PPOD_IDX_SHIFT) & ddp->idx_mask;
  406. if (idx < ddp->nppods) {
  407. struct cxgb3i_gather_list *gl = ddp->gl_map[idx];
  408. unsigned int npods;
  409. if (!gl || !gl->nelem) {
  410. ddp_log_error("release 0x%x, idx 0x%x, gl 0x%p, %u.\n",
  411. tag, idx, gl, gl ? gl->nelem : 0);
  412. return;
  413. }
  414. npods = (gl->nelem + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT;
  415. ddp_log_debug("ddp tag 0x%x, release idx 0x%x, npods %u.\n",
  416. tag, idx, npods);
  417. clear_ddp_map(ddp, tag, idx, npods);
  418. ddp_unmark_entries(ddp, idx, npods);
  419. cxgb3i_ddp_release_gl(gl, ddp->pdev);
  420. } else
  421. ddp_log_error("ddp tag 0x%x, idx 0x%x > max 0x%x.\n",
  422. tag, idx, ddp->nppods);
  423. }
  424. static int setup_conn_pgidx(struct t3cdev *tdev, unsigned int tid, int pg_idx,
  425. int reply)
  426. {
  427. struct sk_buff *skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
  428. GFP_KERNEL);
  429. struct cpl_set_tcb_field *req;
  430. u64 val = pg_idx < DDP_PGIDX_MAX ? pg_idx : 0;
  431. if (!skb)
  432. return -ENOMEM;
  433. /* set up ulp submode and page size */
  434. req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req));
  435. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
  436. OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
  437. req->reply = V_NO_REPLY(reply ? 0 : 1);
  438. req->cpu_idx = 0;
  439. req->word = htons(31);
  440. req->mask = cpu_to_be64(0xF0000000);
  441. req->val = cpu_to_be64(val << 28);
  442. skb->priority = CPL_PRIORITY_CONTROL;
  443. cxgb3_ofld_send(tdev, skb);
  444. return 0;
  445. }
  446. /**
  447. * cxgb3i_setup_conn_host_pagesize - setup the conn.'s ddp page size
  448. * @tdev: t3cdev adapter
  449. * @tid: connection id
  450. * @reply: request reply from h/w
  451. * set up the ddp page size based on the host PAGE_SIZE for a connection
  452. * identified by tid
  453. */
  454. int cxgb3i_setup_conn_host_pagesize(struct t3cdev *tdev, unsigned int tid,
  455. int reply)
  456. {
  457. return setup_conn_pgidx(tdev, tid, page_idx, reply);
  458. }
  459. /**
  460. * cxgb3i_setup_conn_pagesize - setup the conn.'s ddp page size
  461. * @tdev: t3cdev adapter
  462. * @tid: connection id
  463. * @reply: request reply from h/w
  464. * @pgsz: ddp page size
  465. * set up the ddp page size for a connection identified by tid
  466. */
  467. int cxgb3i_setup_conn_pagesize(struct t3cdev *tdev, unsigned int tid,
  468. int reply, unsigned long pgsz)
  469. {
  470. int pgidx = cxgb3i_ddp_find_page_index(pgsz);
  471. return setup_conn_pgidx(tdev, tid, pgidx, reply);
  472. }
  473. /**
  474. * cxgb3i_setup_conn_digest - setup conn. digest setting
  475. * @tdev: t3cdev adapter
  476. * @tid: connection id
  477. * @hcrc: header digest enabled
  478. * @dcrc: data digest enabled
  479. * @reply: request reply from h/w
  480. * set up the iscsi digest settings for a connection identified by tid
  481. */
  482. int cxgb3i_setup_conn_digest(struct t3cdev *tdev, unsigned int tid,
  483. int hcrc, int dcrc, int reply)
  484. {
  485. struct sk_buff *skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
  486. GFP_KERNEL);
  487. struct cpl_set_tcb_field *req;
  488. u64 val = (hcrc ? 1 : 0) | (dcrc ? 2 : 0);
  489. if (!skb)
  490. return -ENOMEM;
  491. /* set up ulp submode and page size */
  492. req = (struct cpl_set_tcb_field *)skb_put(skb, sizeof(*req));
  493. req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
  494. OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
  495. req->reply = V_NO_REPLY(reply ? 0 : 1);
  496. req->cpu_idx = 0;
  497. req->word = htons(31);
  498. req->mask = cpu_to_be64(0x0F000000);
  499. req->val = cpu_to_be64(val << 24);
  500. skb->priority = CPL_PRIORITY_CONTROL;
  501. cxgb3_ofld_send(tdev, skb);
  502. return 0;
  503. }
  504. /**
  505. * cxgb3i_adapter_ddp_info - read the adapter's ddp information
  506. * @tdev: t3cdev adapter
  507. * @tformat: tag format
  508. * @txsz: max tx pdu payload size, filled in by this func.
  509. * @rxsz: max rx pdu payload size, filled in by this func.
  510. * setup the tag format for a given iscsi entity
  511. */
  512. int cxgb3i_adapter_ddp_info(struct t3cdev *tdev,
  513. struct cxgb3i_tag_format *tformat,
  514. unsigned int *txsz, unsigned int *rxsz)
  515. {
  516. struct cxgb3i_ddp_info *ddp;
  517. unsigned char idx_bits;
  518. if (!tformat)
  519. return -EINVAL;
  520. if (!tdev->ulp_iscsi)
  521. return -EINVAL;
  522. ddp = (struct cxgb3i_ddp_info *)tdev->ulp_iscsi;
  523. idx_bits = 32 - tformat->sw_bits;
  524. tformat->rsvd_bits = ddp->idx_bits;
  525. tformat->rsvd_shift = PPOD_IDX_SHIFT;
  526. tformat->rsvd_mask = (1 << tformat->rsvd_bits) - 1;
  527. ddp_log_info("tag format: sw %u, rsvd %u,%u, mask 0x%x.\n",
  528. tformat->sw_bits, tformat->rsvd_bits,
  529. tformat->rsvd_shift, tformat->rsvd_mask);
  530. *txsz = min_t(unsigned int, ULP2_MAX_PDU_PAYLOAD,
  531. ddp->max_txsz - ISCSI_PDU_NONPAYLOAD_LEN);
  532. *rxsz = min_t(unsigned int, ULP2_MAX_PDU_PAYLOAD,
  533. ddp->max_rxsz - ISCSI_PDU_NONPAYLOAD_LEN);
  534. ddp_log_info("max payload size: %u/%u, %u/%u.\n",
  535. *txsz, ddp->max_txsz, *rxsz, ddp->max_rxsz);
  536. return 0;
  537. }
  538. /**
  539. * cxgb3i_ddp_cleanup - release the cxgb3 adapter's ddp resource
  540. * @tdev: t3cdev adapter
  541. * release all the resource held by the ddp pagepod manager for a given
  542. * adapter if needed
  543. */
  544. static void ddp_cleanup(struct kref *kref)
  545. {
  546. struct cxgb3i_ddp_info *ddp = container_of(kref,
  547. struct cxgb3i_ddp_info,
  548. refcnt);
  549. int i = 0;
  550. ddp_log_info("kref release ddp 0x%p, t3dev 0x%p.\n", ddp, ddp->tdev);
  551. ddp->tdev->ulp_iscsi = NULL;
  552. while (i < ddp->nppods) {
  553. struct cxgb3i_gather_list *gl = ddp->gl_map[i];
  554. if (gl) {
  555. int npods = (gl->nelem + PPOD_PAGES_MAX - 1)
  556. >> PPOD_PAGES_SHIFT;
  557. ddp_log_info("t3dev 0x%p, ddp %d + %d.\n",
  558. ddp->tdev, i, npods);
  559. kfree(gl);
  560. ddp_free_gl_skb(ddp, i, npods);
  561. i += npods;
  562. } else
  563. i++;
  564. }
  565. cxgb3i_free_big_mem(ddp);
  566. }
  567. void cxgb3i_ddp_cleanup(struct t3cdev *tdev)
  568. {
  569. struct cxgb3i_ddp_info *ddp = (struct cxgb3i_ddp_info *)tdev->ulp_iscsi;
  570. ddp_log_info("t3dev 0x%p, release ddp 0x%p.\n", tdev, ddp);
  571. if (ddp)
  572. kref_put(&ddp->refcnt, ddp_cleanup);
  573. }
  574. /**
  575. * ddp_init - initialize the cxgb3 adapter's ddp resource
  576. * @tdev: t3cdev adapter
  577. * initialize the ddp pagepod manager for a given adapter
  578. */
  579. static void ddp_init(struct t3cdev *tdev)
  580. {
  581. struct cxgb3i_ddp_info *ddp = tdev->ulp_iscsi;
  582. struct ulp_iscsi_info uinfo;
  583. unsigned int ppmax, bits;
  584. int i, err;
  585. if (ddp) {
  586. kref_get(&ddp->refcnt);
  587. ddp_log_warn("t3dev 0x%p, ddp 0x%p already set up.\n",
  588. tdev, tdev->ulp_iscsi);
  589. return;
  590. }
  591. err = tdev->ctl(tdev, ULP_ISCSI_GET_PARAMS, &uinfo);
  592. if (err < 0) {
  593. ddp_log_error("%s, failed to get iscsi param err=%d.\n",
  594. tdev->name, err);
  595. return;
  596. }
  597. ppmax = (uinfo.ulimit - uinfo.llimit + 1) >> PPOD_SIZE_SHIFT;
  598. bits = __ilog2_u32(ppmax) + 1;
  599. if (bits > PPOD_IDX_MAX_SIZE)
  600. bits = PPOD_IDX_MAX_SIZE;
  601. ppmax = (1 << (bits - 1)) - 1;
  602. ddp = cxgb3i_alloc_big_mem(sizeof(struct cxgb3i_ddp_info) +
  603. ppmax *
  604. (sizeof(struct cxgb3i_gather_list *) +
  605. sizeof(struct sk_buff *)),
  606. GFP_KERNEL);
  607. if (!ddp) {
  608. ddp_log_warn("%s unable to alloc ddp 0x%d, ddp disabled.\n",
  609. tdev->name, ppmax);
  610. return;
  611. }
  612. ddp->gl_map = (struct cxgb3i_gather_list **)(ddp + 1);
  613. ddp->gl_skb = (struct sk_buff **)(((char *)ddp->gl_map) +
  614. ppmax *
  615. sizeof(struct cxgb3i_gather_list *));
  616. spin_lock_init(&ddp->map_lock);
  617. kref_init(&ddp->refcnt);
  618. ddp->tdev = tdev;
  619. ddp->pdev = uinfo.pdev;
  620. ddp->max_txsz = min_t(unsigned int, uinfo.max_txsz, ULP2_MAX_PKT_SIZE);
  621. ddp->max_rxsz = min_t(unsigned int, uinfo.max_rxsz, ULP2_MAX_PKT_SIZE);
  622. ddp->llimit = uinfo.llimit;
  623. ddp->ulimit = uinfo.ulimit;
  624. ddp->nppods = ppmax;
  625. ddp->idx_last = ppmax;
  626. ddp->idx_bits = bits;
  627. ddp->idx_mask = (1 << bits) - 1;
  628. ddp->rsvd_tag_mask = (1 << (bits + PPOD_IDX_SHIFT)) - 1;
  629. uinfo.tagmask = ddp->idx_mask << PPOD_IDX_SHIFT;
  630. for (i = 0; i < DDP_PGIDX_MAX; i++)
  631. uinfo.pgsz_factor[i] = ddp_page_order[i];
  632. uinfo.ulimit = uinfo.llimit + (ppmax << PPOD_SIZE_SHIFT);
  633. err = tdev->ctl(tdev, ULP_ISCSI_SET_PARAMS, &uinfo);
  634. if (err < 0) {
  635. ddp_log_warn("%s unable to set iscsi param err=%d, "
  636. "ddp disabled.\n", tdev->name, err);
  637. goto free_ddp_map;
  638. }
  639. tdev->ulp_iscsi = ddp;
  640. ddp_log_info("tdev 0x%p, nppods %u, bits %u, mask 0x%x,0x%x pkt %u/%u,"
  641. " %u/%u.\n",
  642. tdev, ppmax, ddp->idx_bits, ddp->idx_mask,
  643. ddp->rsvd_tag_mask, ddp->max_txsz, uinfo.max_txsz,
  644. ddp->max_rxsz, uinfo.max_rxsz);
  645. return;
  646. free_ddp_map:
  647. cxgb3i_free_big_mem(ddp);
  648. }
  649. /**
  650. * cxgb3i_ddp_init - initialize ddp functions
  651. */
  652. void cxgb3i_ddp_init(struct t3cdev *tdev)
  653. {
  654. if (page_idx == DDP_PGIDX_MAX) {
  655. page_idx = cxgb3i_ddp_find_page_index(PAGE_SIZE);
  656. if (page_idx == DDP_PGIDX_MAX) {
  657. ddp_log_info("system PAGE_SIZE %lu, update hw.\n",
  658. PAGE_SIZE);
  659. if (cxgb3i_ddp_adjust_page_table() < 0) {
  660. ddp_log_info("PAGE_SIZE %lu, ddp disabled.\n",
  661. PAGE_SIZE);
  662. return;
  663. }
  664. page_idx = cxgb3i_ddp_find_page_index(PAGE_SIZE);
  665. }
  666. ddp_log_info("system PAGE_SIZE %lu, ddp idx %u.\n",
  667. PAGE_SIZE, page_idx);
  668. }
  669. ddp_init(tdev);
  670. }