aic7xxx_core.c 212 KB

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  1. /*
  2. * Core routines and tables shareable across OS platforms.
  3. *
  4. * Copyright (c) 1994-2002 Justin T. Gibbs.
  5. * Copyright (c) 2000-2002 Adaptec Inc.
  6. * All rights reserved.
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions, and the following disclaimer,
  13. * without modification.
  14. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15. * substantially similar to the "NO WARRANTY" disclaimer below
  16. * ("Disclaimer") and any redistribution must be conditioned upon
  17. * including a substantially similar Disclaimer requirement for further
  18. * binary redistribution.
  19. * 3. Neither the names of the above-listed copyright holders nor the names
  20. * of any contributors may be used to endorse or promote products derived
  21. * from this software without specific prior written permission.
  22. *
  23. * Alternatively, this software may be distributed under the terms of the
  24. * GNU General Public License ("GPL") version 2 as published by the Free
  25. * Software Foundation.
  26. *
  27. * NO WARRANTY
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGES.
  39. *
  40. * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
  41. */
  42. #ifdef __linux__
  43. #include "aic7xxx_osm.h"
  44. #include "aic7xxx_inline.h"
  45. #include "aicasm/aicasm_insformat.h"
  46. #else
  47. #include <dev/aic7xxx/aic7xxx_osm.h>
  48. #include <dev/aic7xxx/aic7xxx_inline.h>
  49. #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
  50. #endif
  51. /***************************** Lookup Tables **********************************/
  52. static const char *const ahc_chip_names[] = {
  53. "NONE",
  54. "aic7770",
  55. "aic7850",
  56. "aic7855",
  57. "aic7859",
  58. "aic7860",
  59. "aic7870",
  60. "aic7880",
  61. "aic7895",
  62. "aic7895C",
  63. "aic7890/91",
  64. "aic7896/97",
  65. "aic7892",
  66. "aic7899"
  67. };
  68. static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names);
  69. /*
  70. * Hardware error codes.
  71. */
  72. struct ahc_hard_error_entry {
  73. uint8_t errno;
  74. const char *errmesg;
  75. };
  76. static const struct ahc_hard_error_entry ahc_hard_errors[] = {
  77. { ILLHADDR, "Illegal Host Access" },
  78. { ILLSADDR, "Illegal Sequencer Address referrenced" },
  79. { ILLOPCODE, "Illegal Opcode in sequencer program" },
  80. { SQPARERR, "Sequencer Parity Error" },
  81. { DPARERR, "Data-path Parity Error" },
  82. { MPARERR, "Scratch or SCB Memory Parity Error" },
  83. { PCIERRSTAT, "PCI Error detected" },
  84. { CIOPARERR, "CIOBUS Parity Error" },
  85. };
  86. static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
  87. static const struct ahc_phase_table_entry ahc_phase_table[] =
  88. {
  89. { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
  90. { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
  91. { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
  92. { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
  93. { P_COMMAND, MSG_NOOP, "in Command phase" },
  94. { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
  95. { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
  96. { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
  97. { P_BUSFREE, MSG_NOOP, "while idle" },
  98. { 0, MSG_NOOP, "in unknown phase" }
  99. };
  100. /*
  101. * In most cases we only wish to itterate over real phases, so
  102. * exclude the last element from the count.
  103. */
  104. static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
  105. /*
  106. * Valid SCSIRATE values. (p. 3-17)
  107. * Provides a mapping of tranfer periods in ns to the proper value to
  108. * stick in the scsixfer reg.
  109. */
  110. static const struct ahc_syncrate ahc_syncrates[] =
  111. {
  112. /* ultra2 fast/ultra period rate */
  113. { 0x42, 0x000, 9, "80.0" },
  114. { 0x03, 0x000, 10, "40.0" },
  115. { 0x04, 0x000, 11, "33.0" },
  116. { 0x05, 0x100, 12, "20.0" },
  117. { 0x06, 0x110, 15, "16.0" },
  118. { 0x07, 0x120, 18, "13.4" },
  119. { 0x08, 0x000, 25, "10.0" },
  120. { 0x19, 0x010, 31, "8.0" },
  121. { 0x1a, 0x020, 37, "6.67" },
  122. { 0x1b, 0x030, 43, "5.7" },
  123. { 0x1c, 0x040, 50, "5.0" },
  124. { 0x00, 0x050, 56, "4.4" },
  125. { 0x00, 0x060, 62, "4.0" },
  126. { 0x00, 0x070, 68, "3.6" },
  127. { 0x00, 0x000, 0, NULL }
  128. };
  129. /* Our Sequencer Program */
  130. #include "aic7xxx_seq.h"
  131. /**************************** Function Declarations ***************************/
  132. static void ahc_force_renegotiation(struct ahc_softc *ahc,
  133. struct ahc_devinfo *devinfo);
  134. static struct ahc_tmode_tstate*
  135. ahc_alloc_tstate(struct ahc_softc *ahc,
  136. u_int scsi_id, char channel);
  137. #ifdef AHC_TARGET_MODE
  138. static void ahc_free_tstate(struct ahc_softc *ahc,
  139. u_int scsi_id, char channel, int force);
  140. #endif
  141. static const struct ahc_syncrate*
  142. ahc_devlimited_syncrate(struct ahc_softc *ahc,
  143. struct ahc_initiator_tinfo *,
  144. u_int *period,
  145. u_int *ppr_options,
  146. role_t role);
  147. static void ahc_update_pending_scbs(struct ahc_softc *ahc);
  148. static void ahc_fetch_devinfo(struct ahc_softc *ahc,
  149. struct ahc_devinfo *devinfo);
  150. static void ahc_scb_devinfo(struct ahc_softc *ahc,
  151. struct ahc_devinfo *devinfo,
  152. struct scb *scb);
  153. static void ahc_assert_atn(struct ahc_softc *ahc);
  154. static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
  155. struct ahc_devinfo *devinfo,
  156. struct scb *scb);
  157. static void ahc_build_transfer_msg(struct ahc_softc *ahc,
  158. struct ahc_devinfo *devinfo);
  159. static void ahc_construct_sdtr(struct ahc_softc *ahc,
  160. struct ahc_devinfo *devinfo,
  161. u_int period, u_int offset);
  162. static void ahc_construct_wdtr(struct ahc_softc *ahc,
  163. struct ahc_devinfo *devinfo,
  164. u_int bus_width);
  165. static void ahc_construct_ppr(struct ahc_softc *ahc,
  166. struct ahc_devinfo *devinfo,
  167. u_int period, u_int offset,
  168. u_int bus_width, u_int ppr_options);
  169. static void ahc_clear_msg_state(struct ahc_softc *ahc);
  170. static void ahc_handle_proto_violation(struct ahc_softc *ahc);
  171. static void ahc_handle_message_phase(struct ahc_softc *ahc);
  172. typedef enum {
  173. AHCMSG_1B,
  174. AHCMSG_2B,
  175. AHCMSG_EXT
  176. } ahc_msgtype;
  177. static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
  178. u_int msgval, int full);
  179. static int ahc_parse_msg(struct ahc_softc *ahc,
  180. struct ahc_devinfo *devinfo);
  181. static int ahc_handle_msg_reject(struct ahc_softc *ahc,
  182. struct ahc_devinfo *devinfo);
  183. static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
  184. struct ahc_devinfo *devinfo);
  185. static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
  186. static void ahc_handle_devreset(struct ahc_softc *ahc,
  187. struct ahc_devinfo *devinfo,
  188. cam_status status, char *message,
  189. int verbose_level);
  190. #ifdef AHC_TARGET_MODE
  191. static void ahc_setup_target_msgin(struct ahc_softc *ahc,
  192. struct ahc_devinfo *devinfo,
  193. struct scb *scb);
  194. #endif
  195. static bus_dmamap_callback_t ahc_dmamap_cb;
  196. static void ahc_build_free_scb_list(struct ahc_softc *ahc);
  197. static int ahc_init_scbdata(struct ahc_softc *ahc);
  198. static void ahc_fini_scbdata(struct ahc_softc *ahc);
  199. static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
  200. struct scb *prev_scb,
  201. struct scb *scb);
  202. static int ahc_qinfifo_count(struct ahc_softc *ahc);
  203. static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
  204. u_int prev, u_int scbptr);
  205. static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
  206. static u_int ahc_rem_wscb(struct ahc_softc *ahc,
  207. u_int scbpos, u_int prev);
  208. static void ahc_reset_current_bus(struct ahc_softc *ahc);
  209. #ifdef AHC_DUMP_SEQ
  210. static void ahc_dumpseq(struct ahc_softc *ahc);
  211. #endif
  212. static int ahc_loadseq(struct ahc_softc *ahc);
  213. static int ahc_check_patch(struct ahc_softc *ahc,
  214. const struct patch **start_patch,
  215. u_int start_instr, u_int *skip_addr);
  216. static void ahc_download_instr(struct ahc_softc *ahc,
  217. u_int instrptr, uint8_t *dconsts);
  218. #ifdef AHC_TARGET_MODE
  219. static void ahc_queue_lstate_event(struct ahc_softc *ahc,
  220. struct ahc_tmode_lstate *lstate,
  221. u_int initiator_id,
  222. u_int event_type,
  223. u_int event_arg);
  224. static void ahc_update_scsiid(struct ahc_softc *ahc,
  225. u_int targid_mask);
  226. static int ahc_handle_target_cmd(struct ahc_softc *ahc,
  227. struct target_cmd *cmd);
  228. #endif
  229. static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
  230. static void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
  231. static void ahc_busy_tcl(struct ahc_softc *ahc,
  232. u_int tcl, u_int busyid);
  233. /************************** SCB and SCB queue management **********************/
  234. static void ahc_run_untagged_queues(struct ahc_softc *ahc);
  235. static void ahc_run_untagged_queue(struct ahc_softc *ahc,
  236. struct scb_tailq *queue);
  237. /****************************** Initialization ********************************/
  238. static void ahc_alloc_scbs(struct ahc_softc *ahc);
  239. static void ahc_shutdown(void *arg);
  240. /*************************** Interrupt Services *******************************/
  241. static void ahc_clear_intstat(struct ahc_softc *ahc);
  242. static void ahc_run_qoutfifo(struct ahc_softc *ahc);
  243. #ifdef AHC_TARGET_MODE
  244. static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
  245. #endif
  246. static void ahc_handle_brkadrint(struct ahc_softc *ahc);
  247. static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
  248. static void ahc_handle_scsiint(struct ahc_softc *ahc,
  249. u_int intstat);
  250. static void ahc_clear_critical_section(struct ahc_softc *ahc);
  251. /***************************** Error Recovery *********************************/
  252. static void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
  253. static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
  254. char channel, int lun, u_int tag,
  255. role_t role, uint32_t status);
  256. static void ahc_calc_residual(struct ahc_softc *ahc,
  257. struct scb *scb);
  258. /*********************** Untagged Transaction Routines ************************/
  259. static inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
  260. static inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
  261. /*
  262. * Block our completion routine from starting the next untagged
  263. * transaction for this target or target lun.
  264. */
  265. static inline void
  266. ahc_freeze_untagged_queues(struct ahc_softc *ahc)
  267. {
  268. if ((ahc->flags & AHC_SCB_BTT) == 0)
  269. ahc->untagged_queue_lock++;
  270. }
  271. /*
  272. * Allow the next untagged transaction for this target or target lun
  273. * to be executed. We use a counting semaphore to allow the lock
  274. * to be acquired recursively. Once the count drops to zero, the
  275. * transaction queues will be run.
  276. */
  277. static inline void
  278. ahc_release_untagged_queues(struct ahc_softc *ahc)
  279. {
  280. if ((ahc->flags & AHC_SCB_BTT) == 0) {
  281. ahc->untagged_queue_lock--;
  282. if (ahc->untagged_queue_lock == 0)
  283. ahc_run_untagged_queues(ahc);
  284. }
  285. }
  286. /************************* Sequencer Execution Control ************************/
  287. /*
  288. * Work around any chip bugs related to halting sequencer execution.
  289. * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
  290. * reading a register that will set this signal and deassert it.
  291. * Without this workaround, if the chip is paused, by an interrupt or
  292. * manual pause while accessing scb ram, accesses to certain registers
  293. * will hang the system (infinite pci retries).
  294. */
  295. static void
  296. ahc_pause_bug_fix(struct ahc_softc *ahc)
  297. {
  298. if ((ahc->features & AHC_ULTRA2) != 0)
  299. (void)ahc_inb(ahc, CCSCBCTL);
  300. }
  301. /*
  302. * Determine whether the sequencer has halted code execution.
  303. * Returns non-zero status if the sequencer is stopped.
  304. */
  305. int
  306. ahc_is_paused(struct ahc_softc *ahc)
  307. {
  308. return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
  309. }
  310. /*
  311. * Request that the sequencer stop and wait, indefinitely, for it
  312. * to stop. The sequencer will only acknowledge that it is paused
  313. * once it has reached an instruction boundary and PAUSEDIS is
  314. * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
  315. * for critical sections.
  316. */
  317. void
  318. ahc_pause(struct ahc_softc *ahc)
  319. {
  320. ahc_outb(ahc, HCNTRL, ahc->pause);
  321. /*
  322. * Since the sequencer can disable pausing in a critical section, we
  323. * must loop until it actually stops.
  324. */
  325. while (ahc_is_paused(ahc) == 0)
  326. ;
  327. ahc_pause_bug_fix(ahc);
  328. }
  329. /*
  330. * Allow the sequencer to continue program execution.
  331. * We check here to ensure that no additional interrupt
  332. * sources that would cause the sequencer to halt have been
  333. * asserted. If, for example, a SCSI bus reset is detected
  334. * while we are fielding a different, pausing, interrupt type,
  335. * we don't want to release the sequencer before going back
  336. * into our interrupt handler and dealing with this new
  337. * condition.
  338. */
  339. void
  340. ahc_unpause(struct ahc_softc *ahc)
  341. {
  342. if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
  343. ahc_outb(ahc, HCNTRL, ahc->unpause);
  344. }
  345. /************************** Memory mapping routines ***************************/
  346. static struct ahc_dma_seg *
  347. ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
  348. {
  349. int sg_index;
  350. sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
  351. /* sg_list_phys points to entry 1, not 0 */
  352. sg_index++;
  353. return (&scb->sg_list[sg_index]);
  354. }
  355. static uint32_t
  356. ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
  357. {
  358. int sg_index;
  359. /* sg_list_phys points to entry 1, not 0 */
  360. sg_index = sg - &scb->sg_list[1];
  361. return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
  362. }
  363. static uint32_t
  364. ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
  365. {
  366. return (ahc->scb_data->hscb_busaddr
  367. + (sizeof(struct hardware_scb) * index));
  368. }
  369. static void
  370. ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
  371. {
  372. ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
  373. ahc->scb_data->hscb_dmamap,
  374. /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
  375. /*len*/sizeof(*scb->hscb), op);
  376. }
  377. void
  378. ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
  379. {
  380. if (scb->sg_count == 0)
  381. return;
  382. ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
  383. /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
  384. * sizeof(struct ahc_dma_seg),
  385. /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
  386. }
  387. #ifdef AHC_TARGET_MODE
  388. static uint32_t
  389. ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
  390. {
  391. return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
  392. }
  393. #endif
  394. /*********************** Miscelaneous Support Functions ***********************/
  395. /*
  396. * Determine whether the sequencer reported a residual
  397. * for this SCB/transaction.
  398. */
  399. static void
  400. ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
  401. {
  402. uint32_t sgptr;
  403. sgptr = ahc_le32toh(scb->hscb->sgptr);
  404. if ((sgptr & SG_RESID_VALID) != 0)
  405. ahc_calc_residual(ahc, scb);
  406. }
  407. /*
  408. * Return pointers to the transfer negotiation information
  409. * for the specified our_id/remote_id pair.
  410. */
  411. struct ahc_initiator_tinfo *
  412. ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
  413. u_int remote_id, struct ahc_tmode_tstate **tstate)
  414. {
  415. /*
  416. * Transfer data structures are stored from the perspective
  417. * of the target role. Since the parameters for a connection
  418. * in the initiator role to a given target are the same as
  419. * when the roles are reversed, we pretend we are the target.
  420. */
  421. if (channel == 'B')
  422. our_id += 8;
  423. *tstate = ahc->enabled_targets[our_id];
  424. return (&(*tstate)->transinfo[remote_id]);
  425. }
  426. uint16_t
  427. ahc_inw(struct ahc_softc *ahc, u_int port)
  428. {
  429. uint16_t r = ahc_inb(ahc, port+1) << 8;
  430. return r | ahc_inb(ahc, port);
  431. }
  432. void
  433. ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
  434. {
  435. ahc_outb(ahc, port, value & 0xFF);
  436. ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
  437. }
  438. uint32_t
  439. ahc_inl(struct ahc_softc *ahc, u_int port)
  440. {
  441. return ((ahc_inb(ahc, port))
  442. | (ahc_inb(ahc, port+1) << 8)
  443. | (ahc_inb(ahc, port+2) << 16)
  444. | (ahc_inb(ahc, port+3) << 24));
  445. }
  446. void
  447. ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
  448. {
  449. ahc_outb(ahc, port, (value) & 0xFF);
  450. ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
  451. ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
  452. ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
  453. }
  454. uint64_t
  455. ahc_inq(struct ahc_softc *ahc, u_int port)
  456. {
  457. return ((ahc_inb(ahc, port))
  458. | (ahc_inb(ahc, port+1) << 8)
  459. | (ahc_inb(ahc, port+2) << 16)
  460. | (ahc_inb(ahc, port+3) << 24)
  461. | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
  462. | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
  463. | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
  464. | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
  465. }
  466. void
  467. ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
  468. {
  469. ahc_outb(ahc, port, value & 0xFF);
  470. ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
  471. ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
  472. ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
  473. ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
  474. ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
  475. ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
  476. ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
  477. }
  478. /*
  479. * Get a free scb. If there are none, see if we can allocate a new SCB.
  480. */
  481. struct scb *
  482. ahc_get_scb(struct ahc_softc *ahc)
  483. {
  484. struct scb *scb;
  485. if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
  486. ahc_alloc_scbs(ahc);
  487. scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
  488. if (scb == NULL)
  489. return (NULL);
  490. }
  491. SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
  492. return (scb);
  493. }
  494. /*
  495. * Return an SCB resource to the free list.
  496. */
  497. void
  498. ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
  499. {
  500. struct hardware_scb *hscb;
  501. hscb = scb->hscb;
  502. /* Clean up for the next user */
  503. ahc->scb_data->scbindex[hscb->tag] = NULL;
  504. scb->flags = SCB_FREE;
  505. hscb->control = 0;
  506. SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
  507. /* Notify the OSM that a resource is now available. */
  508. ahc_platform_scb_free(ahc, scb);
  509. }
  510. struct scb *
  511. ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
  512. {
  513. struct scb* scb;
  514. scb = ahc->scb_data->scbindex[tag];
  515. if (scb != NULL)
  516. ahc_sync_scb(ahc, scb,
  517. BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  518. return (scb);
  519. }
  520. static void
  521. ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
  522. {
  523. struct hardware_scb *q_hscb;
  524. u_int saved_tag;
  525. /*
  526. * Our queuing method is a bit tricky. The card
  527. * knows in advance which HSCB to download, and we
  528. * can't disappoint it. To achieve this, the next
  529. * SCB to download is saved off in ahc->next_queued_scb.
  530. * When we are called to queue "an arbitrary scb",
  531. * we copy the contents of the incoming HSCB to the one
  532. * the sequencer knows about, swap HSCB pointers and
  533. * finally assign the SCB to the tag indexed location
  534. * in the scb_array. This makes sure that we can still
  535. * locate the correct SCB by SCB_TAG.
  536. */
  537. q_hscb = ahc->next_queued_scb->hscb;
  538. saved_tag = q_hscb->tag;
  539. memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
  540. if ((scb->flags & SCB_CDB32_PTR) != 0) {
  541. q_hscb->shared_data.cdb_ptr =
  542. ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
  543. + offsetof(struct hardware_scb, cdb32));
  544. }
  545. q_hscb->tag = saved_tag;
  546. q_hscb->next = scb->hscb->tag;
  547. /* Now swap HSCB pointers. */
  548. ahc->next_queued_scb->hscb = scb->hscb;
  549. scb->hscb = q_hscb;
  550. /* Now define the mapping from tag to SCB in the scbindex */
  551. ahc->scb_data->scbindex[scb->hscb->tag] = scb;
  552. }
  553. /*
  554. * Tell the sequencer about a new transaction to execute.
  555. */
  556. void
  557. ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
  558. {
  559. ahc_swap_with_next_hscb(ahc, scb);
  560. if (scb->hscb->tag == SCB_LIST_NULL
  561. || scb->hscb->next == SCB_LIST_NULL)
  562. panic("Attempt to queue invalid SCB tag %x:%x\n",
  563. scb->hscb->tag, scb->hscb->next);
  564. /*
  565. * Setup data "oddness".
  566. */
  567. scb->hscb->lun &= LID;
  568. if (ahc_get_transfer_length(scb) & 0x1)
  569. scb->hscb->lun |= SCB_XFERLEN_ODD;
  570. /*
  571. * Keep a history of SCBs we've downloaded in the qinfifo.
  572. */
  573. ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
  574. /*
  575. * Make sure our data is consistent from the
  576. * perspective of the adapter.
  577. */
  578. ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  579. /* Tell the adapter about the newly queued SCB */
  580. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  581. ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
  582. } else {
  583. if ((ahc->features & AHC_AUTOPAUSE) == 0)
  584. ahc_pause(ahc);
  585. ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
  586. if ((ahc->features & AHC_AUTOPAUSE) == 0)
  587. ahc_unpause(ahc);
  588. }
  589. }
  590. struct scsi_sense_data *
  591. ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
  592. {
  593. int offset;
  594. offset = scb - ahc->scb_data->scbarray;
  595. return (&ahc->scb_data->sense[offset]);
  596. }
  597. static uint32_t
  598. ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
  599. {
  600. int offset;
  601. offset = scb - ahc->scb_data->scbarray;
  602. return (ahc->scb_data->sense_busaddr
  603. + (offset * sizeof(struct scsi_sense_data)));
  604. }
  605. /************************** Interrupt Processing ******************************/
  606. static void
  607. ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
  608. {
  609. ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
  610. /*offset*/0, /*len*/256, op);
  611. }
  612. static void
  613. ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
  614. {
  615. #ifdef AHC_TARGET_MODE
  616. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  617. ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
  618. ahc->shared_data_dmamap,
  619. ahc_targetcmd_offset(ahc, 0),
  620. sizeof(struct target_cmd) * AHC_TMODE_CMDS,
  621. op);
  622. }
  623. #endif
  624. }
  625. /*
  626. * See if the firmware has posted any completed commands
  627. * into our in-core command complete fifos.
  628. */
  629. #define AHC_RUN_QOUTFIFO 0x1
  630. #define AHC_RUN_TQINFIFO 0x2
  631. static u_int
  632. ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
  633. {
  634. u_int retval;
  635. retval = 0;
  636. ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
  637. /*offset*/ahc->qoutfifonext, /*len*/1,
  638. BUS_DMASYNC_POSTREAD);
  639. if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
  640. retval |= AHC_RUN_QOUTFIFO;
  641. #ifdef AHC_TARGET_MODE
  642. if ((ahc->flags & AHC_TARGETROLE) != 0
  643. && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
  644. ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
  645. ahc->shared_data_dmamap,
  646. ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
  647. /*len*/sizeof(struct target_cmd),
  648. BUS_DMASYNC_POSTREAD);
  649. if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
  650. retval |= AHC_RUN_TQINFIFO;
  651. }
  652. #endif
  653. return (retval);
  654. }
  655. /*
  656. * Catch an interrupt from the adapter
  657. */
  658. int
  659. ahc_intr(struct ahc_softc *ahc)
  660. {
  661. u_int intstat;
  662. if ((ahc->pause & INTEN) == 0) {
  663. /*
  664. * Our interrupt is not enabled on the chip
  665. * and may be disabled for re-entrancy reasons,
  666. * so just return. This is likely just a shared
  667. * interrupt.
  668. */
  669. return (0);
  670. }
  671. /*
  672. * Instead of directly reading the interrupt status register,
  673. * infer the cause of the interrupt by checking our in-core
  674. * completion queues. This avoids a costly PCI bus read in
  675. * most cases.
  676. */
  677. if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
  678. && (ahc_check_cmdcmpltqueues(ahc) != 0))
  679. intstat = CMDCMPLT;
  680. else {
  681. intstat = ahc_inb(ahc, INTSTAT);
  682. }
  683. if ((intstat & INT_PEND) == 0) {
  684. #if AHC_PCI_CONFIG > 0
  685. if (ahc->unsolicited_ints > 500) {
  686. ahc->unsolicited_ints = 0;
  687. if ((ahc->chip & AHC_PCI) != 0
  688. && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
  689. ahc->bus_intr(ahc);
  690. }
  691. #endif
  692. ahc->unsolicited_ints++;
  693. return (0);
  694. }
  695. ahc->unsolicited_ints = 0;
  696. if (intstat & CMDCMPLT) {
  697. ahc_outb(ahc, CLRINT, CLRCMDINT);
  698. /*
  699. * Ensure that the chip sees that we've cleared
  700. * this interrupt before we walk the output fifo.
  701. * Otherwise, we may, due to posted bus writes,
  702. * clear the interrupt after we finish the scan,
  703. * and after the sequencer has added new entries
  704. * and asserted the interrupt again.
  705. */
  706. ahc_flush_device_writes(ahc);
  707. ahc_run_qoutfifo(ahc);
  708. #ifdef AHC_TARGET_MODE
  709. if ((ahc->flags & AHC_TARGETROLE) != 0)
  710. ahc_run_tqinfifo(ahc, /*paused*/FALSE);
  711. #endif
  712. }
  713. /*
  714. * Handle statuses that may invalidate our cached
  715. * copy of INTSTAT separately.
  716. */
  717. if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
  718. /* Hot eject. Do nothing */
  719. } else if (intstat & BRKADRINT) {
  720. ahc_handle_brkadrint(ahc);
  721. } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
  722. ahc_pause_bug_fix(ahc);
  723. if ((intstat & SEQINT) != 0)
  724. ahc_handle_seqint(ahc, intstat);
  725. if ((intstat & SCSIINT) != 0)
  726. ahc_handle_scsiint(ahc, intstat);
  727. }
  728. return (1);
  729. }
  730. /************************* Sequencer Execution Control ************************/
  731. /*
  732. * Restart the sequencer program from address zero
  733. */
  734. static void
  735. ahc_restart(struct ahc_softc *ahc)
  736. {
  737. uint8_t sblkctl;
  738. ahc_pause(ahc);
  739. /* No more pending messages. */
  740. ahc_clear_msg_state(ahc);
  741. ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
  742. ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
  743. ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
  744. ahc_outb(ahc, LASTPHASE, P_BUSFREE);
  745. ahc_outb(ahc, SAVED_SCSIID, 0xFF);
  746. ahc_outb(ahc, SAVED_LUN, 0xFF);
  747. /*
  748. * Ensure that the sequencer's idea of TQINPOS
  749. * matches our own. The sequencer increments TQINPOS
  750. * only after it sees a DMA complete and a reset could
  751. * occur before the increment leaving the kernel to believe
  752. * the command arrived but the sequencer to not.
  753. */
  754. ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
  755. /* Always allow reselection */
  756. ahc_outb(ahc, SCSISEQ,
  757. ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
  758. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  759. /* Ensure that no DMA operations are in progress */
  760. ahc_outb(ahc, CCSCBCNT, 0);
  761. ahc_outb(ahc, CCSGCTL, 0);
  762. ahc_outb(ahc, CCSCBCTL, 0);
  763. }
  764. /*
  765. * If we were in the process of DMA'ing SCB data into
  766. * an SCB, replace that SCB on the free list. This prevents
  767. * an SCB leak.
  768. */
  769. if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
  770. ahc_add_curscb_to_free_list(ahc);
  771. ahc_outb(ahc, SEQ_FLAGS2,
  772. ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
  773. }
  774. /*
  775. * Clear any pending sequencer interrupt. It is no
  776. * longer relevant since we're resetting the Program
  777. * Counter.
  778. */
  779. ahc_outb(ahc, CLRINT, CLRSEQINT);
  780. ahc_outb(ahc, MWI_RESIDUAL, 0);
  781. ahc_outb(ahc, SEQCTL, ahc->seqctl);
  782. ahc_outb(ahc, SEQADDR0, 0);
  783. ahc_outb(ahc, SEQADDR1, 0);
  784. /*
  785. * Take the LED out of diagnostic mode on PM resume, too
  786. */
  787. sblkctl = ahc_inb(ahc, SBLKCTL);
  788. ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
  789. ahc_unpause(ahc);
  790. }
  791. /************************* Input/Output Queues ********************************/
  792. static void
  793. ahc_run_qoutfifo(struct ahc_softc *ahc)
  794. {
  795. struct scb *scb;
  796. u_int scb_index;
  797. ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
  798. while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
  799. scb_index = ahc->qoutfifo[ahc->qoutfifonext];
  800. if ((ahc->qoutfifonext & 0x03) == 0x03) {
  801. u_int modnext;
  802. /*
  803. * Clear 32bits of QOUTFIFO at a time
  804. * so that we don't clobber an incoming
  805. * byte DMA to the array on architectures
  806. * that only support 32bit load and store
  807. * operations.
  808. */
  809. modnext = ahc->qoutfifonext & ~0x3;
  810. *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
  811. ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
  812. ahc->shared_data_dmamap,
  813. /*offset*/modnext, /*len*/4,
  814. BUS_DMASYNC_PREREAD);
  815. }
  816. ahc->qoutfifonext++;
  817. scb = ahc_lookup_scb(ahc, scb_index);
  818. if (scb == NULL) {
  819. printf("%s: WARNING no command for scb %d "
  820. "(cmdcmplt)\nQOUTPOS = %d\n",
  821. ahc_name(ahc), scb_index,
  822. (ahc->qoutfifonext - 1) & 0xFF);
  823. continue;
  824. }
  825. /*
  826. * Save off the residual
  827. * if there is one.
  828. */
  829. ahc_update_residual(ahc, scb);
  830. ahc_done(ahc, scb);
  831. }
  832. }
  833. static void
  834. ahc_run_untagged_queues(struct ahc_softc *ahc)
  835. {
  836. int i;
  837. for (i = 0; i < 16; i++)
  838. ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
  839. }
  840. static void
  841. ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
  842. {
  843. struct scb *scb;
  844. if (ahc->untagged_queue_lock != 0)
  845. return;
  846. if ((scb = TAILQ_FIRST(queue)) != NULL
  847. && (scb->flags & SCB_ACTIVE) == 0) {
  848. scb->flags |= SCB_ACTIVE;
  849. ahc_queue_scb(ahc, scb);
  850. }
  851. }
  852. /************************* Interrupt Handling *********************************/
  853. static void
  854. ahc_handle_brkadrint(struct ahc_softc *ahc)
  855. {
  856. /*
  857. * We upset the sequencer :-(
  858. * Lookup the error message
  859. */
  860. int i;
  861. int error;
  862. error = ahc_inb(ahc, ERROR);
  863. for (i = 0; error != 1 && i < num_errors; i++)
  864. error >>= 1;
  865. printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
  866. ahc_name(ahc), ahc_hard_errors[i].errmesg,
  867. ahc_inb(ahc, SEQADDR0) |
  868. (ahc_inb(ahc, SEQADDR1) << 8));
  869. ahc_dump_card_state(ahc);
  870. /* Tell everyone that this HBA is no longer available */
  871. ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
  872. CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
  873. CAM_NO_HBA);
  874. /* Disable all interrupt sources by resetting the controller */
  875. ahc_shutdown(ahc);
  876. }
  877. static void
  878. ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
  879. {
  880. struct scb *scb;
  881. struct ahc_devinfo devinfo;
  882. ahc_fetch_devinfo(ahc, &devinfo);
  883. /*
  884. * Clear the upper byte that holds SEQINT status
  885. * codes and clear the SEQINT bit. We will unpause
  886. * the sequencer, if appropriate, after servicing
  887. * the request.
  888. */
  889. ahc_outb(ahc, CLRINT, CLRSEQINT);
  890. switch (intstat & SEQINT_MASK) {
  891. case BAD_STATUS:
  892. {
  893. u_int scb_index;
  894. struct hardware_scb *hscb;
  895. /*
  896. * Set the default return value to 0 (don't
  897. * send sense). The sense code will change
  898. * this if needed.
  899. */
  900. ahc_outb(ahc, RETURN_1, 0);
  901. /*
  902. * The sequencer will notify us when a command
  903. * has an error that would be of interest to
  904. * the kernel. This allows us to leave the sequencer
  905. * running in the common case of command completes
  906. * without error. The sequencer will already have
  907. * dma'd the SCB back up to us, so we can reference
  908. * the in kernel copy directly.
  909. */
  910. scb_index = ahc_inb(ahc, SCB_TAG);
  911. scb = ahc_lookup_scb(ahc, scb_index);
  912. if (scb == NULL) {
  913. ahc_print_devinfo(ahc, &devinfo);
  914. printf("ahc_intr - referenced scb "
  915. "not valid during seqint 0x%x scb(%d)\n",
  916. intstat, scb_index);
  917. ahc_dump_card_state(ahc);
  918. panic("for safety");
  919. goto unpause;
  920. }
  921. hscb = scb->hscb;
  922. /* Don't want to clobber the original sense code */
  923. if ((scb->flags & SCB_SENSE) != 0) {
  924. /*
  925. * Clear the SCB_SENSE Flag and have
  926. * the sequencer do a normal command
  927. * complete.
  928. */
  929. scb->flags &= ~SCB_SENSE;
  930. ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
  931. break;
  932. }
  933. ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
  934. /* Freeze the queue until the client sees the error. */
  935. ahc_freeze_devq(ahc, scb);
  936. ahc_freeze_scb(scb);
  937. ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
  938. switch (hscb->shared_data.status.scsi_status) {
  939. case SCSI_STATUS_OK:
  940. printf("%s: Interrupted for staus of 0???\n",
  941. ahc_name(ahc));
  942. break;
  943. case SCSI_STATUS_CMD_TERMINATED:
  944. case SCSI_STATUS_CHECK_COND:
  945. {
  946. struct ahc_dma_seg *sg;
  947. struct scsi_sense *sc;
  948. struct ahc_initiator_tinfo *targ_info;
  949. struct ahc_tmode_tstate *tstate;
  950. struct ahc_transinfo *tinfo;
  951. #ifdef AHC_DEBUG
  952. if (ahc_debug & AHC_SHOW_SENSE) {
  953. ahc_print_path(ahc, scb);
  954. printf("SCB %d: requests Check Status\n",
  955. scb->hscb->tag);
  956. }
  957. #endif
  958. if (ahc_perform_autosense(scb) == 0)
  959. break;
  960. targ_info = ahc_fetch_transinfo(ahc,
  961. devinfo.channel,
  962. devinfo.our_scsiid,
  963. devinfo.target,
  964. &tstate);
  965. tinfo = &targ_info->curr;
  966. sg = scb->sg_list;
  967. sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
  968. /*
  969. * Save off the residual if there is one.
  970. */
  971. ahc_update_residual(ahc, scb);
  972. #ifdef AHC_DEBUG
  973. if (ahc_debug & AHC_SHOW_SENSE) {
  974. ahc_print_path(ahc, scb);
  975. printf("Sending Sense\n");
  976. }
  977. #endif
  978. sg->addr = ahc_get_sense_bufaddr(ahc, scb);
  979. sg->len = ahc_get_sense_bufsize(ahc, scb);
  980. sg->len |= AHC_DMA_LAST_SEG;
  981. /* Fixup byte order */
  982. sg->addr = ahc_htole32(sg->addr);
  983. sg->len = ahc_htole32(sg->len);
  984. sc->opcode = REQUEST_SENSE;
  985. sc->byte2 = 0;
  986. if (tinfo->protocol_version <= SCSI_REV_2
  987. && SCB_GET_LUN(scb) < 8)
  988. sc->byte2 = SCB_GET_LUN(scb) << 5;
  989. sc->unused[0] = 0;
  990. sc->unused[1] = 0;
  991. sc->length = sg->len;
  992. sc->control = 0;
  993. /*
  994. * We can't allow the target to disconnect.
  995. * This will be an untagged transaction and
  996. * having the target disconnect will make this
  997. * transaction indestinguishable from outstanding
  998. * tagged transactions.
  999. */
  1000. hscb->control = 0;
  1001. /*
  1002. * This request sense could be because the
  1003. * the device lost power or in some other
  1004. * way has lost our transfer negotiations.
  1005. * Renegotiate if appropriate. Unit attention
  1006. * errors will be reported before any data
  1007. * phases occur.
  1008. */
  1009. if (ahc_get_residual(scb)
  1010. == ahc_get_transfer_length(scb)) {
  1011. ahc_update_neg_request(ahc, &devinfo,
  1012. tstate, targ_info,
  1013. AHC_NEG_IF_NON_ASYNC);
  1014. }
  1015. if (tstate->auto_negotiate & devinfo.target_mask) {
  1016. hscb->control |= MK_MESSAGE;
  1017. scb->flags &= ~SCB_NEGOTIATE;
  1018. scb->flags |= SCB_AUTO_NEGOTIATE;
  1019. }
  1020. hscb->cdb_len = sizeof(*sc);
  1021. hscb->dataptr = sg->addr;
  1022. hscb->datacnt = sg->len;
  1023. hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
  1024. hscb->sgptr = ahc_htole32(hscb->sgptr);
  1025. scb->sg_count = 1;
  1026. scb->flags |= SCB_SENSE;
  1027. ahc_qinfifo_requeue_tail(ahc, scb);
  1028. ahc_outb(ahc, RETURN_1, SEND_SENSE);
  1029. /*
  1030. * Ensure we have enough time to actually
  1031. * retrieve the sense.
  1032. */
  1033. ahc_scb_timer_reset(scb, 5 * 1000000);
  1034. break;
  1035. }
  1036. default:
  1037. break;
  1038. }
  1039. break;
  1040. }
  1041. case NO_MATCH:
  1042. {
  1043. /* Ensure we don't leave the selection hardware on */
  1044. ahc_outb(ahc, SCSISEQ,
  1045. ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
  1046. printf("%s:%c:%d: no active SCB for reconnecting "
  1047. "target - issuing BUS DEVICE RESET\n",
  1048. ahc_name(ahc), devinfo.channel, devinfo.target);
  1049. printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
  1050. "ARG_1 == 0x%x ACCUM = 0x%x\n",
  1051. ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
  1052. ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
  1053. printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
  1054. "SINDEX == 0x%x\n",
  1055. ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
  1056. ahc_index_busy_tcl(ahc,
  1057. BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
  1058. ahc_inb(ahc, SAVED_LUN))),
  1059. ahc_inb(ahc, SINDEX));
  1060. printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
  1061. "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
  1062. ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
  1063. ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
  1064. ahc_inb(ahc, SCB_CONTROL));
  1065. printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
  1066. ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
  1067. printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
  1068. printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
  1069. ahc_dump_card_state(ahc);
  1070. ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
  1071. ahc->msgout_len = 1;
  1072. ahc->msgout_index = 0;
  1073. ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  1074. ahc_outb(ahc, MSG_OUT, HOST_MSG);
  1075. ahc_assert_atn(ahc);
  1076. break;
  1077. }
  1078. case SEND_REJECT:
  1079. {
  1080. u_int rejbyte = ahc_inb(ahc, ACCUM);
  1081. printf("%s:%c:%d: Warning - unknown message received from "
  1082. "target (0x%x). Rejecting\n",
  1083. ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
  1084. break;
  1085. }
  1086. case PROTO_VIOLATION:
  1087. {
  1088. ahc_handle_proto_violation(ahc);
  1089. break;
  1090. }
  1091. case IGN_WIDE_RES:
  1092. ahc_handle_ign_wide_residue(ahc, &devinfo);
  1093. break;
  1094. case PDATA_REINIT:
  1095. ahc_reinitialize_dataptrs(ahc);
  1096. break;
  1097. case BAD_PHASE:
  1098. {
  1099. u_int lastphase;
  1100. lastphase = ahc_inb(ahc, LASTPHASE);
  1101. printf("%s:%c:%d: unknown scsi bus phase %x, "
  1102. "lastphase = 0x%x. Attempting to continue\n",
  1103. ahc_name(ahc), devinfo.channel, devinfo.target,
  1104. lastphase, ahc_inb(ahc, SCSISIGI));
  1105. break;
  1106. }
  1107. case MISSED_BUSFREE:
  1108. {
  1109. u_int lastphase;
  1110. lastphase = ahc_inb(ahc, LASTPHASE);
  1111. printf("%s:%c:%d: Missed busfree. "
  1112. "Lastphase = 0x%x, Curphase = 0x%x\n",
  1113. ahc_name(ahc), devinfo.channel, devinfo.target,
  1114. lastphase, ahc_inb(ahc, SCSISIGI));
  1115. ahc_restart(ahc);
  1116. return;
  1117. }
  1118. case HOST_MSG_LOOP:
  1119. {
  1120. /*
  1121. * The sequencer has encountered a message phase
  1122. * that requires host assistance for completion.
  1123. * While handling the message phase(s), we will be
  1124. * notified by the sequencer after each byte is
  1125. * transfered so we can track bus phase changes.
  1126. *
  1127. * If this is the first time we've seen a HOST_MSG_LOOP
  1128. * interrupt, initialize the state of the host message
  1129. * loop.
  1130. */
  1131. if (ahc->msg_type == MSG_TYPE_NONE) {
  1132. struct scb *scb;
  1133. u_int scb_index;
  1134. u_int bus_phase;
  1135. bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
  1136. if (bus_phase != P_MESGIN
  1137. && bus_phase != P_MESGOUT) {
  1138. printf("ahc_intr: HOST_MSG_LOOP bad "
  1139. "phase 0x%x\n",
  1140. bus_phase);
  1141. /*
  1142. * Probably transitioned to bus free before
  1143. * we got here. Just punt the message.
  1144. */
  1145. ahc_clear_intstat(ahc);
  1146. ahc_restart(ahc);
  1147. return;
  1148. }
  1149. scb_index = ahc_inb(ahc, SCB_TAG);
  1150. scb = ahc_lookup_scb(ahc, scb_index);
  1151. if (devinfo.role == ROLE_INITIATOR) {
  1152. if (bus_phase == P_MESGOUT) {
  1153. if (scb == NULL)
  1154. panic("HOST_MSG_LOOP with "
  1155. "invalid SCB %x\n",
  1156. scb_index);
  1157. ahc_setup_initiator_msgout(ahc,
  1158. &devinfo,
  1159. scb);
  1160. } else {
  1161. ahc->msg_type =
  1162. MSG_TYPE_INITIATOR_MSGIN;
  1163. ahc->msgin_index = 0;
  1164. }
  1165. }
  1166. #ifdef AHC_TARGET_MODE
  1167. else {
  1168. if (bus_phase == P_MESGOUT) {
  1169. ahc->msg_type =
  1170. MSG_TYPE_TARGET_MSGOUT;
  1171. ahc->msgin_index = 0;
  1172. }
  1173. else
  1174. ahc_setup_target_msgin(ahc,
  1175. &devinfo,
  1176. scb);
  1177. }
  1178. #endif
  1179. }
  1180. ahc_handle_message_phase(ahc);
  1181. break;
  1182. }
  1183. case PERR_DETECTED:
  1184. {
  1185. /*
  1186. * If we've cleared the parity error interrupt
  1187. * but the sequencer still believes that SCSIPERR
  1188. * is true, it must be that the parity error is
  1189. * for the currently presented byte on the bus,
  1190. * and we are not in a phase (data-in) where we will
  1191. * eventually ack this byte. Ack the byte and
  1192. * throw it away in the hope that the target will
  1193. * take us to message out to deliver the appropriate
  1194. * error message.
  1195. */
  1196. if ((intstat & SCSIINT) == 0
  1197. && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
  1198. if ((ahc->features & AHC_DT) == 0) {
  1199. u_int curphase;
  1200. /*
  1201. * The hardware will only let you ack bytes
  1202. * if the expected phase in SCSISIGO matches
  1203. * the current phase. Make sure this is
  1204. * currently the case.
  1205. */
  1206. curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
  1207. ahc_outb(ahc, LASTPHASE, curphase);
  1208. ahc_outb(ahc, SCSISIGO, curphase);
  1209. }
  1210. if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
  1211. int wait;
  1212. /*
  1213. * In a data phase. Faster to bitbucket
  1214. * the data than to individually ack each
  1215. * byte. This is also the only strategy
  1216. * that will work with AUTOACK enabled.
  1217. */
  1218. ahc_outb(ahc, SXFRCTL1,
  1219. ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
  1220. wait = 5000;
  1221. while (--wait != 0) {
  1222. if ((ahc_inb(ahc, SCSISIGI)
  1223. & (CDI|MSGI)) != 0)
  1224. break;
  1225. ahc_delay(100);
  1226. }
  1227. ahc_outb(ahc, SXFRCTL1,
  1228. ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
  1229. if (wait == 0) {
  1230. struct scb *scb;
  1231. u_int scb_index;
  1232. ahc_print_devinfo(ahc, &devinfo);
  1233. printf("Unable to clear parity error. "
  1234. "Resetting bus.\n");
  1235. scb_index = ahc_inb(ahc, SCB_TAG);
  1236. scb = ahc_lookup_scb(ahc, scb_index);
  1237. if (scb != NULL)
  1238. ahc_set_transaction_status(scb,
  1239. CAM_UNCOR_PARITY);
  1240. ahc_reset_channel(ahc, devinfo.channel,
  1241. /*init reset*/TRUE);
  1242. }
  1243. } else {
  1244. ahc_inb(ahc, SCSIDATL);
  1245. }
  1246. }
  1247. break;
  1248. }
  1249. case DATA_OVERRUN:
  1250. {
  1251. /*
  1252. * When the sequencer detects an overrun, it
  1253. * places the controller in "BITBUCKET" mode
  1254. * and allows the target to complete its transfer.
  1255. * Unfortunately, none of the counters get updated
  1256. * when the controller is in this mode, so we have
  1257. * no way of knowing how large the overrun was.
  1258. */
  1259. u_int scbindex = ahc_inb(ahc, SCB_TAG);
  1260. u_int lastphase = ahc_inb(ahc, LASTPHASE);
  1261. u_int i;
  1262. scb = ahc_lookup_scb(ahc, scbindex);
  1263. for (i = 0; i < num_phases; i++) {
  1264. if (lastphase == ahc_phase_table[i].phase)
  1265. break;
  1266. }
  1267. ahc_print_path(ahc, scb);
  1268. printf("data overrun detected %s."
  1269. " Tag == 0x%x.\n",
  1270. ahc_phase_table[i].phasemsg,
  1271. scb->hscb->tag);
  1272. ahc_print_path(ahc, scb);
  1273. printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
  1274. ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
  1275. ahc_get_transfer_length(scb), scb->sg_count);
  1276. if (scb->sg_count > 0) {
  1277. for (i = 0; i < scb->sg_count; i++) {
  1278. printf("sg[%d] - Addr 0x%x%x : Length %d\n",
  1279. i,
  1280. (ahc_le32toh(scb->sg_list[i].len) >> 24
  1281. & SG_HIGH_ADDR_BITS),
  1282. ahc_le32toh(scb->sg_list[i].addr),
  1283. ahc_le32toh(scb->sg_list[i].len)
  1284. & AHC_SG_LEN_MASK);
  1285. }
  1286. }
  1287. /*
  1288. * Set this and it will take effect when the
  1289. * target does a command complete.
  1290. */
  1291. ahc_freeze_devq(ahc, scb);
  1292. if ((scb->flags & SCB_SENSE) == 0) {
  1293. ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
  1294. } else {
  1295. scb->flags &= ~SCB_SENSE;
  1296. ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
  1297. }
  1298. ahc_freeze_scb(scb);
  1299. if ((ahc->features & AHC_ULTRA2) != 0) {
  1300. /*
  1301. * Clear the channel in case we return
  1302. * to data phase later.
  1303. */
  1304. ahc_outb(ahc, SXFRCTL0,
  1305. ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
  1306. ahc_outb(ahc, SXFRCTL0,
  1307. ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
  1308. }
  1309. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  1310. u_int dscommand1;
  1311. /* Ensure HHADDR is 0 for future DMA operations. */
  1312. dscommand1 = ahc_inb(ahc, DSCOMMAND1);
  1313. ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
  1314. ahc_outb(ahc, HADDR, 0);
  1315. ahc_outb(ahc, DSCOMMAND1, dscommand1);
  1316. }
  1317. break;
  1318. }
  1319. case MKMSG_FAILED:
  1320. {
  1321. u_int scbindex;
  1322. printf("%s:%c:%d:%d: Attempt to issue message failed\n",
  1323. ahc_name(ahc), devinfo.channel, devinfo.target,
  1324. devinfo.lun);
  1325. scbindex = ahc_inb(ahc, SCB_TAG);
  1326. scb = ahc_lookup_scb(ahc, scbindex);
  1327. if (scb != NULL
  1328. && (scb->flags & SCB_RECOVERY_SCB) != 0)
  1329. /*
  1330. * Ensure that we didn't put a second instance of this
  1331. * SCB into the QINFIFO.
  1332. */
  1333. ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
  1334. SCB_GET_CHANNEL(ahc, scb),
  1335. SCB_GET_LUN(scb), scb->hscb->tag,
  1336. ROLE_INITIATOR, /*status*/0,
  1337. SEARCH_REMOVE);
  1338. break;
  1339. }
  1340. case NO_FREE_SCB:
  1341. {
  1342. printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
  1343. ahc_dump_card_state(ahc);
  1344. panic("for safety");
  1345. break;
  1346. }
  1347. case SCB_MISMATCH:
  1348. {
  1349. u_int scbptr;
  1350. scbptr = ahc_inb(ahc, SCBPTR);
  1351. printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
  1352. scbptr, ahc_inb(ahc, ARG_1),
  1353. ahc->scb_data->hscbs[scbptr].tag);
  1354. ahc_dump_card_state(ahc);
  1355. panic("for saftey");
  1356. break;
  1357. }
  1358. case OUT_OF_RANGE:
  1359. {
  1360. printf("%s: BTT calculation out of range\n", ahc_name(ahc));
  1361. printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
  1362. "ARG_1 == 0x%x ACCUM = 0x%x\n",
  1363. ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
  1364. ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
  1365. printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
  1366. "SINDEX == 0x%x\n, A == 0x%x\n",
  1367. ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
  1368. ahc_index_busy_tcl(ahc,
  1369. BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
  1370. ahc_inb(ahc, SAVED_LUN))),
  1371. ahc_inb(ahc, SINDEX),
  1372. ahc_inb(ahc, ACCUM));
  1373. printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
  1374. "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
  1375. ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
  1376. ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
  1377. ahc_inb(ahc, SCB_CONTROL));
  1378. printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
  1379. ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
  1380. ahc_dump_card_state(ahc);
  1381. panic("for safety");
  1382. break;
  1383. }
  1384. default:
  1385. printf("ahc_intr: seqint, "
  1386. "intstat == 0x%x, scsisigi = 0x%x\n",
  1387. intstat, ahc_inb(ahc, SCSISIGI));
  1388. break;
  1389. }
  1390. unpause:
  1391. /*
  1392. * The sequencer is paused immediately on
  1393. * a SEQINT, so we should restart it when
  1394. * we're done.
  1395. */
  1396. ahc_unpause(ahc);
  1397. }
  1398. static void
  1399. ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
  1400. {
  1401. u_int scb_index;
  1402. u_int status0;
  1403. u_int status;
  1404. struct scb *scb;
  1405. char cur_channel;
  1406. char intr_channel;
  1407. if ((ahc->features & AHC_TWIN) != 0
  1408. && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
  1409. cur_channel = 'B';
  1410. else
  1411. cur_channel = 'A';
  1412. intr_channel = cur_channel;
  1413. if ((ahc->features & AHC_ULTRA2) != 0)
  1414. status0 = ahc_inb(ahc, SSTAT0) & IOERR;
  1415. else
  1416. status0 = 0;
  1417. status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
  1418. if (status == 0 && status0 == 0) {
  1419. if ((ahc->features & AHC_TWIN) != 0) {
  1420. /* Try the other channel */
  1421. ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
  1422. status = ahc_inb(ahc, SSTAT1)
  1423. & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
  1424. intr_channel = (cur_channel == 'A') ? 'B' : 'A';
  1425. }
  1426. if (status == 0) {
  1427. printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
  1428. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1429. ahc_unpause(ahc);
  1430. return;
  1431. }
  1432. }
  1433. /* Make sure the sequencer is in a safe location. */
  1434. ahc_clear_critical_section(ahc);
  1435. scb_index = ahc_inb(ahc, SCB_TAG);
  1436. scb = ahc_lookup_scb(ahc, scb_index);
  1437. if (scb != NULL
  1438. && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
  1439. scb = NULL;
  1440. if ((ahc->features & AHC_ULTRA2) != 0
  1441. && (status0 & IOERR) != 0) {
  1442. int now_lvd;
  1443. now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
  1444. printf("%s: Transceiver State Has Changed to %s mode\n",
  1445. ahc_name(ahc), now_lvd ? "LVD" : "SE");
  1446. ahc_outb(ahc, CLRSINT0, CLRIOERR);
  1447. /*
  1448. * When transitioning to SE mode, the reset line
  1449. * glitches, triggering an arbitration bug in some
  1450. * Ultra2 controllers. This bug is cleared when we
  1451. * assert the reset line. Since a reset glitch has
  1452. * already occurred with this transition and a
  1453. * transceiver state change is handled just like
  1454. * a bus reset anyway, asserting the reset line
  1455. * ourselves is safe.
  1456. */
  1457. ahc_reset_channel(ahc, intr_channel,
  1458. /*Initiate Reset*/now_lvd == 0);
  1459. } else if ((status & SCSIRSTI) != 0) {
  1460. printf("%s: Someone reset channel %c\n",
  1461. ahc_name(ahc), intr_channel);
  1462. if (intr_channel != cur_channel)
  1463. ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
  1464. ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
  1465. } else if ((status & SCSIPERR) != 0) {
  1466. /*
  1467. * Determine the bus phase and queue an appropriate message.
  1468. * SCSIPERR is latched true as soon as a parity error
  1469. * occurs. If the sequencer acked the transfer that
  1470. * caused the parity error and the currently presented
  1471. * transfer on the bus has correct parity, SCSIPERR will
  1472. * be cleared by CLRSCSIPERR. Use this to determine if
  1473. * we should look at the last phase the sequencer recorded,
  1474. * or the current phase presented on the bus.
  1475. */
  1476. struct ahc_devinfo devinfo;
  1477. u_int mesg_out;
  1478. u_int curphase;
  1479. u_int errorphase;
  1480. u_int lastphase;
  1481. u_int scsirate;
  1482. u_int i;
  1483. u_int sstat2;
  1484. int silent;
  1485. lastphase = ahc_inb(ahc, LASTPHASE);
  1486. curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
  1487. sstat2 = ahc_inb(ahc, SSTAT2);
  1488. ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
  1489. /*
  1490. * For all phases save DATA, the sequencer won't
  1491. * automatically ack a byte that has a parity error
  1492. * in it. So the only way that the current phase
  1493. * could be 'data-in' is if the parity error is for
  1494. * an already acked byte in the data phase. During
  1495. * synchronous data-in transfers, we may actually
  1496. * ack bytes before latching the current phase in
  1497. * LASTPHASE, leading to the discrepancy between
  1498. * curphase and lastphase.
  1499. */
  1500. if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
  1501. || curphase == P_DATAIN || curphase == P_DATAIN_DT)
  1502. errorphase = curphase;
  1503. else
  1504. errorphase = lastphase;
  1505. for (i = 0; i < num_phases; i++) {
  1506. if (errorphase == ahc_phase_table[i].phase)
  1507. break;
  1508. }
  1509. mesg_out = ahc_phase_table[i].mesg_out;
  1510. silent = FALSE;
  1511. if (scb != NULL) {
  1512. if (SCB_IS_SILENT(scb))
  1513. silent = TRUE;
  1514. else
  1515. ahc_print_path(ahc, scb);
  1516. scb->flags |= SCB_TRANSMISSION_ERROR;
  1517. } else
  1518. printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
  1519. SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
  1520. scsirate = ahc_inb(ahc, SCSIRATE);
  1521. if (silent == FALSE) {
  1522. printf("parity error detected %s. "
  1523. "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
  1524. ahc_phase_table[i].phasemsg,
  1525. ahc_inw(ahc, SEQADDR0),
  1526. scsirate);
  1527. if ((ahc->features & AHC_DT) != 0) {
  1528. if ((sstat2 & CRCVALERR) != 0)
  1529. printf("\tCRC Value Mismatch\n");
  1530. if ((sstat2 & CRCENDERR) != 0)
  1531. printf("\tNo terminal CRC packet "
  1532. "recevied\n");
  1533. if ((sstat2 & CRCREQERR) != 0)
  1534. printf("\tIllegal CRC packet "
  1535. "request\n");
  1536. if ((sstat2 & DUAL_EDGE_ERR) != 0)
  1537. printf("\tUnexpected %sDT Data Phase\n",
  1538. (scsirate & SINGLE_EDGE)
  1539. ? "" : "non-");
  1540. }
  1541. }
  1542. if ((ahc->features & AHC_DT) != 0
  1543. && (sstat2 & DUAL_EDGE_ERR) != 0) {
  1544. /*
  1545. * This error applies regardless of
  1546. * data direction, so ignore the value
  1547. * in the phase table.
  1548. */
  1549. mesg_out = MSG_INITIATOR_DET_ERR;
  1550. }
  1551. /*
  1552. * We've set the hardware to assert ATN if we
  1553. * get a parity error on "in" phases, so all we
  1554. * need to do is stuff the message buffer with
  1555. * the appropriate message. "In" phases have set
  1556. * mesg_out to something other than MSG_NOP.
  1557. */
  1558. if (mesg_out != MSG_NOOP) {
  1559. if (ahc->msg_type != MSG_TYPE_NONE)
  1560. ahc->send_msg_perror = TRUE;
  1561. else
  1562. ahc_outb(ahc, MSG_OUT, mesg_out);
  1563. }
  1564. /*
  1565. * Force a renegotiation with this target just in
  1566. * case we are out of sync for some external reason
  1567. * unknown (or unreported) by the target.
  1568. */
  1569. ahc_fetch_devinfo(ahc, &devinfo);
  1570. ahc_force_renegotiation(ahc, &devinfo);
  1571. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1572. ahc_unpause(ahc);
  1573. } else if ((status & SELTO) != 0) {
  1574. u_int scbptr;
  1575. /* Stop the selection */
  1576. ahc_outb(ahc, SCSISEQ, 0);
  1577. /* No more pending messages */
  1578. ahc_clear_msg_state(ahc);
  1579. /* Clear interrupt state */
  1580. ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
  1581. ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
  1582. /*
  1583. * Although the driver does not care about the
  1584. * 'Selection in Progress' status bit, the busy
  1585. * LED does. SELINGO is only cleared by a sucessfull
  1586. * selection, so we must manually clear it to insure
  1587. * the LED turns off just incase no future successful
  1588. * selections occur (e.g. no devices on the bus).
  1589. */
  1590. ahc_outb(ahc, CLRSINT0, CLRSELINGO);
  1591. scbptr = ahc_inb(ahc, WAITING_SCBH);
  1592. ahc_outb(ahc, SCBPTR, scbptr);
  1593. scb_index = ahc_inb(ahc, SCB_TAG);
  1594. scb = ahc_lookup_scb(ahc, scb_index);
  1595. if (scb == NULL) {
  1596. printf("%s: ahc_intr - referenced scb not "
  1597. "valid during SELTO scb(%d, %d)\n",
  1598. ahc_name(ahc), scbptr, scb_index);
  1599. ahc_dump_card_state(ahc);
  1600. } else {
  1601. struct ahc_devinfo devinfo;
  1602. #ifdef AHC_DEBUG
  1603. if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
  1604. ahc_print_path(ahc, scb);
  1605. printf("Saw Selection Timeout for SCB 0x%x\n",
  1606. scb_index);
  1607. }
  1608. #endif
  1609. ahc_scb_devinfo(ahc, &devinfo, scb);
  1610. ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
  1611. ahc_freeze_devq(ahc, scb);
  1612. /*
  1613. * Cancel any pending transactions on the device
  1614. * now that it seems to be missing. This will
  1615. * also revert us to async/narrow transfers until
  1616. * we can renegotiate with the device.
  1617. */
  1618. ahc_handle_devreset(ahc, &devinfo,
  1619. CAM_SEL_TIMEOUT,
  1620. "Selection Timeout",
  1621. /*verbose_level*/1);
  1622. }
  1623. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1624. ahc_restart(ahc);
  1625. } else if ((status & BUSFREE) != 0
  1626. && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
  1627. struct ahc_devinfo devinfo;
  1628. u_int lastphase;
  1629. u_int saved_scsiid;
  1630. u_int saved_lun;
  1631. u_int target;
  1632. u_int initiator_role_id;
  1633. char channel;
  1634. int printerror;
  1635. /*
  1636. * Clear our selection hardware as soon as possible.
  1637. * We may have an entry in the waiting Q for this target,
  1638. * that is affected by this busfree and we don't want to
  1639. * go about selecting the target while we handle the event.
  1640. */
  1641. ahc_outb(ahc, SCSISEQ,
  1642. ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
  1643. /*
  1644. * Disable busfree interrupts and clear the busfree
  1645. * interrupt status. We do this here so that several
  1646. * bus transactions occur prior to clearing the SCSIINT
  1647. * latch. It can take a bit for the clearing to take effect.
  1648. */
  1649. ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
  1650. ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
  1651. /*
  1652. * Look at what phase we were last in.
  1653. * If its message out, chances are pretty good
  1654. * that the busfree was in response to one of
  1655. * our abort requests.
  1656. */
  1657. lastphase = ahc_inb(ahc, LASTPHASE);
  1658. saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
  1659. saved_lun = ahc_inb(ahc, SAVED_LUN);
  1660. target = SCSIID_TARGET(ahc, saved_scsiid);
  1661. initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
  1662. channel = SCSIID_CHANNEL(ahc, saved_scsiid);
  1663. ahc_compile_devinfo(&devinfo, initiator_role_id,
  1664. target, saved_lun, channel, ROLE_INITIATOR);
  1665. printerror = 1;
  1666. if (lastphase == P_MESGOUT) {
  1667. u_int tag;
  1668. tag = SCB_LIST_NULL;
  1669. if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
  1670. || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
  1671. if (ahc->msgout_buf[ahc->msgout_index - 1]
  1672. == MSG_ABORT_TAG)
  1673. tag = scb->hscb->tag;
  1674. ahc_print_path(ahc, scb);
  1675. printf("SCB %d - Abort%s Completed.\n",
  1676. scb->hscb->tag, tag == SCB_LIST_NULL ?
  1677. "" : " Tag");
  1678. ahc_abort_scbs(ahc, target, channel,
  1679. saved_lun, tag,
  1680. ROLE_INITIATOR,
  1681. CAM_REQ_ABORTED);
  1682. printerror = 0;
  1683. } else if (ahc_sent_msg(ahc, AHCMSG_1B,
  1684. MSG_BUS_DEV_RESET, TRUE)) {
  1685. #ifdef __FreeBSD__
  1686. /*
  1687. * Don't mark the user's request for this BDR
  1688. * as completing with CAM_BDR_SENT. CAM3
  1689. * specifies CAM_REQ_CMP.
  1690. */
  1691. if (scb != NULL
  1692. && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
  1693. && ahc_match_scb(ahc, scb, target, channel,
  1694. CAM_LUN_WILDCARD,
  1695. SCB_LIST_NULL,
  1696. ROLE_INITIATOR)) {
  1697. ahc_set_transaction_status(scb, CAM_REQ_CMP);
  1698. }
  1699. #endif
  1700. ahc_compile_devinfo(&devinfo,
  1701. initiator_role_id,
  1702. target,
  1703. CAM_LUN_WILDCARD,
  1704. channel,
  1705. ROLE_INITIATOR);
  1706. ahc_handle_devreset(ahc, &devinfo,
  1707. CAM_BDR_SENT,
  1708. "Bus Device Reset",
  1709. /*verbose_level*/0);
  1710. printerror = 0;
  1711. } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
  1712. MSG_EXT_PPR, FALSE)) {
  1713. struct ahc_initiator_tinfo *tinfo;
  1714. struct ahc_tmode_tstate *tstate;
  1715. /*
  1716. * PPR Rejected. Try non-ppr negotiation
  1717. * and retry command.
  1718. */
  1719. tinfo = ahc_fetch_transinfo(ahc,
  1720. devinfo.channel,
  1721. devinfo.our_scsiid,
  1722. devinfo.target,
  1723. &tstate);
  1724. tinfo->curr.transport_version = 2;
  1725. tinfo->goal.transport_version = 2;
  1726. tinfo->goal.ppr_options = 0;
  1727. ahc_qinfifo_requeue_tail(ahc, scb);
  1728. printerror = 0;
  1729. } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
  1730. MSG_EXT_WDTR, FALSE)) {
  1731. /*
  1732. * Negotiation Rejected. Go-narrow and
  1733. * retry command.
  1734. */
  1735. ahc_set_width(ahc, &devinfo,
  1736. MSG_EXT_WDTR_BUS_8_BIT,
  1737. AHC_TRANS_CUR|AHC_TRANS_GOAL,
  1738. /*paused*/TRUE);
  1739. ahc_qinfifo_requeue_tail(ahc, scb);
  1740. printerror = 0;
  1741. } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
  1742. MSG_EXT_SDTR, FALSE)) {
  1743. /*
  1744. * Negotiation Rejected. Go-async and
  1745. * retry command.
  1746. */
  1747. ahc_set_syncrate(ahc, &devinfo,
  1748. /*syncrate*/NULL,
  1749. /*period*/0, /*offset*/0,
  1750. /*ppr_options*/0,
  1751. AHC_TRANS_CUR|AHC_TRANS_GOAL,
  1752. /*paused*/TRUE);
  1753. ahc_qinfifo_requeue_tail(ahc, scb);
  1754. printerror = 0;
  1755. }
  1756. }
  1757. if (printerror != 0) {
  1758. u_int i;
  1759. if (scb != NULL) {
  1760. u_int tag;
  1761. if ((scb->hscb->control & TAG_ENB) != 0)
  1762. tag = scb->hscb->tag;
  1763. else
  1764. tag = SCB_LIST_NULL;
  1765. ahc_print_path(ahc, scb);
  1766. ahc_abort_scbs(ahc, target, channel,
  1767. SCB_GET_LUN(scb), tag,
  1768. ROLE_INITIATOR,
  1769. CAM_UNEXP_BUSFREE);
  1770. } else {
  1771. /*
  1772. * We had not fully identified this connection,
  1773. * so we cannot abort anything.
  1774. */
  1775. printf("%s: ", ahc_name(ahc));
  1776. }
  1777. for (i = 0; i < num_phases; i++) {
  1778. if (lastphase == ahc_phase_table[i].phase)
  1779. break;
  1780. }
  1781. if (lastphase != P_BUSFREE) {
  1782. /*
  1783. * Renegotiate with this device at the
  1784. * next oportunity just in case this busfree
  1785. * is due to a negotiation mismatch with the
  1786. * device.
  1787. */
  1788. ahc_force_renegotiation(ahc, &devinfo);
  1789. }
  1790. printf("Unexpected busfree %s\n"
  1791. "SEQADDR == 0x%x\n",
  1792. ahc_phase_table[i].phasemsg,
  1793. ahc_inb(ahc, SEQADDR0)
  1794. | (ahc_inb(ahc, SEQADDR1) << 8));
  1795. }
  1796. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1797. ahc_restart(ahc);
  1798. } else {
  1799. printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
  1800. ahc_name(ahc), status);
  1801. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1802. }
  1803. }
  1804. /*
  1805. * Force renegotiation to occur the next time we initiate
  1806. * a command to the current device.
  1807. */
  1808. static void
  1809. ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  1810. {
  1811. struct ahc_initiator_tinfo *targ_info;
  1812. struct ahc_tmode_tstate *tstate;
  1813. targ_info = ahc_fetch_transinfo(ahc,
  1814. devinfo->channel,
  1815. devinfo->our_scsiid,
  1816. devinfo->target,
  1817. &tstate);
  1818. ahc_update_neg_request(ahc, devinfo, tstate,
  1819. targ_info, AHC_NEG_IF_NON_ASYNC);
  1820. }
  1821. #define AHC_MAX_STEPS 2000
  1822. static void
  1823. ahc_clear_critical_section(struct ahc_softc *ahc)
  1824. {
  1825. int stepping;
  1826. int steps;
  1827. u_int simode0;
  1828. u_int simode1;
  1829. if (ahc->num_critical_sections == 0)
  1830. return;
  1831. stepping = FALSE;
  1832. steps = 0;
  1833. simode0 = 0;
  1834. simode1 = 0;
  1835. for (;;) {
  1836. struct cs *cs;
  1837. u_int seqaddr;
  1838. u_int i;
  1839. seqaddr = ahc_inb(ahc, SEQADDR0)
  1840. | (ahc_inb(ahc, SEQADDR1) << 8);
  1841. /*
  1842. * Seqaddr represents the next instruction to execute,
  1843. * so we are really executing the instruction just
  1844. * before it.
  1845. */
  1846. if (seqaddr != 0)
  1847. seqaddr -= 1;
  1848. cs = ahc->critical_sections;
  1849. for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
  1850. if (cs->begin < seqaddr && cs->end >= seqaddr)
  1851. break;
  1852. }
  1853. if (i == ahc->num_critical_sections)
  1854. break;
  1855. if (steps > AHC_MAX_STEPS) {
  1856. printf("%s: Infinite loop in critical section\n",
  1857. ahc_name(ahc));
  1858. ahc_dump_card_state(ahc);
  1859. panic("critical section loop");
  1860. }
  1861. steps++;
  1862. if (stepping == FALSE) {
  1863. /*
  1864. * Disable all interrupt sources so that the
  1865. * sequencer will not be stuck by a pausing
  1866. * interrupt condition while we attempt to
  1867. * leave a critical section.
  1868. */
  1869. simode0 = ahc_inb(ahc, SIMODE0);
  1870. ahc_outb(ahc, SIMODE0, 0);
  1871. simode1 = ahc_inb(ahc, SIMODE1);
  1872. if ((ahc->features & AHC_DT) != 0)
  1873. /*
  1874. * On DT class controllers, we
  1875. * use the enhanced busfree logic.
  1876. * Unfortunately we cannot re-enable
  1877. * busfree detection within the
  1878. * current connection, so we must
  1879. * leave it on while single stepping.
  1880. */
  1881. ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
  1882. else
  1883. ahc_outb(ahc, SIMODE1, 0);
  1884. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1885. ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
  1886. stepping = TRUE;
  1887. }
  1888. if ((ahc->features & AHC_DT) != 0) {
  1889. ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
  1890. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1891. }
  1892. ahc_outb(ahc, HCNTRL, ahc->unpause);
  1893. while (!ahc_is_paused(ahc))
  1894. ahc_delay(200);
  1895. }
  1896. if (stepping) {
  1897. ahc_outb(ahc, SIMODE0, simode0);
  1898. ahc_outb(ahc, SIMODE1, simode1);
  1899. ahc_outb(ahc, SEQCTL, ahc->seqctl);
  1900. }
  1901. }
  1902. /*
  1903. * Clear any pending interrupt status.
  1904. */
  1905. static void
  1906. ahc_clear_intstat(struct ahc_softc *ahc)
  1907. {
  1908. /* Clear any interrupt conditions this may have caused */
  1909. ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
  1910. |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
  1911. CLRREQINIT);
  1912. ahc_flush_device_writes(ahc);
  1913. ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
  1914. ahc_flush_device_writes(ahc);
  1915. ahc_outb(ahc, CLRINT, CLRSCSIINT);
  1916. ahc_flush_device_writes(ahc);
  1917. }
  1918. /**************************** Debugging Routines ******************************/
  1919. #ifdef AHC_DEBUG
  1920. uint32_t ahc_debug = AHC_DEBUG_OPTS;
  1921. #endif
  1922. #if 0 /* unused */
  1923. static void
  1924. ahc_print_scb(struct scb *scb)
  1925. {
  1926. int i;
  1927. struct hardware_scb *hscb = scb->hscb;
  1928. printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
  1929. (void *)scb,
  1930. hscb->control,
  1931. hscb->scsiid,
  1932. hscb->lun,
  1933. hscb->cdb_len);
  1934. printf("Shared Data: ");
  1935. for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
  1936. printf("%#02x", hscb->shared_data.cdb[i]);
  1937. printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
  1938. ahc_le32toh(hscb->dataptr),
  1939. ahc_le32toh(hscb->datacnt),
  1940. ahc_le32toh(hscb->sgptr),
  1941. hscb->tag);
  1942. if (scb->sg_count > 0) {
  1943. for (i = 0; i < scb->sg_count; i++) {
  1944. printf("sg[%d] - Addr 0x%x%x : Length %d\n",
  1945. i,
  1946. (ahc_le32toh(scb->sg_list[i].len) >> 24
  1947. & SG_HIGH_ADDR_BITS),
  1948. ahc_le32toh(scb->sg_list[i].addr),
  1949. ahc_le32toh(scb->sg_list[i].len));
  1950. }
  1951. }
  1952. }
  1953. #endif
  1954. /************************* Transfer Negotiation *******************************/
  1955. /*
  1956. * Allocate per target mode instance (ID we respond to as a target)
  1957. * transfer negotiation data structures.
  1958. */
  1959. static struct ahc_tmode_tstate *
  1960. ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
  1961. {
  1962. struct ahc_tmode_tstate *master_tstate;
  1963. struct ahc_tmode_tstate *tstate;
  1964. int i;
  1965. master_tstate = ahc->enabled_targets[ahc->our_id];
  1966. if (channel == 'B') {
  1967. scsi_id += 8;
  1968. master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
  1969. }
  1970. if (ahc->enabled_targets[scsi_id] != NULL
  1971. && ahc->enabled_targets[scsi_id] != master_tstate)
  1972. panic("%s: ahc_alloc_tstate - Target already allocated",
  1973. ahc_name(ahc));
  1974. tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
  1975. M_DEVBUF, M_NOWAIT);
  1976. if (tstate == NULL)
  1977. return (NULL);
  1978. /*
  1979. * If we have allocated a master tstate, copy user settings from
  1980. * the master tstate (taken from SRAM or the EEPROM) for this
  1981. * channel, but reset our current and goal settings to async/narrow
  1982. * until an initiator talks to us.
  1983. */
  1984. if (master_tstate != NULL) {
  1985. memcpy(tstate, master_tstate, sizeof(*tstate));
  1986. memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
  1987. tstate->ultraenb = 0;
  1988. for (i = 0; i < AHC_NUM_TARGETS; i++) {
  1989. memset(&tstate->transinfo[i].curr, 0,
  1990. sizeof(tstate->transinfo[i].curr));
  1991. memset(&tstate->transinfo[i].goal, 0,
  1992. sizeof(tstate->transinfo[i].goal));
  1993. }
  1994. } else
  1995. memset(tstate, 0, sizeof(*tstate));
  1996. ahc->enabled_targets[scsi_id] = tstate;
  1997. return (tstate);
  1998. }
  1999. #ifdef AHC_TARGET_MODE
  2000. /*
  2001. * Free per target mode instance (ID we respond to as a target)
  2002. * transfer negotiation data structures.
  2003. */
  2004. static void
  2005. ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
  2006. {
  2007. struct ahc_tmode_tstate *tstate;
  2008. /*
  2009. * Don't clean up our "master" tstate.
  2010. * It has our default user settings.
  2011. */
  2012. if (((channel == 'B' && scsi_id == ahc->our_id_b)
  2013. || (channel == 'A' && scsi_id == ahc->our_id))
  2014. && force == FALSE)
  2015. return;
  2016. if (channel == 'B')
  2017. scsi_id += 8;
  2018. tstate = ahc->enabled_targets[scsi_id];
  2019. if (tstate != NULL)
  2020. free(tstate, M_DEVBUF);
  2021. ahc->enabled_targets[scsi_id] = NULL;
  2022. }
  2023. #endif
  2024. /*
  2025. * Called when we have an active connection to a target on the bus,
  2026. * this function finds the nearest syncrate to the input period limited
  2027. * by the capabilities of the bus connectivity of and sync settings for
  2028. * the target.
  2029. */
  2030. const struct ahc_syncrate *
  2031. ahc_devlimited_syncrate(struct ahc_softc *ahc,
  2032. struct ahc_initiator_tinfo *tinfo,
  2033. u_int *period, u_int *ppr_options, role_t role)
  2034. {
  2035. struct ahc_transinfo *transinfo;
  2036. u_int maxsync;
  2037. if ((ahc->features & AHC_ULTRA2) != 0) {
  2038. if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
  2039. && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
  2040. maxsync = AHC_SYNCRATE_DT;
  2041. } else {
  2042. maxsync = AHC_SYNCRATE_ULTRA;
  2043. /* Can't do DT on an SE bus */
  2044. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  2045. }
  2046. } else if ((ahc->features & AHC_ULTRA) != 0) {
  2047. maxsync = AHC_SYNCRATE_ULTRA;
  2048. } else {
  2049. maxsync = AHC_SYNCRATE_FAST;
  2050. }
  2051. /*
  2052. * Never allow a value higher than our current goal
  2053. * period otherwise we may allow a target initiated
  2054. * negotiation to go above the limit as set by the
  2055. * user. In the case of an initiator initiated
  2056. * sync negotiation, we limit based on the user
  2057. * setting. This allows the system to still accept
  2058. * incoming negotiations even if target initiated
  2059. * negotiation is not performed.
  2060. */
  2061. if (role == ROLE_TARGET)
  2062. transinfo = &tinfo->user;
  2063. else
  2064. transinfo = &tinfo->goal;
  2065. *ppr_options &= transinfo->ppr_options;
  2066. if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
  2067. maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
  2068. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  2069. }
  2070. if (transinfo->period == 0) {
  2071. *period = 0;
  2072. *ppr_options = 0;
  2073. return (NULL);
  2074. }
  2075. *period = max(*period, (u_int)transinfo->period);
  2076. return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
  2077. }
  2078. /*
  2079. * Look up the valid period to SCSIRATE conversion in our table.
  2080. * Return the period and offset that should be sent to the target
  2081. * if this was the beginning of an SDTR.
  2082. */
  2083. const struct ahc_syncrate *
  2084. ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
  2085. u_int *ppr_options, u_int maxsync)
  2086. {
  2087. const struct ahc_syncrate *syncrate;
  2088. if ((ahc->features & AHC_DT) == 0)
  2089. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  2090. /* Skip all DT only entries if DT is not available */
  2091. if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
  2092. && maxsync < AHC_SYNCRATE_ULTRA2)
  2093. maxsync = AHC_SYNCRATE_ULTRA2;
  2094. /* Now set the maxsync based on the card capabilities
  2095. * DT is already done above */
  2096. if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
  2097. && maxsync < AHC_SYNCRATE_ULTRA)
  2098. maxsync = AHC_SYNCRATE_ULTRA;
  2099. if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
  2100. && maxsync < AHC_SYNCRATE_FAST)
  2101. maxsync = AHC_SYNCRATE_FAST;
  2102. for (syncrate = &ahc_syncrates[maxsync];
  2103. syncrate->rate != NULL;
  2104. syncrate++) {
  2105. /*
  2106. * The Ultra2 table doesn't go as low
  2107. * as for the Fast/Ultra cards.
  2108. */
  2109. if ((ahc->features & AHC_ULTRA2) != 0
  2110. && (syncrate->sxfr_u2 == 0))
  2111. break;
  2112. if (*period <= syncrate->period) {
  2113. /*
  2114. * When responding to a target that requests
  2115. * sync, the requested rate may fall between
  2116. * two rates that we can output, but still be
  2117. * a rate that we can receive. Because of this,
  2118. * we want to respond to the target with
  2119. * the same rate that it sent to us even
  2120. * if the period we use to send data to it
  2121. * is lower. Only lower the response period
  2122. * if we must.
  2123. */
  2124. if (syncrate == &ahc_syncrates[maxsync])
  2125. *period = syncrate->period;
  2126. /*
  2127. * At some speeds, we only support
  2128. * ST transfers.
  2129. */
  2130. if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
  2131. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  2132. break;
  2133. }
  2134. }
  2135. if ((*period == 0)
  2136. || (syncrate->rate == NULL)
  2137. || ((ahc->features & AHC_ULTRA2) != 0
  2138. && (syncrate->sxfr_u2 == 0))) {
  2139. /* Use asynchronous transfers. */
  2140. *period = 0;
  2141. syncrate = NULL;
  2142. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  2143. }
  2144. return (syncrate);
  2145. }
  2146. /*
  2147. * Convert from an entry in our syncrate table to the SCSI equivalent
  2148. * sync "period" factor.
  2149. */
  2150. u_int
  2151. ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
  2152. {
  2153. const struct ahc_syncrate *syncrate;
  2154. if ((ahc->features & AHC_ULTRA2) != 0)
  2155. scsirate &= SXFR_ULTRA2;
  2156. else
  2157. scsirate &= SXFR;
  2158. /* now set maxsync based on card capabilities */
  2159. if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
  2160. maxsync = AHC_SYNCRATE_ULTRA2;
  2161. if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
  2162. && maxsync < AHC_SYNCRATE_ULTRA)
  2163. maxsync = AHC_SYNCRATE_ULTRA;
  2164. if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
  2165. && maxsync < AHC_SYNCRATE_FAST)
  2166. maxsync = AHC_SYNCRATE_FAST;
  2167. syncrate = &ahc_syncrates[maxsync];
  2168. while (syncrate->rate != NULL) {
  2169. if ((ahc->features & AHC_ULTRA2) != 0) {
  2170. if (syncrate->sxfr_u2 == 0)
  2171. break;
  2172. else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
  2173. return (syncrate->period);
  2174. } else if (scsirate == (syncrate->sxfr & SXFR)) {
  2175. return (syncrate->period);
  2176. }
  2177. syncrate++;
  2178. }
  2179. return (0); /* async */
  2180. }
  2181. /*
  2182. * Truncate the given synchronous offset to a value the
  2183. * current adapter type and syncrate are capable of.
  2184. */
  2185. static void
  2186. ahc_validate_offset(struct ahc_softc *ahc,
  2187. struct ahc_initiator_tinfo *tinfo,
  2188. const struct ahc_syncrate *syncrate,
  2189. u_int *offset, int wide, role_t role)
  2190. {
  2191. u_int maxoffset;
  2192. /* Limit offset to what we can do */
  2193. if (syncrate == NULL) {
  2194. maxoffset = 0;
  2195. } else if ((ahc->features & AHC_ULTRA2) != 0) {
  2196. maxoffset = MAX_OFFSET_ULTRA2;
  2197. } else {
  2198. if (wide)
  2199. maxoffset = MAX_OFFSET_16BIT;
  2200. else
  2201. maxoffset = MAX_OFFSET_8BIT;
  2202. }
  2203. *offset = min(*offset, maxoffset);
  2204. if (tinfo != NULL) {
  2205. if (role == ROLE_TARGET)
  2206. *offset = min(*offset, (u_int)tinfo->user.offset);
  2207. else
  2208. *offset = min(*offset, (u_int)tinfo->goal.offset);
  2209. }
  2210. }
  2211. /*
  2212. * Truncate the given transfer width parameter to a value the
  2213. * current adapter type is capable of.
  2214. */
  2215. static void
  2216. ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
  2217. u_int *bus_width, role_t role)
  2218. {
  2219. switch (*bus_width) {
  2220. default:
  2221. if (ahc->features & AHC_WIDE) {
  2222. /* Respond Wide */
  2223. *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
  2224. break;
  2225. }
  2226. /* FALLTHROUGH */
  2227. case MSG_EXT_WDTR_BUS_8_BIT:
  2228. *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
  2229. break;
  2230. }
  2231. if (tinfo != NULL) {
  2232. if (role == ROLE_TARGET)
  2233. *bus_width = min((u_int)tinfo->user.width, *bus_width);
  2234. else
  2235. *bus_width = min((u_int)tinfo->goal.width, *bus_width);
  2236. }
  2237. }
  2238. /*
  2239. * Update the bitmask of targets for which the controller should
  2240. * negotiate with at the next convenient oportunity. This currently
  2241. * means the next time we send the initial identify messages for
  2242. * a new transaction.
  2243. */
  2244. int
  2245. ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2246. struct ahc_tmode_tstate *tstate,
  2247. struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
  2248. {
  2249. u_int auto_negotiate_orig;
  2250. auto_negotiate_orig = tstate->auto_negotiate;
  2251. if (neg_type == AHC_NEG_ALWAYS) {
  2252. /*
  2253. * Force our "current" settings to be
  2254. * unknown so that unless a bus reset
  2255. * occurs the need to renegotiate is
  2256. * recorded persistently.
  2257. */
  2258. if ((ahc->features & AHC_WIDE) != 0)
  2259. tinfo->curr.width = AHC_WIDTH_UNKNOWN;
  2260. tinfo->curr.period = AHC_PERIOD_UNKNOWN;
  2261. tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
  2262. }
  2263. if (tinfo->curr.period != tinfo->goal.period
  2264. || tinfo->curr.width != tinfo->goal.width
  2265. || tinfo->curr.offset != tinfo->goal.offset
  2266. || tinfo->curr.ppr_options != tinfo->goal.ppr_options
  2267. || (neg_type == AHC_NEG_IF_NON_ASYNC
  2268. && (tinfo->goal.offset != 0
  2269. || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
  2270. || tinfo->goal.ppr_options != 0)))
  2271. tstate->auto_negotiate |= devinfo->target_mask;
  2272. else
  2273. tstate->auto_negotiate &= ~devinfo->target_mask;
  2274. return (auto_negotiate_orig != tstate->auto_negotiate);
  2275. }
  2276. /*
  2277. * Update the user/goal/curr tables of synchronous negotiation
  2278. * parameters as well as, in the case of a current or active update,
  2279. * any data structures on the host controller. In the case of an
  2280. * active update, the specified target is currently talking to us on
  2281. * the bus, so the transfer parameter update must take effect
  2282. * immediately.
  2283. */
  2284. void
  2285. ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2286. const struct ahc_syncrate *syncrate, u_int period,
  2287. u_int offset, u_int ppr_options, u_int type, int paused)
  2288. {
  2289. struct ahc_initiator_tinfo *tinfo;
  2290. struct ahc_tmode_tstate *tstate;
  2291. u_int old_period;
  2292. u_int old_offset;
  2293. u_int old_ppr;
  2294. int active;
  2295. int update_needed;
  2296. active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
  2297. update_needed = 0;
  2298. if (syncrate == NULL) {
  2299. period = 0;
  2300. offset = 0;
  2301. }
  2302. tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
  2303. devinfo->target, &tstate);
  2304. if ((type & AHC_TRANS_USER) != 0) {
  2305. tinfo->user.period = period;
  2306. tinfo->user.offset = offset;
  2307. tinfo->user.ppr_options = ppr_options;
  2308. }
  2309. if ((type & AHC_TRANS_GOAL) != 0) {
  2310. tinfo->goal.period = period;
  2311. tinfo->goal.offset = offset;
  2312. tinfo->goal.ppr_options = ppr_options;
  2313. }
  2314. old_period = tinfo->curr.period;
  2315. old_offset = tinfo->curr.offset;
  2316. old_ppr = tinfo->curr.ppr_options;
  2317. if ((type & AHC_TRANS_CUR) != 0
  2318. && (old_period != period
  2319. || old_offset != offset
  2320. || old_ppr != ppr_options)) {
  2321. u_int scsirate;
  2322. update_needed++;
  2323. scsirate = tinfo->scsirate;
  2324. if ((ahc->features & AHC_ULTRA2) != 0) {
  2325. scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
  2326. if (syncrate != NULL) {
  2327. scsirate |= syncrate->sxfr_u2;
  2328. if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
  2329. scsirate |= ENABLE_CRC;
  2330. else
  2331. scsirate |= SINGLE_EDGE;
  2332. }
  2333. } else {
  2334. scsirate &= ~(SXFR|SOFS);
  2335. /*
  2336. * Ensure Ultra mode is set properly for
  2337. * this target.
  2338. */
  2339. tstate->ultraenb &= ~devinfo->target_mask;
  2340. if (syncrate != NULL) {
  2341. if (syncrate->sxfr & ULTRA_SXFR) {
  2342. tstate->ultraenb |=
  2343. devinfo->target_mask;
  2344. }
  2345. scsirate |= syncrate->sxfr & SXFR;
  2346. scsirate |= offset & SOFS;
  2347. }
  2348. if (active) {
  2349. u_int sxfrctl0;
  2350. sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
  2351. sxfrctl0 &= ~FAST20;
  2352. if (tstate->ultraenb & devinfo->target_mask)
  2353. sxfrctl0 |= FAST20;
  2354. ahc_outb(ahc, SXFRCTL0, sxfrctl0);
  2355. }
  2356. }
  2357. if (active) {
  2358. ahc_outb(ahc, SCSIRATE, scsirate);
  2359. if ((ahc->features & AHC_ULTRA2) != 0)
  2360. ahc_outb(ahc, SCSIOFFSET, offset);
  2361. }
  2362. tinfo->scsirate = scsirate;
  2363. tinfo->curr.period = period;
  2364. tinfo->curr.offset = offset;
  2365. tinfo->curr.ppr_options = ppr_options;
  2366. ahc_send_async(ahc, devinfo->channel, devinfo->target,
  2367. CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
  2368. if (bootverbose) {
  2369. if (offset != 0) {
  2370. printf("%s: target %d synchronous at %sMHz%s, "
  2371. "offset = 0x%x\n", ahc_name(ahc),
  2372. devinfo->target, syncrate->rate,
  2373. (ppr_options & MSG_EXT_PPR_DT_REQ)
  2374. ? " DT" : "", offset);
  2375. } else {
  2376. printf("%s: target %d using "
  2377. "asynchronous transfers\n",
  2378. ahc_name(ahc), devinfo->target);
  2379. }
  2380. }
  2381. }
  2382. update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
  2383. tinfo, AHC_NEG_TO_GOAL);
  2384. if (update_needed)
  2385. ahc_update_pending_scbs(ahc);
  2386. }
  2387. /*
  2388. * Update the user/goal/curr tables of wide negotiation
  2389. * parameters as well as, in the case of a current or active update,
  2390. * any data structures on the host controller. In the case of an
  2391. * active update, the specified target is currently talking to us on
  2392. * the bus, so the transfer parameter update must take effect
  2393. * immediately.
  2394. */
  2395. void
  2396. ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2397. u_int width, u_int type, int paused)
  2398. {
  2399. struct ahc_initiator_tinfo *tinfo;
  2400. struct ahc_tmode_tstate *tstate;
  2401. u_int oldwidth;
  2402. int active;
  2403. int update_needed;
  2404. active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
  2405. update_needed = 0;
  2406. tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
  2407. devinfo->target, &tstate);
  2408. if ((type & AHC_TRANS_USER) != 0)
  2409. tinfo->user.width = width;
  2410. if ((type & AHC_TRANS_GOAL) != 0)
  2411. tinfo->goal.width = width;
  2412. oldwidth = tinfo->curr.width;
  2413. if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
  2414. u_int scsirate;
  2415. update_needed++;
  2416. scsirate = tinfo->scsirate;
  2417. scsirate &= ~WIDEXFER;
  2418. if (width == MSG_EXT_WDTR_BUS_16_BIT)
  2419. scsirate |= WIDEXFER;
  2420. tinfo->scsirate = scsirate;
  2421. if (active)
  2422. ahc_outb(ahc, SCSIRATE, scsirate);
  2423. tinfo->curr.width = width;
  2424. ahc_send_async(ahc, devinfo->channel, devinfo->target,
  2425. CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
  2426. if (bootverbose) {
  2427. printf("%s: target %d using %dbit transfers\n",
  2428. ahc_name(ahc), devinfo->target,
  2429. 8 * (0x01 << width));
  2430. }
  2431. }
  2432. update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
  2433. tinfo, AHC_NEG_TO_GOAL);
  2434. if (update_needed)
  2435. ahc_update_pending_scbs(ahc);
  2436. }
  2437. /*
  2438. * Update the current state of tagged queuing for a given target.
  2439. */
  2440. static void
  2441. ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
  2442. struct ahc_devinfo *devinfo, ahc_queue_alg alg)
  2443. {
  2444. struct scsi_device *sdev = cmd->device;
  2445. ahc_platform_set_tags(ahc, sdev, devinfo, alg);
  2446. ahc_send_async(ahc, devinfo->channel, devinfo->target,
  2447. devinfo->lun, AC_TRANSFER_NEG);
  2448. }
  2449. /*
  2450. * When the transfer settings for a connection change, update any
  2451. * in-transit SCBs to contain the new data so the hardware will
  2452. * be set correctly during future (re)selections.
  2453. */
  2454. static void
  2455. ahc_update_pending_scbs(struct ahc_softc *ahc)
  2456. {
  2457. struct scb *pending_scb;
  2458. int pending_scb_count;
  2459. int i;
  2460. int paused;
  2461. u_int saved_scbptr;
  2462. /*
  2463. * Traverse the pending SCB list and ensure that all of the
  2464. * SCBs there have the proper settings.
  2465. */
  2466. pending_scb_count = 0;
  2467. LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
  2468. struct ahc_devinfo devinfo;
  2469. struct hardware_scb *pending_hscb;
  2470. struct ahc_initiator_tinfo *tinfo;
  2471. struct ahc_tmode_tstate *tstate;
  2472. ahc_scb_devinfo(ahc, &devinfo, pending_scb);
  2473. tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
  2474. devinfo.our_scsiid,
  2475. devinfo.target, &tstate);
  2476. pending_hscb = pending_scb->hscb;
  2477. pending_hscb->control &= ~ULTRAENB;
  2478. if ((tstate->ultraenb & devinfo.target_mask) != 0)
  2479. pending_hscb->control |= ULTRAENB;
  2480. pending_hscb->scsirate = tinfo->scsirate;
  2481. pending_hscb->scsioffset = tinfo->curr.offset;
  2482. if ((tstate->auto_negotiate & devinfo.target_mask) == 0
  2483. && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
  2484. pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
  2485. pending_hscb->control &= ~MK_MESSAGE;
  2486. }
  2487. ahc_sync_scb(ahc, pending_scb,
  2488. BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  2489. pending_scb_count++;
  2490. }
  2491. if (pending_scb_count == 0)
  2492. return;
  2493. if (ahc_is_paused(ahc)) {
  2494. paused = 1;
  2495. } else {
  2496. paused = 0;
  2497. ahc_pause(ahc);
  2498. }
  2499. saved_scbptr = ahc_inb(ahc, SCBPTR);
  2500. /* Ensure that the hscbs down on the card match the new information */
  2501. for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
  2502. struct hardware_scb *pending_hscb;
  2503. u_int control;
  2504. u_int scb_tag;
  2505. ahc_outb(ahc, SCBPTR, i);
  2506. scb_tag = ahc_inb(ahc, SCB_TAG);
  2507. pending_scb = ahc_lookup_scb(ahc, scb_tag);
  2508. if (pending_scb == NULL)
  2509. continue;
  2510. pending_hscb = pending_scb->hscb;
  2511. control = ahc_inb(ahc, SCB_CONTROL);
  2512. control &= ~(ULTRAENB|MK_MESSAGE);
  2513. control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
  2514. ahc_outb(ahc, SCB_CONTROL, control);
  2515. ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
  2516. ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
  2517. }
  2518. ahc_outb(ahc, SCBPTR, saved_scbptr);
  2519. if (paused == 0)
  2520. ahc_unpause(ahc);
  2521. }
  2522. /**************************** Pathing Information *****************************/
  2523. static void
  2524. ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  2525. {
  2526. u_int saved_scsiid;
  2527. role_t role;
  2528. int our_id;
  2529. if (ahc_inb(ahc, SSTAT0) & TARGET)
  2530. role = ROLE_TARGET;
  2531. else
  2532. role = ROLE_INITIATOR;
  2533. if (role == ROLE_TARGET
  2534. && (ahc->features & AHC_MULTI_TID) != 0
  2535. && (ahc_inb(ahc, SEQ_FLAGS)
  2536. & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
  2537. /* We were selected, so pull our id from TARGIDIN */
  2538. our_id = ahc_inb(ahc, TARGIDIN) & OID;
  2539. } else if ((ahc->features & AHC_ULTRA2) != 0)
  2540. our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
  2541. else
  2542. our_id = ahc_inb(ahc, SCSIID) & OID;
  2543. saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
  2544. ahc_compile_devinfo(devinfo,
  2545. our_id,
  2546. SCSIID_TARGET(ahc, saved_scsiid),
  2547. ahc_inb(ahc, SAVED_LUN),
  2548. SCSIID_CHANNEL(ahc, saved_scsiid),
  2549. role);
  2550. }
  2551. static const struct ahc_phase_table_entry*
  2552. ahc_lookup_phase_entry(int phase)
  2553. {
  2554. const struct ahc_phase_table_entry *entry;
  2555. const struct ahc_phase_table_entry *last_entry;
  2556. /*
  2557. * num_phases doesn't include the default entry which
  2558. * will be returned if the phase doesn't match.
  2559. */
  2560. last_entry = &ahc_phase_table[num_phases];
  2561. for (entry = ahc_phase_table; entry < last_entry; entry++) {
  2562. if (phase == entry->phase)
  2563. break;
  2564. }
  2565. return (entry);
  2566. }
  2567. void
  2568. ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
  2569. u_int lun, char channel, role_t role)
  2570. {
  2571. devinfo->our_scsiid = our_id;
  2572. devinfo->target = target;
  2573. devinfo->lun = lun;
  2574. devinfo->target_offset = target;
  2575. devinfo->channel = channel;
  2576. devinfo->role = role;
  2577. if (channel == 'B')
  2578. devinfo->target_offset += 8;
  2579. devinfo->target_mask = (0x01 << devinfo->target_offset);
  2580. }
  2581. void
  2582. ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  2583. {
  2584. printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
  2585. devinfo->target, devinfo->lun);
  2586. }
  2587. static void
  2588. ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2589. struct scb *scb)
  2590. {
  2591. role_t role;
  2592. int our_id;
  2593. our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
  2594. role = ROLE_INITIATOR;
  2595. if ((scb->flags & SCB_TARGET_SCB) != 0)
  2596. role = ROLE_TARGET;
  2597. ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
  2598. SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
  2599. }
  2600. /************************ Message Phase Processing ****************************/
  2601. static void
  2602. ahc_assert_atn(struct ahc_softc *ahc)
  2603. {
  2604. u_int scsisigo;
  2605. scsisigo = ATNO;
  2606. if ((ahc->features & AHC_DT) == 0)
  2607. scsisigo |= ahc_inb(ahc, SCSISIGI);
  2608. ahc_outb(ahc, SCSISIGO, scsisigo);
  2609. }
  2610. /*
  2611. * When an initiator transaction with the MK_MESSAGE flag either reconnects
  2612. * or enters the initial message out phase, we are interrupted. Fill our
  2613. * outgoing message buffer with the appropriate message and beging handing
  2614. * the message phase(s) manually.
  2615. */
  2616. static void
  2617. ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2618. struct scb *scb)
  2619. {
  2620. /*
  2621. * To facilitate adding multiple messages together,
  2622. * each routine should increment the index and len
  2623. * variables instead of setting them explicitly.
  2624. */
  2625. ahc->msgout_index = 0;
  2626. ahc->msgout_len = 0;
  2627. if ((scb->flags & SCB_DEVICE_RESET) == 0
  2628. && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
  2629. u_int identify_msg;
  2630. identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
  2631. if ((scb->hscb->control & DISCENB) != 0)
  2632. identify_msg |= MSG_IDENTIFY_DISCFLAG;
  2633. ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
  2634. ahc->msgout_len++;
  2635. if ((scb->hscb->control & TAG_ENB) != 0) {
  2636. ahc->msgout_buf[ahc->msgout_index++] =
  2637. scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
  2638. ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
  2639. ahc->msgout_len += 2;
  2640. }
  2641. }
  2642. if (scb->flags & SCB_DEVICE_RESET) {
  2643. ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
  2644. ahc->msgout_len++;
  2645. ahc_print_path(ahc, scb);
  2646. printf("Bus Device Reset Message Sent\n");
  2647. /*
  2648. * Clear our selection hardware in advance of
  2649. * the busfree. We may have an entry in the waiting
  2650. * Q for this target, and we don't want to go about
  2651. * selecting while we handle the busfree and blow it
  2652. * away.
  2653. */
  2654. ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
  2655. } else if ((scb->flags & SCB_ABORT) != 0) {
  2656. if ((scb->hscb->control & TAG_ENB) != 0)
  2657. ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
  2658. else
  2659. ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
  2660. ahc->msgout_len++;
  2661. ahc_print_path(ahc, scb);
  2662. printf("Abort%s Message Sent\n",
  2663. (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
  2664. /*
  2665. * Clear our selection hardware in advance of
  2666. * the busfree. We may have an entry in the waiting
  2667. * Q for this target, and we don't want to go about
  2668. * selecting while we handle the busfree and blow it
  2669. * away.
  2670. */
  2671. ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
  2672. } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
  2673. ahc_build_transfer_msg(ahc, devinfo);
  2674. } else {
  2675. printf("ahc_intr: AWAITING_MSG for an SCB that "
  2676. "does not have a waiting message\n");
  2677. printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
  2678. devinfo->target_mask);
  2679. panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
  2680. "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
  2681. ahc_inb(ahc, MSG_OUT), scb->flags);
  2682. }
  2683. /*
  2684. * Clear the MK_MESSAGE flag from the SCB so we aren't
  2685. * asked to send this message again.
  2686. */
  2687. ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
  2688. scb->hscb->control &= ~MK_MESSAGE;
  2689. ahc->msgout_index = 0;
  2690. ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  2691. }
  2692. /*
  2693. * Build an appropriate transfer negotiation message for the
  2694. * currently active target.
  2695. */
  2696. static void
  2697. ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  2698. {
  2699. /*
  2700. * We need to initiate transfer negotiations.
  2701. * If our current and goal settings are identical,
  2702. * we want to renegotiate due to a check condition.
  2703. */
  2704. struct ahc_initiator_tinfo *tinfo;
  2705. struct ahc_tmode_tstate *tstate;
  2706. const struct ahc_syncrate *rate;
  2707. int dowide;
  2708. int dosync;
  2709. int doppr;
  2710. u_int period;
  2711. u_int ppr_options;
  2712. u_int offset;
  2713. tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
  2714. devinfo->target, &tstate);
  2715. /*
  2716. * Filter our period based on the current connection.
  2717. * If we can't perform DT transfers on this segment (not in LVD
  2718. * mode for instance), then our decision to issue a PPR message
  2719. * may change.
  2720. */
  2721. period = tinfo->goal.period;
  2722. offset = tinfo->goal.offset;
  2723. ppr_options = tinfo->goal.ppr_options;
  2724. /* Target initiated PPR is not allowed in the SCSI spec */
  2725. if (devinfo->role == ROLE_TARGET)
  2726. ppr_options = 0;
  2727. rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
  2728. &ppr_options, devinfo->role);
  2729. dowide = tinfo->curr.width != tinfo->goal.width;
  2730. dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
  2731. /*
  2732. * Only use PPR if we have options that need it, even if the device
  2733. * claims to support it. There might be an expander in the way
  2734. * that doesn't.
  2735. */
  2736. doppr = ppr_options != 0;
  2737. if (!dowide && !dosync && !doppr) {
  2738. dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
  2739. dosync = tinfo->goal.offset != 0;
  2740. }
  2741. if (!dowide && !dosync && !doppr) {
  2742. /*
  2743. * Force async with a WDTR message if we have a wide bus,
  2744. * or just issue an SDTR with a 0 offset.
  2745. */
  2746. if ((ahc->features & AHC_WIDE) != 0)
  2747. dowide = 1;
  2748. else
  2749. dosync = 1;
  2750. if (bootverbose) {
  2751. ahc_print_devinfo(ahc, devinfo);
  2752. printf("Ensuring async\n");
  2753. }
  2754. }
  2755. /* Target initiated PPR is not allowed in the SCSI spec */
  2756. if (devinfo->role == ROLE_TARGET)
  2757. doppr = 0;
  2758. /*
  2759. * Both the PPR message and SDTR message require the
  2760. * goal syncrate to be limited to what the target device
  2761. * is capable of handling (based on whether an LVD->SE
  2762. * expander is on the bus), so combine these two cases.
  2763. * Regardless, guarantee that if we are using WDTR and SDTR
  2764. * messages that WDTR comes first.
  2765. */
  2766. if (doppr || (dosync && !dowide)) {
  2767. offset = tinfo->goal.offset;
  2768. ahc_validate_offset(ahc, tinfo, rate, &offset,
  2769. doppr ? tinfo->goal.width
  2770. : tinfo->curr.width,
  2771. devinfo->role);
  2772. if (doppr) {
  2773. ahc_construct_ppr(ahc, devinfo, period, offset,
  2774. tinfo->goal.width, ppr_options);
  2775. } else {
  2776. ahc_construct_sdtr(ahc, devinfo, period, offset);
  2777. }
  2778. } else {
  2779. ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
  2780. }
  2781. }
  2782. /*
  2783. * Build a synchronous negotiation message in our message
  2784. * buffer based on the input parameters.
  2785. */
  2786. static void
  2787. ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2788. u_int period, u_int offset)
  2789. {
  2790. if (offset == 0)
  2791. period = AHC_ASYNC_XFER_PERIOD;
  2792. ahc->msgout_index += spi_populate_sync_msg(
  2793. ahc->msgout_buf + ahc->msgout_index, period, offset);
  2794. ahc->msgout_len += 5;
  2795. if (bootverbose) {
  2796. printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
  2797. ahc_name(ahc), devinfo->channel, devinfo->target,
  2798. devinfo->lun, period, offset);
  2799. }
  2800. }
  2801. /*
  2802. * Build a wide negotiation message in our message
  2803. * buffer based on the input parameters.
  2804. */
  2805. static void
  2806. ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2807. u_int bus_width)
  2808. {
  2809. ahc->msgout_index += spi_populate_width_msg(
  2810. ahc->msgout_buf + ahc->msgout_index, bus_width);
  2811. ahc->msgout_len += 4;
  2812. if (bootverbose) {
  2813. printf("(%s:%c:%d:%d): Sending WDTR %x\n",
  2814. ahc_name(ahc), devinfo->channel, devinfo->target,
  2815. devinfo->lun, bus_width);
  2816. }
  2817. }
  2818. /*
  2819. * Build a parallel protocol request message in our message
  2820. * buffer based on the input parameters.
  2821. */
  2822. static void
  2823. ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  2824. u_int period, u_int offset, u_int bus_width,
  2825. u_int ppr_options)
  2826. {
  2827. if (offset == 0)
  2828. period = AHC_ASYNC_XFER_PERIOD;
  2829. ahc->msgout_index += spi_populate_ppr_msg(
  2830. ahc->msgout_buf + ahc->msgout_index, period, offset,
  2831. bus_width, ppr_options);
  2832. ahc->msgout_len += 8;
  2833. if (bootverbose) {
  2834. printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
  2835. "offset %x, ppr_options %x\n", ahc_name(ahc),
  2836. devinfo->channel, devinfo->target, devinfo->lun,
  2837. bus_width, period, offset, ppr_options);
  2838. }
  2839. }
  2840. /*
  2841. * Clear any active message state.
  2842. */
  2843. static void
  2844. ahc_clear_msg_state(struct ahc_softc *ahc)
  2845. {
  2846. ahc->msgout_len = 0;
  2847. ahc->msgin_index = 0;
  2848. ahc->msg_type = MSG_TYPE_NONE;
  2849. if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
  2850. /*
  2851. * The target didn't care to respond to our
  2852. * message request, so clear ATN.
  2853. */
  2854. ahc_outb(ahc, CLRSINT1, CLRATNO);
  2855. }
  2856. ahc_outb(ahc, MSG_OUT, MSG_NOOP);
  2857. ahc_outb(ahc, SEQ_FLAGS2,
  2858. ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
  2859. }
  2860. static void
  2861. ahc_handle_proto_violation(struct ahc_softc *ahc)
  2862. {
  2863. struct ahc_devinfo devinfo;
  2864. struct scb *scb;
  2865. u_int scbid;
  2866. u_int seq_flags;
  2867. u_int curphase;
  2868. u_int lastphase;
  2869. int found;
  2870. ahc_fetch_devinfo(ahc, &devinfo);
  2871. scbid = ahc_inb(ahc, SCB_TAG);
  2872. scb = ahc_lookup_scb(ahc, scbid);
  2873. seq_flags = ahc_inb(ahc, SEQ_FLAGS);
  2874. curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
  2875. lastphase = ahc_inb(ahc, LASTPHASE);
  2876. if ((seq_flags & NOT_IDENTIFIED) != 0) {
  2877. /*
  2878. * The reconnecting target either did not send an
  2879. * identify message, or did, but we didn't find an SCB
  2880. * to match.
  2881. */
  2882. ahc_print_devinfo(ahc, &devinfo);
  2883. printf("Target did not send an IDENTIFY message. "
  2884. "LASTPHASE = 0x%x.\n", lastphase);
  2885. scb = NULL;
  2886. } else if (scb == NULL) {
  2887. /*
  2888. * We don't seem to have an SCB active for this
  2889. * transaction. Print an error and reset the bus.
  2890. */
  2891. ahc_print_devinfo(ahc, &devinfo);
  2892. printf("No SCB found during protocol violation\n");
  2893. goto proto_violation_reset;
  2894. } else {
  2895. ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
  2896. if ((seq_flags & NO_CDB_SENT) != 0) {
  2897. ahc_print_path(ahc, scb);
  2898. printf("No or incomplete CDB sent to device.\n");
  2899. } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
  2900. /*
  2901. * The target never bothered to provide status to
  2902. * us prior to completing the command. Since we don't
  2903. * know the disposition of this command, we must attempt
  2904. * to abort it. Assert ATN and prepare to send an abort
  2905. * message.
  2906. */
  2907. ahc_print_path(ahc, scb);
  2908. printf("Completed command without status.\n");
  2909. } else {
  2910. ahc_print_path(ahc, scb);
  2911. printf("Unknown protocol violation.\n");
  2912. ahc_dump_card_state(ahc);
  2913. }
  2914. }
  2915. if ((lastphase & ~P_DATAIN_DT) == 0
  2916. || lastphase == P_COMMAND) {
  2917. proto_violation_reset:
  2918. /*
  2919. * Target either went directly to data/command
  2920. * phase or didn't respond to our ATN.
  2921. * The only safe thing to do is to blow
  2922. * it away with a bus reset.
  2923. */
  2924. found = ahc_reset_channel(ahc, 'A', TRUE);
  2925. printf("%s: Issued Channel %c Bus Reset. "
  2926. "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
  2927. } else {
  2928. /*
  2929. * Leave the selection hardware off in case
  2930. * this abort attempt will affect yet to
  2931. * be sent commands.
  2932. */
  2933. ahc_outb(ahc, SCSISEQ,
  2934. ahc_inb(ahc, SCSISEQ) & ~ENSELO);
  2935. ahc_assert_atn(ahc);
  2936. ahc_outb(ahc, MSG_OUT, HOST_MSG);
  2937. if (scb == NULL) {
  2938. ahc_print_devinfo(ahc, &devinfo);
  2939. ahc->msgout_buf[0] = MSG_ABORT_TASK;
  2940. ahc->msgout_len = 1;
  2941. ahc->msgout_index = 0;
  2942. ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  2943. } else {
  2944. ahc_print_path(ahc, scb);
  2945. scb->flags |= SCB_ABORT;
  2946. }
  2947. printf("Protocol violation %s. Attempting to abort.\n",
  2948. ahc_lookup_phase_entry(curphase)->phasemsg);
  2949. }
  2950. }
  2951. /*
  2952. * Manual message loop handler.
  2953. */
  2954. static void
  2955. ahc_handle_message_phase(struct ahc_softc *ahc)
  2956. {
  2957. struct ahc_devinfo devinfo;
  2958. u_int bus_phase;
  2959. int end_session;
  2960. ahc_fetch_devinfo(ahc, &devinfo);
  2961. end_session = FALSE;
  2962. bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
  2963. reswitch:
  2964. switch (ahc->msg_type) {
  2965. case MSG_TYPE_INITIATOR_MSGOUT:
  2966. {
  2967. int lastbyte;
  2968. int phasemis;
  2969. int msgdone;
  2970. if (ahc->msgout_len == 0)
  2971. panic("HOST_MSG_LOOP interrupt with no active message");
  2972. #ifdef AHC_DEBUG
  2973. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
  2974. ahc_print_devinfo(ahc, &devinfo);
  2975. printf("INITIATOR_MSG_OUT");
  2976. }
  2977. #endif
  2978. phasemis = bus_phase != P_MESGOUT;
  2979. if (phasemis) {
  2980. #ifdef AHC_DEBUG
  2981. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
  2982. printf(" PHASEMIS %s\n",
  2983. ahc_lookup_phase_entry(bus_phase)
  2984. ->phasemsg);
  2985. }
  2986. #endif
  2987. if (bus_phase == P_MESGIN) {
  2988. /*
  2989. * Change gears and see if
  2990. * this messages is of interest to
  2991. * us or should be passed back to
  2992. * the sequencer.
  2993. */
  2994. ahc_outb(ahc, CLRSINT1, CLRATNO);
  2995. ahc->send_msg_perror = FALSE;
  2996. ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
  2997. ahc->msgin_index = 0;
  2998. goto reswitch;
  2999. }
  3000. end_session = TRUE;
  3001. break;
  3002. }
  3003. if (ahc->send_msg_perror) {
  3004. ahc_outb(ahc, CLRSINT1, CLRATNO);
  3005. ahc_outb(ahc, CLRSINT1, CLRREQINIT);
  3006. #ifdef AHC_DEBUG
  3007. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
  3008. printf(" byte 0x%x\n", ahc->send_msg_perror);
  3009. #endif
  3010. ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
  3011. break;
  3012. }
  3013. msgdone = ahc->msgout_index == ahc->msgout_len;
  3014. if (msgdone) {
  3015. /*
  3016. * The target has requested a retry.
  3017. * Re-assert ATN, reset our message index to
  3018. * 0, and try again.
  3019. */
  3020. ahc->msgout_index = 0;
  3021. ahc_assert_atn(ahc);
  3022. }
  3023. lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
  3024. if (lastbyte) {
  3025. /* Last byte is signified by dropping ATN */
  3026. ahc_outb(ahc, CLRSINT1, CLRATNO);
  3027. }
  3028. /*
  3029. * Clear our interrupt status and present
  3030. * the next byte on the bus.
  3031. */
  3032. ahc_outb(ahc, CLRSINT1, CLRREQINIT);
  3033. #ifdef AHC_DEBUG
  3034. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
  3035. printf(" byte 0x%x\n",
  3036. ahc->msgout_buf[ahc->msgout_index]);
  3037. #endif
  3038. ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
  3039. break;
  3040. }
  3041. case MSG_TYPE_INITIATOR_MSGIN:
  3042. {
  3043. int phasemis;
  3044. int message_done;
  3045. #ifdef AHC_DEBUG
  3046. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
  3047. ahc_print_devinfo(ahc, &devinfo);
  3048. printf("INITIATOR_MSG_IN");
  3049. }
  3050. #endif
  3051. phasemis = bus_phase != P_MESGIN;
  3052. if (phasemis) {
  3053. #ifdef AHC_DEBUG
  3054. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
  3055. printf(" PHASEMIS %s\n",
  3056. ahc_lookup_phase_entry(bus_phase)
  3057. ->phasemsg);
  3058. }
  3059. #endif
  3060. ahc->msgin_index = 0;
  3061. if (bus_phase == P_MESGOUT
  3062. && (ahc->send_msg_perror == TRUE
  3063. || (ahc->msgout_len != 0
  3064. && ahc->msgout_index == 0))) {
  3065. ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  3066. goto reswitch;
  3067. }
  3068. end_session = TRUE;
  3069. break;
  3070. }
  3071. /* Pull the byte in without acking it */
  3072. ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
  3073. #ifdef AHC_DEBUG
  3074. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
  3075. printf(" byte 0x%x\n",
  3076. ahc->msgin_buf[ahc->msgin_index]);
  3077. #endif
  3078. message_done = ahc_parse_msg(ahc, &devinfo);
  3079. if (message_done) {
  3080. /*
  3081. * Clear our incoming message buffer in case there
  3082. * is another message following this one.
  3083. */
  3084. ahc->msgin_index = 0;
  3085. /*
  3086. * If this message illicited a response,
  3087. * assert ATN so the target takes us to the
  3088. * message out phase.
  3089. */
  3090. if (ahc->msgout_len != 0) {
  3091. #ifdef AHC_DEBUG
  3092. if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
  3093. ahc_print_devinfo(ahc, &devinfo);
  3094. printf("Asserting ATN for response\n");
  3095. }
  3096. #endif
  3097. ahc_assert_atn(ahc);
  3098. }
  3099. } else
  3100. ahc->msgin_index++;
  3101. if (message_done == MSGLOOP_TERMINATED) {
  3102. end_session = TRUE;
  3103. } else {
  3104. /* Ack the byte */
  3105. ahc_outb(ahc, CLRSINT1, CLRREQINIT);
  3106. ahc_inb(ahc, SCSIDATL);
  3107. }
  3108. break;
  3109. }
  3110. case MSG_TYPE_TARGET_MSGIN:
  3111. {
  3112. int msgdone;
  3113. int msgout_request;
  3114. if (ahc->msgout_len == 0)
  3115. panic("Target MSGIN with no active message");
  3116. /*
  3117. * If we interrupted a mesgout session, the initiator
  3118. * will not know this until our first REQ. So, we
  3119. * only honor mesgout requests after we've sent our
  3120. * first byte.
  3121. */
  3122. if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
  3123. && ahc->msgout_index > 0)
  3124. msgout_request = TRUE;
  3125. else
  3126. msgout_request = FALSE;
  3127. if (msgout_request) {
  3128. /*
  3129. * Change gears and see if
  3130. * this messages is of interest to
  3131. * us or should be passed back to
  3132. * the sequencer.
  3133. */
  3134. ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
  3135. ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
  3136. ahc->msgin_index = 0;
  3137. /* Dummy read to REQ for first byte */
  3138. ahc_inb(ahc, SCSIDATL);
  3139. ahc_outb(ahc, SXFRCTL0,
  3140. ahc_inb(ahc, SXFRCTL0) | SPIOEN);
  3141. break;
  3142. }
  3143. msgdone = ahc->msgout_index == ahc->msgout_len;
  3144. if (msgdone) {
  3145. ahc_outb(ahc, SXFRCTL0,
  3146. ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
  3147. end_session = TRUE;
  3148. break;
  3149. }
  3150. /*
  3151. * Present the next byte on the bus.
  3152. */
  3153. ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
  3154. ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
  3155. break;
  3156. }
  3157. case MSG_TYPE_TARGET_MSGOUT:
  3158. {
  3159. int lastbyte;
  3160. int msgdone;
  3161. /*
  3162. * The initiator signals that this is
  3163. * the last byte by dropping ATN.
  3164. */
  3165. lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
  3166. /*
  3167. * Read the latched byte, but turn off SPIOEN first
  3168. * so that we don't inadvertently cause a REQ for the
  3169. * next byte.
  3170. */
  3171. ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
  3172. ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
  3173. msgdone = ahc_parse_msg(ahc, &devinfo);
  3174. if (msgdone == MSGLOOP_TERMINATED) {
  3175. /*
  3176. * The message is *really* done in that it caused
  3177. * us to go to bus free. The sequencer has already
  3178. * been reset at this point, so pull the ejection
  3179. * handle.
  3180. */
  3181. return;
  3182. }
  3183. ahc->msgin_index++;
  3184. /*
  3185. * XXX Read spec about initiator dropping ATN too soon
  3186. * and use msgdone to detect it.
  3187. */
  3188. if (msgdone == MSGLOOP_MSGCOMPLETE) {
  3189. ahc->msgin_index = 0;
  3190. /*
  3191. * If this message illicited a response, transition
  3192. * to the Message in phase and send it.
  3193. */
  3194. if (ahc->msgout_len != 0) {
  3195. ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
  3196. ahc_outb(ahc, SXFRCTL0,
  3197. ahc_inb(ahc, SXFRCTL0) | SPIOEN);
  3198. ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
  3199. ahc->msgin_index = 0;
  3200. break;
  3201. }
  3202. }
  3203. if (lastbyte)
  3204. end_session = TRUE;
  3205. else {
  3206. /* Ask for the next byte. */
  3207. ahc_outb(ahc, SXFRCTL0,
  3208. ahc_inb(ahc, SXFRCTL0) | SPIOEN);
  3209. }
  3210. break;
  3211. }
  3212. default:
  3213. panic("Unknown REQINIT message type");
  3214. }
  3215. if (end_session) {
  3216. ahc_clear_msg_state(ahc);
  3217. ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
  3218. } else
  3219. ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
  3220. }
  3221. /*
  3222. * See if we sent a particular extended message to the target.
  3223. * If "full" is true, return true only if the target saw the full
  3224. * message. If "full" is false, return true if the target saw at
  3225. * least the first byte of the message.
  3226. */
  3227. static int
  3228. ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
  3229. {
  3230. int found;
  3231. u_int index;
  3232. found = FALSE;
  3233. index = 0;
  3234. while (index < ahc->msgout_len) {
  3235. if (ahc->msgout_buf[index] == MSG_EXTENDED) {
  3236. u_int end_index;
  3237. end_index = index + 1 + ahc->msgout_buf[index + 1];
  3238. if (ahc->msgout_buf[index+2] == msgval
  3239. && type == AHCMSG_EXT) {
  3240. if (full) {
  3241. if (ahc->msgout_index > end_index)
  3242. found = TRUE;
  3243. } else if (ahc->msgout_index > index)
  3244. found = TRUE;
  3245. }
  3246. index = end_index;
  3247. } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
  3248. && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
  3249. /* Skip tag type and tag id or residue param*/
  3250. index += 2;
  3251. } else {
  3252. /* Single byte message */
  3253. if (type == AHCMSG_1B
  3254. && ahc->msgout_buf[index] == msgval
  3255. && ahc->msgout_index > index)
  3256. found = TRUE;
  3257. index++;
  3258. }
  3259. if (found)
  3260. break;
  3261. }
  3262. return (found);
  3263. }
  3264. /*
  3265. * Wait for a complete incoming message, parse it, and respond accordingly.
  3266. */
  3267. static int
  3268. ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  3269. {
  3270. struct ahc_initiator_tinfo *tinfo;
  3271. struct ahc_tmode_tstate *tstate;
  3272. int reject;
  3273. int done;
  3274. int response;
  3275. u_int targ_scsirate;
  3276. done = MSGLOOP_IN_PROG;
  3277. response = FALSE;
  3278. reject = FALSE;
  3279. tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
  3280. devinfo->target, &tstate);
  3281. targ_scsirate = tinfo->scsirate;
  3282. /*
  3283. * Parse as much of the message as is available,
  3284. * rejecting it if we don't support it. When
  3285. * the entire message is available and has been
  3286. * handled, return MSGLOOP_MSGCOMPLETE, indicating
  3287. * that we have parsed an entire message.
  3288. *
  3289. * In the case of extended messages, we accept the length
  3290. * byte outright and perform more checking once we know the
  3291. * extended message type.
  3292. */
  3293. switch (ahc->msgin_buf[0]) {
  3294. case MSG_DISCONNECT:
  3295. case MSG_SAVEDATAPOINTER:
  3296. case MSG_CMDCOMPLETE:
  3297. case MSG_RESTOREPOINTERS:
  3298. case MSG_IGN_WIDE_RESIDUE:
  3299. /*
  3300. * End our message loop as these are messages
  3301. * the sequencer handles on its own.
  3302. */
  3303. done = MSGLOOP_TERMINATED;
  3304. break;
  3305. case MSG_MESSAGE_REJECT:
  3306. response = ahc_handle_msg_reject(ahc, devinfo);
  3307. /* FALLTHROUGH */
  3308. case MSG_NOOP:
  3309. done = MSGLOOP_MSGCOMPLETE;
  3310. break;
  3311. case MSG_EXTENDED:
  3312. {
  3313. /* Wait for enough of the message to begin validation */
  3314. if (ahc->msgin_index < 2)
  3315. break;
  3316. switch (ahc->msgin_buf[2]) {
  3317. case MSG_EXT_SDTR:
  3318. {
  3319. const struct ahc_syncrate *syncrate;
  3320. u_int period;
  3321. u_int ppr_options;
  3322. u_int offset;
  3323. u_int saved_offset;
  3324. if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
  3325. reject = TRUE;
  3326. break;
  3327. }
  3328. /*
  3329. * Wait until we have both args before validating
  3330. * and acting on this message.
  3331. *
  3332. * Add one to MSG_EXT_SDTR_LEN to account for
  3333. * the extended message preamble.
  3334. */
  3335. if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
  3336. break;
  3337. period = ahc->msgin_buf[3];
  3338. ppr_options = 0;
  3339. saved_offset = offset = ahc->msgin_buf[4];
  3340. syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
  3341. &ppr_options,
  3342. devinfo->role);
  3343. ahc_validate_offset(ahc, tinfo, syncrate, &offset,
  3344. targ_scsirate & WIDEXFER,
  3345. devinfo->role);
  3346. if (bootverbose) {
  3347. printf("(%s:%c:%d:%d): Received "
  3348. "SDTR period %x, offset %x\n\t"
  3349. "Filtered to period %x, offset %x\n",
  3350. ahc_name(ahc), devinfo->channel,
  3351. devinfo->target, devinfo->lun,
  3352. ahc->msgin_buf[3], saved_offset,
  3353. period, offset);
  3354. }
  3355. ahc_set_syncrate(ahc, devinfo,
  3356. syncrate, period,
  3357. offset, ppr_options,
  3358. AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
  3359. /*paused*/TRUE);
  3360. /*
  3361. * See if we initiated Sync Negotiation
  3362. * and didn't have to fall down to async
  3363. * transfers.
  3364. */
  3365. if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
  3366. /* We started it */
  3367. if (saved_offset != offset) {
  3368. /* Went too low - force async */
  3369. reject = TRUE;
  3370. }
  3371. } else {
  3372. /*
  3373. * Send our own SDTR in reply
  3374. */
  3375. if (bootverbose
  3376. && devinfo->role == ROLE_INITIATOR) {
  3377. printf("(%s:%c:%d:%d): Target "
  3378. "Initiated SDTR\n",
  3379. ahc_name(ahc), devinfo->channel,
  3380. devinfo->target, devinfo->lun);
  3381. }
  3382. ahc->msgout_index = 0;
  3383. ahc->msgout_len = 0;
  3384. ahc_construct_sdtr(ahc, devinfo,
  3385. period, offset);
  3386. ahc->msgout_index = 0;
  3387. response = TRUE;
  3388. }
  3389. done = MSGLOOP_MSGCOMPLETE;
  3390. break;
  3391. }
  3392. case MSG_EXT_WDTR:
  3393. {
  3394. u_int bus_width;
  3395. u_int saved_width;
  3396. u_int sending_reply;
  3397. sending_reply = FALSE;
  3398. if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
  3399. reject = TRUE;
  3400. break;
  3401. }
  3402. /*
  3403. * Wait until we have our arg before validating
  3404. * and acting on this message.
  3405. *
  3406. * Add one to MSG_EXT_WDTR_LEN to account for
  3407. * the extended message preamble.
  3408. */
  3409. if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
  3410. break;
  3411. bus_width = ahc->msgin_buf[3];
  3412. saved_width = bus_width;
  3413. ahc_validate_width(ahc, tinfo, &bus_width,
  3414. devinfo->role);
  3415. if (bootverbose) {
  3416. printf("(%s:%c:%d:%d): Received WDTR "
  3417. "%x filtered to %x\n",
  3418. ahc_name(ahc), devinfo->channel,
  3419. devinfo->target, devinfo->lun,
  3420. saved_width, bus_width);
  3421. }
  3422. if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
  3423. /*
  3424. * Don't send a WDTR back to the
  3425. * target, since we asked first.
  3426. * If the width went higher than our
  3427. * request, reject it.
  3428. */
  3429. if (saved_width > bus_width) {
  3430. reject = TRUE;
  3431. printf("(%s:%c:%d:%d): requested %dBit "
  3432. "transfers. Rejecting...\n",
  3433. ahc_name(ahc), devinfo->channel,
  3434. devinfo->target, devinfo->lun,
  3435. 8 * (0x01 << bus_width));
  3436. bus_width = 0;
  3437. }
  3438. } else {
  3439. /*
  3440. * Send our own WDTR in reply
  3441. */
  3442. if (bootverbose
  3443. && devinfo->role == ROLE_INITIATOR) {
  3444. printf("(%s:%c:%d:%d): Target "
  3445. "Initiated WDTR\n",
  3446. ahc_name(ahc), devinfo->channel,
  3447. devinfo->target, devinfo->lun);
  3448. }
  3449. ahc->msgout_index = 0;
  3450. ahc->msgout_len = 0;
  3451. ahc_construct_wdtr(ahc, devinfo, bus_width);
  3452. ahc->msgout_index = 0;
  3453. response = TRUE;
  3454. sending_reply = TRUE;
  3455. }
  3456. /*
  3457. * After a wide message, we are async, but
  3458. * some devices don't seem to honor this portion
  3459. * of the spec. Force a renegotiation of the
  3460. * sync component of our transfer agreement even
  3461. * if our goal is async. By updating our width
  3462. * after forcing the negotiation, we avoid
  3463. * renegotiating for width.
  3464. */
  3465. ahc_update_neg_request(ahc, devinfo, tstate,
  3466. tinfo, AHC_NEG_ALWAYS);
  3467. ahc_set_width(ahc, devinfo, bus_width,
  3468. AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
  3469. /*paused*/TRUE);
  3470. if (sending_reply == FALSE && reject == FALSE) {
  3471. /*
  3472. * We will always have an SDTR to send.
  3473. */
  3474. ahc->msgout_index = 0;
  3475. ahc->msgout_len = 0;
  3476. ahc_build_transfer_msg(ahc, devinfo);
  3477. ahc->msgout_index = 0;
  3478. response = TRUE;
  3479. }
  3480. done = MSGLOOP_MSGCOMPLETE;
  3481. break;
  3482. }
  3483. case MSG_EXT_PPR:
  3484. {
  3485. const struct ahc_syncrate *syncrate;
  3486. u_int period;
  3487. u_int offset;
  3488. u_int bus_width;
  3489. u_int ppr_options;
  3490. u_int saved_width;
  3491. u_int saved_offset;
  3492. u_int saved_ppr_options;
  3493. if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
  3494. reject = TRUE;
  3495. break;
  3496. }
  3497. /*
  3498. * Wait until we have all args before validating
  3499. * and acting on this message.
  3500. *
  3501. * Add one to MSG_EXT_PPR_LEN to account for
  3502. * the extended message preamble.
  3503. */
  3504. if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
  3505. break;
  3506. period = ahc->msgin_buf[3];
  3507. offset = ahc->msgin_buf[5];
  3508. bus_width = ahc->msgin_buf[6];
  3509. saved_width = bus_width;
  3510. ppr_options = ahc->msgin_buf[7];
  3511. /*
  3512. * According to the spec, a DT only
  3513. * period factor with no DT option
  3514. * set implies async.
  3515. */
  3516. if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
  3517. && period == 9)
  3518. offset = 0;
  3519. saved_ppr_options = ppr_options;
  3520. saved_offset = offset;
  3521. /*
  3522. * Mask out any options we don't support
  3523. * on any controller. Transfer options are
  3524. * only available if we are negotiating wide.
  3525. */
  3526. ppr_options &= MSG_EXT_PPR_DT_REQ;
  3527. if (bus_width == 0)
  3528. ppr_options = 0;
  3529. ahc_validate_width(ahc, tinfo, &bus_width,
  3530. devinfo->role);
  3531. syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
  3532. &ppr_options,
  3533. devinfo->role);
  3534. ahc_validate_offset(ahc, tinfo, syncrate,
  3535. &offset, bus_width,
  3536. devinfo->role);
  3537. if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
  3538. /*
  3539. * If we are unable to do any of the
  3540. * requested options (we went too low),
  3541. * then we'll have to reject the message.
  3542. */
  3543. if (saved_width > bus_width
  3544. || saved_offset != offset
  3545. || saved_ppr_options != ppr_options) {
  3546. reject = TRUE;
  3547. period = 0;
  3548. offset = 0;
  3549. bus_width = 0;
  3550. ppr_options = 0;
  3551. syncrate = NULL;
  3552. }
  3553. } else {
  3554. if (devinfo->role != ROLE_TARGET)
  3555. printf("(%s:%c:%d:%d): Target "
  3556. "Initiated PPR\n",
  3557. ahc_name(ahc), devinfo->channel,
  3558. devinfo->target, devinfo->lun);
  3559. else
  3560. printf("(%s:%c:%d:%d): Initiator "
  3561. "Initiated PPR\n",
  3562. ahc_name(ahc), devinfo->channel,
  3563. devinfo->target, devinfo->lun);
  3564. ahc->msgout_index = 0;
  3565. ahc->msgout_len = 0;
  3566. ahc_construct_ppr(ahc, devinfo, period, offset,
  3567. bus_width, ppr_options);
  3568. ahc->msgout_index = 0;
  3569. response = TRUE;
  3570. }
  3571. if (bootverbose) {
  3572. printf("(%s:%c:%d:%d): Received PPR width %x, "
  3573. "period %x, offset %x,options %x\n"
  3574. "\tFiltered to width %x, period %x, "
  3575. "offset %x, options %x\n",
  3576. ahc_name(ahc), devinfo->channel,
  3577. devinfo->target, devinfo->lun,
  3578. saved_width, ahc->msgin_buf[3],
  3579. saved_offset, saved_ppr_options,
  3580. bus_width, period, offset, ppr_options);
  3581. }
  3582. ahc_set_width(ahc, devinfo, bus_width,
  3583. AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
  3584. /*paused*/TRUE);
  3585. ahc_set_syncrate(ahc, devinfo,
  3586. syncrate, period,
  3587. offset, ppr_options,
  3588. AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
  3589. /*paused*/TRUE);
  3590. done = MSGLOOP_MSGCOMPLETE;
  3591. break;
  3592. }
  3593. default:
  3594. /* Unknown extended message. Reject it. */
  3595. reject = TRUE;
  3596. break;
  3597. }
  3598. break;
  3599. }
  3600. #ifdef AHC_TARGET_MODE
  3601. case MSG_BUS_DEV_RESET:
  3602. ahc_handle_devreset(ahc, devinfo,
  3603. CAM_BDR_SENT,
  3604. "Bus Device Reset Received",
  3605. /*verbose_level*/0);
  3606. ahc_restart(ahc);
  3607. done = MSGLOOP_TERMINATED;
  3608. break;
  3609. case MSG_ABORT_TAG:
  3610. case MSG_ABORT:
  3611. case MSG_CLEAR_QUEUE:
  3612. {
  3613. int tag;
  3614. /* Target mode messages */
  3615. if (devinfo->role != ROLE_TARGET) {
  3616. reject = TRUE;
  3617. break;
  3618. }
  3619. tag = SCB_LIST_NULL;
  3620. if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
  3621. tag = ahc_inb(ahc, INITIATOR_TAG);
  3622. ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
  3623. devinfo->lun, tag, ROLE_TARGET,
  3624. CAM_REQ_ABORTED);
  3625. tstate = ahc->enabled_targets[devinfo->our_scsiid];
  3626. if (tstate != NULL) {
  3627. struct ahc_tmode_lstate* lstate;
  3628. lstate = tstate->enabled_luns[devinfo->lun];
  3629. if (lstate != NULL) {
  3630. ahc_queue_lstate_event(ahc, lstate,
  3631. devinfo->our_scsiid,
  3632. ahc->msgin_buf[0],
  3633. /*arg*/tag);
  3634. ahc_send_lstate_events(ahc, lstate);
  3635. }
  3636. }
  3637. ahc_restart(ahc);
  3638. done = MSGLOOP_TERMINATED;
  3639. break;
  3640. }
  3641. #endif
  3642. case MSG_TERM_IO_PROC:
  3643. default:
  3644. reject = TRUE;
  3645. break;
  3646. }
  3647. if (reject) {
  3648. /*
  3649. * Setup to reject the message.
  3650. */
  3651. ahc->msgout_index = 0;
  3652. ahc->msgout_len = 1;
  3653. ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
  3654. done = MSGLOOP_MSGCOMPLETE;
  3655. response = TRUE;
  3656. }
  3657. if (done != MSGLOOP_IN_PROG && !response)
  3658. /* Clear the outgoing message buffer */
  3659. ahc->msgout_len = 0;
  3660. return (done);
  3661. }
  3662. /*
  3663. * Process a message reject message.
  3664. */
  3665. static int
  3666. ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  3667. {
  3668. /*
  3669. * What we care about here is if we had an
  3670. * outstanding SDTR or WDTR message for this
  3671. * target. If we did, this is a signal that
  3672. * the target is refusing negotiation.
  3673. */
  3674. struct scb *scb;
  3675. struct ahc_initiator_tinfo *tinfo;
  3676. struct ahc_tmode_tstate *tstate;
  3677. u_int scb_index;
  3678. u_int last_msg;
  3679. int response = 0;
  3680. scb_index = ahc_inb(ahc, SCB_TAG);
  3681. scb = ahc_lookup_scb(ahc, scb_index);
  3682. tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
  3683. devinfo->our_scsiid,
  3684. devinfo->target, &tstate);
  3685. /* Might be necessary */
  3686. last_msg = ahc_inb(ahc, LAST_MSG);
  3687. if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
  3688. /*
  3689. * Target does not support the PPR message.
  3690. * Attempt to negotiate SPI-2 style.
  3691. */
  3692. if (bootverbose) {
  3693. printf("(%s:%c:%d:%d): PPR Rejected. "
  3694. "Trying WDTR/SDTR\n",
  3695. ahc_name(ahc), devinfo->channel,
  3696. devinfo->target, devinfo->lun);
  3697. }
  3698. tinfo->goal.ppr_options = 0;
  3699. tinfo->curr.transport_version = 2;
  3700. tinfo->goal.transport_version = 2;
  3701. ahc->msgout_index = 0;
  3702. ahc->msgout_len = 0;
  3703. ahc_build_transfer_msg(ahc, devinfo);
  3704. ahc->msgout_index = 0;
  3705. response = 1;
  3706. } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
  3707. /* note 8bit xfers */
  3708. printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
  3709. "8bit transfers\n", ahc_name(ahc),
  3710. devinfo->channel, devinfo->target, devinfo->lun);
  3711. ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  3712. AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
  3713. /*paused*/TRUE);
  3714. /*
  3715. * No need to clear the sync rate. If the target
  3716. * did not accept the command, our syncrate is
  3717. * unaffected. If the target started the negotiation,
  3718. * but rejected our response, we already cleared the
  3719. * sync rate before sending our WDTR.
  3720. */
  3721. if (tinfo->goal.offset != tinfo->curr.offset) {
  3722. /* Start the sync negotiation */
  3723. ahc->msgout_index = 0;
  3724. ahc->msgout_len = 0;
  3725. ahc_build_transfer_msg(ahc, devinfo);
  3726. ahc->msgout_index = 0;
  3727. response = 1;
  3728. }
  3729. } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
  3730. /* note asynch xfers and clear flag */
  3731. ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
  3732. /*offset*/0, /*ppr_options*/0,
  3733. AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
  3734. /*paused*/TRUE);
  3735. printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
  3736. "Using asynchronous transfers\n",
  3737. ahc_name(ahc), devinfo->channel,
  3738. devinfo->target, devinfo->lun);
  3739. } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
  3740. int tag_type;
  3741. int mask;
  3742. tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
  3743. if (tag_type == MSG_SIMPLE_TASK) {
  3744. printf("(%s:%c:%d:%d): refuses tagged commands. "
  3745. "Performing non-tagged I/O\n", ahc_name(ahc),
  3746. devinfo->channel, devinfo->target, devinfo->lun);
  3747. ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
  3748. mask = ~0x23;
  3749. } else {
  3750. printf("(%s:%c:%d:%d): refuses %s tagged commands. "
  3751. "Performing simple queue tagged I/O only\n",
  3752. ahc_name(ahc), devinfo->channel, devinfo->target,
  3753. devinfo->lun, tag_type == MSG_ORDERED_TASK
  3754. ? "ordered" : "head of queue");
  3755. ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
  3756. mask = ~0x03;
  3757. }
  3758. /*
  3759. * Resend the identify for this CCB as the target
  3760. * may believe that the selection is invalid otherwise.
  3761. */
  3762. ahc_outb(ahc, SCB_CONTROL,
  3763. ahc_inb(ahc, SCB_CONTROL) & mask);
  3764. scb->hscb->control &= mask;
  3765. ahc_set_transaction_tag(scb, /*enabled*/FALSE,
  3766. /*type*/MSG_SIMPLE_TASK);
  3767. ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
  3768. ahc_assert_atn(ahc);
  3769. /*
  3770. * This transaction is now at the head of
  3771. * the untagged queue for this target.
  3772. */
  3773. if ((ahc->flags & AHC_SCB_BTT) == 0) {
  3774. struct scb_tailq *untagged_q;
  3775. untagged_q =
  3776. &(ahc->untagged_queues[devinfo->target_offset]);
  3777. TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
  3778. scb->flags |= SCB_UNTAGGEDQ;
  3779. }
  3780. ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
  3781. scb->hscb->tag);
  3782. /*
  3783. * Requeue all tagged commands for this target
  3784. * currently in our posession so they can be
  3785. * converted to untagged commands.
  3786. */
  3787. ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
  3788. SCB_GET_CHANNEL(ahc, scb),
  3789. SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
  3790. ROLE_INITIATOR, CAM_REQUEUE_REQ,
  3791. SEARCH_COMPLETE);
  3792. } else {
  3793. /*
  3794. * Otherwise, we ignore it.
  3795. */
  3796. printf("%s:%c:%d: Message reject for %x -- ignored\n",
  3797. ahc_name(ahc), devinfo->channel, devinfo->target,
  3798. last_msg);
  3799. }
  3800. return (response);
  3801. }
  3802. /*
  3803. * Process an ingnore wide residue message.
  3804. */
  3805. static void
  3806. ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
  3807. {
  3808. u_int scb_index;
  3809. struct scb *scb;
  3810. scb_index = ahc_inb(ahc, SCB_TAG);
  3811. scb = ahc_lookup_scb(ahc, scb_index);
  3812. /*
  3813. * XXX Actually check data direction in the sequencer?
  3814. * Perhaps add datadir to some spare bits in the hscb?
  3815. */
  3816. if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
  3817. || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
  3818. /*
  3819. * Ignore the message if we haven't
  3820. * seen an appropriate data phase yet.
  3821. */
  3822. } else {
  3823. /*
  3824. * If the residual occurred on the last
  3825. * transfer and the transfer request was
  3826. * expected to end on an odd count, do
  3827. * nothing. Otherwise, subtract a byte
  3828. * and update the residual count accordingly.
  3829. */
  3830. uint32_t sgptr;
  3831. sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
  3832. if ((sgptr & SG_LIST_NULL) != 0
  3833. && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
  3834. /*
  3835. * If the residual occurred on the last
  3836. * transfer and the transfer request was
  3837. * expected to end on an odd count, do
  3838. * nothing.
  3839. */
  3840. } else {
  3841. struct ahc_dma_seg *sg;
  3842. uint32_t data_cnt;
  3843. uint32_t data_addr;
  3844. uint32_t sglen;
  3845. /* Pull in all of the sgptr */
  3846. sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
  3847. data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
  3848. if ((sgptr & SG_LIST_NULL) != 0) {
  3849. /*
  3850. * The residual data count is not updated
  3851. * for the command run to completion case.
  3852. * Explicitly zero the count.
  3853. */
  3854. data_cnt &= ~AHC_SG_LEN_MASK;
  3855. }
  3856. data_addr = ahc_inl(ahc, SHADDR);
  3857. data_cnt += 1;
  3858. data_addr -= 1;
  3859. sgptr &= SG_PTR_MASK;
  3860. sg = ahc_sg_bus_to_virt(scb, sgptr);
  3861. /*
  3862. * The residual sg ptr points to the next S/G
  3863. * to load so we must go back one.
  3864. */
  3865. sg--;
  3866. sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
  3867. if (sg != scb->sg_list
  3868. && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
  3869. sg--;
  3870. sglen = ahc_le32toh(sg->len);
  3871. /*
  3872. * Preserve High Address and SG_LIST bits
  3873. * while setting the count to 1.
  3874. */
  3875. data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
  3876. data_addr = ahc_le32toh(sg->addr)
  3877. + (sglen & AHC_SG_LEN_MASK) - 1;
  3878. /*
  3879. * Increment sg so it points to the
  3880. * "next" sg.
  3881. */
  3882. sg++;
  3883. sgptr = ahc_sg_virt_to_bus(scb, sg);
  3884. }
  3885. ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
  3886. ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
  3887. /*
  3888. * Toggle the "oddness" of the transfer length
  3889. * to handle this mid-transfer ignore wide
  3890. * residue. This ensures that the oddness is
  3891. * correct for subsequent data transfers.
  3892. */
  3893. ahc_outb(ahc, SCB_LUN,
  3894. ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
  3895. }
  3896. }
  3897. }
  3898. /*
  3899. * Reinitialize the data pointers for the active transfer
  3900. * based on its current residual.
  3901. */
  3902. static void
  3903. ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
  3904. {
  3905. struct scb *scb;
  3906. struct ahc_dma_seg *sg;
  3907. u_int scb_index;
  3908. uint32_t sgptr;
  3909. uint32_t resid;
  3910. uint32_t dataptr;
  3911. scb_index = ahc_inb(ahc, SCB_TAG);
  3912. scb = ahc_lookup_scb(ahc, scb_index);
  3913. sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
  3914. | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
  3915. | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
  3916. | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
  3917. sgptr &= SG_PTR_MASK;
  3918. sg = ahc_sg_bus_to_virt(scb, sgptr);
  3919. /* The residual sg_ptr always points to the next sg */
  3920. sg--;
  3921. resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
  3922. | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
  3923. | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
  3924. dataptr = ahc_le32toh(sg->addr)
  3925. + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
  3926. - resid;
  3927. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  3928. u_int dscommand1;
  3929. dscommand1 = ahc_inb(ahc, DSCOMMAND1);
  3930. ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
  3931. ahc_outb(ahc, HADDR,
  3932. (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
  3933. ahc_outb(ahc, DSCOMMAND1, dscommand1);
  3934. }
  3935. ahc_outb(ahc, HADDR + 3, dataptr >> 24);
  3936. ahc_outb(ahc, HADDR + 2, dataptr >> 16);
  3937. ahc_outb(ahc, HADDR + 1, dataptr >> 8);
  3938. ahc_outb(ahc, HADDR, dataptr);
  3939. ahc_outb(ahc, HCNT + 2, resid >> 16);
  3940. ahc_outb(ahc, HCNT + 1, resid >> 8);
  3941. ahc_outb(ahc, HCNT, resid);
  3942. if ((ahc->features & AHC_ULTRA2) == 0) {
  3943. ahc_outb(ahc, STCNT + 2, resid >> 16);
  3944. ahc_outb(ahc, STCNT + 1, resid >> 8);
  3945. ahc_outb(ahc, STCNT, resid);
  3946. }
  3947. }
  3948. /*
  3949. * Handle the effects of issuing a bus device reset message.
  3950. */
  3951. static void
  3952. ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  3953. cam_status status, char *message, int verbose_level)
  3954. {
  3955. #ifdef AHC_TARGET_MODE
  3956. struct ahc_tmode_tstate* tstate;
  3957. u_int lun;
  3958. #endif
  3959. int found;
  3960. found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
  3961. CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
  3962. status);
  3963. #ifdef AHC_TARGET_MODE
  3964. /*
  3965. * Send an immediate notify ccb to all target mord peripheral
  3966. * drivers affected by this action.
  3967. */
  3968. tstate = ahc->enabled_targets[devinfo->our_scsiid];
  3969. if (tstate != NULL) {
  3970. for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
  3971. struct ahc_tmode_lstate* lstate;
  3972. lstate = tstate->enabled_luns[lun];
  3973. if (lstate == NULL)
  3974. continue;
  3975. ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
  3976. MSG_BUS_DEV_RESET, /*arg*/0);
  3977. ahc_send_lstate_events(ahc, lstate);
  3978. }
  3979. }
  3980. #endif
  3981. /*
  3982. * Go back to async/narrow transfers and renegotiate.
  3983. */
  3984. ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  3985. AHC_TRANS_CUR, /*paused*/TRUE);
  3986. ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
  3987. /*period*/0, /*offset*/0, /*ppr_options*/0,
  3988. AHC_TRANS_CUR, /*paused*/TRUE);
  3989. if (status != CAM_SEL_TIMEOUT)
  3990. ahc_send_async(ahc, devinfo->channel, devinfo->target,
  3991. CAM_LUN_WILDCARD, AC_SENT_BDR);
  3992. if (message != NULL
  3993. && (verbose_level <= bootverbose))
  3994. printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
  3995. message, devinfo->channel, devinfo->target, found);
  3996. }
  3997. #ifdef AHC_TARGET_MODE
  3998. static void
  3999. ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
  4000. struct scb *scb)
  4001. {
  4002. /*
  4003. * To facilitate adding multiple messages together,
  4004. * each routine should increment the index and len
  4005. * variables instead of setting them explicitly.
  4006. */
  4007. ahc->msgout_index = 0;
  4008. ahc->msgout_len = 0;
  4009. if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
  4010. ahc_build_transfer_msg(ahc, devinfo);
  4011. else
  4012. panic("ahc_intr: AWAITING target message with no message");
  4013. ahc->msgout_index = 0;
  4014. ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
  4015. }
  4016. #endif
  4017. /**************************** Initialization **********************************/
  4018. /*
  4019. * Allocate a controller structure for a new device
  4020. * and perform initial initializion.
  4021. */
  4022. struct ahc_softc *
  4023. ahc_alloc(void *platform_arg, char *name)
  4024. {
  4025. struct ahc_softc *ahc;
  4026. int i;
  4027. #ifndef __FreeBSD__
  4028. ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
  4029. if (!ahc) {
  4030. printf("aic7xxx: cannot malloc softc!\n");
  4031. free(name, M_DEVBUF);
  4032. return NULL;
  4033. }
  4034. #else
  4035. ahc = device_get_softc((device_t)platform_arg);
  4036. #endif
  4037. memset(ahc, 0, sizeof(*ahc));
  4038. ahc->seep_config = malloc(sizeof(*ahc->seep_config),
  4039. M_DEVBUF, M_NOWAIT);
  4040. if (ahc->seep_config == NULL) {
  4041. #ifndef __FreeBSD__
  4042. free(ahc, M_DEVBUF);
  4043. #endif
  4044. free(name, M_DEVBUF);
  4045. return (NULL);
  4046. }
  4047. LIST_INIT(&ahc->pending_scbs);
  4048. /* We don't know our unit number until the OSM sets it */
  4049. ahc->name = name;
  4050. ahc->unit = -1;
  4051. ahc->description = NULL;
  4052. ahc->channel = 'A';
  4053. ahc->channel_b = 'B';
  4054. ahc->chip = AHC_NONE;
  4055. ahc->features = AHC_FENONE;
  4056. ahc->bugs = AHC_BUGNONE;
  4057. ahc->flags = AHC_FNONE;
  4058. /*
  4059. * Default to all error reporting enabled with the
  4060. * sequencer operating at its fastest speed.
  4061. * The bus attach code may modify this.
  4062. */
  4063. ahc->seqctl = FASTMODE;
  4064. for (i = 0; i < AHC_NUM_TARGETS; i++)
  4065. TAILQ_INIT(&ahc->untagged_queues[i]);
  4066. if (ahc_platform_alloc(ahc, platform_arg) != 0) {
  4067. ahc_free(ahc);
  4068. ahc = NULL;
  4069. }
  4070. return (ahc);
  4071. }
  4072. int
  4073. ahc_softc_init(struct ahc_softc *ahc)
  4074. {
  4075. /* The IRQMS bit is only valid on VL and EISA chips */
  4076. if ((ahc->chip & AHC_PCI) == 0)
  4077. ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
  4078. else
  4079. ahc->unpause = 0;
  4080. ahc->pause = ahc->unpause | PAUSE;
  4081. /* XXX The shared scb data stuff should be deprecated */
  4082. if (ahc->scb_data == NULL) {
  4083. ahc->scb_data = malloc(sizeof(*ahc->scb_data),
  4084. M_DEVBUF, M_NOWAIT);
  4085. if (ahc->scb_data == NULL)
  4086. return (ENOMEM);
  4087. memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
  4088. }
  4089. return (0);
  4090. }
  4091. void
  4092. ahc_set_unit(struct ahc_softc *ahc, int unit)
  4093. {
  4094. ahc->unit = unit;
  4095. }
  4096. void
  4097. ahc_set_name(struct ahc_softc *ahc, char *name)
  4098. {
  4099. if (ahc->name != NULL)
  4100. free(ahc->name, M_DEVBUF);
  4101. ahc->name = name;
  4102. }
  4103. void
  4104. ahc_free(struct ahc_softc *ahc)
  4105. {
  4106. int i;
  4107. switch (ahc->init_level) {
  4108. default:
  4109. case 5:
  4110. ahc_shutdown(ahc);
  4111. /* FALLTHROUGH */
  4112. case 4:
  4113. ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
  4114. ahc->shared_data_dmamap);
  4115. /* FALLTHROUGH */
  4116. case 3:
  4117. ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
  4118. ahc->shared_data_dmamap);
  4119. ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
  4120. ahc->shared_data_dmamap);
  4121. /* FALLTHROUGH */
  4122. case 2:
  4123. ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
  4124. case 1:
  4125. #ifndef __linux__
  4126. ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
  4127. #endif
  4128. break;
  4129. case 0:
  4130. break;
  4131. }
  4132. #ifndef __linux__
  4133. ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
  4134. #endif
  4135. ahc_platform_free(ahc);
  4136. ahc_fini_scbdata(ahc);
  4137. for (i = 0; i < AHC_NUM_TARGETS; i++) {
  4138. struct ahc_tmode_tstate *tstate;
  4139. tstate = ahc->enabled_targets[i];
  4140. if (tstate != NULL) {
  4141. #ifdef AHC_TARGET_MODE
  4142. int j;
  4143. for (j = 0; j < AHC_NUM_LUNS; j++) {
  4144. struct ahc_tmode_lstate *lstate;
  4145. lstate = tstate->enabled_luns[j];
  4146. if (lstate != NULL) {
  4147. xpt_free_path(lstate->path);
  4148. free(lstate, M_DEVBUF);
  4149. }
  4150. }
  4151. #endif
  4152. free(tstate, M_DEVBUF);
  4153. }
  4154. }
  4155. #ifdef AHC_TARGET_MODE
  4156. if (ahc->black_hole != NULL) {
  4157. xpt_free_path(ahc->black_hole->path);
  4158. free(ahc->black_hole, M_DEVBUF);
  4159. }
  4160. #endif
  4161. if (ahc->name != NULL)
  4162. free(ahc->name, M_DEVBUF);
  4163. if (ahc->seep_config != NULL)
  4164. free(ahc->seep_config, M_DEVBUF);
  4165. #ifndef __FreeBSD__
  4166. free(ahc, M_DEVBUF);
  4167. #endif
  4168. return;
  4169. }
  4170. static void
  4171. ahc_shutdown(void *arg)
  4172. {
  4173. struct ahc_softc *ahc;
  4174. int i;
  4175. ahc = (struct ahc_softc *)arg;
  4176. /* This will reset most registers to 0, but not all */
  4177. ahc_reset(ahc, /*reinit*/FALSE);
  4178. ahc_outb(ahc, SCSISEQ, 0);
  4179. ahc_outb(ahc, SXFRCTL0, 0);
  4180. ahc_outb(ahc, DSPCISTATUS, 0);
  4181. for (i = TARG_SCSIRATE; i < SCSICONF; i++)
  4182. ahc_outb(ahc, i, 0);
  4183. }
  4184. /*
  4185. * Reset the controller and record some information about it
  4186. * that is only available just after a reset. If "reinit" is
  4187. * non-zero, this reset occured after initial configuration
  4188. * and the caller requests that the chip be fully reinitialized
  4189. * to a runable state. Chip interrupts are *not* enabled after
  4190. * a reinitialization. The caller must enable interrupts via
  4191. * ahc_intr_enable().
  4192. */
  4193. int
  4194. ahc_reset(struct ahc_softc *ahc, int reinit)
  4195. {
  4196. u_int sblkctl;
  4197. u_int sxfrctl1_a, sxfrctl1_b;
  4198. int error;
  4199. int wait;
  4200. /*
  4201. * Preserve the value of the SXFRCTL1 register for all channels.
  4202. * It contains settings that affect termination and we don't want
  4203. * to disturb the integrity of the bus.
  4204. */
  4205. ahc_pause(ahc);
  4206. sxfrctl1_b = 0;
  4207. if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
  4208. u_int sblkctl;
  4209. /*
  4210. * Save channel B's settings in case this chip
  4211. * is setup for TWIN channel operation.
  4212. */
  4213. sblkctl = ahc_inb(ahc, SBLKCTL);
  4214. ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
  4215. sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
  4216. ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
  4217. }
  4218. sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
  4219. ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
  4220. /*
  4221. * Ensure that the reset has finished. We delay 1000us
  4222. * prior to reading the register to make sure the chip
  4223. * has sufficiently completed its reset to handle register
  4224. * accesses.
  4225. */
  4226. wait = 1000;
  4227. do {
  4228. ahc_delay(1000);
  4229. } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
  4230. if (wait == 0) {
  4231. printf("%s: WARNING - Failed chip reset! "
  4232. "Trying to initialize anyway.\n", ahc_name(ahc));
  4233. }
  4234. ahc_outb(ahc, HCNTRL, ahc->pause);
  4235. /* Determine channel configuration */
  4236. sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
  4237. /* No Twin Channel PCI cards */
  4238. if ((ahc->chip & AHC_PCI) != 0)
  4239. sblkctl &= ~SELBUSB;
  4240. switch (sblkctl) {
  4241. case 0:
  4242. /* Single Narrow Channel */
  4243. break;
  4244. case 2:
  4245. /* Wide Channel */
  4246. ahc->features |= AHC_WIDE;
  4247. break;
  4248. case 8:
  4249. /* Twin Channel */
  4250. ahc->features |= AHC_TWIN;
  4251. break;
  4252. default:
  4253. printf(" Unsupported adapter type. Ignoring\n");
  4254. return(-1);
  4255. }
  4256. /*
  4257. * Reload sxfrctl1.
  4258. *
  4259. * We must always initialize STPWEN to 1 before we
  4260. * restore the saved values. STPWEN is initialized
  4261. * to a tri-state condition which can only be cleared
  4262. * by turning it on.
  4263. */
  4264. if ((ahc->features & AHC_TWIN) != 0) {
  4265. u_int sblkctl;
  4266. sblkctl = ahc_inb(ahc, SBLKCTL);
  4267. ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
  4268. ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
  4269. ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
  4270. }
  4271. ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
  4272. error = 0;
  4273. if (reinit != 0)
  4274. /*
  4275. * If a recovery action has forced a chip reset,
  4276. * re-initialize the chip to our liking.
  4277. */
  4278. error = ahc->bus_chip_init(ahc);
  4279. #ifdef AHC_DUMP_SEQ
  4280. else
  4281. ahc_dumpseq(ahc);
  4282. #endif
  4283. return (error);
  4284. }
  4285. /*
  4286. * Determine the number of SCBs available on the controller
  4287. */
  4288. int
  4289. ahc_probe_scbs(struct ahc_softc *ahc) {
  4290. int i;
  4291. for (i = 0; i < AHC_SCB_MAX; i++) {
  4292. ahc_outb(ahc, SCBPTR, i);
  4293. ahc_outb(ahc, SCB_BASE, i);
  4294. if (ahc_inb(ahc, SCB_BASE) != i)
  4295. break;
  4296. ahc_outb(ahc, SCBPTR, 0);
  4297. if (ahc_inb(ahc, SCB_BASE) != 0)
  4298. break;
  4299. }
  4300. return (i);
  4301. }
  4302. static void
  4303. ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  4304. {
  4305. dma_addr_t *baddr;
  4306. baddr = (dma_addr_t *)arg;
  4307. *baddr = segs->ds_addr;
  4308. }
  4309. static void
  4310. ahc_build_free_scb_list(struct ahc_softc *ahc)
  4311. {
  4312. int scbsize;
  4313. int i;
  4314. scbsize = 32;
  4315. if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
  4316. scbsize = 64;
  4317. for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
  4318. int j;
  4319. ahc_outb(ahc, SCBPTR, i);
  4320. /*
  4321. * Touch all SCB bytes to avoid parity errors
  4322. * should one of our debugging routines read
  4323. * an otherwise uninitiatlized byte.
  4324. */
  4325. for (j = 0; j < scbsize; j++)
  4326. ahc_outb(ahc, SCB_BASE+j, 0xFF);
  4327. /* Clear the control byte. */
  4328. ahc_outb(ahc, SCB_CONTROL, 0);
  4329. /* Set the next pointer */
  4330. if ((ahc->flags & AHC_PAGESCBS) != 0)
  4331. ahc_outb(ahc, SCB_NEXT, i+1);
  4332. else
  4333. ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
  4334. /* Make the tag number, SCSIID, and lun invalid */
  4335. ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
  4336. ahc_outb(ahc, SCB_SCSIID, 0xFF);
  4337. ahc_outb(ahc, SCB_LUN, 0xFF);
  4338. }
  4339. if ((ahc->flags & AHC_PAGESCBS) != 0) {
  4340. /* SCB 0 heads the free list. */
  4341. ahc_outb(ahc, FREE_SCBH, 0);
  4342. } else {
  4343. /* No free list. */
  4344. ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
  4345. }
  4346. /* Make sure that the last SCB terminates the free list */
  4347. ahc_outb(ahc, SCBPTR, i-1);
  4348. ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
  4349. }
  4350. static int
  4351. ahc_init_scbdata(struct ahc_softc *ahc)
  4352. {
  4353. struct scb_data *scb_data;
  4354. scb_data = ahc->scb_data;
  4355. SLIST_INIT(&scb_data->free_scbs);
  4356. SLIST_INIT(&scb_data->sg_maps);
  4357. /* Allocate SCB resources */
  4358. scb_data->scbarray =
  4359. (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
  4360. M_DEVBUF, M_NOWAIT);
  4361. if (scb_data->scbarray == NULL)
  4362. return (ENOMEM);
  4363. memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
  4364. /* Determine the number of hardware SCBs and initialize them */
  4365. scb_data->maxhscbs = ahc_probe_scbs(ahc);
  4366. if (ahc->scb_data->maxhscbs == 0) {
  4367. printf("%s: No SCB space found\n", ahc_name(ahc));
  4368. return (ENXIO);
  4369. }
  4370. /*
  4371. * Create our DMA tags. These tags define the kinds of device
  4372. * accessible memory allocations and memory mappings we will
  4373. * need to perform during normal operation.
  4374. *
  4375. * Unless we need to further restrict the allocation, we rely
  4376. * on the restrictions of the parent dmat, hence the common
  4377. * use of MAXADDR and MAXSIZE.
  4378. */
  4379. /* DMA tag for our hardware scb structures */
  4380. if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
  4381. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  4382. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  4383. /*highaddr*/BUS_SPACE_MAXADDR,
  4384. /*filter*/NULL, /*filterarg*/NULL,
  4385. AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
  4386. /*nsegments*/1,
  4387. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  4388. /*flags*/0, &scb_data->hscb_dmat) != 0) {
  4389. goto error_exit;
  4390. }
  4391. scb_data->init_level++;
  4392. /* Allocation for our hscbs */
  4393. if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
  4394. (void **)&scb_data->hscbs,
  4395. BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
  4396. goto error_exit;
  4397. }
  4398. scb_data->init_level++;
  4399. /* And permanently map them */
  4400. ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
  4401. scb_data->hscbs,
  4402. AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
  4403. ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
  4404. scb_data->init_level++;
  4405. /* DMA tag for our sense buffers */
  4406. if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
  4407. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  4408. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  4409. /*highaddr*/BUS_SPACE_MAXADDR,
  4410. /*filter*/NULL, /*filterarg*/NULL,
  4411. AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
  4412. /*nsegments*/1,
  4413. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  4414. /*flags*/0, &scb_data->sense_dmat) != 0) {
  4415. goto error_exit;
  4416. }
  4417. scb_data->init_level++;
  4418. /* Allocate them */
  4419. if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
  4420. (void **)&scb_data->sense,
  4421. BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
  4422. goto error_exit;
  4423. }
  4424. scb_data->init_level++;
  4425. /* And permanently map them */
  4426. ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
  4427. scb_data->sense,
  4428. AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
  4429. ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
  4430. scb_data->init_level++;
  4431. /* DMA tag for our S/G structures. We allocate in page sized chunks */
  4432. if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
  4433. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  4434. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  4435. /*highaddr*/BUS_SPACE_MAXADDR,
  4436. /*filter*/NULL, /*filterarg*/NULL,
  4437. PAGE_SIZE, /*nsegments*/1,
  4438. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  4439. /*flags*/0, &scb_data->sg_dmat) != 0) {
  4440. goto error_exit;
  4441. }
  4442. scb_data->init_level++;
  4443. /* Perform initial CCB allocation */
  4444. memset(scb_data->hscbs, 0,
  4445. AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
  4446. ahc_alloc_scbs(ahc);
  4447. if (scb_data->numscbs == 0) {
  4448. printf("%s: ahc_init_scbdata - "
  4449. "Unable to allocate initial scbs\n",
  4450. ahc_name(ahc));
  4451. goto error_exit;
  4452. }
  4453. /*
  4454. * Reserve the next queued SCB.
  4455. */
  4456. ahc->next_queued_scb = ahc_get_scb(ahc);
  4457. /*
  4458. * Note that we were successfull
  4459. */
  4460. return (0);
  4461. error_exit:
  4462. return (ENOMEM);
  4463. }
  4464. static void
  4465. ahc_fini_scbdata(struct ahc_softc *ahc)
  4466. {
  4467. struct scb_data *scb_data;
  4468. scb_data = ahc->scb_data;
  4469. if (scb_data == NULL)
  4470. return;
  4471. switch (scb_data->init_level) {
  4472. default:
  4473. case 7:
  4474. {
  4475. struct sg_map_node *sg_map;
  4476. while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
  4477. SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
  4478. ahc_dmamap_unload(ahc, scb_data->sg_dmat,
  4479. sg_map->sg_dmamap);
  4480. ahc_dmamem_free(ahc, scb_data->sg_dmat,
  4481. sg_map->sg_vaddr,
  4482. sg_map->sg_dmamap);
  4483. free(sg_map, M_DEVBUF);
  4484. }
  4485. ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
  4486. }
  4487. case 6:
  4488. ahc_dmamap_unload(ahc, scb_data->sense_dmat,
  4489. scb_data->sense_dmamap);
  4490. case 5:
  4491. ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
  4492. scb_data->sense_dmamap);
  4493. ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
  4494. scb_data->sense_dmamap);
  4495. case 4:
  4496. ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
  4497. case 3:
  4498. ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
  4499. scb_data->hscb_dmamap);
  4500. case 2:
  4501. ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
  4502. scb_data->hscb_dmamap);
  4503. ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
  4504. scb_data->hscb_dmamap);
  4505. case 1:
  4506. ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
  4507. break;
  4508. case 0:
  4509. break;
  4510. }
  4511. if (scb_data->scbarray != NULL)
  4512. free(scb_data->scbarray, M_DEVBUF);
  4513. }
  4514. static void
  4515. ahc_alloc_scbs(struct ahc_softc *ahc)
  4516. {
  4517. struct scb_data *scb_data;
  4518. struct scb *next_scb;
  4519. struct sg_map_node *sg_map;
  4520. dma_addr_t physaddr;
  4521. struct ahc_dma_seg *segs;
  4522. int newcount;
  4523. int i;
  4524. scb_data = ahc->scb_data;
  4525. if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
  4526. /* Can't allocate any more */
  4527. return;
  4528. next_scb = &scb_data->scbarray[scb_data->numscbs];
  4529. sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
  4530. if (sg_map == NULL)
  4531. return;
  4532. /* Allocate S/G space for the next batch of SCBS */
  4533. if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
  4534. (void **)&sg_map->sg_vaddr,
  4535. BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
  4536. free(sg_map, M_DEVBUF);
  4537. return;
  4538. }
  4539. SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
  4540. ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
  4541. sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
  4542. &sg_map->sg_physaddr, /*flags*/0);
  4543. segs = sg_map->sg_vaddr;
  4544. physaddr = sg_map->sg_physaddr;
  4545. newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
  4546. newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
  4547. for (i = 0; i < newcount; i++) {
  4548. struct scb_platform_data *pdata;
  4549. #ifndef __linux__
  4550. int error;
  4551. #endif
  4552. pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
  4553. M_DEVBUF, M_NOWAIT);
  4554. if (pdata == NULL)
  4555. break;
  4556. next_scb->platform_data = pdata;
  4557. next_scb->sg_map = sg_map;
  4558. next_scb->sg_list = segs;
  4559. /*
  4560. * The sequencer always starts with the second entry.
  4561. * The first entry is embedded in the scb.
  4562. */
  4563. next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
  4564. next_scb->ahc_softc = ahc;
  4565. next_scb->flags = SCB_FREE;
  4566. #ifndef __linux__
  4567. error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
  4568. &next_scb->dmamap);
  4569. if (error != 0)
  4570. break;
  4571. #endif
  4572. next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
  4573. next_scb->hscb->tag = ahc->scb_data->numscbs;
  4574. SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
  4575. next_scb, links.sle);
  4576. segs += AHC_NSEG;
  4577. physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
  4578. next_scb++;
  4579. ahc->scb_data->numscbs++;
  4580. }
  4581. }
  4582. void
  4583. ahc_controller_info(struct ahc_softc *ahc, char *buf)
  4584. {
  4585. int len;
  4586. len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
  4587. buf += len;
  4588. if ((ahc->features & AHC_TWIN) != 0)
  4589. len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
  4590. "B SCSI Id=%d, primary %c, ",
  4591. ahc->our_id, ahc->our_id_b,
  4592. (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
  4593. else {
  4594. const char *speed;
  4595. const char *type;
  4596. speed = "";
  4597. if ((ahc->features & AHC_ULTRA) != 0) {
  4598. speed = "Ultra ";
  4599. } else if ((ahc->features & AHC_DT) != 0) {
  4600. speed = "Ultra160 ";
  4601. } else if ((ahc->features & AHC_ULTRA2) != 0) {
  4602. speed = "Ultra2 ";
  4603. }
  4604. if ((ahc->features & AHC_WIDE) != 0) {
  4605. type = "Wide";
  4606. } else {
  4607. type = "Single";
  4608. }
  4609. len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
  4610. speed, type, ahc->channel, ahc->our_id);
  4611. }
  4612. buf += len;
  4613. if ((ahc->flags & AHC_PAGESCBS) != 0)
  4614. sprintf(buf, "%d/%d SCBs",
  4615. ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
  4616. else
  4617. sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
  4618. }
  4619. int
  4620. ahc_chip_init(struct ahc_softc *ahc)
  4621. {
  4622. int term;
  4623. int error;
  4624. u_int i;
  4625. u_int scsi_conf;
  4626. u_int scsiseq_template;
  4627. uint32_t physaddr;
  4628. ahc_outb(ahc, SEQ_FLAGS, 0);
  4629. ahc_outb(ahc, SEQ_FLAGS2, 0);
  4630. /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
  4631. if (ahc->features & AHC_TWIN) {
  4632. /*
  4633. * Setup Channel B first.
  4634. */
  4635. ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
  4636. term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
  4637. ahc_outb(ahc, SCSIID, ahc->our_id_b);
  4638. scsi_conf = ahc_inb(ahc, SCSICONF + 1);
  4639. ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
  4640. |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
  4641. if ((ahc->features & AHC_ULTRA2) != 0)
  4642. ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
  4643. ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
  4644. ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
  4645. /* Select Channel A */
  4646. ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
  4647. }
  4648. term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
  4649. if ((ahc->features & AHC_ULTRA2) != 0)
  4650. ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
  4651. else
  4652. ahc_outb(ahc, SCSIID, ahc->our_id);
  4653. scsi_conf = ahc_inb(ahc, SCSICONF);
  4654. ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
  4655. |term|ahc->seltime
  4656. |ENSTIMER|ACTNEGEN);
  4657. if ((ahc->features & AHC_ULTRA2) != 0)
  4658. ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
  4659. ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
  4660. ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
  4661. /* There are no untagged SCBs active yet. */
  4662. for (i = 0; i < 16; i++) {
  4663. ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
  4664. if ((ahc->flags & AHC_SCB_BTT) != 0) {
  4665. int lun;
  4666. /*
  4667. * The SCB based BTT allows an entry per
  4668. * target and lun pair.
  4669. */
  4670. for (lun = 1; lun < AHC_NUM_LUNS; lun++)
  4671. ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
  4672. }
  4673. }
  4674. /* All of our queues are empty */
  4675. for (i = 0; i < 256; i++)
  4676. ahc->qoutfifo[i] = SCB_LIST_NULL;
  4677. ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
  4678. for (i = 0; i < 256; i++)
  4679. ahc->qinfifo[i] = SCB_LIST_NULL;
  4680. if ((ahc->features & AHC_MULTI_TID) != 0) {
  4681. ahc_outb(ahc, TARGID, 0);
  4682. ahc_outb(ahc, TARGID + 1, 0);
  4683. }
  4684. /*
  4685. * Tell the sequencer where it can find our arrays in memory.
  4686. */
  4687. physaddr = ahc->scb_data->hscb_busaddr;
  4688. ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
  4689. ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
  4690. ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
  4691. ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
  4692. physaddr = ahc->shared_data_busaddr;
  4693. ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
  4694. ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
  4695. ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
  4696. ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
  4697. /*
  4698. * Initialize the group code to command length table.
  4699. * This overrides the values in TARG_SCSIRATE, so only
  4700. * setup the table after we have processed that information.
  4701. */
  4702. ahc_outb(ahc, CMDSIZE_TABLE, 5);
  4703. ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
  4704. ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
  4705. ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
  4706. ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
  4707. ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
  4708. ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
  4709. ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
  4710. if ((ahc->features & AHC_HS_MAILBOX) != 0)
  4711. ahc_outb(ahc, HS_MAILBOX, 0);
  4712. /* Tell the sequencer of our initial queue positions */
  4713. if ((ahc->features & AHC_TARGETMODE) != 0) {
  4714. ahc->tqinfifonext = 1;
  4715. ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
  4716. ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
  4717. }
  4718. ahc->qinfifonext = 0;
  4719. ahc->qoutfifonext = 0;
  4720. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  4721. ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
  4722. ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
  4723. ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
  4724. ahc_outb(ahc, SDSCB_QOFF, 0);
  4725. } else {
  4726. ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
  4727. ahc_outb(ahc, QINPOS, ahc->qinfifonext);
  4728. ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
  4729. }
  4730. /* We don't have any waiting selections */
  4731. ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
  4732. /* Our disconnection list is empty too */
  4733. ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
  4734. /* Message out buffer starts empty */
  4735. ahc_outb(ahc, MSG_OUT, MSG_NOOP);
  4736. /*
  4737. * Setup the allowed SCSI Sequences based on operational mode.
  4738. * If we are a target, we'll enable select in operations once
  4739. * we've had a lun enabled.
  4740. */
  4741. scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
  4742. if ((ahc->flags & AHC_INITIATORROLE) != 0)
  4743. scsiseq_template |= ENRSELI;
  4744. ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
  4745. /* Initialize our list of free SCBs. */
  4746. ahc_build_free_scb_list(ahc);
  4747. /*
  4748. * Tell the sequencer which SCB will be the next one it receives.
  4749. */
  4750. ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
  4751. /*
  4752. * Load the Sequencer program and Enable the adapter
  4753. * in "fast" mode.
  4754. */
  4755. if (bootverbose)
  4756. printf("%s: Downloading Sequencer Program...",
  4757. ahc_name(ahc));
  4758. error = ahc_loadseq(ahc);
  4759. if (error != 0)
  4760. return (error);
  4761. if ((ahc->features & AHC_ULTRA2) != 0) {
  4762. int wait;
  4763. /*
  4764. * Wait for up to 500ms for our transceivers
  4765. * to settle. If the adapter does not have
  4766. * a cable attached, the transceivers may
  4767. * never settle, so don't complain if we
  4768. * fail here.
  4769. */
  4770. for (wait = 5000;
  4771. (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
  4772. wait--)
  4773. ahc_delay(100);
  4774. }
  4775. ahc_restart(ahc);
  4776. return (0);
  4777. }
  4778. /*
  4779. * Start the board, ready for normal operation
  4780. */
  4781. int
  4782. ahc_init(struct ahc_softc *ahc)
  4783. {
  4784. int max_targ;
  4785. u_int i;
  4786. u_int scsi_conf;
  4787. u_int ultraenb;
  4788. u_int discenable;
  4789. u_int tagenable;
  4790. size_t driver_data_size;
  4791. #ifdef AHC_DEBUG
  4792. if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
  4793. ahc->flags |= AHC_SEQUENCER_DEBUG;
  4794. #endif
  4795. #ifdef AHC_PRINT_SRAM
  4796. printf("Scratch Ram:");
  4797. for (i = 0x20; i < 0x5f; i++) {
  4798. if (((i % 8) == 0) && (i != 0)) {
  4799. printf ("\n ");
  4800. }
  4801. printf (" 0x%x", ahc_inb(ahc, i));
  4802. }
  4803. if ((ahc->features & AHC_MORE_SRAM) != 0) {
  4804. for (i = 0x70; i < 0x7f; i++) {
  4805. if (((i % 8) == 0) && (i != 0)) {
  4806. printf ("\n ");
  4807. }
  4808. printf (" 0x%x", ahc_inb(ahc, i));
  4809. }
  4810. }
  4811. printf ("\n");
  4812. /*
  4813. * Reading uninitialized scratch ram may
  4814. * generate parity errors.
  4815. */
  4816. ahc_outb(ahc, CLRINT, CLRPARERR);
  4817. ahc_outb(ahc, CLRINT, CLRBRKADRINT);
  4818. #endif
  4819. max_targ = 15;
  4820. /*
  4821. * Assume we have a board at this stage and it has been reset.
  4822. */
  4823. if ((ahc->flags & AHC_USEDEFAULTS) != 0)
  4824. ahc->our_id = ahc->our_id_b = 7;
  4825. /*
  4826. * Default to allowing initiator operations.
  4827. */
  4828. ahc->flags |= AHC_INITIATORROLE;
  4829. /*
  4830. * Only allow target mode features if this unit has them enabled.
  4831. */
  4832. if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
  4833. ahc->features &= ~AHC_TARGETMODE;
  4834. #ifndef __linux__
  4835. /* DMA tag for mapping buffers into device visible space. */
  4836. if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
  4837. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  4838. /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
  4839. ? (dma_addr_t)0x7FFFFFFFFFULL
  4840. : BUS_SPACE_MAXADDR_32BIT,
  4841. /*highaddr*/BUS_SPACE_MAXADDR,
  4842. /*filter*/NULL, /*filterarg*/NULL,
  4843. /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
  4844. /*nsegments*/AHC_NSEG,
  4845. /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
  4846. /*flags*/BUS_DMA_ALLOCNOW,
  4847. &ahc->buffer_dmat) != 0) {
  4848. return (ENOMEM);
  4849. }
  4850. #endif
  4851. ahc->init_level++;
  4852. /*
  4853. * DMA tag for our command fifos and other data in system memory
  4854. * the card's sequencer must be able to access. For initiator
  4855. * roles, we need to allocate space for the qinfifo and qoutfifo.
  4856. * The qinfifo and qoutfifo are composed of 256 1 byte elements.
  4857. * When providing for the target mode role, we must additionally
  4858. * provide space for the incoming target command fifo and an extra
  4859. * byte to deal with a dma bug in some chip versions.
  4860. */
  4861. driver_data_size = 2 * 256 * sizeof(uint8_t);
  4862. if ((ahc->features & AHC_TARGETMODE) != 0)
  4863. driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
  4864. + /*DMA WideOdd Bug Buffer*/1;
  4865. if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
  4866. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  4867. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  4868. /*highaddr*/BUS_SPACE_MAXADDR,
  4869. /*filter*/NULL, /*filterarg*/NULL,
  4870. driver_data_size,
  4871. /*nsegments*/1,
  4872. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  4873. /*flags*/0, &ahc->shared_data_dmat) != 0) {
  4874. return (ENOMEM);
  4875. }
  4876. ahc->init_level++;
  4877. /* Allocation of driver data */
  4878. if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
  4879. (void **)&ahc->qoutfifo,
  4880. BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
  4881. return (ENOMEM);
  4882. }
  4883. ahc->init_level++;
  4884. /* And permanently map it in */
  4885. ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
  4886. ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
  4887. &ahc->shared_data_busaddr, /*flags*/0);
  4888. if ((ahc->features & AHC_TARGETMODE) != 0) {
  4889. ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
  4890. ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
  4891. ahc->dma_bug_buf = ahc->shared_data_busaddr
  4892. + driver_data_size - 1;
  4893. /* All target command blocks start out invalid. */
  4894. for (i = 0; i < AHC_TMODE_CMDS; i++)
  4895. ahc->targetcmds[i].cmd_valid = 0;
  4896. ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
  4897. ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
  4898. }
  4899. ahc->qinfifo = &ahc->qoutfifo[256];
  4900. ahc->init_level++;
  4901. /* Allocate SCB data now that buffer_dmat is initialized */
  4902. if (ahc->scb_data->maxhscbs == 0)
  4903. if (ahc_init_scbdata(ahc) != 0)
  4904. return (ENOMEM);
  4905. /*
  4906. * Allocate a tstate to house information for our
  4907. * initiator presence on the bus as well as the user
  4908. * data for any target mode initiator.
  4909. */
  4910. if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
  4911. printf("%s: unable to allocate ahc_tmode_tstate. "
  4912. "Failing attach\n", ahc_name(ahc));
  4913. return (ENOMEM);
  4914. }
  4915. if ((ahc->features & AHC_TWIN) != 0) {
  4916. if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
  4917. printf("%s: unable to allocate ahc_tmode_tstate. "
  4918. "Failing attach\n", ahc_name(ahc));
  4919. return (ENOMEM);
  4920. }
  4921. }
  4922. if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
  4923. ahc->flags |= AHC_PAGESCBS;
  4924. } else {
  4925. ahc->flags &= ~AHC_PAGESCBS;
  4926. }
  4927. #ifdef AHC_DEBUG
  4928. if (ahc_debug & AHC_SHOW_MISC) {
  4929. printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
  4930. "ahc_dma %u bytes\n",
  4931. ahc_name(ahc),
  4932. (u_int)sizeof(struct hardware_scb),
  4933. (u_int)sizeof(struct scb),
  4934. (u_int)sizeof(struct ahc_dma_seg));
  4935. }
  4936. #endif /* AHC_DEBUG */
  4937. /*
  4938. * Look at the information that board initialization or
  4939. * the board bios has left us.
  4940. */
  4941. if (ahc->features & AHC_TWIN) {
  4942. scsi_conf = ahc_inb(ahc, SCSICONF + 1);
  4943. if ((scsi_conf & RESET_SCSI) != 0
  4944. && (ahc->flags & AHC_INITIATORROLE) != 0)
  4945. ahc->flags |= AHC_RESET_BUS_B;
  4946. }
  4947. scsi_conf = ahc_inb(ahc, SCSICONF);
  4948. if ((scsi_conf & RESET_SCSI) != 0
  4949. && (ahc->flags & AHC_INITIATORROLE) != 0)
  4950. ahc->flags |= AHC_RESET_BUS_A;
  4951. ultraenb = 0;
  4952. tagenable = ALL_TARGETS_MASK;
  4953. /* Grab the disconnection disable table and invert it for our needs */
  4954. if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
  4955. printf("%s: Host Adapter Bios disabled. Using default SCSI "
  4956. "device parameters\n", ahc_name(ahc));
  4957. ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
  4958. AHC_TERM_ENB_A|AHC_TERM_ENB_B;
  4959. discenable = ALL_TARGETS_MASK;
  4960. if ((ahc->features & AHC_ULTRA) != 0)
  4961. ultraenb = ALL_TARGETS_MASK;
  4962. } else {
  4963. discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
  4964. | ahc_inb(ahc, DISC_DSB));
  4965. if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
  4966. ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
  4967. | ahc_inb(ahc, ULTRA_ENB);
  4968. }
  4969. if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
  4970. max_targ = 7;
  4971. for (i = 0; i <= max_targ; i++) {
  4972. struct ahc_initiator_tinfo *tinfo;
  4973. struct ahc_tmode_tstate *tstate;
  4974. u_int our_id;
  4975. u_int target_id;
  4976. char channel;
  4977. channel = 'A';
  4978. our_id = ahc->our_id;
  4979. target_id = i;
  4980. if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
  4981. channel = 'B';
  4982. our_id = ahc->our_id_b;
  4983. target_id = i % 8;
  4984. }
  4985. tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
  4986. target_id, &tstate);
  4987. /* Default to async narrow across the board */
  4988. memset(tinfo, 0, sizeof(*tinfo));
  4989. if (ahc->flags & AHC_USEDEFAULTS) {
  4990. if ((ahc->features & AHC_WIDE) != 0)
  4991. tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
  4992. /*
  4993. * These will be truncated when we determine the
  4994. * connection type we have with the target.
  4995. */
  4996. tinfo->user.period = ahc_syncrates->period;
  4997. tinfo->user.offset = MAX_OFFSET;
  4998. } else {
  4999. u_int scsirate;
  5000. uint16_t mask;
  5001. /* Take the settings leftover in scratch RAM. */
  5002. scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
  5003. mask = (0x01 << i);
  5004. if ((ahc->features & AHC_ULTRA2) != 0) {
  5005. u_int offset;
  5006. u_int maxsync;
  5007. if ((scsirate & SOFS) == 0x0F) {
  5008. /*
  5009. * Haven't negotiated yet,
  5010. * so the format is different.
  5011. */
  5012. scsirate = (scsirate & SXFR) >> 4
  5013. | (ultraenb & mask)
  5014. ? 0x08 : 0x0
  5015. | (scsirate & WIDEXFER);
  5016. offset = MAX_OFFSET_ULTRA2;
  5017. } else
  5018. offset = ahc_inb(ahc, TARG_OFFSET + i);
  5019. if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
  5020. /* Set to the lowest sync rate, 5MHz */
  5021. scsirate |= 0x1c;
  5022. maxsync = AHC_SYNCRATE_ULTRA2;
  5023. if ((ahc->features & AHC_DT) != 0)
  5024. maxsync = AHC_SYNCRATE_DT;
  5025. tinfo->user.period =
  5026. ahc_find_period(ahc, scsirate, maxsync);
  5027. if (offset == 0)
  5028. tinfo->user.period = 0;
  5029. else
  5030. tinfo->user.offset = MAX_OFFSET;
  5031. if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
  5032. && (ahc->features & AHC_DT) != 0)
  5033. tinfo->user.ppr_options =
  5034. MSG_EXT_PPR_DT_REQ;
  5035. } else if ((scsirate & SOFS) != 0) {
  5036. if ((scsirate & SXFR) == 0x40
  5037. && (ultraenb & mask) != 0) {
  5038. /* Treat 10MHz as a non-ultra speed */
  5039. scsirate &= ~SXFR;
  5040. ultraenb &= ~mask;
  5041. }
  5042. tinfo->user.period =
  5043. ahc_find_period(ahc, scsirate,
  5044. (ultraenb & mask)
  5045. ? AHC_SYNCRATE_ULTRA
  5046. : AHC_SYNCRATE_FAST);
  5047. if (tinfo->user.period != 0)
  5048. tinfo->user.offset = MAX_OFFSET;
  5049. }
  5050. if (tinfo->user.period == 0)
  5051. tinfo->user.offset = 0;
  5052. if ((scsirate & WIDEXFER) != 0
  5053. && (ahc->features & AHC_WIDE) != 0)
  5054. tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
  5055. tinfo->user.protocol_version = 4;
  5056. if ((ahc->features & AHC_DT) != 0)
  5057. tinfo->user.transport_version = 3;
  5058. else
  5059. tinfo->user.transport_version = 2;
  5060. tinfo->goal.protocol_version = 2;
  5061. tinfo->goal.transport_version = 2;
  5062. tinfo->curr.protocol_version = 2;
  5063. tinfo->curr.transport_version = 2;
  5064. }
  5065. tstate->ultraenb = 0;
  5066. }
  5067. ahc->user_discenable = discenable;
  5068. ahc->user_tagenable = tagenable;
  5069. return (ahc->bus_chip_init(ahc));
  5070. }
  5071. void
  5072. ahc_intr_enable(struct ahc_softc *ahc, int enable)
  5073. {
  5074. u_int hcntrl;
  5075. hcntrl = ahc_inb(ahc, HCNTRL);
  5076. hcntrl &= ~INTEN;
  5077. ahc->pause &= ~INTEN;
  5078. ahc->unpause &= ~INTEN;
  5079. if (enable) {
  5080. hcntrl |= INTEN;
  5081. ahc->pause |= INTEN;
  5082. ahc->unpause |= INTEN;
  5083. }
  5084. ahc_outb(ahc, HCNTRL, hcntrl);
  5085. }
  5086. /*
  5087. * Ensure that the card is paused in a location
  5088. * outside of all critical sections and that all
  5089. * pending work is completed prior to returning.
  5090. * This routine should only be called from outside
  5091. * an interrupt context.
  5092. */
  5093. void
  5094. ahc_pause_and_flushwork(struct ahc_softc *ahc)
  5095. {
  5096. int intstat;
  5097. int maxloops;
  5098. int paused;
  5099. maxloops = 1000;
  5100. ahc->flags |= AHC_ALL_INTERRUPTS;
  5101. paused = FALSE;
  5102. do {
  5103. if (paused) {
  5104. ahc_unpause(ahc);
  5105. /*
  5106. * Give the sequencer some time to service
  5107. * any active selections.
  5108. */
  5109. ahc_delay(500);
  5110. }
  5111. ahc_intr(ahc);
  5112. ahc_pause(ahc);
  5113. paused = TRUE;
  5114. ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
  5115. intstat = ahc_inb(ahc, INTSTAT);
  5116. if ((intstat & INT_PEND) == 0) {
  5117. ahc_clear_critical_section(ahc);
  5118. intstat = ahc_inb(ahc, INTSTAT);
  5119. }
  5120. } while (--maxloops
  5121. && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
  5122. && ((intstat & INT_PEND) != 0
  5123. || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
  5124. if (maxloops == 0) {
  5125. printf("Infinite interrupt loop, INTSTAT = %x",
  5126. ahc_inb(ahc, INTSTAT));
  5127. }
  5128. ahc_platform_flushwork(ahc);
  5129. ahc->flags &= ~AHC_ALL_INTERRUPTS;
  5130. }
  5131. #ifdef CONFIG_PM
  5132. int
  5133. ahc_suspend(struct ahc_softc *ahc)
  5134. {
  5135. ahc_pause_and_flushwork(ahc);
  5136. if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
  5137. ahc_unpause(ahc);
  5138. return (EBUSY);
  5139. }
  5140. #ifdef AHC_TARGET_MODE
  5141. /*
  5142. * XXX What about ATIOs that have not yet been serviced?
  5143. * Perhaps we should just refuse to be suspended if we
  5144. * are acting in a target role.
  5145. */
  5146. if (ahc->pending_device != NULL) {
  5147. ahc_unpause(ahc);
  5148. return (EBUSY);
  5149. }
  5150. #endif
  5151. ahc_shutdown(ahc);
  5152. return (0);
  5153. }
  5154. int
  5155. ahc_resume(struct ahc_softc *ahc)
  5156. {
  5157. ahc_reset(ahc, /*reinit*/TRUE);
  5158. ahc_intr_enable(ahc, TRUE);
  5159. ahc_restart(ahc);
  5160. return (0);
  5161. }
  5162. #endif
  5163. /************************** Busy Target Table *********************************/
  5164. /*
  5165. * Return the untagged transaction id for a given target/channel lun.
  5166. * Optionally, clear the entry.
  5167. */
  5168. static u_int
  5169. ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
  5170. {
  5171. u_int scbid;
  5172. u_int target_offset;
  5173. if ((ahc->flags & AHC_SCB_BTT) != 0) {
  5174. u_int saved_scbptr;
  5175. saved_scbptr = ahc_inb(ahc, SCBPTR);
  5176. ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
  5177. scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
  5178. ahc_outb(ahc, SCBPTR, saved_scbptr);
  5179. } else {
  5180. target_offset = TCL_TARGET_OFFSET(tcl);
  5181. scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
  5182. }
  5183. return (scbid);
  5184. }
  5185. static void
  5186. ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
  5187. {
  5188. u_int target_offset;
  5189. if ((ahc->flags & AHC_SCB_BTT) != 0) {
  5190. u_int saved_scbptr;
  5191. saved_scbptr = ahc_inb(ahc, SCBPTR);
  5192. ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
  5193. ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
  5194. ahc_outb(ahc, SCBPTR, saved_scbptr);
  5195. } else {
  5196. target_offset = TCL_TARGET_OFFSET(tcl);
  5197. ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
  5198. }
  5199. }
  5200. static void
  5201. ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
  5202. {
  5203. u_int target_offset;
  5204. if ((ahc->flags & AHC_SCB_BTT) != 0) {
  5205. u_int saved_scbptr;
  5206. saved_scbptr = ahc_inb(ahc, SCBPTR);
  5207. ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
  5208. ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
  5209. ahc_outb(ahc, SCBPTR, saved_scbptr);
  5210. } else {
  5211. target_offset = TCL_TARGET_OFFSET(tcl);
  5212. ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
  5213. }
  5214. }
  5215. /************************** SCB and SCB queue management **********************/
  5216. int
  5217. ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
  5218. char channel, int lun, u_int tag, role_t role)
  5219. {
  5220. int targ = SCB_GET_TARGET(ahc, scb);
  5221. char chan = SCB_GET_CHANNEL(ahc, scb);
  5222. int slun = SCB_GET_LUN(scb);
  5223. int match;
  5224. match = ((chan == channel) || (channel == ALL_CHANNELS));
  5225. if (match != 0)
  5226. match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
  5227. if (match != 0)
  5228. match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
  5229. if (match != 0) {
  5230. #ifdef AHC_TARGET_MODE
  5231. int group;
  5232. group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
  5233. if (role == ROLE_INITIATOR) {
  5234. match = (group != XPT_FC_GROUP_TMODE)
  5235. && ((tag == scb->hscb->tag)
  5236. || (tag == SCB_LIST_NULL));
  5237. } else if (role == ROLE_TARGET) {
  5238. match = (group == XPT_FC_GROUP_TMODE)
  5239. && ((tag == scb->io_ctx->csio.tag_id)
  5240. || (tag == SCB_LIST_NULL));
  5241. }
  5242. #else /* !AHC_TARGET_MODE */
  5243. match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
  5244. #endif /* AHC_TARGET_MODE */
  5245. }
  5246. return match;
  5247. }
  5248. static void
  5249. ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
  5250. {
  5251. int target;
  5252. char channel;
  5253. int lun;
  5254. target = SCB_GET_TARGET(ahc, scb);
  5255. lun = SCB_GET_LUN(scb);
  5256. channel = SCB_GET_CHANNEL(ahc, scb);
  5257. ahc_search_qinfifo(ahc, target, channel, lun,
  5258. /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
  5259. CAM_REQUEUE_REQ, SEARCH_COMPLETE);
  5260. ahc_platform_freeze_devq(ahc, scb);
  5261. }
  5262. void
  5263. ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
  5264. {
  5265. struct scb *prev_scb;
  5266. prev_scb = NULL;
  5267. if (ahc_qinfifo_count(ahc) != 0) {
  5268. u_int prev_tag;
  5269. uint8_t prev_pos;
  5270. prev_pos = ahc->qinfifonext - 1;
  5271. prev_tag = ahc->qinfifo[prev_pos];
  5272. prev_scb = ahc_lookup_scb(ahc, prev_tag);
  5273. }
  5274. ahc_qinfifo_requeue(ahc, prev_scb, scb);
  5275. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  5276. ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
  5277. } else {
  5278. ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
  5279. }
  5280. }
  5281. static void
  5282. ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
  5283. struct scb *scb)
  5284. {
  5285. if (prev_scb == NULL) {
  5286. ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
  5287. } else {
  5288. prev_scb->hscb->next = scb->hscb->tag;
  5289. ahc_sync_scb(ahc, prev_scb,
  5290. BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  5291. }
  5292. ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
  5293. scb->hscb->next = ahc->next_queued_scb->hscb->tag;
  5294. ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  5295. }
  5296. static int
  5297. ahc_qinfifo_count(struct ahc_softc *ahc)
  5298. {
  5299. uint8_t qinpos;
  5300. uint8_t diff;
  5301. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  5302. qinpos = ahc_inb(ahc, SNSCB_QOFF);
  5303. ahc_outb(ahc, SNSCB_QOFF, qinpos);
  5304. } else
  5305. qinpos = ahc_inb(ahc, QINPOS);
  5306. diff = ahc->qinfifonext - qinpos;
  5307. return (diff);
  5308. }
  5309. int
  5310. ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
  5311. int lun, u_int tag, role_t role, uint32_t status,
  5312. ahc_search_action action)
  5313. {
  5314. struct scb *scb;
  5315. struct scb *prev_scb;
  5316. uint8_t qinstart;
  5317. uint8_t qinpos;
  5318. uint8_t qintail;
  5319. uint8_t next;
  5320. uint8_t prev;
  5321. uint8_t curscbptr;
  5322. int found;
  5323. int have_qregs;
  5324. qintail = ahc->qinfifonext;
  5325. have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
  5326. if (have_qregs) {
  5327. qinstart = ahc_inb(ahc, SNSCB_QOFF);
  5328. ahc_outb(ahc, SNSCB_QOFF, qinstart);
  5329. } else
  5330. qinstart = ahc_inb(ahc, QINPOS);
  5331. qinpos = qinstart;
  5332. found = 0;
  5333. prev_scb = NULL;
  5334. if (action == SEARCH_COMPLETE) {
  5335. /*
  5336. * Don't attempt to run any queued untagged transactions
  5337. * until we are done with the abort process.
  5338. */
  5339. ahc_freeze_untagged_queues(ahc);
  5340. }
  5341. /*
  5342. * Start with an empty queue. Entries that are not chosen
  5343. * for removal will be re-added to the queue as we go.
  5344. */
  5345. ahc->qinfifonext = qinpos;
  5346. ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
  5347. while (qinpos != qintail) {
  5348. scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
  5349. if (scb == NULL) {
  5350. printf("qinpos = %d, SCB index = %d\n",
  5351. qinpos, ahc->qinfifo[qinpos]);
  5352. panic("Loop 1\n");
  5353. }
  5354. if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
  5355. /*
  5356. * We found an scb that needs to be acted on.
  5357. */
  5358. found++;
  5359. switch (action) {
  5360. case SEARCH_COMPLETE:
  5361. {
  5362. cam_status ostat;
  5363. cam_status cstat;
  5364. ostat = ahc_get_transaction_status(scb);
  5365. if (ostat == CAM_REQ_INPROG)
  5366. ahc_set_transaction_status(scb, status);
  5367. cstat = ahc_get_transaction_status(scb);
  5368. if (cstat != CAM_REQ_CMP)
  5369. ahc_freeze_scb(scb);
  5370. if ((scb->flags & SCB_ACTIVE) == 0)
  5371. printf("Inactive SCB in qinfifo\n");
  5372. ahc_done(ahc, scb);
  5373. /* FALLTHROUGH */
  5374. }
  5375. case SEARCH_REMOVE:
  5376. break;
  5377. case SEARCH_COUNT:
  5378. ahc_qinfifo_requeue(ahc, prev_scb, scb);
  5379. prev_scb = scb;
  5380. break;
  5381. }
  5382. } else {
  5383. ahc_qinfifo_requeue(ahc, prev_scb, scb);
  5384. prev_scb = scb;
  5385. }
  5386. qinpos++;
  5387. }
  5388. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  5389. ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
  5390. } else {
  5391. ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
  5392. }
  5393. if (action != SEARCH_COUNT
  5394. && (found != 0)
  5395. && (qinstart != ahc->qinfifonext)) {
  5396. /*
  5397. * The sequencer may be in the process of dmaing
  5398. * down the SCB at the beginning of the queue.
  5399. * This could be problematic if either the first,
  5400. * or the second SCB is removed from the queue
  5401. * (the first SCB includes a pointer to the "next"
  5402. * SCB to dma). If we have removed any entries, swap
  5403. * the first element in the queue with the next HSCB
  5404. * so the sequencer will notice that NEXT_QUEUED_SCB
  5405. * has changed during its dma attempt and will retry
  5406. * the DMA.
  5407. */
  5408. scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
  5409. if (scb == NULL) {
  5410. printf("found = %d, qinstart = %d, qinfifionext = %d\n",
  5411. found, qinstart, ahc->qinfifonext);
  5412. panic("First/Second Qinfifo fixup\n");
  5413. }
  5414. /*
  5415. * ahc_swap_with_next_hscb forces our next pointer to
  5416. * point to the reserved SCB for future commands. Save
  5417. * and restore our original next pointer to maintain
  5418. * queue integrity.
  5419. */
  5420. next = scb->hscb->next;
  5421. ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
  5422. ahc_swap_with_next_hscb(ahc, scb);
  5423. scb->hscb->next = next;
  5424. ahc->qinfifo[qinstart] = scb->hscb->tag;
  5425. /* Tell the card about the new head of the qinfifo. */
  5426. ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
  5427. /* Fixup the tail "next" pointer. */
  5428. qintail = ahc->qinfifonext - 1;
  5429. scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
  5430. scb->hscb->next = ahc->next_queued_scb->hscb->tag;
  5431. }
  5432. /*
  5433. * Search waiting for selection list.
  5434. */
  5435. curscbptr = ahc_inb(ahc, SCBPTR);
  5436. next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
  5437. prev = SCB_LIST_NULL;
  5438. while (next != SCB_LIST_NULL) {
  5439. uint8_t scb_index;
  5440. ahc_outb(ahc, SCBPTR, next);
  5441. scb_index = ahc_inb(ahc, SCB_TAG);
  5442. if (scb_index >= ahc->scb_data->numscbs) {
  5443. printf("Waiting List inconsistency. "
  5444. "SCB index == %d, yet numscbs == %d.",
  5445. scb_index, ahc->scb_data->numscbs);
  5446. ahc_dump_card_state(ahc);
  5447. panic("for safety");
  5448. }
  5449. scb = ahc_lookup_scb(ahc, scb_index);
  5450. if (scb == NULL) {
  5451. printf("scb_index = %d, next = %d\n",
  5452. scb_index, next);
  5453. panic("Waiting List traversal\n");
  5454. }
  5455. if (ahc_match_scb(ahc, scb, target, channel,
  5456. lun, SCB_LIST_NULL, role)) {
  5457. /*
  5458. * We found an scb that needs to be acted on.
  5459. */
  5460. found++;
  5461. switch (action) {
  5462. case SEARCH_COMPLETE:
  5463. {
  5464. cam_status ostat;
  5465. cam_status cstat;
  5466. ostat = ahc_get_transaction_status(scb);
  5467. if (ostat == CAM_REQ_INPROG)
  5468. ahc_set_transaction_status(scb,
  5469. status);
  5470. cstat = ahc_get_transaction_status(scb);
  5471. if (cstat != CAM_REQ_CMP)
  5472. ahc_freeze_scb(scb);
  5473. if ((scb->flags & SCB_ACTIVE) == 0)
  5474. printf("Inactive SCB in Waiting List\n");
  5475. ahc_done(ahc, scb);
  5476. /* FALLTHROUGH */
  5477. }
  5478. case SEARCH_REMOVE:
  5479. next = ahc_rem_wscb(ahc, next, prev);
  5480. break;
  5481. case SEARCH_COUNT:
  5482. prev = next;
  5483. next = ahc_inb(ahc, SCB_NEXT);
  5484. break;
  5485. }
  5486. } else {
  5487. prev = next;
  5488. next = ahc_inb(ahc, SCB_NEXT);
  5489. }
  5490. }
  5491. ahc_outb(ahc, SCBPTR, curscbptr);
  5492. found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
  5493. channel, lun, status, action);
  5494. if (action == SEARCH_COMPLETE)
  5495. ahc_release_untagged_queues(ahc);
  5496. return (found);
  5497. }
  5498. int
  5499. ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
  5500. int target, char channel, int lun, uint32_t status,
  5501. ahc_search_action action)
  5502. {
  5503. struct scb *scb;
  5504. int maxtarget;
  5505. int found;
  5506. int i;
  5507. if (action == SEARCH_COMPLETE) {
  5508. /*
  5509. * Don't attempt to run any queued untagged transactions
  5510. * until we are done with the abort process.
  5511. */
  5512. ahc_freeze_untagged_queues(ahc);
  5513. }
  5514. found = 0;
  5515. i = 0;
  5516. if ((ahc->flags & AHC_SCB_BTT) == 0) {
  5517. maxtarget = 16;
  5518. if (target != CAM_TARGET_WILDCARD) {
  5519. i = target;
  5520. if (channel == 'B')
  5521. i += 8;
  5522. maxtarget = i + 1;
  5523. }
  5524. } else {
  5525. maxtarget = 0;
  5526. }
  5527. for (; i < maxtarget; i++) {
  5528. struct scb_tailq *untagged_q;
  5529. struct scb *next_scb;
  5530. untagged_q = &(ahc->untagged_queues[i]);
  5531. next_scb = TAILQ_FIRST(untagged_q);
  5532. while (next_scb != NULL) {
  5533. scb = next_scb;
  5534. next_scb = TAILQ_NEXT(scb, links.tqe);
  5535. /*
  5536. * The head of the list may be the currently
  5537. * active untagged command for a device.
  5538. * We're only searching for commands that
  5539. * have not been started. A transaction
  5540. * marked active but still in the qinfifo
  5541. * is removed by the qinfifo scanning code
  5542. * above.
  5543. */
  5544. if ((scb->flags & SCB_ACTIVE) != 0)
  5545. continue;
  5546. if (ahc_match_scb(ahc, scb, target, channel, lun,
  5547. SCB_LIST_NULL, ROLE_INITIATOR) == 0
  5548. || (ctx != NULL && ctx != scb->io_ctx))
  5549. continue;
  5550. /*
  5551. * We found an scb that needs to be acted on.
  5552. */
  5553. found++;
  5554. switch (action) {
  5555. case SEARCH_COMPLETE:
  5556. {
  5557. cam_status ostat;
  5558. cam_status cstat;
  5559. ostat = ahc_get_transaction_status(scb);
  5560. if (ostat == CAM_REQ_INPROG)
  5561. ahc_set_transaction_status(scb, status);
  5562. cstat = ahc_get_transaction_status(scb);
  5563. if (cstat != CAM_REQ_CMP)
  5564. ahc_freeze_scb(scb);
  5565. if ((scb->flags & SCB_ACTIVE) == 0)
  5566. printf("Inactive SCB in untaggedQ\n");
  5567. ahc_done(ahc, scb);
  5568. break;
  5569. }
  5570. case SEARCH_REMOVE:
  5571. scb->flags &= ~SCB_UNTAGGEDQ;
  5572. TAILQ_REMOVE(untagged_q, scb, links.tqe);
  5573. break;
  5574. case SEARCH_COUNT:
  5575. break;
  5576. }
  5577. }
  5578. }
  5579. if (action == SEARCH_COMPLETE)
  5580. ahc_release_untagged_queues(ahc);
  5581. return (found);
  5582. }
  5583. int
  5584. ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
  5585. int lun, u_int tag, int stop_on_first, int remove,
  5586. int save_state)
  5587. {
  5588. struct scb *scbp;
  5589. u_int next;
  5590. u_int prev;
  5591. u_int count;
  5592. u_int active_scb;
  5593. count = 0;
  5594. next = ahc_inb(ahc, DISCONNECTED_SCBH);
  5595. prev = SCB_LIST_NULL;
  5596. if (save_state) {
  5597. /* restore this when we're done */
  5598. active_scb = ahc_inb(ahc, SCBPTR);
  5599. } else
  5600. /* Silence compiler */
  5601. active_scb = SCB_LIST_NULL;
  5602. while (next != SCB_LIST_NULL) {
  5603. u_int scb_index;
  5604. ahc_outb(ahc, SCBPTR, next);
  5605. scb_index = ahc_inb(ahc, SCB_TAG);
  5606. if (scb_index >= ahc->scb_data->numscbs) {
  5607. printf("Disconnected List inconsistency. "
  5608. "SCB index == %d, yet numscbs == %d.",
  5609. scb_index, ahc->scb_data->numscbs);
  5610. ahc_dump_card_state(ahc);
  5611. panic("for safety");
  5612. }
  5613. if (next == prev) {
  5614. panic("Disconnected List Loop. "
  5615. "cur SCBPTR == %x, prev SCBPTR == %x.",
  5616. next, prev);
  5617. }
  5618. scbp = ahc_lookup_scb(ahc, scb_index);
  5619. if (ahc_match_scb(ahc, scbp, target, channel, lun,
  5620. tag, ROLE_INITIATOR)) {
  5621. count++;
  5622. if (remove) {
  5623. next =
  5624. ahc_rem_scb_from_disc_list(ahc, prev, next);
  5625. } else {
  5626. prev = next;
  5627. next = ahc_inb(ahc, SCB_NEXT);
  5628. }
  5629. if (stop_on_first)
  5630. break;
  5631. } else {
  5632. prev = next;
  5633. next = ahc_inb(ahc, SCB_NEXT);
  5634. }
  5635. }
  5636. if (save_state)
  5637. ahc_outb(ahc, SCBPTR, active_scb);
  5638. return (count);
  5639. }
  5640. /*
  5641. * Remove an SCB from the on chip list of disconnected transactions.
  5642. * This is empty/unused if we are not performing SCB paging.
  5643. */
  5644. static u_int
  5645. ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
  5646. {
  5647. u_int next;
  5648. ahc_outb(ahc, SCBPTR, scbptr);
  5649. next = ahc_inb(ahc, SCB_NEXT);
  5650. ahc_outb(ahc, SCB_CONTROL, 0);
  5651. ahc_add_curscb_to_free_list(ahc);
  5652. if (prev != SCB_LIST_NULL) {
  5653. ahc_outb(ahc, SCBPTR, prev);
  5654. ahc_outb(ahc, SCB_NEXT, next);
  5655. } else
  5656. ahc_outb(ahc, DISCONNECTED_SCBH, next);
  5657. return (next);
  5658. }
  5659. /*
  5660. * Add the SCB as selected by SCBPTR onto the on chip list of
  5661. * free hardware SCBs. This list is empty/unused if we are not
  5662. * performing SCB paging.
  5663. */
  5664. static void
  5665. ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
  5666. {
  5667. /*
  5668. * Invalidate the tag so that our abort
  5669. * routines don't think it's active.
  5670. */
  5671. ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
  5672. if ((ahc->flags & AHC_PAGESCBS) != 0) {
  5673. ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
  5674. ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
  5675. }
  5676. }
  5677. /*
  5678. * Manipulate the waiting for selection list and return the
  5679. * scb that follows the one that we remove.
  5680. */
  5681. static u_int
  5682. ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
  5683. {
  5684. u_int curscb, next;
  5685. /*
  5686. * Select the SCB we want to abort and
  5687. * pull the next pointer out of it.
  5688. */
  5689. curscb = ahc_inb(ahc, SCBPTR);
  5690. ahc_outb(ahc, SCBPTR, scbpos);
  5691. next = ahc_inb(ahc, SCB_NEXT);
  5692. /* Clear the necessary fields */
  5693. ahc_outb(ahc, SCB_CONTROL, 0);
  5694. ahc_add_curscb_to_free_list(ahc);
  5695. /* update the waiting list */
  5696. if (prev == SCB_LIST_NULL) {
  5697. /* First in the list */
  5698. ahc_outb(ahc, WAITING_SCBH, next);
  5699. /*
  5700. * Ensure we aren't attempting to perform
  5701. * selection for this entry.
  5702. */
  5703. ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
  5704. } else {
  5705. /*
  5706. * Select the scb that pointed to us
  5707. * and update its next pointer.
  5708. */
  5709. ahc_outb(ahc, SCBPTR, prev);
  5710. ahc_outb(ahc, SCB_NEXT, next);
  5711. }
  5712. /*
  5713. * Point us back at the original scb position.
  5714. */
  5715. ahc_outb(ahc, SCBPTR, curscb);
  5716. return next;
  5717. }
  5718. /******************************** Error Handling ******************************/
  5719. /*
  5720. * Abort all SCBs that match the given description (target/channel/lun/tag),
  5721. * setting their status to the passed in status if the status has not already
  5722. * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
  5723. * is paused before it is called.
  5724. */
  5725. static int
  5726. ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
  5727. int lun, u_int tag, role_t role, uint32_t status)
  5728. {
  5729. struct scb *scbp;
  5730. struct scb *scbp_next;
  5731. u_int active_scb;
  5732. int i, j;
  5733. int maxtarget;
  5734. int minlun;
  5735. int maxlun;
  5736. int found;
  5737. /*
  5738. * Don't attempt to run any queued untagged transactions
  5739. * until we are done with the abort process.
  5740. */
  5741. ahc_freeze_untagged_queues(ahc);
  5742. /* restore this when we're done */
  5743. active_scb = ahc_inb(ahc, SCBPTR);
  5744. found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
  5745. role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
  5746. /*
  5747. * Clean out the busy target table for any untagged commands.
  5748. */
  5749. i = 0;
  5750. maxtarget = 16;
  5751. if (target != CAM_TARGET_WILDCARD) {
  5752. i = target;
  5753. if (channel == 'B')
  5754. i += 8;
  5755. maxtarget = i + 1;
  5756. }
  5757. if (lun == CAM_LUN_WILDCARD) {
  5758. /*
  5759. * Unless we are using an SCB based
  5760. * busy targets table, there is only
  5761. * one table entry for all luns of
  5762. * a target.
  5763. */
  5764. minlun = 0;
  5765. maxlun = 1;
  5766. if ((ahc->flags & AHC_SCB_BTT) != 0)
  5767. maxlun = AHC_NUM_LUNS;
  5768. } else {
  5769. minlun = lun;
  5770. maxlun = lun + 1;
  5771. }
  5772. if (role != ROLE_TARGET) {
  5773. for (;i < maxtarget; i++) {
  5774. for (j = minlun;j < maxlun; j++) {
  5775. u_int scbid;
  5776. u_int tcl;
  5777. tcl = BUILD_TCL(i << 4, j);
  5778. scbid = ahc_index_busy_tcl(ahc, tcl);
  5779. scbp = ahc_lookup_scb(ahc, scbid);
  5780. if (scbp == NULL
  5781. || ahc_match_scb(ahc, scbp, target, channel,
  5782. lun, tag, role) == 0)
  5783. continue;
  5784. ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
  5785. }
  5786. }
  5787. /*
  5788. * Go through the disconnected list and remove any entries we
  5789. * have queued for completion, 0'ing their control byte too.
  5790. * We save the active SCB and restore it ourselves, so there
  5791. * is no reason for this search to restore it too.
  5792. */
  5793. ahc_search_disc_list(ahc, target, channel, lun, tag,
  5794. /*stop_on_first*/FALSE, /*remove*/TRUE,
  5795. /*save_state*/FALSE);
  5796. }
  5797. /*
  5798. * Go through the hardware SCB array looking for commands that
  5799. * were active but not on any list. In some cases, these remnants
  5800. * might not still have mappings in the scbindex array (e.g. unexpected
  5801. * bus free with the same scb queued for an abort). Don't hold this
  5802. * against them.
  5803. */
  5804. for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
  5805. u_int scbid;
  5806. ahc_outb(ahc, SCBPTR, i);
  5807. scbid = ahc_inb(ahc, SCB_TAG);
  5808. scbp = ahc_lookup_scb(ahc, scbid);
  5809. if ((scbp == NULL && scbid != SCB_LIST_NULL)
  5810. || (scbp != NULL
  5811. && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
  5812. ahc_add_curscb_to_free_list(ahc);
  5813. }
  5814. /*
  5815. * Go through the pending CCB list and look for
  5816. * commands for this target that are still active.
  5817. * These are other tagged commands that were
  5818. * disconnected when the reset occurred.
  5819. */
  5820. scbp_next = LIST_FIRST(&ahc->pending_scbs);
  5821. while (scbp_next != NULL) {
  5822. scbp = scbp_next;
  5823. scbp_next = LIST_NEXT(scbp, pending_links);
  5824. if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
  5825. cam_status ostat;
  5826. ostat = ahc_get_transaction_status(scbp);
  5827. if (ostat == CAM_REQ_INPROG)
  5828. ahc_set_transaction_status(scbp, status);
  5829. if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
  5830. ahc_freeze_scb(scbp);
  5831. if ((scbp->flags & SCB_ACTIVE) == 0)
  5832. printf("Inactive SCB on pending list\n");
  5833. ahc_done(ahc, scbp);
  5834. found++;
  5835. }
  5836. }
  5837. ahc_outb(ahc, SCBPTR, active_scb);
  5838. ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
  5839. ahc_release_untagged_queues(ahc);
  5840. return found;
  5841. }
  5842. static void
  5843. ahc_reset_current_bus(struct ahc_softc *ahc)
  5844. {
  5845. uint8_t scsiseq;
  5846. ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
  5847. scsiseq = ahc_inb(ahc, SCSISEQ);
  5848. ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
  5849. ahc_flush_device_writes(ahc);
  5850. ahc_delay(AHC_BUSRESET_DELAY);
  5851. /* Turn off the bus reset */
  5852. ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
  5853. ahc_clear_intstat(ahc);
  5854. /* Re-enable reset interrupts */
  5855. ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
  5856. }
  5857. int
  5858. ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
  5859. {
  5860. struct ahc_devinfo devinfo;
  5861. u_int initiator, target, max_scsiid;
  5862. u_int sblkctl;
  5863. u_int scsiseq;
  5864. u_int simode1;
  5865. int found;
  5866. int restart_needed;
  5867. char cur_channel;
  5868. ahc->pending_device = NULL;
  5869. ahc_compile_devinfo(&devinfo,
  5870. CAM_TARGET_WILDCARD,
  5871. CAM_TARGET_WILDCARD,
  5872. CAM_LUN_WILDCARD,
  5873. channel, ROLE_UNKNOWN);
  5874. ahc_pause(ahc);
  5875. /* Make sure the sequencer is in a safe location. */
  5876. ahc_clear_critical_section(ahc);
  5877. /*
  5878. * Run our command complete fifos to ensure that we perform
  5879. * completion processing on any commands that 'completed'
  5880. * before the reset occurred.
  5881. */
  5882. ahc_run_qoutfifo(ahc);
  5883. #ifdef AHC_TARGET_MODE
  5884. /*
  5885. * XXX - In Twin mode, the tqinfifo may have commands
  5886. * for an unaffected channel in it. However, if
  5887. * we have run out of ATIO resources to drain that
  5888. * queue, we may not get them all out here. Further,
  5889. * the blocked transactions for the reset channel
  5890. * should just be killed off, irrespecitve of whether
  5891. * we are blocked on ATIO resources. Write a routine
  5892. * to compact the tqinfifo appropriately.
  5893. */
  5894. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  5895. ahc_run_tqinfifo(ahc, /*paused*/TRUE);
  5896. }
  5897. #endif
  5898. /*
  5899. * Reset the bus if we are initiating this reset
  5900. */
  5901. sblkctl = ahc_inb(ahc, SBLKCTL);
  5902. cur_channel = 'A';
  5903. if ((ahc->features & AHC_TWIN) != 0
  5904. && ((sblkctl & SELBUSB) != 0))
  5905. cur_channel = 'B';
  5906. scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
  5907. if (cur_channel != channel) {
  5908. /* Case 1: Command for another bus is active
  5909. * Stealthily reset the other bus without
  5910. * upsetting the current bus.
  5911. */
  5912. ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
  5913. simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
  5914. #ifdef AHC_TARGET_MODE
  5915. /*
  5916. * Bus resets clear ENSELI, so we cannot
  5917. * defer re-enabling bus reset interrupts
  5918. * if we are in target mode.
  5919. */
  5920. if ((ahc->flags & AHC_TARGETROLE) != 0)
  5921. simode1 |= ENSCSIRST;
  5922. #endif
  5923. ahc_outb(ahc, SIMODE1, simode1);
  5924. if (initiate_reset)
  5925. ahc_reset_current_bus(ahc);
  5926. ahc_clear_intstat(ahc);
  5927. ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
  5928. ahc_outb(ahc, SBLKCTL, sblkctl);
  5929. restart_needed = FALSE;
  5930. } else {
  5931. /* Case 2: A command from this bus is active or we're idle */
  5932. simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
  5933. #ifdef AHC_TARGET_MODE
  5934. /*
  5935. * Bus resets clear ENSELI, so we cannot
  5936. * defer re-enabling bus reset interrupts
  5937. * if we are in target mode.
  5938. */
  5939. if ((ahc->flags & AHC_TARGETROLE) != 0)
  5940. simode1 |= ENSCSIRST;
  5941. #endif
  5942. ahc_outb(ahc, SIMODE1, simode1);
  5943. if (initiate_reset)
  5944. ahc_reset_current_bus(ahc);
  5945. ahc_clear_intstat(ahc);
  5946. ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
  5947. restart_needed = TRUE;
  5948. }
  5949. /*
  5950. * Clean up all the state information for the
  5951. * pending transactions on this bus.
  5952. */
  5953. found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
  5954. CAM_LUN_WILDCARD, SCB_LIST_NULL,
  5955. ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
  5956. max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
  5957. #ifdef AHC_TARGET_MODE
  5958. /*
  5959. * Send an immediate notify ccb to all target more peripheral
  5960. * drivers affected by this action.
  5961. */
  5962. for (target = 0; target <= max_scsiid; target++) {
  5963. struct ahc_tmode_tstate* tstate;
  5964. u_int lun;
  5965. tstate = ahc->enabled_targets[target];
  5966. if (tstate == NULL)
  5967. continue;
  5968. for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
  5969. struct ahc_tmode_lstate* lstate;
  5970. lstate = tstate->enabled_luns[lun];
  5971. if (lstate == NULL)
  5972. continue;
  5973. ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
  5974. EVENT_TYPE_BUS_RESET, /*arg*/0);
  5975. ahc_send_lstate_events(ahc, lstate);
  5976. }
  5977. }
  5978. #endif
  5979. /* Notify the XPT that a bus reset occurred */
  5980. ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
  5981. CAM_LUN_WILDCARD, AC_BUS_RESET);
  5982. /*
  5983. * Revert to async/narrow transfers until we renegotiate.
  5984. */
  5985. for (target = 0; target <= max_scsiid; target++) {
  5986. if (ahc->enabled_targets[target] == NULL)
  5987. continue;
  5988. for (initiator = 0; initiator <= max_scsiid; initiator++) {
  5989. struct ahc_devinfo devinfo;
  5990. ahc_compile_devinfo(&devinfo, target, initiator,
  5991. CAM_LUN_WILDCARD,
  5992. channel, ROLE_UNKNOWN);
  5993. ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  5994. AHC_TRANS_CUR, /*paused*/TRUE);
  5995. ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
  5996. /*period*/0, /*offset*/0,
  5997. /*ppr_options*/0, AHC_TRANS_CUR,
  5998. /*paused*/TRUE);
  5999. }
  6000. }
  6001. if (restart_needed)
  6002. ahc_restart(ahc);
  6003. else
  6004. ahc_unpause(ahc);
  6005. return found;
  6006. }
  6007. /***************************** Residual Processing ****************************/
  6008. /*
  6009. * Calculate the residual for a just completed SCB.
  6010. */
  6011. static void
  6012. ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
  6013. {
  6014. struct hardware_scb *hscb;
  6015. struct status_pkt *spkt;
  6016. uint32_t sgptr;
  6017. uint32_t resid_sgptr;
  6018. uint32_t resid;
  6019. /*
  6020. * 5 cases.
  6021. * 1) No residual.
  6022. * SG_RESID_VALID clear in sgptr.
  6023. * 2) Transferless command
  6024. * 3) Never performed any transfers.
  6025. * sgptr has SG_FULL_RESID set.
  6026. * 4) No residual but target did not
  6027. * save data pointers after the
  6028. * last transfer, so sgptr was
  6029. * never updated.
  6030. * 5) We have a partial residual.
  6031. * Use residual_sgptr to determine
  6032. * where we are.
  6033. */
  6034. hscb = scb->hscb;
  6035. sgptr = ahc_le32toh(hscb->sgptr);
  6036. if ((sgptr & SG_RESID_VALID) == 0)
  6037. /* Case 1 */
  6038. return;
  6039. sgptr &= ~SG_RESID_VALID;
  6040. if ((sgptr & SG_LIST_NULL) != 0)
  6041. /* Case 2 */
  6042. return;
  6043. spkt = &hscb->shared_data.status;
  6044. resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
  6045. if ((sgptr & SG_FULL_RESID) != 0) {
  6046. /* Case 3 */
  6047. resid = ahc_get_transfer_length(scb);
  6048. } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
  6049. /* Case 4 */
  6050. return;
  6051. } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
  6052. panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
  6053. } else {
  6054. struct ahc_dma_seg *sg;
  6055. /*
  6056. * Remainder of the SG where the transfer
  6057. * stopped.
  6058. */
  6059. resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
  6060. sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
  6061. /* The residual sg_ptr always points to the next sg */
  6062. sg--;
  6063. /*
  6064. * Add up the contents of all residual
  6065. * SG segments that are after the SG where
  6066. * the transfer stopped.
  6067. */
  6068. while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
  6069. sg++;
  6070. resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
  6071. }
  6072. }
  6073. if ((scb->flags & SCB_SENSE) == 0)
  6074. ahc_set_residual(scb, resid);
  6075. else
  6076. ahc_set_sense_residual(scb, resid);
  6077. #ifdef AHC_DEBUG
  6078. if ((ahc_debug & AHC_SHOW_MISC) != 0) {
  6079. ahc_print_path(ahc, scb);
  6080. printf("Handled %sResidual of %d bytes\n",
  6081. (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
  6082. }
  6083. #endif
  6084. }
  6085. /******************************* Target Mode **********************************/
  6086. #ifdef AHC_TARGET_MODE
  6087. /*
  6088. * Add a target mode event to this lun's queue
  6089. */
  6090. static void
  6091. ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
  6092. u_int initiator_id, u_int event_type, u_int event_arg)
  6093. {
  6094. struct ahc_tmode_event *event;
  6095. int pending;
  6096. xpt_freeze_devq(lstate->path, /*count*/1);
  6097. if (lstate->event_w_idx >= lstate->event_r_idx)
  6098. pending = lstate->event_w_idx - lstate->event_r_idx;
  6099. else
  6100. pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
  6101. - (lstate->event_r_idx - lstate->event_w_idx);
  6102. if (event_type == EVENT_TYPE_BUS_RESET
  6103. || event_type == MSG_BUS_DEV_RESET) {
  6104. /*
  6105. * Any earlier events are irrelevant, so reset our buffer.
  6106. * This has the effect of allowing us to deal with reset
  6107. * floods (an external device holding down the reset line)
  6108. * without losing the event that is really interesting.
  6109. */
  6110. lstate->event_r_idx = 0;
  6111. lstate->event_w_idx = 0;
  6112. xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
  6113. }
  6114. if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
  6115. xpt_print_path(lstate->path);
  6116. printf("immediate event %x:%x lost\n",
  6117. lstate->event_buffer[lstate->event_r_idx].event_type,
  6118. lstate->event_buffer[lstate->event_r_idx].event_arg);
  6119. lstate->event_r_idx++;
  6120. if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
  6121. lstate->event_r_idx = 0;
  6122. xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
  6123. }
  6124. event = &lstate->event_buffer[lstate->event_w_idx];
  6125. event->initiator_id = initiator_id;
  6126. event->event_type = event_type;
  6127. event->event_arg = event_arg;
  6128. lstate->event_w_idx++;
  6129. if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
  6130. lstate->event_w_idx = 0;
  6131. }
  6132. /*
  6133. * Send any target mode events queued up waiting
  6134. * for immediate notify resources.
  6135. */
  6136. void
  6137. ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
  6138. {
  6139. struct ccb_hdr *ccbh;
  6140. struct ccb_immed_notify *inot;
  6141. while (lstate->event_r_idx != lstate->event_w_idx
  6142. && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
  6143. struct ahc_tmode_event *event;
  6144. event = &lstate->event_buffer[lstate->event_r_idx];
  6145. SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
  6146. inot = (struct ccb_immed_notify *)ccbh;
  6147. switch (event->event_type) {
  6148. case EVENT_TYPE_BUS_RESET:
  6149. ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
  6150. break;
  6151. default:
  6152. ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
  6153. inot->message_args[0] = event->event_type;
  6154. inot->message_args[1] = event->event_arg;
  6155. break;
  6156. }
  6157. inot->initiator_id = event->initiator_id;
  6158. inot->sense_len = 0;
  6159. xpt_done((union ccb *)inot);
  6160. lstate->event_r_idx++;
  6161. if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
  6162. lstate->event_r_idx = 0;
  6163. }
  6164. }
  6165. #endif
  6166. /******************** Sequencer Program Patching/Download *********************/
  6167. #ifdef AHC_DUMP_SEQ
  6168. void
  6169. ahc_dumpseq(struct ahc_softc* ahc)
  6170. {
  6171. int i;
  6172. ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
  6173. ahc_outb(ahc, SEQADDR0, 0);
  6174. ahc_outb(ahc, SEQADDR1, 0);
  6175. for (i = 0; i < ahc->instruction_ram_size; i++) {
  6176. uint8_t ins_bytes[4];
  6177. ahc_insb(ahc, SEQRAM, ins_bytes, 4);
  6178. printf("0x%08x\n", ins_bytes[0] << 24
  6179. | ins_bytes[1] << 16
  6180. | ins_bytes[2] << 8
  6181. | ins_bytes[3]);
  6182. }
  6183. }
  6184. #endif
  6185. static int
  6186. ahc_loadseq(struct ahc_softc *ahc)
  6187. {
  6188. struct cs cs_table[num_critical_sections];
  6189. u_int begin_set[num_critical_sections];
  6190. u_int end_set[num_critical_sections];
  6191. const struct patch *cur_patch;
  6192. u_int cs_count;
  6193. u_int cur_cs;
  6194. u_int i;
  6195. u_int skip_addr;
  6196. u_int sg_prefetch_cnt;
  6197. int downloaded;
  6198. uint8_t download_consts[7];
  6199. /*
  6200. * Start out with 0 critical sections
  6201. * that apply to this firmware load.
  6202. */
  6203. cs_count = 0;
  6204. cur_cs = 0;
  6205. memset(begin_set, 0, sizeof(begin_set));
  6206. memset(end_set, 0, sizeof(end_set));
  6207. /* Setup downloadable constant table */
  6208. download_consts[QOUTFIFO_OFFSET] = 0;
  6209. if (ahc->targetcmds != NULL)
  6210. download_consts[QOUTFIFO_OFFSET] += 32;
  6211. download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
  6212. download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
  6213. download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
  6214. sg_prefetch_cnt = ahc->pci_cachesize;
  6215. if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
  6216. sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
  6217. download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
  6218. download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
  6219. download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
  6220. cur_patch = patches;
  6221. downloaded = 0;
  6222. skip_addr = 0;
  6223. ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
  6224. ahc_outb(ahc, SEQADDR0, 0);
  6225. ahc_outb(ahc, SEQADDR1, 0);
  6226. for (i = 0; i < sizeof(seqprog)/4; i++) {
  6227. if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
  6228. /*
  6229. * Don't download this instruction as it
  6230. * is in a patch that was removed.
  6231. */
  6232. continue;
  6233. }
  6234. if (downloaded == ahc->instruction_ram_size) {
  6235. /*
  6236. * We're about to exceed the instruction
  6237. * storage capacity for this chip. Fail
  6238. * the load.
  6239. */
  6240. printf("\n%s: Program too large for instruction memory "
  6241. "size of %d!\n", ahc_name(ahc),
  6242. ahc->instruction_ram_size);
  6243. return (ENOMEM);
  6244. }
  6245. /*
  6246. * Move through the CS table until we find a CS
  6247. * that might apply to this instruction.
  6248. */
  6249. for (; cur_cs < num_critical_sections; cur_cs++) {
  6250. if (critical_sections[cur_cs].end <= i) {
  6251. if (begin_set[cs_count] == TRUE
  6252. && end_set[cs_count] == FALSE) {
  6253. cs_table[cs_count].end = downloaded;
  6254. end_set[cs_count] = TRUE;
  6255. cs_count++;
  6256. }
  6257. continue;
  6258. }
  6259. if (critical_sections[cur_cs].begin <= i
  6260. && begin_set[cs_count] == FALSE) {
  6261. cs_table[cs_count].begin = downloaded;
  6262. begin_set[cs_count] = TRUE;
  6263. }
  6264. break;
  6265. }
  6266. ahc_download_instr(ahc, i, download_consts);
  6267. downloaded++;
  6268. }
  6269. ahc->num_critical_sections = cs_count;
  6270. if (cs_count != 0) {
  6271. cs_count *= sizeof(struct cs);
  6272. ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
  6273. if (ahc->critical_sections == NULL)
  6274. panic("ahc_loadseq: Could not malloc");
  6275. memcpy(ahc->critical_sections, cs_table, cs_count);
  6276. }
  6277. ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
  6278. if (bootverbose) {
  6279. printf(" %d instructions downloaded\n", downloaded);
  6280. printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
  6281. ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
  6282. }
  6283. return (0);
  6284. }
  6285. static int
  6286. ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
  6287. u_int start_instr, u_int *skip_addr)
  6288. {
  6289. const struct patch *cur_patch;
  6290. const struct patch *last_patch;
  6291. u_int num_patches;
  6292. num_patches = ARRAY_SIZE(patches);
  6293. last_patch = &patches[num_patches];
  6294. cur_patch = *start_patch;
  6295. while (cur_patch < last_patch && start_instr == cur_patch->begin) {
  6296. if (cur_patch->patch_func(ahc) == 0) {
  6297. /* Start rejecting code */
  6298. *skip_addr = start_instr + cur_patch->skip_instr;
  6299. cur_patch += cur_patch->skip_patch;
  6300. } else {
  6301. /* Accepted this patch. Advance to the next
  6302. * one and wait for our intruction pointer to
  6303. * hit this point.
  6304. */
  6305. cur_patch++;
  6306. }
  6307. }
  6308. *start_patch = cur_patch;
  6309. if (start_instr < *skip_addr)
  6310. /* Still skipping */
  6311. return (0);
  6312. return (1);
  6313. }
  6314. static void
  6315. ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
  6316. {
  6317. union ins_formats instr;
  6318. struct ins_format1 *fmt1_ins;
  6319. struct ins_format3 *fmt3_ins;
  6320. u_int opcode;
  6321. /*
  6322. * The firmware is always compiled into a little endian format.
  6323. */
  6324. instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
  6325. fmt1_ins = &instr.format1;
  6326. fmt3_ins = NULL;
  6327. /* Pull the opcode */
  6328. opcode = instr.format1.opcode;
  6329. switch (opcode) {
  6330. case AIC_OP_JMP:
  6331. case AIC_OP_JC:
  6332. case AIC_OP_JNC:
  6333. case AIC_OP_CALL:
  6334. case AIC_OP_JNE:
  6335. case AIC_OP_JNZ:
  6336. case AIC_OP_JE:
  6337. case AIC_OP_JZ:
  6338. {
  6339. const struct patch *cur_patch;
  6340. int address_offset;
  6341. u_int address;
  6342. u_int skip_addr;
  6343. u_int i;
  6344. fmt3_ins = &instr.format3;
  6345. address_offset = 0;
  6346. address = fmt3_ins->address;
  6347. cur_patch = patches;
  6348. skip_addr = 0;
  6349. for (i = 0; i < address;) {
  6350. ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
  6351. if (skip_addr > i) {
  6352. int end_addr;
  6353. end_addr = min(address, skip_addr);
  6354. address_offset += end_addr - i;
  6355. i = skip_addr;
  6356. } else {
  6357. i++;
  6358. }
  6359. }
  6360. address -= address_offset;
  6361. fmt3_ins->address = address;
  6362. /* FALLTHROUGH */
  6363. }
  6364. case AIC_OP_OR:
  6365. case AIC_OP_AND:
  6366. case AIC_OP_XOR:
  6367. case AIC_OP_ADD:
  6368. case AIC_OP_ADC:
  6369. case AIC_OP_BMOV:
  6370. if (fmt1_ins->parity != 0) {
  6371. fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
  6372. }
  6373. fmt1_ins->parity = 0;
  6374. if ((ahc->features & AHC_CMD_CHAN) == 0
  6375. && opcode == AIC_OP_BMOV) {
  6376. /*
  6377. * Block move was added at the same time
  6378. * as the command channel. Verify that
  6379. * this is only a move of a single element
  6380. * and convert the BMOV to a MOV
  6381. * (AND with an immediate of FF).
  6382. */
  6383. if (fmt1_ins->immediate != 1)
  6384. panic("%s: BMOV not supported\n",
  6385. ahc_name(ahc));
  6386. fmt1_ins->opcode = AIC_OP_AND;
  6387. fmt1_ins->immediate = 0xff;
  6388. }
  6389. /* FALLTHROUGH */
  6390. case AIC_OP_ROL:
  6391. if ((ahc->features & AHC_ULTRA2) != 0) {
  6392. int i, count;
  6393. /* Calculate odd parity for the instruction */
  6394. for (i = 0, count = 0; i < 31; i++) {
  6395. uint32_t mask;
  6396. mask = 0x01 << i;
  6397. if ((instr.integer & mask) != 0)
  6398. count++;
  6399. }
  6400. if ((count & 0x01) == 0)
  6401. instr.format1.parity = 1;
  6402. } else {
  6403. /* Compress the instruction for older sequencers */
  6404. if (fmt3_ins != NULL) {
  6405. instr.integer =
  6406. fmt3_ins->immediate
  6407. | (fmt3_ins->source << 8)
  6408. | (fmt3_ins->address << 16)
  6409. | (fmt3_ins->opcode << 25);
  6410. } else {
  6411. instr.integer =
  6412. fmt1_ins->immediate
  6413. | (fmt1_ins->source << 8)
  6414. | (fmt1_ins->destination << 16)
  6415. | (fmt1_ins->ret << 24)
  6416. | (fmt1_ins->opcode << 25);
  6417. }
  6418. }
  6419. /* The sequencer is a little endian cpu */
  6420. instr.integer = ahc_htole32(instr.integer);
  6421. ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
  6422. break;
  6423. default:
  6424. panic("Unknown opcode encountered in seq program");
  6425. break;
  6426. }
  6427. }
  6428. int
  6429. ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries,
  6430. const char *name, u_int address, u_int value,
  6431. u_int *cur_column, u_int wrap_point)
  6432. {
  6433. int printed;
  6434. u_int printed_mask;
  6435. if (cur_column != NULL && *cur_column >= wrap_point) {
  6436. printf("\n");
  6437. *cur_column = 0;
  6438. }
  6439. printed = printf("%s[0x%x]", name, value);
  6440. if (table == NULL) {
  6441. printed += printf(" ");
  6442. *cur_column += printed;
  6443. return (printed);
  6444. }
  6445. printed_mask = 0;
  6446. while (printed_mask != 0xFF) {
  6447. int entry;
  6448. for (entry = 0; entry < num_entries; entry++) {
  6449. if (((value & table[entry].mask)
  6450. != table[entry].value)
  6451. || ((printed_mask & table[entry].mask)
  6452. == table[entry].mask))
  6453. continue;
  6454. printed += printf("%s%s",
  6455. printed_mask == 0 ? ":(" : "|",
  6456. table[entry].name);
  6457. printed_mask |= table[entry].mask;
  6458. break;
  6459. }
  6460. if (entry >= num_entries)
  6461. break;
  6462. }
  6463. if (printed_mask != 0)
  6464. printed += printf(") ");
  6465. else
  6466. printed += printf(" ");
  6467. if (cur_column != NULL)
  6468. *cur_column += printed;
  6469. return (printed);
  6470. }
  6471. void
  6472. ahc_dump_card_state(struct ahc_softc *ahc)
  6473. {
  6474. struct scb *scb;
  6475. struct scb_tailq *untagged_q;
  6476. u_int cur_col;
  6477. int paused;
  6478. int target;
  6479. int maxtarget;
  6480. int i;
  6481. uint8_t last_phase;
  6482. uint8_t qinpos;
  6483. uint8_t qintail;
  6484. uint8_t qoutpos;
  6485. uint8_t scb_index;
  6486. uint8_t saved_scbptr;
  6487. if (ahc_is_paused(ahc)) {
  6488. paused = 1;
  6489. } else {
  6490. paused = 0;
  6491. ahc_pause(ahc);
  6492. }
  6493. saved_scbptr = ahc_inb(ahc, SCBPTR);
  6494. last_phase = ahc_inb(ahc, LASTPHASE);
  6495. printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
  6496. "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
  6497. ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
  6498. ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
  6499. if (paused)
  6500. printf("Card was paused\n");
  6501. printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
  6502. ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
  6503. ahc_inb(ahc, ARG_2));
  6504. printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
  6505. ahc_inb(ahc, SCBPTR));
  6506. cur_col = 0;
  6507. if ((ahc->features & AHC_DT) != 0)
  6508. ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
  6509. ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
  6510. ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
  6511. ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
  6512. ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
  6513. ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
  6514. ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
  6515. ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
  6516. ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
  6517. ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
  6518. ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
  6519. ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
  6520. ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
  6521. ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
  6522. ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
  6523. ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
  6524. ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
  6525. ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
  6526. ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
  6527. if (cur_col != 0)
  6528. printf("\n");
  6529. printf("STACK:");
  6530. for (i = 0; i < STACK_SIZE; i++)
  6531. printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
  6532. printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
  6533. printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
  6534. printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
  6535. /* QINFIFO */
  6536. printf("QINFIFO entries: ");
  6537. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  6538. qinpos = ahc_inb(ahc, SNSCB_QOFF);
  6539. ahc_outb(ahc, SNSCB_QOFF, qinpos);
  6540. } else
  6541. qinpos = ahc_inb(ahc, QINPOS);
  6542. qintail = ahc->qinfifonext;
  6543. while (qinpos != qintail) {
  6544. printf("%d ", ahc->qinfifo[qinpos]);
  6545. qinpos++;
  6546. }
  6547. printf("\n");
  6548. printf("Waiting Queue entries: ");
  6549. scb_index = ahc_inb(ahc, WAITING_SCBH);
  6550. i = 0;
  6551. while (scb_index != SCB_LIST_NULL && i++ < 256) {
  6552. ahc_outb(ahc, SCBPTR, scb_index);
  6553. printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
  6554. scb_index = ahc_inb(ahc, SCB_NEXT);
  6555. }
  6556. printf("\n");
  6557. printf("Disconnected Queue entries: ");
  6558. scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
  6559. i = 0;
  6560. while (scb_index != SCB_LIST_NULL && i++ < 256) {
  6561. ahc_outb(ahc, SCBPTR, scb_index);
  6562. printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
  6563. scb_index = ahc_inb(ahc, SCB_NEXT);
  6564. }
  6565. printf("\n");
  6566. ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
  6567. printf("QOUTFIFO entries: ");
  6568. qoutpos = ahc->qoutfifonext;
  6569. i = 0;
  6570. while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
  6571. printf("%d ", ahc->qoutfifo[qoutpos]);
  6572. qoutpos++;
  6573. }
  6574. printf("\n");
  6575. printf("Sequencer Free SCB List: ");
  6576. scb_index = ahc_inb(ahc, FREE_SCBH);
  6577. i = 0;
  6578. while (scb_index != SCB_LIST_NULL && i++ < 256) {
  6579. ahc_outb(ahc, SCBPTR, scb_index);
  6580. printf("%d ", scb_index);
  6581. scb_index = ahc_inb(ahc, SCB_NEXT);
  6582. }
  6583. printf("\n");
  6584. printf("Sequencer SCB Info: ");
  6585. for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
  6586. ahc_outb(ahc, SCBPTR, i);
  6587. cur_col = printf("\n%3d ", i);
  6588. ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
  6589. ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
  6590. ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
  6591. ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
  6592. }
  6593. printf("\n");
  6594. printf("Pending list: ");
  6595. i = 0;
  6596. LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
  6597. if (i++ > 256)
  6598. break;
  6599. cur_col = printf("\n%3d ", scb->hscb->tag);
  6600. ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
  6601. ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
  6602. ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
  6603. if ((ahc->flags & AHC_PAGESCBS) == 0) {
  6604. ahc_outb(ahc, SCBPTR, scb->hscb->tag);
  6605. printf("(");
  6606. ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
  6607. &cur_col, 60);
  6608. ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
  6609. printf(")");
  6610. }
  6611. }
  6612. printf("\n");
  6613. printf("Kernel Free SCB list: ");
  6614. i = 0;
  6615. SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
  6616. if (i++ > 256)
  6617. break;
  6618. printf("%d ", scb->hscb->tag);
  6619. }
  6620. printf("\n");
  6621. maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
  6622. for (target = 0; target <= maxtarget; target++) {
  6623. untagged_q = &ahc->untagged_queues[target];
  6624. if (TAILQ_FIRST(untagged_q) == NULL)
  6625. continue;
  6626. printf("Untagged Q(%d): ", target);
  6627. i = 0;
  6628. TAILQ_FOREACH(scb, untagged_q, links.tqe) {
  6629. if (i++ > 256)
  6630. break;
  6631. printf("%d ", scb->hscb->tag);
  6632. }
  6633. printf("\n");
  6634. }
  6635. ahc_platform_dump_card_state(ahc);
  6636. printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
  6637. ahc_outb(ahc, SCBPTR, saved_scbptr);
  6638. if (paused == 0)
  6639. ahc_unpause(ahc);
  6640. }
  6641. /************************* Target Mode ****************************************/
  6642. #ifdef AHC_TARGET_MODE
  6643. cam_status
  6644. ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
  6645. struct ahc_tmode_tstate **tstate,
  6646. struct ahc_tmode_lstate **lstate,
  6647. int notfound_failure)
  6648. {
  6649. if ((ahc->features & AHC_TARGETMODE) == 0)
  6650. return (CAM_REQ_INVALID);
  6651. /*
  6652. * Handle the 'black hole' device that sucks up
  6653. * requests to unattached luns on enabled targets.
  6654. */
  6655. if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
  6656. && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
  6657. *tstate = NULL;
  6658. *lstate = ahc->black_hole;
  6659. } else {
  6660. u_int max_id;
  6661. max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
  6662. if (ccb->ccb_h.target_id >= max_id)
  6663. return (CAM_TID_INVALID);
  6664. if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
  6665. return (CAM_LUN_INVALID);
  6666. *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
  6667. *lstate = NULL;
  6668. if (*tstate != NULL)
  6669. *lstate =
  6670. (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
  6671. }
  6672. if (notfound_failure != 0 && *lstate == NULL)
  6673. return (CAM_PATH_INVALID);
  6674. return (CAM_REQ_CMP);
  6675. }
  6676. void
  6677. ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
  6678. {
  6679. struct ahc_tmode_tstate *tstate;
  6680. struct ahc_tmode_lstate *lstate;
  6681. struct ccb_en_lun *cel;
  6682. cam_status status;
  6683. u_long s;
  6684. u_int target;
  6685. u_int lun;
  6686. u_int target_mask;
  6687. u_int our_id;
  6688. int error;
  6689. char channel;
  6690. status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
  6691. /*notfound_failure*/FALSE);
  6692. if (status != CAM_REQ_CMP) {
  6693. ccb->ccb_h.status = status;
  6694. return;
  6695. }
  6696. if (cam_sim_bus(sim) == 0)
  6697. our_id = ahc->our_id;
  6698. else
  6699. our_id = ahc->our_id_b;
  6700. if (ccb->ccb_h.target_id != our_id) {
  6701. /*
  6702. * our_id represents our initiator ID, or
  6703. * the ID of the first target to have an
  6704. * enabled lun in target mode. There are
  6705. * two cases that may preclude enabling a
  6706. * target id other than our_id.
  6707. *
  6708. * o our_id is for an active initiator role.
  6709. * Since the hardware does not support
  6710. * reselections to the initiator role at
  6711. * anything other than our_id, and our_id
  6712. * is used by the hardware to indicate the
  6713. * ID to use for both select-out and
  6714. * reselect-out operations, the only target
  6715. * ID we can support in this mode is our_id.
  6716. *
  6717. * o The MULTARGID feature is not available and
  6718. * a previous target mode ID has been enabled.
  6719. */
  6720. if ((ahc->features & AHC_MULTIROLE) != 0) {
  6721. if ((ahc->features & AHC_MULTI_TID) != 0
  6722. && (ahc->flags & AHC_INITIATORROLE) != 0) {
  6723. /*
  6724. * Only allow additional targets if
  6725. * the initiator role is disabled.
  6726. * The hardware cannot handle a re-select-in
  6727. * on the initiator id during a re-select-out
  6728. * on a different target id.
  6729. */
  6730. status = CAM_TID_INVALID;
  6731. } else if ((ahc->flags & AHC_INITIATORROLE) != 0
  6732. || ahc->enabled_luns > 0) {
  6733. /*
  6734. * Only allow our target id to change
  6735. * if the initiator role is not configured
  6736. * and there are no enabled luns which
  6737. * are attached to the currently registered
  6738. * scsi id.
  6739. */
  6740. status = CAM_TID_INVALID;
  6741. }
  6742. } else if ((ahc->features & AHC_MULTI_TID) == 0
  6743. && ahc->enabled_luns > 0) {
  6744. status = CAM_TID_INVALID;
  6745. }
  6746. }
  6747. if (status != CAM_REQ_CMP) {
  6748. ccb->ccb_h.status = status;
  6749. return;
  6750. }
  6751. /*
  6752. * We now have an id that is valid.
  6753. * If we aren't in target mode, switch modes.
  6754. */
  6755. if ((ahc->flags & AHC_TARGETROLE) == 0
  6756. && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
  6757. u_long s;
  6758. ahc_flag saved_flags;
  6759. printf("Configuring Target Mode\n");
  6760. ahc_lock(ahc, &s);
  6761. if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
  6762. ccb->ccb_h.status = CAM_BUSY;
  6763. ahc_unlock(ahc, &s);
  6764. return;
  6765. }
  6766. saved_flags = ahc->flags;
  6767. ahc->flags |= AHC_TARGETROLE;
  6768. if ((ahc->features & AHC_MULTIROLE) == 0)
  6769. ahc->flags &= ~AHC_INITIATORROLE;
  6770. ahc_pause(ahc);
  6771. error = ahc_loadseq(ahc);
  6772. if (error != 0) {
  6773. /*
  6774. * Restore original configuration and notify
  6775. * the caller that we cannot support target mode.
  6776. * Since the adapter started out in this
  6777. * configuration, the firmware load will succeed,
  6778. * so there is no point in checking ahc_loadseq's
  6779. * return value.
  6780. */
  6781. ahc->flags = saved_flags;
  6782. (void)ahc_loadseq(ahc);
  6783. ahc_restart(ahc);
  6784. ahc_unlock(ahc, &s);
  6785. ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
  6786. return;
  6787. }
  6788. ahc_restart(ahc);
  6789. ahc_unlock(ahc, &s);
  6790. }
  6791. cel = &ccb->cel;
  6792. target = ccb->ccb_h.target_id;
  6793. lun = ccb->ccb_h.target_lun;
  6794. channel = SIM_CHANNEL(ahc, sim);
  6795. target_mask = 0x01 << target;
  6796. if (channel == 'B')
  6797. target_mask <<= 8;
  6798. if (cel->enable != 0) {
  6799. u_int scsiseq;
  6800. /* Are we already enabled?? */
  6801. if (lstate != NULL) {
  6802. xpt_print_path(ccb->ccb_h.path);
  6803. printf("Lun already enabled\n");
  6804. ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
  6805. return;
  6806. }
  6807. if (cel->grp6_len != 0
  6808. || cel->grp7_len != 0) {
  6809. /*
  6810. * Don't (yet?) support vendor
  6811. * specific commands.
  6812. */
  6813. ccb->ccb_h.status = CAM_REQ_INVALID;
  6814. printf("Non-zero Group Codes\n");
  6815. return;
  6816. }
  6817. /*
  6818. * Seems to be okay.
  6819. * Setup our data structures.
  6820. */
  6821. if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
  6822. tstate = ahc_alloc_tstate(ahc, target, channel);
  6823. if (tstate == NULL) {
  6824. xpt_print_path(ccb->ccb_h.path);
  6825. printf("Couldn't allocate tstate\n");
  6826. ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
  6827. return;
  6828. }
  6829. }
  6830. lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
  6831. if (lstate == NULL) {
  6832. xpt_print_path(ccb->ccb_h.path);
  6833. printf("Couldn't allocate lstate\n");
  6834. ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
  6835. return;
  6836. }
  6837. memset(lstate, 0, sizeof(*lstate));
  6838. status = xpt_create_path(&lstate->path, /*periph*/NULL,
  6839. xpt_path_path_id(ccb->ccb_h.path),
  6840. xpt_path_target_id(ccb->ccb_h.path),
  6841. xpt_path_lun_id(ccb->ccb_h.path));
  6842. if (status != CAM_REQ_CMP) {
  6843. free(lstate, M_DEVBUF);
  6844. xpt_print_path(ccb->ccb_h.path);
  6845. printf("Couldn't allocate path\n");
  6846. ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
  6847. return;
  6848. }
  6849. SLIST_INIT(&lstate->accept_tios);
  6850. SLIST_INIT(&lstate->immed_notifies);
  6851. ahc_lock(ahc, &s);
  6852. ahc_pause(ahc);
  6853. if (target != CAM_TARGET_WILDCARD) {
  6854. tstate->enabled_luns[lun] = lstate;
  6855. ahc->enabled_luns++;
  6856. if ((ahc->features & AHC_MULTI_TID) != 0) {
  6857. u_int targid_mask;
  6858. targid_mask = ahc_inb(ahc, TARGID)
  6859. | (ahc_inb(ahc, TARGID + 1) << 8);
  6860. targid_mask |= target_mask;
  6861. ahc_outb(ahc, TARGID, targid_mask);
  6862. ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
  6863. ahc_update_scsiid(ahc, targid_mask);
  6864. } else {
  6865. u_int our_id;
  6866. char channel;
  6867. channel = SIM_CHANNEL(ahc, sim);
  6868. our_id = SIM_SCSI_ID(ahc, sim);
  6869. /*
  6870. * This can only happen if selections
  6871. * are not enabled
  6872. */
  6873. if (target != our_id) {
  6874. u_int sblkctl;
  6875. char cur_channel;
  6876. int swap;
  6877. sblkctl = ahc_inb(ahc, SBLKCTL);
  6878. cur_channel = (sblkctl & SELBUSB)
  6879. ? 'B' : 'A';
  6880. if ((ahc->features & AHC_TWIN) == 0)
  6881. cur_channel = 'A';
  6882. swap = cur_channel != channel;
  6883. if (channel == 'A')
  6884. ahc->our_id = target;
  6885. else
  6886. ahc->our_id_b = target;
  6887. if (swap)
  6888. ahc_outb(ahc, SBLKCTL,
  6889. sblkctl ^ SELBUSB);
  6890. ahc_outb(ahc, SCSIID, target);
  6891. if (swap)
  6892. ahc_outb(ahc, SBLKCTL, sblkctl);
  6893. }
  6894. }
  6895. } else
  6896. ahc->black_hole = lstate;
  6897. /* Allow select-in operations */
  6898. if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
  6899. scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
  6900. scsiseq |= ENSELI;
  6901. ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
  6902. scsiseq = ahc_inb(ahc, SCSISEQ);
  6903. scsiseq |= ENSELI;
  6904. ahc_outb(ahc, SCSISEQ, scsiseq);
  6905. }
  6906. ahc_unpause(ahc);
  6907. ahc_unlock(ahc, &s);
  6908. ccb->ccb_h.status = CAM_REQ_CMP;
  6909. xpt_print_path(ccb->ccb_h.path);
  6910. printf("Lun now enabled for target mode\n");
  6911. } else {
  6912. struct scb *scb;
  6913. int i, empty;
  6914. if (lstate == NULL) {
  6915. ccb->ccb_h.status = CAM_LUN_INVALID;
  6916. return;
  6917. }
  6918. ahc_lock(ahc, &s);
  6919. ccb->ccb_h.status = CAM_REQ_CMP;
  6920. LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
  6921. struct ccb_hdr *ccbh;
  6922. ccbh = &scb->io_ctx->ccb_h;
  6923. if (ccbh->func_code == XPT_CONT_TARGET_IO
  6924. && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
  6925. printf("CTIO pending\n");
  6926. ccb->ccb_h.status = CAM_REQ_INVALID;
  6927. ahc_unlock(ahc, &s);
  6928. return;
  6929. }
  6930. }
  6931. if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
  6932. printf("ATIOs pending\n");
  6933. ccb->ccb_h.status = CAM_REQ_INVALID;
  6934. }
  6935. if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
  6936. printf("INOTs pending\n");
  6937. ccb->ccb_h.status = CAM_REQ_INVALID;
  6938. }
  6939. if (ccb->ccb_h.status != CAM_REQ_CMP) {
  6940. ahc_unlock(ahc, &s);
  6941. return;
  6942. }
  6943. xpt_print_path(ccb->ccb_h.path);
  6944. printf("Target mode disabled\n");
  6945. xpt_free_path(lstate->path);
  6946. free(lstate, M_DEVBUF);
  6947. ahc_pause(ahc);
  6948. /* Can we clean up the target too? */
  6949. if (target != CAM_TARGET_WILDCARD) {
  6950. tstate->enabled_luns[lun] = NULL;
  6951. ahc->enabled_luns--;
  6952. for (empty = 1, i = 0; i < 8; i++)
  6953. if (tstate->enabled_luns[i] != NULL) {
  6954. empty = 0;
  6955. break;
  6956. }
  6957. if (empty) {
  6958. ahc_free_tstate(ahc, target, channel,
  6959. /*force*/FALSE);
  6960. if (ahc->features & AHC_MULTI_TID) {
  6961. u_int targid_mask;
  6962. targid_mask = ahc_inb(ahc, TARGID)
  6963. | (ahc_inb(ahc, TARGID + 1)
  6964. << 8);
  6965. targid_mask &= ~target_mask;
  6966. ahc_outb(ahc, TARGID, targid_mask);
  6967. ahc_outb(ahc, TARGID+1,
  6968. (targid_mask >> 8));
  6969. ahc_update_scsiid(ahc, targid_mask);
  6970. }
  6971. }
  6972. } else {
  6973. ahc->black_hole = NULL;
  6974. /*
  6975. * We can't allow selections without
  6976. * our black hole device.
  6977. */
  6978. empty = TRUE;
  6979. }
  6980. if (ahc->enabled_luns == 0) {
  6981. /* Disallow select-in */
  6982. u_int scsiseq;
  6983. scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
  6984. scsiseq &= ~ENSELI;
  6985. ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
  6986. scsiseq = ahc_inb(ahc, SCSISEQ);
  6987. scsiseq &= ~ENSELI;
  6988. ahc_outb(ahc, SCSISEQ, scsiseq);
  6989. if ((ahc->features & AHC_MULTIROLE) == 0) {
  6990. printf("Configuring Initiator Mode\n");
  6991. ahc->flags &= ~AHC_TARGETROLE;
  6992. ahc->flags |= AHC_INITIATORROLE;
  6993. /*
  6994. * Returning to a configuration that
  6995. * fit previously will always succeed.
  6996. */
  6997. (void)ahc_loadseq(ahc);
  6998. ahc_restart(ahc);
  6999. /*
  7000. * Unpaused. The extra unpause
  7001. * that follows is harmless.
  7002. */
  7003. }
  7004. }
  7005. ahc_unpause(ahc);
  7006. ahc_unlock(ahc, &s);
  7007. }
  7008. }
  7009. static void
  7010. ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
  7011. {
  7012. u_int scsiid_mask;
  7013. u_int scsiid;
  7014. if ((ahc->features & AHC_MULTI_TID) == 0)
  7015. panic("ahc_update_scsiid called on non-multitid unit\n");
  7016. /*
  7017. * Since we will rely on the TARGID mask
  7018. * for selection enables, ensure that OID
  7019. * in SCSIID is not set to some other ID
  7020. * that we don't want to allow selections on.
  7021. */
  7022. if ((ahc->features & AHC_ULTRA2) != 0)
  7023. scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
  7024. else
  7025. scsiid = ahc_inb(ahc, SCSIID);
  7026. scsiid_mask = 0x1 << (scsiid & OID);
  7027. if ((targid_mask & scsiid_mask) == 0) {
  7028. u_int our_id;
  7029. /* ffs counts from 1 */
  7030. our_id = ffs(targid_mask);
  7031. if (our_id == 0)
  7032. our_id = ahc->our_id;
  7033. else
  7034. our_id--;
  7035. scsiid &= TID;
  7036. scsiid |= our_id;
  7037. }
  7038. if ((ahc->features & AHC_ULTRA2) != 0)
  7039. ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
  7040. else
  7041. ahc_outb(ahc, SCSIID, scsiid);
  7042. }
  7043. static void
  7044. ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
  7045. {
  7046. struct target_cmd *cmd;
  7047. /*
  7048. * If the card supports auto-access pause,
  7049. * we can access the card directly regardless
  7050. * of whether it is paused or not.
  7051. */
  7052. if ((ahc->features & AHC_AUTOPAUSE) != 0)
  7053. paused = TRUE;
  7054. ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
  7055. while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
  7056. /*
  7057. * Only advance through the queue if we
  7058. * have the resources to process the command.
  7059. */
  7060. if (ahc_handle_target_cmd(ahc, cmd) != 0)
  7061. break;
  7062. cmd->cmd_valid = 0;
  7063. ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
  7064. ahc->shared_data_dmamap,
  7065. ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
  7066. sizeof(struct target_cmd),
  7067. BUS_DMASYNC_PREREAD);
  7068. ahc->tqinfifonext++;
  7069. /*
  7070. * Lazily update our position in the target mode incoming
  7071. * command queue as seen by the sequencer.
  7072. */
  7073. if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
  7074. if ((ahc->features & AHC_HS_MAILBOX) != 0) {
  7075. u_int hs_mailbox;
  7076. hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
  7077. hs_mailbox &= ~HOST_TQINPOS;
  7078. hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
  7079. ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
  7080. } else {
  7081. if (!paused)
  7082. ahc_pause(ahc);
  7083. ahc_outb(ahc, KERNEL_TQINPOS,
  7084. ahc->tqinfifonext & HOST_TQINPOS);
  7085. if (!paused)
  7086. ahc_unpause(ahc);
  7087. }
  7088. }
  7089. }
  7090. }
  7091. static int
  7092. ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
  7093. {
  7094. struct ahc_tmode_tstate *tstate;
  7095. struct ahc_tmode_lstate *lstate;
  7096. struct ccb_accept_tio *atio;
  7097. uint8_t *byte;
  7098. int initiator;
  7099. int target;
  7100. int lun;
  7101. initiator = SCSIID_TARGET(ahc, cmd->scsiid);
  7102. target = SCSIID_OUR_ID(cmd->scsiid);
  7103. lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
  7104. byte = cmd->bytes;
  7105. tstate = ahc->enabled_targets[target];
  7106. lstate = NULL;
  7107. if (tstate != NULL)
  7108. lstate = tstate->enabled_luns[lun];
  7109. /*
  7110. * Commands for disabled luns go to the black hole driver.
  7111. */
  7112. if (lstate == NULL)
  7113. lstate = ahc->black_hole;
  7114. atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
  7115. if (atio == NULL) {
  7116. ahc->flags |= AHC_TQINFIFO_BLOCKED;
  7117. /*
  7118. * Wait for more ATIOs from the peripheral driver for this lun.
  7119. */
  7120. if (bootverbose)
  7121. printf("%s: ATIOs exhausted\n", ahc_name(ahc));
  7122. return (1);
  7123. } else
  7124. ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
  7125. #if 0
  7126. printf("Incoming command from %d for %d:%d%s\n",
  7127. initiator, target, lun,
  7128. lstate == ahc->black_hole ? "(Black Holed)" : "");
  7129. #endif
  7130. SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
  7131. if (lstate == ahc->black_hole) {
  7132. /* Fill in the wildcards */
  7133. atio->ccb_h.target_id = target;
  7134. atio->ccb_h.target_lun = lun;
  7135. }
  7136. /*
  7137. * Package it up and send it off to
  7138. * whomever has this lun enabled.
  7139. */
  7140. atio->sense_len = 0;
  7141. atio->init_id = initiator;
  7142. if (byte[0] != 0xFF) {
  7143. /* Tag was included */
  7144. atio->tag_action = *byte++;
  7145. atio->tag_id = *byte++;
  7146. atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
  7147. } else {
  7148. atio->ccb_h.flags = 0;
  7149. }
  7150. byte++;
  7151. /* Okay. Now determine the cdb size based on the command code */
  7152. switch (*byte >> CMD_GROUP_CODE_SHIFT) {
  7153. case 0:
  7154. atio->cdb_len = 6;
  7155. break;
  7156. case 1:
  7157. case 2:
  7158. atio->cdb_len = 10;
  7159. break;
  7160. case 4:
  7161. atio->cdb_len = 16;
  7162. break;
  7163. case 5:
  7164. atio->cdb_len = 12;
  7165. break;
  7166. case 3:
  7167. default:
  7168. /* Only copy the opcode. */
  7169. atio->cdb_len = 1;
  7170. printf("Reserved or VU command code type encountered\n");
  7171. break;
  7172. }
  7173. memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
  7174. atio->ccb_h.status |= CAM_CDB_RECVD;
  7175. if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
  7176. /*
  7177. * We weren't allowed to disconnect.
  7178. * We're hanging on the bus until a
  7179. * continue target I/O comes in response
  7180. * to this accept tio.
  7181. */
  7182. #if 0
  7183. printf("Received Immediate Command %d:%d:%d - %p\n",
  7184. initiator, target, lun, ahc->pending_device);
  7185. #endif
  7186. ahc->pending_device = lstate;
  7187. ahc_freeze_ccb((union ccb *)atio);
  7188. atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
  7189. }
  7190. xpt_done((union ccb*)atio);
  7191. return (0);
  7192. }
  7193. #endif