em28xx-core.c 30 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include <media/v4l2-common.h>
  25. #include "em28xx.h"
  26. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  27. static unsigned int core_debug;
  28. module_param(core_debug, int, 0644);
  29. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  30. #define em28xx_coredbg(fmt, arg...) do {\
  31. if (core_debug) \
  32. printk(KERN_INFO "%s %s :"fmt, \
  33. dev->name, __func__ , ##arg); } while (0)
  34. static unsigned int reg_debug;
  35. module_param(reg_debug, int, 0644);
  36. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  37. #define em28xx_regdbg(fmt, arg...) do {\
  38. if (reg_debug) \
  39. printk(KERN_INFO "%s %s :"fmt, \
  40. dev->name, __func__ , ##arg); } while (0)
  41. static int alt = EM28XX_PINOUT;
  42. module_param(alt, int, 0644);
  43. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  44. static unsigned int disable_vbi;
  45. module_param(disable_vbi, int, 0644);
  46. MODULE_PARM_DESC(disable_vbi, "disable vbi support");
  47. /* FIXME */
  48. #define em28xx_isocdbg(fmt, arg...) do {\
  49. if (core_debug) \
  50. printk(KERN_INFO "%s %s :"fmt, \
  51. dev->name, __func__ , ##arg); } while (0)
  52. /*
  53. * em28xx_read_reg_req()
  54. * reads data from the usb device specifying bRequest
  55. */
  56. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  57. char *buf, int len)
  58. {
  59. int ret;
  60. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  61. if (dev->state & DEV_DISCONNECTED)
  62. return -ENODEV;
  63. if (len > URB_MAX_CTRL_SIZE)
  64. return -EINVAL;
  65. if (reg_debug) {
  66. printk(KERN_DEBUG "(pipe 0x%08x): "
  67. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  68. pipe,
  69. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  70. req, 0, 0,
  71. reg & 0xff, reg >> 8,
  72. len & 0xff, len >> 8);
  73. }
  74. mutex_lock(&dev->ctrl_urb_lock);
  75. ret = usb_control_msg(dev->udev, pipe, req,
  76. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  77. 0x0000, reg, dev->urb_buf, len, HZ);
  78. if (ret < 0) {
  79. if (reg_debug)
  80. printk(" failed!\n");
  81. mutex_unlock(&dev->ctrl_urb_lock);
  82. return ret;
  83. }
  84. if (len)
  85. memcpy(buf, dev->urb_buf, len);
  86. mutex_unlock(&dev->ctrl_urb_lock);
  87. if (reg_debug) {
  88. int byte;
  89. printk("<<<");
  90. for (byte = 0; byte < len; byte++)
  91. printk(" %02x", (unsigned char)buf[byte]);
  92. printk("\n");
  93. }
  94. return ret;
  95. }
  96. /*
  97. * em28xx_read_reg_req()
  98. * reads data from the usb device specifying bRequest
  99. */
  100. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  101. {
  102. int ret;
  103. u8 val;
  104. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  105. if (ret < 0)
  106. return ret;
  107. return val;
  108. }
  109. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  110. {
  111. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  112. }
  113. /*
  114. * em28xx_write_regs_req()
  115. * sends data to the usb device, specifying bRequest
  116. */
  117. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  118. int len)
  119. {
  120. int ret;
  121. int pipe = usb_sndctrlpipe(dev->udev, 0);
  122. if (dev->state & DEV_DISCONNECTED)
  123. return -ENODEV;
  124. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  125. return -EINVAL;
  126. if (reg_debug) {
  127. int byte;
  128. printk(KERN_DEBUG "(pipe 0x%08x): "
  129. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  130. pipe,
  131. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  132. req, 0, 0,
  133. reg & 0xff, reg >> 8,
  134. len & 0xff, len >> 8);
  135. for (byte = 0; byte < len; byte++)
  136. printk(" %02x", (unsigned char)buf[byte]);
  137. printk("\n");
  138. }
  139. mutex_lock(&dev->ctrl_urb_lock);
  140. memcpy(dev->urb_buf, buf, len);
  141. ret = usb_control_msg(dev->udev, pipe, req,
  142. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  143. 0x0000, reg, dev->urb_buf, len, HZ);
  144. mutex_unlock(&dev->ctrl_urb_lock);
  145. if (dev->wait_after_write)
  146. msleep(dev->wait_after_write);
  147. return ret;
  148. }
  149. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  150. {
  151. int rc;
  152. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  153. /* Stores GPO/GPIO values at the cache, if changed
  154. Only write values should be stored, since input on a GPIO
  155. register will return the input bits.
  156. Not sure what happens on reading GPO register.
  157. */
  158. if (rc >= 0) {
  159. if (reg == dev->reg_gpo_num)
  160. dev->reg_gpo = buf[0];
  161. else if (reg == dev->reg_gpio_num)
  162. dev->reg_gpio = buf[0];
  163. }
  164. return rc;
  165. }
  166. /* Write a single register */
  167. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  168. {
  169. return em28xx_write_regs(dev, reg, &val, 1);
  170. }
  171. /*
  172. * em28xx_write_reg_bits()
  173. * sets only some bits (specified by bitmask) of a register, by first reading
  174. * the actual value
  175. */
  176. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  177. u8 bitmask)
  178. {
  179. int oldval;
  180. u8 newval;
  181. /* Uses cache for gpo/gpio registers */
  182. if (reg == dev->reg_gpo_num)
  183. oldval = dev->reg_gpo;
  184. else if (reg == dev->reg_gpio_num)
  185. oldval = dev->reg_gpio;
  186. else
  187. oldval = em28xx_read_reg(dev, reg);
  188. if (oldval < 0)
  189. return oldval;
  190. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  191. return em28xx_write_regs(dev, reg, &newval, 1);
  192. }
  193. /*
  194. * em28xx_is_ac97_ready()
  195. * Checks if ac97 is ready
  196. */
  197. static int em28xx_is_ac97_ready(struct em28xx *dev)
  198. {
  199. int ret, i;
  200. /* Wait up to 50 ms for AC97 command to complete */
  201. for (i = 0; i < 10; i++, msleep(5)) {
  202. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  203. if (ret < 0)
  204. return ret;
  205. if (!(ret & 0x01))
  206. return 0;
  207. }
  208. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  209. return -EBUSY;
  210. }
  211. /*
  212. * em28xx_read_ac97()
  213. * write a 16 bit value to the specified AC97 address (LSB first!)
  214. */
  215. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  216. {
  217. int ret;
  218. u8 addr = (reg & 0x7f) | 0x80;
  219. u16 val;
  220. ret = em28xx_is_ac97_ready(dev);
  221. if (ret < 0)
  222. return ret;
  223. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  224. if (ret < 0)
  225. return ret;
  226. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  227. (u8 *)&val, sizeof(val));
  228. if (ret < 0)
  229. return ret;
  230. return le16_to_cpu(val);
  231. }
  232. /*
  233. * em28xx_write_ac97()
  234. * write a 16 bit value to the specified AC97 address (LSB first!)
  235. */
  236. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  237. {
  238. int ret;
  239. u8 addr = reg & 0x7f;
  240. __le16 value;
  241. value = cpu_to_le16(val);
  242. ret = em28xx_is_ac97_ready(dev);
  243. if (ret < 0)
  244. return ret;
  245. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  246. if (ret < 0)
  247. return ret;
  248. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  249. if (ret < 0)
  250. return ret;
  251. return 0;
  252. }
  253. struct em28xx_vol_table {
  254. enum em28xx_amux mux;
  255. u8 reg;
  256. };
  257. static struct em28xx_vol_table inputs[] = {
  258. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  259. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  260. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  261. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  262. { EM28XX_AMUX_CD, AC97_CD_VOL },
  263. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  264. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  265. };
  266. static int set_ac97_input(struct em28xx *dev)
  267. {
  268. int ret, i;
  269. enum em28xx_amux amux = dev->ctl_ainput;
  270. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  271. em28xx should point to LINE IN, while AC97 should use VIDEO
  272. */
  273. if (amux == EM28XX_AMUX_VIDEO2)
  274. amux = EM28XX_AMUX_VIDEO;
  275. /* Mute all entres but the one that were selected */
  276. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  277. if (amux == inputs[i].mux)
  278. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  279. else
  280. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  281. if (ret < 0)
  282. em28xx_warn("couldn't setup AC97 register %d\n",
  283. inputs[i].reg);
  284. }
  285. return 0;
  286. }
  287. static int em28xx_set_audio_source(struct em28xx *dev)
  288. {
  289. int ret;
  290. u8 input;
  291. if (dev->board.is_em2800) {
  292. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  293. input = EM2800_AUDIO_SRC_TUNER;
  294. else
  295. input = EM2800_AUDIO_SRC_LINE;
  296. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  297. if (ret < 0)
  298. return ret;
  299. }
  300. if (dev->board.has_msp34xx)
  301. input = EM28XX_AUDIO_SRC_TUNER;
  302. else {
  303. switch (dev->ctl_ainput) {
  304. case EM28XX_AMUX_VIDEO:
  305. input = EM28XX_AUDIO_SRC_TUNER;
  306. break;
  307. default:
  308. input = EM28XX_AUDIO_SRC_LINE;
  309. break;
  310. }
  311. }
  312. if (dev->board.mute_gpio && dev->mute)
  313. em28xx_gpio_set(dev, dev->board.mute_gpio);
  314. else
  315. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  316. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  317. if (ret < 0)
  318. return ret;
  319. msleep(5);
  320. switch (dev->audio_mode.ac97) {
  321. case EM28XX_NO_AC97:
  322. break;
  323. default:
  324. ret = set_ac97_input(dev);
  325. }
  326. return ret;
  327. }
  328. static const struct em28xx_vol_table outputs[] = {
  329. { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
  330. { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
  331. { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
  332. { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
  333. { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
  334. };
  335. int em28xx_audio_analog_set(struct em28xx *dev)
  336. {
  337. int ret, i;
  338. u8 xclk;
  339. if (!dev->audio_mode.has_audio)
  340. return 0;
  341. /* It is assumed that all devices use master volume for output.
  342. It would be possible to use also line output.
  343. */
  344. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  345. /* Mute all outputs */
  346. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  347. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  348. if (ret < 0)
  349. em28xx_warn("couldn't setup AC97 register %d\n",
  350. outputs[i].reg);
  351. }
  352. }
  353. xclk = dev->board.xclk & 0x7f;
  354. if (!dev->mute)
  355. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  356. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  357. if (ret < 0)
  358. return ret;
  359. msleep(10);
  360. /* Selects the proper audio input */
  361. ret = em28xx_set_audio_source(dev);
  362. /* Sets volume */
  363. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  364. int vol;
  365. em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
  366. em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
  367. em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
  368. /* LSB: left channel - both channels with the same level */
  369. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  370. /* Mute device, if needed */
  371. if (dev->mute)
  372. vol |= 0x8000;
  373. /* Sets volume */
  374. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  375. if (dev->ctl_aoutput & outputs[i].mux)
  376. ret = em28xx_write_ac97(dev, outputs[i].reg,
  377. vol);
  378. if (ret < 0)
  379. em28xx_warn("couldn't setup AC97 register %d\n",
  380. outputs[i].reg);
  381. }
  382. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  383. int sel = ac97_return_record_select(dev->ctl_aoutput);
  384. /* Use the same input for both left and right
  385. channels */
  386. sel |= (sel << 8);
  387. em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
  388. }
  389. }
  390. return ret;
  391. }
  392. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  393. int em28xx_audio_setup(struct em28xx *dev)
  394. {
  395. int vid1, vid2, feat, cfg;
  396. u32 vid;
  397. if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
  398. /* Digital only device - don't load any alsa module */
  399. dev->audio_mode.has_audio = 0;
  400. dev->has_audio_class = 0;
  401. dev->has_alsa_audio = 0;
  402. return 0;
  403. }
  404. /* If device doesn't support Usb Audio Class, use vendor class */
  405. if (!dev->has_audio_class)
  406. dev->has_alsa_audio = 1;
  407. dev->audio_mode.has_audio = 1;
  408. /* See how this device is configured */
  409. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  410. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  411. if (cfg < 0) {
  412. /* Register read error? */
  413. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  414. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  415. /* The device doesn't have vendor audio at all */
  416. dev->has_alsa_audio = 0;
  417. dev->audio_mode.has_audio = 0;
  418. return 0;
  419. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  420. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  421. em28xx_info("I2S Audio (3 sample rates)\n");
  422. dev->audio_mode.i2s_3rates = 1;
  423. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  424. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  425. em28xx_info("I2S Audio (5 sample rates)\n");
  426. dev->audio_mode.i2s_5rates = 1;
  427. }
  428. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  429. /* Skip the code that does AC97 vendor detection */
  430. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  431. goto init_audio;
  432. }
  433. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  434. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  435. if (vid1 < 0) {
  436. /* Device likely doesn't support AC97 */
  437. em28xx_warn("AC97 chip type couldn't be determined\n");
  438. goto init_audio;
  439. }
  440. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  441. if (vid2 < 0)
  442. goto init_audio;
  443. vid = vid1 << 16 | vid2;
  444. dev->audio_mode.ac97_vendor_id = vid;
  445. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  446. feat = em28xx_read_ac97(dev, AC97_RESET);
  447. if (feat < 0)
  448. goto init_audio;
  449. dev->audio_mode.ac97_feat = feat;
  450. em28xx_warn("AC97 features = 0x%04x\n", feat);
  451. /* Try to identify what audio processor we have */
  452. if ((vid == 0xffffffff) && (feat == 0x6a90))
  453. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  454. else if ((vid >> 8) == 0x838476)
  455. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  456. init_audio:
  457. /* Reports detected AC97 processor */
  458. switch (dev->audio_mode.ac97) {
  459. case EM28XX_NO_AC97:
  460. em28xx_info("No AC97 audio processor\n");
  461. break;
  462. case EM28XX_AC97_EM202:
  463. em28xx_info("Empia 202 AC97 audio processor detected\n");
  464. break;
  465. case EM28XX_AC97_SIGMATEL:
  466. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  467. dev->audio_mode.ac97_vendor_id & 0xff);
  468. break;
  469. case EM28XX_AC97_OTHER:
  470. em28xx_warn("Unknown AC97 audio processor detected!\n");
  471. break;
  472. default:
  473. break;
  474. }
  475. return em28xx_audio_analog_set(dev);
  476. }
  477. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  478. int em28xx_colorlevels_set_default(struct em28xx *dev)
  479. {
  480. em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
  481. em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
  482. em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
  483. em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
  484. em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
  485. em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
  486. em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
  487. em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
  488. em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
  489. em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
  490. em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
  491. em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
  492. return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
  493. }
  494. int em28xx_capture_start(struct em28xx *dev, int start)
  495. {
  496. int rc;
  497. if (dev->chip_id == CHIP_ID_EM2874) {
  498. /* The Transport Stream Enable Register moved in em2874 */
  499. if (!start) {
  500. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  501. 0x00,
  502. EM2874_TS1_CAPTURE_ENABLE);
  503. return rc;
  504. }
  505. /* Enable Transport Stream */
  506. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  507. EM2874_TS1_CAPTURE_ENABLE,
  508. EM2874_TS1_CAPTURE_ENABLE);
  509. return rc;
  510. }
  511. /* FIXME: which is the best order? */
  512. /* video registers are sampled by VREF */
  513. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  514. start ? 0x10 : 0x00, 0x10);
  515. if (rc < 0)
  516. return rc;
  517. if (!start) {
  518. /* disable video capture */
  519. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  520. return rc;
  521. }
  522. if (dev->board.is_webcam)
  523. rc = em28xx_write_reg(dev, 0x13, 0x0c);
  524. /* enable video capture */
  525. rc = em28xx_write_reg(dev, 0x48, 0x00);
  526. if (dev->mode == EM28XX_ANALOG_MODE)
  527. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  528. else
  529. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  530. msleep(6);
  531. return rc;
  532. }
  533. int em28xx_vbi_supported(struct em28xx *dev)
  534. {
  535. /* Modprobe option to manually disable */
  536. if (disable_vbi == 1)
  537. return 0;
  538. if (dev->chip_id == CHIP_ID_EM2860 ||
  539. dev->chip_id == CHIP_ID_EM2883)
  540. return 1;
  541. /* Version of em28xx that does not support VBI */
  542. return 0;
  543. }
  544. int em28xx_set_outfmt(struct em28xx *dev)
  545. {
  546. int ret;
  547. u8 vinctrl;
  548. ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
  549. dev->format->reg | 0x20, 0xff);
  550. if (ret < 0)
  551. return ret;
  552. ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
  553. if (ret < 0)
  554. return ret;
  555. vinctrl = dev->vinctl;
  556. if (em28xx_vbi_supported(dev) == 1) {
  557. vinctrl |= EM28XX_VINCTRL_VBI_RAW;
  558. em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
  559. em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
  560. em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, 0xb4);
  561. em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, 0x0c);
  562. }
  563. return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
  564. }
  565. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  566. u8 ymin, u8 ymax)
  567. {
  568. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  569. xmin, ymin, xmax, ymax);
  570. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  571. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  572. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  573. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  574. }
  575. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  576. u16 width, u16 height)
  577. {
  578. u8 cwidth = width;
  579. u8 cheight = height;
  580. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  581. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  582. (width | (overflow & 2) << 7),
  583. (height | (overflow & 1) << 8));
  584. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  585. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  586. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  587. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  588. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  589. }
  590. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  591. {
  592. u8 mode;
  593. /* the em2800 scaler only supports scaling down to 50% */
  594. if (dev->board.is_em2800) {
  595. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  596. } else {
  597. u8 buf[2];
  598. buf[0] = h;
  599. buf[1] = h >> 8;
  600. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  601. buf[0] = v;
  602. buf[1] = v >> 8;
  603. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  604. /* it seems that both H and V scalers must be active
  605. to work correctly */
  606. mode = (h || v) ? 0x30 : 0x00;
  607. }
  608. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  609. }
  610. /* FIXME: this only function read values from dev */
  611. int em28xx_resolution_set(struct em28xx *dev)
  612. {
  613. int width, height;
  614. width = norm_maxw(dev);
  615. height = norm_maxh(dev);
  616. if (!dev->progressive)
  617. height >>= norm_maxh(dev);
  618. em28xx_set_outfmt(dev);
  619. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  620. /* If we don't set the start position to 4 in VBI mode, we end up
  621. with line 21 being YUYV encoded instead of being in 8-bit
  622. greyscale */
  623. if (em28xx_vbi_supported(dev) == 1)
  624. em28xx_capture_area_set(dev, 0, 4, width >> 2, height >> 2);
  625. else
  626. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  627. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  628. }
  629. int em28xx_set_alternate(struct em28xx *dev)
  630. {
  631. int errCode, prev_alt = dev->alt;
  632. int i;
  633. unsigned int min_pkt_size = dev->width * 2 + 4;
  634. /* When image size is bigger than a certain value,
  635. the frame size should be increased, otherwise, only
  636. green screen will be received.
  637. */
  638. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  639. min_pkt_size *= 2;
  640. for (i = 0; i < dev->num_alt; i++) {
  641. /* stop when the selected alt setting offers enough bandwidth */
  642. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  643. dev->alt = i;
  644. break;
  645. /* otherwise make sure that we end up with the maximum bandwidth
  646. because the min_pkt_size equation might be wrong...
  647. */
  648. } else if (dev->alt_max_pkt_size[i] >
  649. dev->alt_max_pkt_size[dev->alt])
  650. dev->alt = i;
  651. }
  652. if (dev->alt != prev_alt) {
  653. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  654. min_pkt_size, dev->alt);
  655. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  656. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  657. dev->alt, dev->max_pkt_size);
  658. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  659. if (errCode < 0) {
  660. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  661. dev->alt, errCode);
  662. return errCode;
  663. }
  664. }
  665. return 0;
  666. }
  667. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  668. {
  669. int rc = 0;
  670. if (!gpio)
  671. return rc;
  672. if (dev->mode != EM28XX_SUSPEND) {
  673. em28xx_write_reg(dev, 0x48, 0x00);
  674. if (dev->mode == EM28XX_ANALOG_MODE)
  675. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  676. else
  677. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  678. msleep(6);
  679. }
  680. /* Send GPIO reset sequences specified at board entry */
  681. while (gpio->sleep >= 0) {
  682. if (gpio->reg >= 0) {
  683. rc = em28xx_write_reg_bits(dev,
  684. gpio->reg,
  685. gpio->val,
  686. gpio->mask);
  687. if (rc < 0)
  688. return rc;
  689. }
  690. if (gpio->sleep > 0)
  691. msleep(gpio->sleep);
  692. gpio++;
  693. }
  694. return rc;
  695. }
  696. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  697. {
  698. if (dev->mode == set_mode)
  699. return 0;
  700. if (set_mode == EM28XX_SUSPEND) {
  701. dev->mode = set_mode;
  702. /* FIXME: add suspend support for ac97 */
  703. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  704. }
  705. dev->mode = set_mode;
  706. if (dev->mode == EM28XX_DIGITAL_MODE)
  707. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  708. else
  709. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  710. }
  711. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  712. /* ------------------------------------------------------------------
  713. URB control
  714. ------------------------------------------------------------------*/
  715. /*
  716. * IRQ callback, called by URB callback
  717. */
  718. static void em28xx_irq_callback(struct urb *urb)
  719. {
  720. struct em28xx *dev = urb->context;
  721. int rc, i;
  722. switch (urb->status) {
  723. case 0: /* success */
  724. case -ETIMEDOUT: /* NAK */
  725. break;
  726. case -ECONNRESET: /* kill */
  727. case -ENOENT:
  728. case -ESHUTDOWN:
  729. return;
  730. default: /* error */
  731. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  732. break;
  733. }
  734. /* Copy data from URB */
  735. spin_lock(&dev->slock);
  736. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  737. spin_unlock(&dev->slock);
  738. /* Reset urb buffers */
  739. for (i = 0; i < urb->number_of_packets; i++) {
  740. urb->iso_frame_desc[i].status = 0;
  741. urb->iso_frame_desc[i].actual_length = 0;
  742. }
  743. urb->status = 0;
  744. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  745. if (urb->status) {
  746. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  747. urb->status);
  748. }
  749. }
  750. /*
  751. * Stop and Deallocate URBs
  752. */
  753. void em28xx_uninit_isoc(struct em28xx *dev)
  754. {
  755. struct urb *urb;
  756. int i;
  757. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  758. dev->isoc_ctl.nfields = -1;
  759. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  760. urb = dev->isoc_ctl.urb[i];
  761. if (urb) {
  762. if (!irqs_disabled())
  763. usb_kill_urb(urb);
  764. else
  765. usb_unlink_urb(urb);
  766. if (dev->isoc_ctl.transfer_buffer[i]) {
  767. usb_buffer_free(dev->udev,
  768. urb->transfer_buffer_length,
  769. dev->isoc_ctl.transfer_buffer[i],
  770. urb->transfer_dma);
  771. }
  772. usb_free_urb(urb);
  773. dev->isoc_ctl.urb[i] = NULL;
  774. }
  775. dev->isoc_ctl.transfer_buffer[i] = NULL;
  776. }
  777. kfree(dev->isoc_ctl.urb);
  778. kfree(dev->isoc_ctl.transfer_buffer);
  779. dev->isoc_ctl.urb = NULL;
  780. dev->isoc_ctl.transfer_buffer = NULL;
  781. dev->isoc_ctl.num_bufs = 0;
  782. em28xx_capture_start(dev, 0);
  783. }
  784. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  785. /*
  786. * Allocate URBs and start IRQ
  787. */
  788. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  789. int num_bufs, int max_pkt_size,
  790. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  791. {
  792. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  793. struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
  794. int i;
  795. int sb_size, pipe;
  796. struct urb *urb;
  797. int j, k;
  798. int rc;
  799. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  800. /* De-allocates all pending stuff */
  801. em28xx_uninit_isoc(dev);
  802. dev->isoc_ctl.isoc_copy = isoc_copy;
  803. dev->isoc_ctl.num_bufs = num_bufs;
  804. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  805. if (!dev->isoc_ctl.urb) {
  806. em28xx_errdev("cannot alloc memory for usb buffers\n");
  807. return -ENOMEM;
  808. }
  809. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  810. GFP_KERNEL);
  811. if (!dev->isoc_ctl.transfer_buffer) {
  812. em28xx_errdev("cannot allocate memory for usb transfer\n");
  813. kfree(dev->isoc_ctl.urb);
  814. return -ENOMEM;
  815. }
  816. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  817. dev->isoc_ctl.vid_buf = NULL;
  818. dev->isoc_ctl.vbi_buf = NULL;
  819. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  820. /* allocate urbs and transfer buffers */
  821. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  822. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  823. if (!urb) {
  824. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  825. em28xx_uninit_isoc(dev);
  826. return -ENOMEM;
  827. }
  828. dev->isoc_ctl.urb[i] = urb;
  829. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  830. sb_size, GFP_KERNEL, &urb->transfer_dma);
  831. if (!dev->isoc_ctl.transfer_buffer[i]) {
  832. em28xx_err("unable to allocate %i bytes for transfer"
  833. " buffer %i%s\n",
  834. sb_size, i,
  835. in_interrupt() ? " while in int" : "");
  836. em28xx_uninit_isoc(dev);
  837. return -ENOMEM;
  838. }
  839. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  840. /* FIXME: this is a hack - should be
  841. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  842. should also be using 'desc.bInterval'
  843. */
  844. pipe = usb_rcvisocpipe(dev->udev,
  845. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  846. usb_fill_int_urb(urb, dev->udev, pipe,
  847. dev->isoc_ctl.transfer_buffer[i], sb_size,
  848. em28xx_irq_callback, dev, 1);
  849. urb->number_of_packets = max_packets;
  850. urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
  851. k = 0;
  852. for (j = 0; j < max_packets; j++) {
  853. urb->iso_frame_desc[j].offset = k;
  854. urb->iso_frame_desc[j].length =
  855. dev->isoc_ctl.max_pkt_size;
  856. k += dev->isoc_ctl.max_pkt_size;
  857. }
  858. }
  859. init_waitqueue_head(&dma_q->wq);
  860. init_waitqueue_head(&vbi_dma_q->wq);
  861. em28xx_capture_start(dev, 1);
  862. /* submit urbs and enables IRQ */
  863. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  864. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  865. if (rc) {
  866. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  867. rc);
  868. em28xx_uninit_isoc(dev);
  869. return rc;
  870. }
  871. }
  872. return 0;
  873. }
  874. EXPORT_SYMBOL_GPL(em28xx_init_isoc);
  875. /* Determine the packet size for the DVB stream for the given device
  876. (underlying value programmed into the eeprom) */
  877. int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
  878. {
  879. unsigned int chip_cfg2;
  880. unsigned int packet_size = 564;
  881. if (dev->chip_id == CHIP_ID_EM2874) {
  882. /* FIXME - for now assume 564 like it was before, but the
  883. em2874 code should be added to return the proper value... */
  884. packet_size = 564;
  885. } else {
  886. /* TS max packet size stored in bits 1-0 of R01 */
  887. chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
  888. switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
  889. case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
  890. packet_size = 188;
  891. break;
  892. case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
  893. packet_size = 376;
  894. break;
  895. case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
  896. packet_size = 564;
  897. break;
  898. case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
  899. packet_size = 752;
  900. break;
  901. }
  902. }
  903. em28xx_coredbg("dvb max packet size=%d\n", packet_size);
  904. return packet_size;
  905. }
  906. EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
  907. /*
  908. * em28xx_wake_i2c()
  909. * configure i2c attached devices
  910. */
  911. void em28xx_wake_i2c(struct em28xx *dev)
  912. {
  913. v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
  914. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
  915. INPUT(dev->ctl_input)->vmux, 0, 0);
  916. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
  917. }
  918. /*
  919. * Device control list
  920. */
  921. static LIST_HEAD(em28xx_devlist);
  922. static DEFINE_MUTEX(em28xx_devlist_mutex);
  923. struct em28xx *em28xx_get_device(int minor,
  924. enum v4l2_buf_type *fh_type,
  925. int *has_radio)
  926. {
  927. struct em28xx *h, *dev = NULL;
  928. *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  929. *has_radio = 0;
  930. mutex_lock(&em28xx_devlist_mutex);
  931. list_for_each_entry(h, &em28xx_devlist, devlist) {
  932. if (h->vdev->minor == minor)
  933. dev = h;
  934. if (h->vbi_dev && h->vbi_dev->minor == minor) {
  935. dev = h;
  936. *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
  937. }
  938. if (h->radio_dev &&
  939. h->radio_dev->minor == minor) {
  940. dev = h;
  941. *has_radio = 1;
  942. }
  943. }
  944. mutex_unlock(&em28xx_devlist_mutex);
  945. return dev;
  946. }
  947. /*
  948. * em28xx_realease_resources()
  949. * unregisters the v4l2,i2c and usb devices
  950. * called when the device gets disconected or at module unload
  951. */
  952. void em28xx_remove_from_devlist(struct em28xx *dev)
  953. {
  954. mutex_lock(&em28xx_devlist_mutex);
  955. list_del(&dev->devlist);
  956. mutex_unlock(&em28xx_devlist_mutex);
  957. };
  958. void em28xx_add_into_devlist(struct em28xx *dev)
  959. {
  960. mutex_lock(&em28xx_devlist_mutex);
  961. list_add_tail(&dev->devlist, &em28xx_devlist);
  962. mutex_unlock(&em28xx_devlist_mutex);
  963. };
  964. /*
  965. * Extension interface
  966. */
  967. static LIST_HEAD(em28xx_extension_devlist);
  968. static DEFINE_MUTEX(em28xx_extension_devlist_lock);
  969. int em28xx_register_extension(struct em28xx_ops *ops)
  970. {
  971. struct em28xx *dev = NULL;
  972. mutex_lock(&em28xx_devlist_mutex);
  973. mutex_lock(&em28xx_extension_devlist_lock);
  974. list_add_tail(&ops->next, &em28xx_extension_devlist);
  975. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  976. if (dev)
  977. ops->init(dev);
  978. }
  979. printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
  980. mutex_unlock(&em28xx_extension_devlist_lock);
  981. mutex_unlock(&em28xx_devlist_mutex);
  982. return 0;
  983. }
  984. EXPORT_SYMBOL(em28xx_register_extension);
  985. void em28xx_unregister_extension(struct em28xx_ops *ops)
  986. {
  987. struct em28xx *dev = NULL;
  988. mutex_lock(&em28xx_devlist_mutex);
  989. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  990. if (dev)
  991. ops->fini(dev);
  992. }
  993. mutex_lock(&em28xx_extension_devlist_lock);
  994. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  995. list_del(&ops->next);
  996. mutex_unlock(&em28xx_extension_devlist_lock);
  997. mutex_unlock(&em28xx_devlist_mutex);
  998. }
  999. EXPORT_SYMBOL(em28xx_unregister_extension);
  1000. void em28xx_init_extension(struct em28xx *dev)
  1001. {
  1002. struct em28xx_ops *ops = NULL;
  1003. mutex_lock(&em28xx_extension_devlist_lock);
  1004. if (!list_empty(&em28xx_extension_devlist)) {
  1005. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1006. if (ops->init)
  1007. ops->init(dev);
  1008. }
  1009. }
  1010. mutex_unlock(&em28xx_extension_devlist_lock);
  1011. }
  1012. void em28xx_close_extension(struct em28xx *dev)
  1013. {
  1014. struct em28xx_ops *ops = NULL;
  1015. mutex_lock(&em28xx_extension_devlist_lock);
  1016. if (!list_empty(&em28xx_extension_devlist)) {
  1017. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1018. if (ops->fini)
  1019. ops->fini(dev);
  1020. }
  1021. }
  1022. mutex_unlock(&em28xx_extension_devlist_lock);
  1023. }