intel_sdvo.c 83 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/delay.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "drm_crtc.h"
  33. #include "intel_drv.h"
  34. #include "drm_edid.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. #include "intel_sdvo_regs.h"
  38. #undef SDVO_DEBUG
  39. static char *tv_format_names[] = {
  40. "NTSC_M" , "NTSC_J" , "NTSC_443",
  41. "PAL_B" , "PAL_D" , "PAL_G" ,
  42. "PAL_H" , "PAL_I" , "PAL_M" ,
  43. "PAL_N" , "PAL_NC" , "PAL_60" ,
  44. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  45. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  46. "SECAM_60"
  47. };
  48. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  49. struct intel_sdvo_priv {
  50. u8 slave_addr;
  51. /* Register for the SDVO device: SDVOB or SDVOC */
  52. int output_device;
  53. /* Active outputs controlled by this SDVO output */
  54. uint16_t controlled_output;
  55. /*
  56. * Capabilities of the SDVO device returned by
  57. * i830_sdvo_get_capabilities()
  58. */
  59. struct intel_sdvo_caps caps;
  60. /* Pixel clock limitations reported by the SDVO device, in kHz */
  61. int pixel_clock_min, pixel_clock_max;
  62. /*
  63. * For multiple function SDVO device,
  64. * this is for current attached outputs.
  65. */
  66. uint16_t attached_output;
  67. /**
  68. * This is set if we're going to treat the device as TV-out.
  69. *
  70. * While we have these nice friendly flags for output types that ought
  71. * to decide this for us, the S-Video output on our HDMI+S-Video card
  72. * shows up as RGB1 (VGA).
  73. */
  74. bool is_tv;
  75. /* This is for current tv format name */
  76. char *tv_format_name;
  77. /* This contains all current supported TV format */
  78. char *tv_format_supported[TV_FORMAT_NUM];
  79. int format_supported_num;
  80. struct drm_property *tv_format_property;
  81. struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
  82. /**
  83. * This is set if we treat the device as HDMI, instead of DVI.
  84. */
  85. bool is_hdmi;
  86. /**
  87. * This is set if we detect output of sdvo device as LVDS.
  88. */
  89. bool is_lvds;
  90. /**
  91. * This is sdvo flags for input timing.
  92. */
  93. uint8_t sdvo_flags;
  94. /**
  95. * This is sdvo fixed pannel mode pointer
  96. */
  97. struct drm_display_mode *sdvo_lvds_fixed_mode;
  98. /**
  99. * Returned SDTV resolutions allowed for the current format, if the
  100. * device reported it.
  101. */
  102. struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  103. /*
  104. * supported encoding mode, used to determine whether HDMI is
  105. * supported
  106. */
  107. struct intel_sdvo_encode encode;
  108. /* DDC bus used by this SDVO output */
  109. uint8_t ddc_bus;
  110. /* Mac mini hack -- use the same DDC as the analog connector */
  111. struct i2c_adapter *analog_ddc_bus;
  112. int save_sdvo_mult;
  113. u16 save_active_outputs;
  114. struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
  115. struct intel_sdvo_dtd save_output_dtd[16];
  116. u32 save_SDVOX;
  117. /* add the property for the SDVO-TV */
  118. struct drm_property *left_property;
  119. struct drm_property *right_property;
  120. struct drm_property *top_property;
  121. struct drm_property *bottom_property;
  122. struct drm_property *hpos_property;
  123. struct drm_property *vpos_property;
  124. /* add the property for the SDVO-TV/LVDS */
  125. struct drm_property *brightness_property;
  126. struct drm_property *contrast_property;
  127. struct drm_property *saturation_property;
  128. struct drm_property *hue_property;
  129. /* Add variable to record current setting for the above property */
  130. u32 left_margin, right_margin, top_margin, bottom_margin;
  131. /* this is to get the range of margin.*/
  132. u32 max_hscan, max_vscan;
  133. u32 max_hpos, cur_hpos;
  134. u32 max_vpos, cur_vpos;
  135. u32 cur_brightness, max_brightness;
  136. u32 cur_contrast, max_contrast;
  137. u32 cur_saturation, max_saturation;
  138. u32 cur_hue, max_hue;
  139. };
  140. static bool
  141. intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
  142. /**
  143. * Writes the SDVOB or SDVOC with the given value, but always writes both
  144. * SDVOB and SDVOC to work around apparent hardware issues (according to
  145. * comments in the BIOS).
  146. */
  147. static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
  148. {
  149. struct drm_device *dev = intel_output->base.dev;
  150. struct drm_i915_private *dev_priv = dev->dev_private;
  151. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  152. u32 bval = val, cval = val;
  153. int i;
  154. if (sdvo_priv->output_device == SDVOB) {
  155. cval = I915_READ(SDVOC);
  156. } else {
  157. bval = I915_READ(SDVOB);
  158. }
  159. /*
  160. * Write the registers twice for luck. Sometimes,
  161. * writing them only once doesn't appear to 'stick'.
  162. * The BIOS does this too. Yay, magic
  163. */
  164. for (i = 0; i < 2; i++)
  165. {
  166. I915_WRITE(SDVOB, bval);
  167. I915_READ(SDVOB);
  168. I915_WRITE(SDVOC, cval);
  169. I915_READ(SDVOC);
  170. }
  171. }
  172. static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
  173. u8 *ch)
  174. {
  175. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  176. u8 out_buf[2];
  177. u8 buf[2];
  178. int ret;
  179. struct i2c_msg msgs[] = {
  180. {
  181. .addr = sdvo_priv->slave_addr >> 1,
  182. .flags = 0,
  183. .len = 1,
  184. .buf = out_buf,
  185. },
  186. {
  187. .addr = sdvo_priv->slave_addr >> 1,
  188. .flags = I2C_M_RD,
  189. .len = 1,
  190. .buf = buf,
  191. }
  192. };
  193. out_buf[0] = addr;
  194. out_buf[1] = 0;
  195. if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
  196. {
  197. *ch = buf[0];
  198. return true;
  199. }
  200. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  201. return false;
  202. }
  203. static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
  204. u8 ch)
  205. {
  206. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  207. u8 out_buf[2];
  208. struct i2c_msg msgs[] = {
  209. {
  210. .addr = sdvo_priv->slave_addr >> 1,
  211. .flags = 0,
  212. .len = 2,
  213. .buf = out_buf,
  214. }
  215. };
  216. out_buf[0] = addr;
  217. out_buf[1] = ch;
  218. if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
  219. {
  220. return true;
  221. }
  222. return false;
  223. }
  224. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  225. /** Mapping of command numbers to names, for debug output */
  226. static const struct _sdvo_cmd_name {
  227. u8 cmd;
  228. char *name;
  229. } sdvo_cmd_names[] = {
  230. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  231. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  232. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  233. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  234. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  235. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  236. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  237. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  238. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  239. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  240. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  241. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  242. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  245. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  273. /* Add the op code for SDVO enhancements */
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  298. /* HDMI op code */
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  319. };
  320. #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
  321. #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
  322. #ifdef SDVO_DEBUG
  323. static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
  324. void *args, int args_len)
  325. {
  326. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  327. int i;
  328. DRM_DEBUG_KMS("%s: W: %02X ",
  329. SDVO_NAME(sdvo_priv), cmd);
  330. for (i = 0; i < args_len; i++)
  331. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  332. for (; i < 8; i++)
  333. DRM_LOG_KMS(" ");
  334. for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
  335. if (cmd == sdvo_cmd_names[i].cmd) {
  336. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  337. break;
  338. }
  339. }
  340. if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
  341. DRM_LOG_KMS("(%02X)", cmd);
  342. DRM_LOG_KMS("\n");
  343. }
  344. #else
  345. #define intel_sdvo_debug_write(o, c, a, l)
  346. #endif
  347. static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
  348. void *args, int args_len)
  349. {
  350. int i;
  351. intel_sdvo_debug_write(intel_output, cmd, args, args_len);
  352. for (i = 0; i < args_len; i++) {
  353. intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
  354. ((u8*)args)[i]);
  355. }
  356. intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
  357. }
  358. #ifdef SDVO_DEBUG
  359. static const char *cmd_status_names[] = {
  360. "Power on",
  361. "Success",
  362. "Not supported",
  363. "Invalid arg",
  364. "Pending",
  365. "Target not specified",
  366. "Scaling not supported"
  367. };
  368. static void intel_sdvo_debug_response(struct intel_output *intel_output,
  369. void *response, int response_len,
  370. u8 status)
  371. {
  372. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  373. int i;
  374. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
  375. for (i = 0; i < response_len; i++)
  376. DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
  377. for (; i < 8; i++)
  378. DRM_LOG_KMS(" ");
  379. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  380. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  381. else
  382. DRM_LOG_KMS("(??? %d)", status);
  383. DRM_LOG_KMS("\n");
  384. }
  385. #else
  386. #define intel_sdvo_debug_response(o, r, l, s)
  387. #endif
  388. static u8 intel_sdvo_read_response(struct intel_output *intel_output,
  389. void *response, int response_len)
  390. {
  391. int i;
  392. u8 status;
  393. u8 retry = 50;
  394. while (retry--) {
  395. /* Read the command response */
  396. for (i = 0; i < response_len; i++) {
  397. intel_sdvo_read_byte(intel_output,
  398. SDVO_I2C_RETURN_0 + i,
  399. &((u8 *)response)[i]);
  400. }
  401. /* read the return status */
  402. intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
  403. &status);
  404. intel_sdvo_debug_response(intel_output, response, response_len,
  405. status);
  406. if (status != SDVO_CMD_STATUS_PENDING)
  407. return status;
  408. mdelay(50);
  409. }
  410. return status;
  411. }
  412. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  413. {
  414. if (mode->clock >= 100000)
  415. return 1;
  416. else if (mode->clock >= 50000)
  417. return 2;
  418. else
  419. return 4;
  420. }
  421. /**
  422. * Don't check status code from this as it switches the bus back to the
  423. * SDVO chips which defeats the purpose of doing a bus switch in the first
  424. * place.
  425. */
  426. static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
  427. u8 target)
  428. {
  429. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
  430. }
  431. static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
  432. {
  433. struct intel_sdvo_set_target_input_args targets = {0};
  434. u8 status;
  435. if (target_0 && target_1)
  436. return SDVO_CMD_STATUS_NOTSUPP;
  437. if (target_1)
  438. targets.target_1 = 1;
  439. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
  440. sizeof(targets));
  441. status = intel_sdvo_read_response(intel_output, NULL, 0);
  442. return (status == SDVO_CMD_STATUS_SUCCESS);
  443. }
  444. /**
  445. * Return whether each input is trained.
  446. *
  447. * This function is making an assumption about the layout of the response,
  448. * which should be checked against the docs.
  449. */
  450. static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
  451. {
  452. struct intel_sdvo_get_trained_inputs_response response;
  453. u8 status;
  454. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
  455. status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
  456. if (status != SDVO_CMD_STATUS_SUCCESS)
  457. return false;
  458. *input_1 = response.input0_trained;
  459. *input_2 = response.input1_trained;
  460. return true;
  461. }
  462. static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
  463. u16 *outputs)
  464. {
  465. u8 status;
  466. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
  467. status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
  468. return (status == SDVO_CMD_STATUS_SUCCESS);
  469. }
  470. static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
  471. u16 outputs)
  472. {
  473. u8 status;
  474. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
  475. sizeof(outputs));
  476. status = intel_sdvo_read_response(intel_output, NULL, 0);
  477. return (status == SDVO_CMD_STATUS_SUCCESS);
  478. }
  479. static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
  480. int mode)
  481. {
  482. u8 status, state = SDVO_ENCODER_STATE_ON;
  483. switch (mode) {
  484. case DRM_MODE_DPMS_ON:
  485. state = SDVO_ENCODER_STATE_ON;
  486. break;
  487. case DRM_MODE_DPMS_STANDBY:
  488. state = SDVO_ENCODER_STATE_STANDBY;
  489. break;
  490. case DRM_MODE_DPMS_SUSPEND:
  491. state = SDVO_ENCODER_STATE_SUSPEND;
  492. break;
  493. case DRM_MODE_DPMS_OFF:
  494. state = SDVO_ENCODER_STATE_OFF;
  495. break;
  496. }
  497. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
  498. sizeof(state));
  499. status = intel_sdvo_read_response(intel_output, NULL, 0);
  500. return (status == SDVO_CMD_STATUS_SUCCESS);
  501. }
  502. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
  503. int *clock_min,
  504. int *clock_max)
  505. {
  506. struct intel_sdvo_pixel_clock_range clocks;
  507. u8 status;
  508. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  509. NULL, 0);
  510. status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
  511. if (status != SDVO_CMD_STATUS_SUCCESS)
  512. return false;
  513. /* Convert the values from units of 10 kHz to kHz. */
  514. *clock_min = clocks.min * 10;
  515. *clock_max = clocks.max * 10;
  516. return true;
  517. }
  518. static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
  519. u16 outputs)
  520. {
  521. u8 status;
  522. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
  523. sizeof(outputs));
  524. status = intel_sdvo_read_response(intel_output, NULL, 0);
  525. return (status == SDVO_CMD_STATUS_SUCCESS);
  526. }
  527. static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
  528. struct intel_sdvo_dtd *dtd)
  529. {
  530. u8 status;
  531. intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
  532. status = intel_sdvo_read_response(intel_output, &dtd->part1,
  533. sizeof(dtd->part1));
  534. if (status != SDVO_CMD_STATUS_SUCCESS)
  535. return false;
  536. intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
  537. status = intel_sdvo_read_response(intel_output, &dtd->part2,
  538. sizeof(dtd->part2));
  539. if (status != SDVO_CMD_STATUS_SUCCESS)
  540. return false;
  541. return true;
  542. }
  543. static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
  544. struct intel_sdvo_dtd *dtd)
  545. {
  546. return intel_sdvo_get_timing(intel_output,
  547. SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
  548. }
  549. static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
  550. struct intel_sdvo_dtd *dtd)
  551. {
  552. return intel_sdvo_get_timing(intel_output,
  553. SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
  554. }
  555. static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
  556. struct intel_sdvo_dtd *dtd)
  557. {
  558. u8 status;
  559. intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
  560. status = intel_sdvo_read_response(intel_output, NULL, 0);
  561. if (status != SDVO_CMD_STATUS_SUCCESS)
  562. return false;
  563. intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  564. status = intel_sdvo_read_response(intel_output, NULL, 0);
  565. if (status != SDVO_CMD_STATUS_SUCCESS)
  566. return false;
  567. return true;
  568. }
  569. static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
  570. struct intel_sdvo_dtd *dtd)
  571. {
  572. return intel_sdvo_set_timing(intel_output,
  573. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  574. }
  575. static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
  576. struct intel_sdvo_dtd *dtd)
  577. {
  578. return intel_sdvo_set_timing(intel_output,
  579. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  580. }
  581. static bool
  582. intel_sdvo_create_preferred_input_timing(struct intel_output *output,
  583. uint16_t clock,
  584. uint16_t width,
  585. uint16_t height)
  586. {
  587. struct intel_sdvo_preferred_input_timing_args args;
  588. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  589. uint8_t status;
  590. memset(&args, 0, sizeof(args));
  591. args.clock = clock;
  592. args.width = width;
  593. args.height = height;
  594. args.interlace = 0;
  595. if (sdvo_priv->is_lvds &&
  596. (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
  597. sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
  598. args.scaled = 1;
  599. intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  600. &args, sizeof(args));
  601. status = intel_sdvo_read_response(output, NULL, 0);
  602. if (status != SDVO_CMD_STATUS_SUCCESS)
  603. return false;
  604. return true;
  605. }
  606. static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
  607. struct intel_sdvo_dtd *dtd)
  608. {
  609. bool status;
  610. intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  611. NULL, 0);
  612. status = intel_sdvo_read_response(output, &dtd->part1,
  613. sizeof(dtd->part1));
  614. if (status != SDVO_CMD_STATUS_SUCCESS)
  615. return false;
  616. intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  617. NULL, 0);
  618. status = intel_sdvo_read_response(output, &dtd->part2,
  619. sizeof(dtd->part2));
  620. if (status != SDVO_CMD_STATUS_SUCCESS)
  621. return false;
  622. return false;
  623. }
  624. static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
  625. {
  626. u8 response, status;
  627. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
  628. status = intel_sdvo_read_response(intel_output, &response, 1);
  629. if (status != SDVO_CMD_STATUS_SUCCESS) {
  630. DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
  631. return SDVO_CLOCK_RATE_MULT_1X;
  632. } else {
  633. DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
  634. }
  635. return response;
  636. }
  637. static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
  638. {
  639. u8 status;
  640. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  641. status = intel_sdvo_read_response(intel_output, NULL, 0);
  642. if (status != SDVO_CMD_STATUS_SUCCESS)
  643. return false;
  644. return true;
  645. }
  646. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  647. struct drm_display_mode *mode)
  648. {
  649. uint16_t width, height;
  650. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  651. uint16_t h_sync_offset, v_sync_offset;
  652. width = mode->crtc_hdisplay;
  653. height = mode->crtc_vdisplay;
  654. /* do some mode translations */
  655. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  656. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  657. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  658. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  659. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  660. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  661. dtd->part1.clock = mode->clock / 10;
  662. dtd->part1.h_active = width & 0xff;
  663. dtd->part1.h_blank = h_blank_len & 0xff;
  664. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  665. ((h_blank_len >> 8) & 0xf);
  666. dtd->part1.v_active = height & 0xff;
  667. dtd->part1.v_blank = v_blank_len & 0xff;
  668. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  669. ((v_blank_len >> 8) & 0xf);
  670. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  671. dtd->part2.h_sync_width = h_sync_len & 0xff;
  672. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  673. (v_sync_len & 0xf);
  674. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  675. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  676. ((v_sync_len & 0x30) >> 4);
  677. dtd->part2.dtd_flags = 0x18;
  678. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  679. dtd->part2.dtd_flags |= 0x2;
  680. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  681. dtd->part2.dtd_flags |= 0x4;
  682. dtd->part2.sdvo_flags = 0;
  683. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  684. dtd->part2.reserved = 0;
  685. }
  686. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  687. struct intel_sdvo_dtd *dtd)
  688. {
  689. mode->hdisplay = dtd->part1.h_active;
  690. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  691. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  692. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  693. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  694. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  695. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  696. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  697. mode->vdisplay = dtd->part1.v_active;
  698. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  699. mode->vsync_start = mode->vdisplay;
  700. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  701. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  702. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  703. mode->vsync_end = mode->vsync_start +
  704. (dtd->part2.v_sync_off_width & 0xf);
  705. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  706. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  707. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  708. mode->clock = dtd->part1.clock * 10;
  709. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  710. if (dtd->part2.dtd_flags & 0x2)
  711. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  712. if (dtd->part2.dtd_flags & 0x4)
  713. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  714. }
  715. static bool intel_sdvo_get_supp_encode(struct intel_output *output,
  716. struct intel_sdvo_encode *encode)
  717. {
  718. uint8_t status;
  719. intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
  720. status = intel_sdvo_read_response(output, encode, sizeof(*encode));
  721. if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
  722. memset(encode, 0, sizeof(*encode));
  723. return false;
  724. }
  725. return true;
  726. }
  727. static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
  728. {
  729. uint8_t status;
  730. intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
  731. status = intel_sdvo_read_response(output, NULL, 0);
  732. return (status == SDVO_CMD_STATUS_SUCCESS);
  733. }
  734. static bool intel_sdvo_set_colorimetry(struct intel_output *output,
  735. uint8_t mode)
  736. {
  737. uint8_t status;
  738. intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  739. status = intel_sdvo_read_response(output, NULL, 0);
  740. return (status == SDVO_CMD_STATUS_SUCCESS);
  741. }
  742. #if 0
  743. static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
  744. {
  745. int i, j;
  746. uint8_t set_buf_index[2];
  747. uint8_t av_split;
  748. uint8_t buf_size;
  749. uint8_t buf[48];
  750. uint8_t *pos;
  751. intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
  752. intel_sdvo_read_response(output, &av_split, 1);
  753. for (i = 0; i <= av_split; i++) {
  754. set_buf_index[0] = i; set_buf_index[1] = 0;
  755. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
  756. set_buf_index, 2);
  757. intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  758. intel_sdvo_read_response(output, &buf_size, 1);
  759. pos = buf;
  760. for (j = 0; j <= buf_size; j += 8) {
  761. intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
  762. NULL, 0);
  763. intel_sdvo_read_response(output, pos, 8);
  764. pos += 8;
  765. }
  766. }
  767. }
  768. #endif
  769. static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
  770. uint8_t *data, int8_t size, uint8_t tx_rate)
  771. {
  772. uint8_t set_buf_index[2];
  773. set_buf_index[0] = index;
  774. set_buf_index[1] = 0;
  775. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
  776. for (; size > 0; size -= 8) {
  777. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
  778. data += 8;
  779. }
  780. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
  781. }
  782. static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
  783. {
  784. uint8_t csum = 0;
  785. int i;
  786. for (i = 0; i < size; i++)
  787. csum += data[i];
  788. return 0x100 - csum;
  789. }
  790. #define DIP_TYPE_AVI 0x82
  791. #define DIP_VERSION_AVI 0x2
  792. #define DIP_LEN_AVI 13
  793. struct dip_infoframe {
  794. uint8_t type;
  795. uint8_t version;
  796. uint8_t len;
  797. uint8_t checksum;
  798. union {
  799. struct {
  800. /* Packet Byte #1 */
  801. uint8_t S:2;
  802. uint8_t B:2;
  803. uint8_t A:1;
  804. uint8_t Y:2;
  805. uint8_t rsvd1:1;
  806. /* Packet Byte #2 */
  807. uint8_t R:4;
  808. uint8_t M:2;
  809. uint8_t C:2;
  810. /* Packet Byte #3 */
  811. uint8_t SC:2;
  812. uint8_t Q:2;
  813. uint8_t EC:3;
  814. uint8_t ITC:1;
  815. /* Packet Byte #4 */
  816. uint8_t VIC:7;
  817. uint8_t rsvd2:1;
  818. /* Packet Byte #5 */
  819. uint8_t PR:4;
  820. uint8_t rsvd3:4;
  821. /* Packet Byte #6~13 */
  822. uint16_t top_bar_end;
  823. uint16_t bottom_bar_start;
  824. uint16_t left_bar_end;
  825. uint16_t right_bar_start;
  826. } avi;
  827. struct {
  828. /* Packet Byte #1 */
  829. uint8_t channel_count:3;
  830. uint8_t rsvd1:1;
  831. uint8_t coding_type:4;
  832. /* Packet Byte #2 */
  833. uint8_t sample_size:2; /* SS0, SS1 */
  834. uint8_t sample_frequency:3;
  835. uint8_t rsvd2:3;
  836. /* Packet Byte #3 */
  837. uint8_t coding_type_private:5;
  838. uint8_t rsvd3:3;
  839. /* Packet Byte #4 */
  840. uint8_t channel_allocation;
  841. /* Packet Byte #5 */
  842. uint8_t rsvd4:3;
  843. uint8_t level_shift:4;
  844. uint8_t downmix_inhibit:1;
  845. } audio;
  846. uint8_t payload[28];
  847. } __attribute__ ((packed)) u;
  848. } __attribute__((packed));
  849. static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
  850. struct drm_display_mode * mode)
  851. {
  852. struct dip_infoframe avi_if = {
  853. .type = DIP_TYPE_AVI,
  854. .version = DIP_VERSION_AVI,
  855. .len = DIP_LEN_AVI,
  856. };
  857. avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
  858. 4 + avi_if.len);
  859. intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
  860. SDVO_HBUF_TX_VSYNC);
  861. }
  862. static void intel_sdvo_set_tv_format(struct intel_output *output)
  863. {
  864. struct intel_sdvo_tv_format format;
  865. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  866. uint32_t format_map, i;
  867. uint8_t status;
  868. for (i = 0; i < TV_FORMAT_NUM; i++)
  869. if (tv_format_names[i] == sdvo_priv->tv_format_name)
  870. break;
  871. format_map = 1 << i;
  872. memset(&format, 0, sizeof(format));
  873. memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
  874. sizeof(format) : sizeof(format_map));
  875. intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
  876. sizeof(format));
  877. status = intel_sdvo_read_response(output, NULL, 0);
  878. if (status != SDVO_CMD_STATUS_SUCCESS)
  879. DRM_DEBUG_KMS("%s: Failed to set TV format\n",
  880. SDVO_NAME(sdvo_priv));
  881. }
  882. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  883. struct drm_display_mode *mode,
  884. struct drm_display_mode *adjusted_mode)
  885. {
  886. struct intel_output *output = enc_to_intel_output(encoder);
  887. struct intel_sdvo_priv *dev_priv = output->dev_priv;
  888. if (dev_priv->is_tv) {
  889. struct intel_sdvo_dtd output_dtd;
  890. bool success;
  891. /* We need to construct preferred input timings based on our
  892. * output timings. To do that, we have to set the output
  893. * timings, even though this isn't really the right place in
  894. * the sequence to do it. Oh well.
  895. */
  896. /* Set output timings */
  897. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  898. intel_sdvo_set_target_output(output,
  899. dev_priv->controlled_output);
  900. intel_sdvo_set_output_timing(output, &output_dtd);
  901. /* Set the input timing to the screen. Assume always input 0. */
  902. intel_sdvo_set_target_input(output, true, false);
  903. success = intel_sdvo_create_preferred_input_timing(output,
  904. mode->clock / 10,
  905. mode->hdisplay,
  906. mode->vdisplay);
  907. if (success) {
  908. struct intel_sdvo_dtd input_dtd;
  909. intel_sdvo_get_preferred_input_timing(output,
  910. &input_dtd);
  911. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  912. dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
  913. drm_mode_set_crtcinfo(adjusted_mode, 0);
  914. mode->clock = adjusted_mode->clock;
  915. adjusted_mode->clock *=
  916. intel_sdvo_get_pixel_multiplier(mode);
  917. } else {
  918. return false;
  919. }
  920. } else if (dev_priv->is_lvds) {
  921. struct intel_sdvo_dtd output_dtd;
  922. bool success;
  923. drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
  924. /* Set output timings */
  925. intel_sdvo_get_dtd_from_mode(&output_dtd,
  926. dev_priv->sdvo_lvds_fixed_mode);
  927. intel_sdvo_set_target_output(output,
  928. dev_priv->controlled_output);
  929. intel_sdvo_set_output_timing(output, &output_dtd);
  930. /* Set the input timing to the screen. Assume always input 0. */
  931. intel_sdvo_set_target_input(output, true, false);
  932. success = intel_sdvo_create_preferred_input_timing(
  933. output,
  934. mode->clock / 10,
  935. mode->hdisplay,
  936. mode->vdisplay);
  937. if (success) {
  938. struct intel_sdvo_dtd input_dtd;
  939. intel_sdvo_get_preferred_input_timing(output,
  940. &input_dtd);
  941. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  942. dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
  943. drm_mode_set_crtcinfo(adjusted_mode, 0);
  944. mode->clock = adjusted_mode->clock;
  945. adjusted_mode->clock *=
  946. intel_sdvo_get_pixel_multiplier(mode);
  947. } else {
  948. return false;
  949. }
  950. } else {
  951. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  952. * SDVO device will be told of the multiplier during mode_set.
  953. */
  954. adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
  955. }
  956. return true;
  957. }
  958. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  959. struct drm_display_mode *mode,
  960. struct drm_display_mode *adjusted_mode)
  961. {
  962. struct drm_device *dev = encoder->dev;
  963. struct drm_i915_private *dev_priv = dev->dev_private;
  964. struct drm_crtc *crtc = encoder->crtc;
  965. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  966. struct intel_output *output = enc_to_intel_output(encoder);
  967. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  968. u32 sdvox = 0;
  969. int sdvo_pixel_multiply;
  970. struct intel_sdvo_in_out_map in_out;
  971. struct intel_sdvo_dtd input_dtd;
  972. u8 status;
  973. if (!mode)
  974. return;
  975. /* First, set the input mapping for the first input to our controlled
  976. * output. This is only correct if we're a single-input device, in
  977. * which case the first input is the output from the appropriate SDVO
  978. * channel on the motherboard. In a two-input device, the first input
  979. * will be SDVOB and the second SDVOC.
  980. */
  981. in_out.in0 = sdvo_priv->controlled_output;
  982. in_out.in1 = 0;
  983. intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
  984. &in_out, sizeof(in_out));
  985. status = intel_sdvo_read_response(output, NULL, 0);
  986. if (sdvo_priv->is_hdmi) {
  987. intel_sdvo_set_avi_infoframe(output, mode);
  988. sdvox |= SDVO_AUDIO_ENABLE;
  989. }
  990. /* We have tried to get input timing in mode_fixup, and filled into
  991. adjusted_mode */
  992. if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
  993. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  994. input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
  995. } else
  996. intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
  997. /* If it's a TV, we already set the output timing in mode_fixup.
  998. * Otherwise, the output timing is equal to the input timing.
  999. */
  1000. if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
  1001. /* Set the output timing to the screen */
  1002. intel_sdvo_set_target_output(output,
  1003. sdvo_priv->controlled_output);
  1004. intel_sdvo_set_output_timing(output, &input_dtd);
  1005. }
  1006. /* Set the input timing to the screen. Assume always input 0. */
  1007. intel_sdvo_set_target_input(output, true, false);
  1008. if (sdvo_priv->is_tv)
  1009. intel_sdvo_set_tv_format(output);
  1010. /* We would like to use intel_sdvo_create_preferred_input_timing() to
  1011. * provide the device with a timing it can support, if it supports that
  1012. * feature. However, presumably we would need to adjust the CRTC to
  1013. * output the preferred timing, and we don't support that currently.
  1014. */
  1015. #if 0
  1016. success = intel_sdvo_create_preferred_input_timing(output, clock,
  1017. width, height);
  1018. if (success) {
  1019. struct intel_sdvo_dtd *input_dtd;
  1020. intel_sdvo_get_preferred_input_timing(output, &input_dtd);
  1021. intel_sdvo_set_input_timing(output, &input_dtd);
  1022. }
  1023. #else
  1024. intel_sdvo_set_input_timing(output, &input_dtd);
  1025. #endif
  1026. switch (intel_sdvo_get_pixel_multiplier(mode)) {
  1027. case 1:
  1028. intel_sdvo_set_clock_rate_mult(output,
  1029. SDVO_CLOCK_RATE_MULT_1X);
  1030. break;
  1031. case 2:
  1032. intel_sdvo_set_clock_rate_mult(output,
  1033. SDVO_CLOCK_RATE_MULT_2X);
  1034. break;
  1035. case 4:
  1036. intel_sdvo_set_clock_rate_mult(output,
  1037. SDVO_CLOCK_RATE_MULT_4X);
  1038. break;
  1039. }
  1040. /* Set the SDVO control regs. */
  1041. if (IS_I965G(dev)) {
  1042. sdvox |= SDVO_BORDER_ENABLE |
  1043. SDVO_VSYNC_ACTIVE_HIGH |
  1044. SDVO_HSYNC_ACTIVE_HIGH;
  1045. } else {
  1046. sdvox |= I915_READ(sdvo_priv->output_device);
  1047. switch (sdvo_priv->output_device) {
  1048. case SDVOB:
  1049. sdvox &= SDVOB_PRESERVE_MASK;
  1050. break;
  1051. case SDVOC:
  1052. sdvox &= SDVOC_PRESERVE_MASK;
  1053. break;
  1054. }
  1055. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1056. }
  1057. if (intel_crtc->pipe == 1)
  1058. sdvox |= SDVO_PIPE_B_SELECT;
  1059. sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
  1060. if (IS_I965G(dev)) {
  1061. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1062. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1063. /* done in crtc_mode_set as it lives inside the dpll register */
  1064. } else {
  1065. sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  1066. }
  1067. if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
  1068. sdvox |= SDVO_STALL_SELECT;
  1069. intel_sdvo_write_sdvox(output, sdvox);
  1070. }
  1071. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  1072. {
  1073. struct drm_device *dev = encoder->dev;
  1074. struct drm_i915_private *dev_priv = dev->dev_private;
  1075. struct intel_output *intel_output = enc_to_intel_output(encoder);
  1076. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1077. u32 temp;
  1078. if (mode != DRM_MODE_DPMS_ON) {
  1079. intel_sdvo_set_active_outputs(intel_output, 0);
  1080. if (0)
  1081. intel_sdvo_set_encoder_power_state(intel_output, mode);
  1082. if (mode == DRM_MODE_DPMS_OFF) {
  1083. temp = I915_READ(sdvo_priv->output_device);
  1084. if ((temp & SDVO_ENABLE) != 0) {
  1085. intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
  1086. }
  1087. }
  1088. } else {
  1089. bool input1, input2;
  1090. int i;
  1091. u8 status;
  1092. temp = I915_READ(sdvo_priv->output_device);
  1093. if ((temp & SDVO_ENABLE) == 0)
  1094. intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
  1095. for (i = 0; i < 2; i++)
  1096. intel_wait_for_vblank(dev);
  1097. status = intel_sdvo_get_trained_inputs(intel_output, &input1,
  1098. &input2);
  1099. /* Warn if the device reported failure to sync.
  1100. * A lot of SDVO devices fail to notify of sync, but it's
  1101. * a given it the status is a success, we succeeded.
  1102. */
  1103. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1104. DRM_DEBUG_KMS("First %s output reported failure to "
  1105. "sync\n", SDVO_NAME(sdvo_priv));
  1106. }
  1107. if (0)
  1108. intel_sdvo_set_encoder_power_state(intel_output, mode);
  1109. intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
  1110. }
  1111. return;
  1112. }
  1113. static void intel_sdvo_save(struct drm_connector *connector)
  1114. {
  1115. struct drm_device *dev = connector->dev;
  1116. struct drm_i915_private *dev_priv = dev->dev_private;
  1117. struct intel_output *intel_output = to_intel_output(connector);
  1118. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1119. int o;
  1120. sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
  1121. intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
  1122. if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
  1123. intel_sdvo_set_target_input(intel_output, true, false);
  1124. intel_sdvo_get_input_timing(intel_output,
  1125. &sdvo_priv->save_input_dtd_1);
  1126. }
  1127. if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
  1128. intel_sdvo_set_target_input(intel_output, false, true);
  1129. intel_sdvo_get_input_timing(intel_output,
  1130. &sdvo_priv->save_input_dtd_2);
  1131. }
  1132. for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
  1133. {
  1134. u16 this_output = (1 << o);
  1135. if (sdvo_priv->caps.output_flags & this_output)
  1136. {
  1137. intel_sdvo_set_target_output(intel_output, this_output);
  1138. intel_sdvo_get_output_timing(intel_output,
  1139. &sdvo_priv->save_output_dtd[o]);
  1140. }
  1141. }
  1142. if (sdvo_priv->is_tv) {
  1143. /* XXX: Save TV format/enhancements. */
  1144. }
  1145. sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
  1146. }
  1147. static void intel_sdvo_restore(struct drm_connector *connector)
  1148. {
  1149. struct drm_device *dev = connector->dev;
  1150. struct intel_output *intel_output = to_intel_output(connector);
  1151. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1152. int o;
  1153. int i;
  1154. bool input1, input2;
  1155. u8 status;
  1156. intel_sdvo_set_active_outputs(intel_output, 0);
  1157. for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
  1158. {
  1159. u16 this_output = (1 << o);
  1160. if (sdvo_priv->caps.output_flags & this_output) {
  1161. intel_sdvo_set_target_output(intel_output, this_output);
  1162. intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
  1163. }
  1164. }
  1165. if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
  1166. intel_sdvo_set_target_input(intel_output, true, false);
  1167. intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
  1168. }
  1169. if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
  1170. intel_sdvo_set_target_input(intel_output, false, true);
  1171. intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
  1172. }
  1173. intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
  1174. if (sdvo_priv->is_tv) {
  1175. /* XXX: Restore TV format/enhancements. */
  1176. }
  1177. intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
  1178. if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
  1179. {
  1180. for (i = 0; i < 2; i++)
  1181. intel_wait_for_vblank(dev);
  1182. status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
  1183. if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
  1184. DRM_DEBUG_KMS("First %s output reported failure to "
  1185. "sync\n", SDVO_NAME(sdvo_priv));
  1186. }
  1187. intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
  1188. }
  1189. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1190. struct drm_display_mode *mode)
  1191. {
  1192. struct intel_output *intel_output = to_intel_output(connector);
  1193. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1194. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1195. return MODE_NO_DBLESCAN;
  1196. if (sdvo_priv->pixel_clock_min > mode->clock)
  1197. return MODE_CLOCK_LOW;
  1198. if (sdvo_priv->pixel_clock_max < mode->clock)
  1199. return MODE_CLOCK_HIGH;
  1200. if (sdvo_priv->is_lvds == true) {
  1201. if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
  1202. return MODE_PANEL;
  1203. if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
  1204. return MODE_PANEL;
  1205. if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
  1206. return MODE_PANEL;
  1207. }
  1208. return MODE_OK;
  1209. }
  1210. static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
  1211. {
  1212. u8 status;
  1213. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
  1214. status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
  1215. if (status != SDVO_CMD_STATUS_SUCCESS)
  1216. return false;
  1217. return true;
  1218. }
  1219. struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1220. {
  1221. struct drm_connector *connector = NULL;
  1222. struct intel_output *iout = NULL;
  1223. struct intel_sdvo_priv *sdvo;
  1224. /* find the sdvo connector */
  1225. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1226. iout = to_intel_output(connector);
  1227. if (iout->type != INTEL_OUTPUT_SDVO)
  1228. continue;
  1229. sdvo = iout->dev_priv;
  1230. if (sdvo->output_device == SDVOB && sdvoB)
  1231. return connector;
  1232. if (sdvo->output_device == SDVOC && !sdvoB)
  1233. return connector;
  1234. }
  1235. return NULL;
  1236. }
  1237. int intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1238. {
  1239. u8 response[2];
  1240. u8 status;
  1241. struct intel_output *intel_output;
  1242. DRM_DEBUG_KMS("\n");
  1243. if (!connector)
  1244. return 0;
  1245. intel_output = to_intel_output(connector);
  1246. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1247. status = intel_sdvo_read_response(intel_output, &response, 2);
  1248. if (response[0] !=0)
  1249. return 1;
  1250. return 0;
  1251. }
  1252. void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1253. {
  1254. u8 response[2];
  1255. u8 status;
  1256. struct intel_output *intel_output = to_intel_output(connector);
  1257. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1258. intel_sdvo_read_response(intel_output, &response, 2);
  1259. if (on) {
  1260. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1261. status = intel_sdvo_read_response(intel_output, &response, 2);
  1262. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1263. } else {
  1264. response[0] = 0;
  1265. response[1] = 0;
  1266. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1267. }
  1268. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1269. intel_sdvo_read_response(intel_output, &response, 2);
  1270. }
  1271. static bool
  1272. intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
  1273. {
  1274. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1275. int caps = 0;
  1276. if (sdvo_priv->caps.output_flags &
  1277. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
  1278. caps++;
  1279. if (sdvo_priv->caps.output_flags &
  1280. (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
  1281. caps++;
  1282. if (sdvo_priv->caps.output_flags &
  1283. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
  1284. caps++;
  1285. if (sdvo_priv->caps.output_flags &
  1286. (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
  1287. caps++;
  1288. if (sdvo_priv->caps.output_flags &
  1289. (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
  1290. caps++;
  1291. if (sdvo_priv->caps.output_flags &
  1292. (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
  1293. caps++;
  1294. if (sdvo_priv->caps.output_flags &
  1295. (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
  1296. caps++;
  1297. return (caps > 1);
  1298. }
  1299. static struct drm_connector *
  1300. intel_find_analog_connector(struct drm_device *dev)
  1301. {
  1302. struct drm_connector *connector;
  1303. struct intel_output *intel_output;
  1304. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1305. intel_output = to_intel_output(connector);
  1306. if (intel_output->type == INTEL_OUTPUT_ANALOG)
  1307. return connector;
  1308. }
  1309. return NULL;
  1310. }
  1311. static int
  1312. intel_analog_is_connected(struct drm_device *dev)
  1313. {
  1314. struct drm_connector *analog_connector;
  1315. analog_connector = intel_find_analog_connector(dev);
  1316. if (!analog_connector)
  1317. return false;
  1318. if (analog_connector->funcs->detect(analog_connector) ==
  1319. connector_status_disconnected)
  1320. return false;
  1321. return true;
  1322. }
  1323. enum drm_connector_status
  1324. intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
  1325. {
  1326. struct intel_output *intel_output = to_intel_output(connector);
  1327. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1328. enum drm_connector_status status = connector_status_connected;
  1329. struct edid *edid = NULL;
  1330. edid = drm_get_edid(&intel_output->base,
  1331. intel_output->ddc_bus);
  1332. /* when there is no edid and no monitor is connected with VGA
  1333. * port, try to use the CRT ddc to read the EDID for DVI-connector
  1334. */
  1335. if (edid == NULL &&
  1336. sdvo_priv->analog_ddc_bus &&
  1337. !intel_analog_is_connected(intel_output->base.dev))
  1338. edid = drm_get_edid(&intel_output->base,
  1339. sdvo_priv->analog_ddc_bus);
  1340. if (edid != NULL) {
  1341. /* Don't report the output as connected if it's a DVI-I
  1342. * connector with a non-digital EDID coming out.
  1343. */
  1344. if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
  1345. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1346. sdvo_priv->is_hdmi =
  1347. drm_detect_hdmi_monitor(edid);
  1348. else
  1349. status = connector_status_disconnected;
  1350. }
  1351. kfree(edid);
  1352. intel_output->base.display_info.raw_edid = NULL;
  1353. } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
  1354. status = connector_status_disconnected;
  1355. return status;
  1356. }
  1357. static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
  1358. {
  1359. uint16_t response;
  1360. u8 status;
  1361. struct intel_output *intel_output = to_intel_output(connector);
  1362. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1363. intel_sdvo_write_cmd(intel_output,
  1364. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
  1365. status = intel_sdvo_read_response(intel_output, &response, 2);
  1366. DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
  1367. if (status != SDVO_CMD_STATUS_SUCCESS)
  1368. return connector_status_unknown;
  1369. if (response == 0)
  1370. return connector_status_disconnected;
  1371. if (intel_sdvo_multifunc_encoder(intel_output) &&
  1372. sdvo_priv->attached_output != response) {
  1373. if (sdvo_priv->controlled_output != response &&
  1374. intel_sdvo_output_setup(intel_output, response) != true)
  1375. return connector_status_unknown;
  1376. sdvo_priv->attached_output = response;
  1377. }
  1378. return intel_sdvo_hdmi_sink_detect(connector, response);
  1379. }
  1380. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1381. {
  1382. struct intel_output *intel_output = to_intel_output(connector);
  1383. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1384. int num_modes;
  1385. /* set the bus switch and get the modes */
  1386. num_modes = intel_ddc_get_modes(intel_output);
  1387. /*
  1388. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1389. * link between analog and digital outputs. So, if the regular SDVO
  1390. * DDC fails, check to see if the analog output is disconnected, in
  1391. * which case we'll look there for the digital DDC data.
  1392. */
  1393. if (num_modes == 0 &&
  1394. sdvo_priv->analog_ddc_bus &&
  1395. !intel_analog_is_connected(intel_output->base.dev)) {
  1396. struct i2c_adapter *digital_ddc_bus;
  1397. /* Switch to the analog ddc bus and try that
  1398. */
  1399. digital_ddc_bus = intel_output->ddc_bus;
  1400. intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
  1401. (void) intel_ddc_get_modes(intel_output);
  1402. intel_output->ddc_bus = digital_ddc_bus;
  1403. }
  1404. }
  1405. /*
  1406. * Set of SDVO TV modes.
  1407. * Note! This is in reply order (see loop in get_tv_modes).
  1408. * XXX: all 60Hz refresh?
  1409. */
  1410. struct drm_display_mode sdvo_tv_modes[] = {
  1411. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1412. 416, 0, 200, 201, 232, 233, 0,
  1413. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1414. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1415. 416, 0, 240, 241, 272, 273, 0,
  1416. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1417. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1418. 496, 0, 300, 301, 332, 333, 0,
  1419. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1420. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1421. 736, 0, 350, 351, 382, 383, 0,
  1422. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1423. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1424. 736, 0, 400, 401, 432, 433, 0,
  1425. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1426. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1427. 736, 0, 480, 481, 512, 513, 0,
  1428. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1429. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1430. 800, 0, 480, 481, 512, 513, 0,
  1431. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1432. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1433. 800, 0, 576, 577, 608, 609, 0,
  1434. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1435. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1436. 816, 0, 350, 351, 382, 383, 0,
  1437. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1438. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1439. 816, 0, 400, 401, 432, 433, 0,
  1440. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1441. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1442. 816, 0, 480, 481, 512, 513, 0,
  1443. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1444. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1445. 816, 0, 540, 541, 572, 573, 0,
  1446. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1447. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1448. 816, 0, 576, 577, 608, 609, 0,
  1449. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1450. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1451. 864, 0, 576, 577, 608, 609, 0,
  1452. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1453. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1454. 896, 0, 600, 601, 632, 633, 0,
  1455. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1456. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1457. 928, 0, 624, 625, 656, 657, 0,
  1458. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1459. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1460. 1016, 0, 766, 767, 798, 799, 0,
  1461. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1462. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1463. 1120, 0, 768, 769, 800, 801, 0,
  1464. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1465. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1466. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1467. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1468. };
  1469. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1470. {
  1471. struct intel_output *output = to_intel_output(connector);
  1472. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1473. struct intel_sdvo_sdtv_resolution_request tv_res;
  1474. uint32_t reply = 0, format_map = 0;
  1475. int i;
  1476. uint8_t status;
  1477. /* Read the list of supported input resolutions for the selected TV
  1478. * format.
  1479. */
  1480. for (i = 0; i < TV_FORMAT_NUM; i++)
  1481. if (tv_format_names[i] == sdvo_priv->tv_format_name)
  1482. break;
  1483. format_map = (1 << i);
  1484. memcpy(&tv_res, &format_map,
  1485. sizeof(struct intel_sdvo_sdtv_resolution_request) >
  1486. sizeof(format_map) ? sizeof(format_map) :
  1487. sizeof(struct intel_sdvo_sdtv_resolution_request));
  1488. intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
  1489. intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1490. &tv_res, sizeof(tv_res));
  1491. status = intel_sdvo_read_response(output, &reply, 3);
  1492. if (status != SDVO_CMD_STATUS_SUCCESS)
  1493. return;
  1494. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1495. if (reply & (1 << i)) {
  1496. struct drm_display_mode *nmode;
  1497. nmode = drm_mode_duplicate(connector->dev,
  1498. &sdvo_tv_modes[i]);
  1499. if (nmode)
  1500. drm_mode_probed_add(connector, nmode);
  1501. }
  1502. }
  1503. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1504. {
  1505. struct intel_output *intel_output = to_intel_output(connector);
  1506. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1507. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1508. struct drm_display_mode *newmode;
  1509. /*
  1510. * Attempt to get the mode list from DDC.
  1511. * Assume that the preferred modes are
  1512. * arranged in priority order.
  1513. */
  1514. intel_ddc_get_modes(intel_output);
  1515. if (list_empty(&connector->probed_modes) == false)
  1516. goto end;
  1517. /* Fetch modes from VBT */
  1518. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1519. newmode = drm_mode_duplicate(connector->dev,
  1520. dev_priv->sdvo_lvds_vbt_mode);
  1521. if (newmode != NULL) {
  1522. /* Guarantee the mode is preferred */
  1523. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1524. DRM_MODE_TYPE_DRIVER);
  1525. drm_mode_probed_add(connector, newmode);
  1526. }
  1527. }
  1528. end:
  1529. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1530. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1531. sdvo_priv->sdvo_lvds_fixed_mode =
  1532. drm_mode_duplicate(connector->dev, newmode);
  1533. break;
  1534. }
  1535. }
  1536. }
  1537. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1538. {
  1539. struct intel_output *output = to_intel_output(connector);
  1540. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1541. if (sdvo_priv->is_tv)
  1542. intel_sdvo_get_tv_modes(connector);
  1543. else if (sdvo_priv->is_lvds == true)
  1544. intel_sdvo_get_lvds_modes(connector);
  1545. else
  1546. intel_sdvo_get_ddc_modes(connector);
  1547. if (list_empty(&connector->probed_modes))
  1548. return 0;
  1549. return 1;
  1550. }
  1551. static
  1552. void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1553. {
  1554. struct intel_output *intel_output = to_intel_output(connector);
  1555. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1556. struct drm_device *dev = connector->dev;
  1557. if (sdvo_priv->is_tv) {
  1558. if (sdvo_priv->left_property)
  1559. drm_property_destroy(dev, sdvo_priv->left_property);
  1560. if (sdvo_priv->right_property)
  1561. drm_property_destroy(dev, sdvo_priv->right_property);
  1562. if (sdvo_priv->top_property)
  1563. drm_property_destroy(dev, sdvo_priv->top_property);
  1564. if (sdvo_priv->bottom_property)
  1565. drm_property_destroy(dev, sdvo_priv->bottom_property);
  1566. if (sdvo_priv->hpos_property)
  1567. drm_property_destroy(dev, sdvo_priv->hpos_property);
  1568. if (sdvo_priv->vpos_property)
  1569. drm_property_destroy(dev, sdvo_priv->vpos_property);
  1570. }
  1571. if (sdvo_priv->is_tv) {
  1572. if (sdvo_priv->saturation_property)
  1573. drm_property_destroy(dev,
  1574. sdvo_priv->saturation_property);
  1575. if (sdvo_priv->contrast_property)
  1576. drm_property_destroy(dev,
  1577. sdvo_priv->contrast_property);
  1578. if (sdvo_priv->hue_property)
  1579. drm_property_destroy(dev, sdvo_priv->hue_property);
  1580. }
  1581. if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
  1582. if (sdvo_priv->brightness_property)
  1583. drm_property_destroy(dev,
  1584. sdvo_priv->brightness_property);
  1585. }
  1586. return;
  1587. }
  1588. static void intel_sdvo_destroy(struct drm_connector *connector)
  1589. {
  1590. struct intel_output *intel_output = to_intel_output(connector);
  1591. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1592. if (intel_output->i2c_bus)
  1593. intel_i2c_destroy(intel_output->i2c_bus);
  1594. if (intel_output->ddc_bus)
  1595. intel_i2c_destroy(intel_output->ddc_bus);
  1596. if (sdvo_priv->analog_ddc_bus)
  1597. intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
  1598. if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
  1599. drm_mode_destroy(connector->dev,
  1600. sdvo_priv->sdvo_lvds_fixed_mode);
  1601. if (sdvo_priv->tv_format_property)
  1602. drm_property_destroy(connector->dev,
  1603. sdvo_priv->tv_format_property);
  1604. if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
  1605. intel_sdvo_destroy_enhance_property(connector);
  1606. drm_sysfs_connector_remove(connector);
  1607. drm_connector_cleanup(connector);
  1608. kfree(intel_output);
  1609. }
  1610. static int
  1611. intel_sdvo_set_property(struct drm_connector *connector,
  1612. struct drm_property *property,
  1613. uint64_t val)
  1614. {
  1615. struct intel_output *intel_output = to_intel_output(connector);
  1616. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1617. struct drm_encoder *encoder = &intel_output->enc;
  1618. struct drm_crtc *crtc = encoder->crtc;
  1619. int ret = 0;
  1620. bool changed = false;
  1621. uint8_t cmd, status;
  1622. uint16_t temp_value;
  1623. ret = drm_connector_property_set_value(connector, property, val);
  1624. if (ret < 0)
  1625. goto out;
  1626. if (property == sdvo_priv->tv_format_property) {
  1627. if (val >= TV_FORMAT_NUM) {
  1628. ret = -EINVAL;
  1629. goto out;
  1630. }
  1631. if (sdvo_priv->tv_format_name ==
  1632. sdvo_priv->tv_format_supported[val])
  1633. goto out;
  1634. sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
  1635. changed = true;
  1636. }
  1637. if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
  1638. cmd = 0;
  1639. temp_value = val;
  1640. if (sdvo_priv->left_property == property) {
  1641. drm_connector_property_set_value(connector,
  1642. sdvo_priv->right_property, val);
  1643. if (sdvo_priv->left_margin == temp_value)
  1644. goto out;
  1645. sdvo_priv->left_margin = temp_value;
  1646. sdvo_priv->right_margin = temp_value;
  1647. temp_value = sdvo_priv->max_hscan -
  1648. sdvo_priv->left_margin;
  1649. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1650. } else if (sdvo_priv->right_property == property) {
  1651. drm_connector_property_set_value(connector,
  1652. sdvo_priv->left_property, val);
  1653. if (sdvo_priv->right_margin == temp_value)
  1654. goto out;
  1655. sdvo_priv->left_margin = temp_value;
  1656. sdvo_priv->right_margin = temp_value;
  1657. temp_value = sdvo_priv->max_hscan -
  1658. sdvo_priv->left_margin;
  1659. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1660. } else if (sdvo_priv->top_property == property) {
  1661. drm_connector_property_set_value(connector,
  1662. sdvo_priv->bottom_property, val);
  1663. if (sdvo_priv->top_margin == temp_value)
  1664. goto out;
  1665. sdvo_priv->top_margin = temp_value;
  1666. sdvo_priv->bottom_margin = temp_value;
  1667. temp_value = sdvo_priv->max_vscan -
  1668. sdvo_priv->top_margin;
  1669. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1670. } else if (sdvo_priv->bottom_property == property) {
  1671. drm_connector_property_set_value(connector,
  1672. sdvo_priv->top_property, val);
  1673. if (sdvo_priv->bottom_margin == temp_value)
  1674. goto out;
  1675. sdvo_priv->top_margin = temp_value;
  1676. sdvo_priv->bottom_margin = temp_value;
  1677. temp_value = sdvo_priv->max_vscan -
  1678. sdvo_priv->top_margin;
  1679. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1680. } else if (sdvo_priv->hpos_property == property) {
  1681. if (sdvo_priv->cur_hpos == temp_value)
  1682. goto out;
  1683. cmd = SDVO_CMD_SET_POSITION_H;
  1684. sdvo_priv->cur_hpos = temp_value;
  1685. } else if (sdvo_priv->vpos_property == property) {
  1686. if (sdvo_priv->cur_vpos == temp_value)
  1687. goto out;
  1688. cmd = SDVO_CMD_SET_POSITION_V;
  1689. sdvo_priv->cur_vpos = temp_value;
  1690. } else if (sdvo_priv->saturation_property == property) {
  1691. if (sdvo_priv->cur_saturation == temp_value)
  1692. goto out;
  1693. cmd = SDVO_CMD_SET_SATURATION;
  1694. sdvo_priv->cur_saturation = temp_value;
  1695. } else if (sdvo_priv->contrast_property == property) {
  1696. if (sdvo_priv->cur_contrast == temp_value)
  1697. goto out;
  1698. cmd = SDVO_CMD_SET_CONTRAST;
  1699. sdvo_priv->cur_contrast = temp_value;
  1700. } else if (sdvo_priv->hue_property == property) {
  1701. if (sdvo_priv->cur_hue == temp_value)
  1702. goto out;
  1703. cmd = SDVO_CMD_SET_HUE;
  1704. sdvo_priv->cur_hue = temp_value;
  1705. } else if (sdvo_priv->brightness_property == property) {
  1706. if (sdvo_priv->cur_brightness == temp_value)
  1707. goto out;
  1708. cmd = SDVO_CMD_SET_BRIGHTNESS;
  1709. sdvo_priv->cur_brightness = temp_value;
  1710. }
  1711. if (cmd) {
  1712. intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2);
  1713. status = intel_sdvo_read_response(intel_output,
  1714. NULL, 0);
  1715. if (status != SDVO_CMD_STATUS_SUCCESS) {
  1716. DRM_DEBUG_KMS("Incorrect SDVO command \n");
  1717. return -EINVAL;
  1718. }
  1719. changed = true;
  1720. }
  1721. }
  1722. if (changed && crtc)
  1723. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1724. crtc->y, crtc->fb);
  1725. out:
  1726. return ret;
  1727. }
  1728. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1729. .dpms = intel_sdvo_dpms,
  1730. .mode_fixup = intel_sdvo_mode_fixup,
  1731. .prepare = intel_encoder_prepare,
  1732. .mode_set = intel_sdvo_mode_set,
  1733. .commit = intel_encoder_commit,
  1734. };
  1735. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1736. .dpms = drm_helper_connector_dpms,
  1737. .save = intel_sdvo_save,
  1738. .restore = intel_sdvo_restore,
  1739. .detect = intel_sdvo_detect,
  1740. .fill_modes = drm_helper_probe_single_connector_modes,
  1741. .set_property = intel_sdvo_set_property,
  1742. .destroy = intel_sdvo_destroy,
  1743. };
  1744. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1745. .get_modes = intel_sdvo_get_modes,
  1746. .mode_valid = intel_sdvo_mode_valid,
  1747. .best_encoder = intel_best_encoder,
  1748. };
  1749. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1750. {
  1751. drm_encoder_cleanup(encoder);
  1752. }
  1753. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1754. .destroy = intel_sdvo_enc_destroy,
  1755. };
  1756. /**
  1757. * Choose the appropriate DDC bus for control bus switch command for this
  1758. * SDVO output based on the controlled output.
  1759. *
  1760. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1761. * outputs, then LVDS outputs.
  1762. */
  1763. static void
  1764. intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
  1765. {
  1766. uint16_t mask = 0;
  1767. unsigned int num_bits;
  1768. /* Make a mask of outputs less than or equal to our own priority in the
  1769. * list.
  1770. */
  1771. switch (dev_priv->controlled_output) {
  1772. case SDVO_OUTPUT_LVDS1:
  1773. mask |= SDVO_OUTPUT_LVDS1;
  1774. case SDVO_OUTPUT_LVDS0:
  1775. mask |= SDVO_OUTPUT_LVDS0;
  1776. case SDVO_OUTPUT_TMDS1:
  1777. mask |= SDVO_OUTPUT_TMDS1;
  1778. case SDVO_OUTPUT_TMDS0:
  1779. mask |= SDVO_OUTPUT_TMDS0;
  1780. case SDVO_OUTPUT_RGB1:
  1781. mask |= SDVO_OUTPUT_RGB1;
  1782. case SDVO_OUTPUT_RGB0:
  1783. mask |= SDVO_OUTPUT_RGB0;
  1784. break;
  1785. }
  1786. /* Count bits to find what number we are in the priority list. */
  1787. mask &= dev_priv->caps.output_flags;
  1788. num_bits = hweight16(mask);
  1789. if (num_bits > 3) {
  1790. /* if more than 3 outputs, default to DDC bus 3 for now */
  1791. num_bits = 3;
  1792. }
  1793. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1794. dev_priv->ddc_bus = 1 << num_bits;
  1795. }
  1796. static bool
  1797. intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
  1798. {
  1799. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1800. uint8_t status;
  1801. intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
  1802. intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
  1803. status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
  1804. if (status != SDVO_CMD_STATUS_SUCCESS)
  1805. return false;
  1806. return true;
  1807. }
  1808. static struct intel_output *
  1809. intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
  1810. {
  1811. struct drm_device *dev = chan->drm_dev;
  1812. struct drm_connector *connector;
  1813. struct intel_output *intel_output = NULL;
  1814. list_for_each_entry(connector,
  1815. &dev->mode_config.connector_list, head) {
  1816. if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
  1817. intel_output = to_intel_output(connector);
  1818. break;
  1819. }
  1820. }
  1821. return intel_output;
  1822. }
  1823. static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
  1824. struct i2c_msg msgs[], int num)
  1825. {
  1826. struct intel_output *intel_output;
  1827. struct intel_sdvo_priv *sdvo_priv;
  1828. struct i2c_algo_bit_data *algo_data;
  1829. const struct i2c_algorithm *algo;
  1830. algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
  1831. intel_output =
  1832. intel_sdvo_chan_to_intel_output(
  1833. (struct intel_i2c_chan *)(algo_data->data));
  1834. if (intel_output == NULL)
  1835. return -EINVAL;
  1836. sdvo_priv = intel_output->dev_priv;
  1837. algo = intel_output->i2c_bus->algo;
  1838. intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
  1839. return algo->master_xfer(i2c_adap, msgs, num);
  1840. }
  1841. static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
  1842. .master_xfer = intel_sdvo_master_xfer,
  1843. };
  1844. static u8
  1845. intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
  1846. {
  1847. struct drm_i915_private *dev_priv = dev->dev_private;
  1848. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1849. if (output_device == SDVOB) {
  1850. my_mapping = &dev_priv->sdvo_mappings[0];
  1851. other_mapping = &dev_priv->sdvo_mappings[1];
  1852. } else {
  1853. my_mapping = &dev_priv->sdvo_mappings[1];
  1854. other_mapping = &dev_priv->sdvo_mappings[0];
  1855. }
  1856. /* If the BIOS described our SDVO device, take advantage of it. */
  1857. if (my_mapping->slave_addr)
  1858. return my_mapping->slave_addr;
  1859. /* If the BIOS only described a different SDVO device, use the
  1860. * address that it isn't using.
  1861. */
  1862. if (other_mapping->slave_addr) {
  1863. if (other_mapping->slave_addr == 0x70)
  1864. return 0x72;
  1865. else
  1866. return 0x70;
  1867. }
  1868. /* No SDVO device info is found for another DVO port,
  1869. * so use mapping assumption we had before BIOS parsing.
  1870. */
  1871. if (output_device == SDVOB)
  1872. return 0x70;
  1873. else
  1874. return 0x72;
  1875. }
  1876. static bool
  1877. intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
  1878. {
  1879. struct drm_connector *connector = &intel_output->base;
  1880. struct drm_encoder *encoder = &intel_output->enc;
  1881. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1882. bool ret = true, registered = false;
  1883. sdvo_priv->is_tv = false;
  1884. intel_output->needs_tv_clock = false;
  1885. sdvo_priv->is_lvds = false;
  1886. if (device_is_registered(&connector->kdev)) {
  1887. drm_sysfs_connector_remove(connector);
  1888. registered = true;
  1889. }
  1890. if (flags &
  1891. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
  1892. if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
  1893. sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
  1894. else
  1895. sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
  1896. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1897. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1898. if (intel_sdvo_get_supp_encode(intel_output,
  1899. &sdvo_priv->encode) &&
  1900. intel_sdvo_get_digital_encoding_mode(intel_output) &&
  1901. sdvo_priv->is_hdmi) {
  1902. /* enable hdmi encoding mode if supported */
  1903. intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
  1904. intel_sdvo_set_colorimetry(intel_output,
  1905. SDVO_COLORIMETRY_RGB256);
  1906. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1907. intel_output->clone_mask =
  1908. (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1909. (1 << INTEL_ANALOG_CLONE_BIT);
  1910. }
  1911. } else if (flags & SDVO_OUTPUT_SVID0) {
  1912. sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
  1913. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1914. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1915. sdvo_priv->is_tv = true;
  1916. intel_output->needs_tv_clock = true;
  1917. intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1918. } else if (flags & SDVO_OUTPUT_RGB0) {
  1919. sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
  1920. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1921. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1922. intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1923. (1 << INTEL_ANALOG_CLONE_BIT);
  1924. } else if (flags & SDVO_OUTPUT_RGB1) {
  1925. sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
  1926. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1927. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1928. intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1929. (1 << INTEL_ANALOG_CLONE_BIT);
  1930. } else if (flags & SDVO_OUTPUT_LVDS0) {
  1931. sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
  1932. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1933. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1934. sdvo_priv->is_lvds = true;
  1935. intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
  1936. (1 << INTEL_SDVO_LVDS_CLONE_BIT);
  1937. } else if (flags & SDVO_OUTPUT_LVDS1) {
  1938. sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
  1939. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1940. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1941. sdvo_priv->is_lvds = true;
  1942. intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
  1943. (1 << INTEL_SDVO_LVDS_CLONE_BIT);
  1944. } else {
  1945. unsigned char bytes[2];
  1946. sdvo_priv->controlled_output = 0;
  1947. memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
  1948. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1949. SDVO_NAME(sdvo_priv),
  1950. bytes[0], bytes[1]);
  1951. ret = false;
  1952. }
  1953. intel_output->crtc_mask = (1 << 0) | (1 << 1);
  1954. if (ret && registered)
  1955. ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
  1956. return ret;
  1957. }
  1958. static void intel_sdvo_tv_create_property(struct drm_connector *connector)
  1959. {
  1960. struct intel_output *intel_output = to_intel_output(connector);
  1961. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1962. struct intel_sdvo_tv_format format;
  1963. uint32_t format_map, i;
  1964. uint8_t status;
  1965. intel_sdvo_set_target_output(intel_output,
  1966. sdvo_priv->controlled_output);
  1967. intel_sdvo_write_cmd(intel_output,
  1968. SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
  1969. status = intel_sdvo_read_response(intel_output,
  1970. &format, sizeof(format));
  1971. if (status != SDVO_CMD_STATUS_SUCCESS)
  1972. return;
  1973. memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
  1974. sizeof(format_map) : sizeof(format));
  1975. if (format_map == 0)
  1976. return;
  1977. sdvo_priv->format_supported_num = 0;
  1978. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1979. if (format_map & (1 << i)) {
  1980. sdvo_priv->tv_format_supported
  1981. [sdvo_priv->format_supported_num++] =
  1982. tv_format_names[i];
  1983. }
  1984. sdvo_priv->tv_format_property =
  1985. drm_property_create(
  1986. connector->dev, DRM_MODE_PROP_ENUM,
  1987. "mode", sdvo_priv->format_supported_num);
  1988. for (i = 0; i < sdvo_priv->format_supported_num; i++)
  1989. drm_property_add_enum(
  1990. sdvo_priv->tv_format_property, i,
  1991. i, sdvo_priv->tv_format_supported[i]);
  1992. sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
  1993. drm_connector_attach_property(
  1994. connector, sdvo_priv->tv_format_property, 0);
  1995. }
  1996. static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
  1997. {
  1998. struct intel_output *intel_output = to_intel_output(connector);
  1999. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  2000. struct intel_sdvo_enhancements_reply sdvo_data;
  2001. struct drm_device *dev = connector->dev;
  2002. uint8_t status;
  2003. uint16_t response, data_value[2];
  2004. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2005. NULL, 0);
  2006. status = intel_sdvo_read_response(intel_output, &sdvo_data,
  2007. sizeof(sdvo_data));
  2008. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2009. DRM_DEBUG_KMS(" incorrect response is returned\n");
  2010. return;
  2011. }
  2012. response = *((uint16_t *)&sdvo_data);
  2013. if (!response) {
  2014. DRM_DEBUG_KMS("No enhancement is supported\n");
  2015. return;
  2016. }
  2017. if (sdvo_priv->is_tv) {
  2018. /* when horizontal overscan is supported, Add the left/right
  2019. * property
  2020. */
  2021. if (sdvo_data.overscan_h) {
  2022. intel_sdvo_write_cmd(intel_output,
  2023. SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
  2024. status = intel_sdvo_read_response(intel_output,
  2025. &data_value, 4);
  2026. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2027. DRM_DEBUG_KMS("Incorrect SDVO max "
  2028. "h_overscan\n");
  2029. return;
  2030. }
  2031. intel_sdvo_write_cmd(intel_output,
  2032. SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
  2033. status = intel_sdvo_read_response(intel_output,
  2034. &response, 2);
  2035. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2036. DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
  2037. return;
  2038. }
  2039. sdvo_priv->max_hscan = data_value[0];
  2040. sdvo_priv->left_margin = data_value[0] - response;
  2041. sdvo_priv->right_margin = sdvo_priv->left_margin;
  2042. sdvo_priv->left_property =
  2043. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2044. "left_margin", 2);
  2045. sdvo_priv->left_property->values[0] = 0;
  2046. sdvo_priv->left_property->values[1] = data_value[0];
  2047. drm_connector_attach_property(connector,
  2048. sdvo_priv->left_property,
  2049. sdvo_priv->left_margin);
  2050. sdvo_priv->right_property =
  2051. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2052. "right_margin", 2);
  2053. sdvo_priv->right_property->values[0] = 0;
  2054. sdvo_priv->right_property->values[1] = data_value[0];
  2055. drm_connector_attach_property(connector,
  2056. sdvo_priv->right_property,
  2057. sdvo_priv->right_margin);
  2058. DRM_DEBUG_KMS("h_overscan: max %d, "
  2059. "default %d, current %d\n",
  2060. data_value[0], data_value[1], response);
  2061. }
  2062. if (sdvo_data.overscan_v) {
  2063. intel_sdvo_write_cmd(intel_output,
  2064. SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
  2065. status = intel_sdvo_read_response(intel_output,
  2066. &data_value, 4);
  2067. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2068. DRM_DEBUG_KMS("Incorrect SDVO max "
  2069. "v_overscan\n");
  2070. return;
  2071. }
  2072. intel_sdvo_write_cmd(intel_output,
  2073. SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
  2074. status = intel_sdvo_read_response(intel_output,
  2075. &response, 2);
  2076. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2077. DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
  2078. return;
  2079. }
  2080. sdvo_priv->max_vscan = data_value[0];
  2081. sdvo_priv->top_margin = data_value[0] - response;
  2082. sdvo_priv->bottom_margin = sdvo_priv->top_margin;
  2083. sdvo_priv->top_property =
  2084. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2085. "top_margin", 2);
  2086. sdvo_priv->top_property->values[0] = 0;
  2087. sdvo_priv->top_property->values[1] = data_value[0];
  2088. drm_connector_attach_property(connector,
  2089. sdvo_priv->top_property,
  2090. sdvo_priv->top_margin);
  2091. sdvo_priv->bottom_property =
  2092. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2093. "bottom_margin", 2);
  2094. sdvo_priv->bottom_property->values[0] = 0;
  2095. sdvo_priv->bottom_property->values[1] = data_value[0];
  2096. drm_connector_attach_property(connector,
  2097. sdvo_priv->bottom_property,
  2098. sdvo_priv->bottom_margin);
  2099. DRM_DEBUG_KMS("v_overscan: max %d, "
  2100. "default %d, current %d\n",
  2101. data_value[0], data_value[1], response);
  2102. }
  2103. if (sdvo_data.position_h) {
  2104. intel_sdvo_write_cmd(intel_output,
  2105. SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
  2106. status = intel_sdvo_read_response(intel_output,
  2107. &data_value, 4);
  2108. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2109. DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
  2110. return;
  2111. }
  2112. intel_sdvo_write_cmd(intel_output,
  2113. SDVO_CMD_GET_POSITION_H, NULL, 0);
  2114. status = intel_sdvo_read_response(intel_output,
  2115. &response, 2);
  2116. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2117. DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
  2118. return;
  2119. }
  2120. sdvo_priv->max_hpos = data_value[0];
  2121. sdvo_priv->cur_hpos = response;
  2122. sdvo_priv->hpos_property =
  2123. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2124. "hpos", 2);
  2125. sdvo_priv->hpos_property->values[0] = 0;
  2126. sdvo_priv->hpos_property->values[1] = data_value[0];
  2127. drm_connector_attach_property(connector,
  2128. sdvo_priv->hpos_property,
  2129. sdvo_priv->cur_hpos);
  2130. DRM_DEBUG_KMS("h_position: max %d, "
  2131. "default %d, current %d\n",
  2132. data_value[0], data_value[1], response);
  2133. }
  2134. if (sdvo_data.position_v) {
  2135. intel_sdvo_write_cmd(intel_output,
  2136. SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
  2137. status = intel_sdvo_read_response(intel_output,
  2138. &data_value, 4);
  2139. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2140. DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
  2141. return;
  2142. }
  2143. intel_sdvo_write_cmd(intel_output,
  2144. SDVO_CMD_GET_POSITION_V, NULL, 0);
  2145. status = intel_sdvo_read_response(intel_output,
  2146. &response, 2);
  2147. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2148. DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
  2149. return;
  2150. }
  2151. sdvo_priv->max_vpos = data_value[0];
  2152. sdvo_priv->cur_vpos = response;
  2153. sdvo_priv->vpos_property =
  2154. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2155. "vpos", 2);
  2156. sdvo_priv->vpos_property->values[0] = 0;
  2157. sdvo_priv->vpos_property->values[1] = data_value[0];
  2158. drm_connector_attach_property(connector,
  2159. sdvo_priv->vpos_property,
  2160. sdvo_priv->cur_vpos);
  2161. DRM_DEBUG_KMS("v_position: max %d, "
  2162. "default %d, current %d\n",
  2163. data_value[0], data_value[1], response);
  2164. }
  2165. }
  2166. if (sdvo_priv->is_tv) {
  2167. if (sdvo_data.saturation) {
  2168. intel_sdvo_write_cmd(intel_output,
  2169. SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
  2170. status = intel_sdvo_read_response(intel_output,
  2171. &data_value, 4);
  2172. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2173. DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
  2174. return;
  2175. }
  2176. intel_sdvo_write_cmd(intel_output,
  2177. SDVO_CMD_GET_SATURATION, NULL, 0);
  2178. status = intel_sdvo_read_response(intel_output,
  2179. &response, 2);
  2180. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2181. DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
  2182. return;
  2183. }
  2184. sdvo_priv->max_saturation = data_value[0];
  2185. sdvo_priv->cur_saturation = response;
  2186. sdvo_priv->saturation_property =
  2187. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2188. "saturation", 2);
  2189. sdvo_priv->saturation_property->values[0] = 0;
  2190. sdvo_priv->saturation_property->values[1] =
  2191. data_value[0];
  2192. drm_connector_attach_property(connector,
  2193. sdvo_priv->saturation_property,
  2194. sdvo_priv->cur_saturation);
  2195. DRM_DEBUG_KMS("saturation: max %d, "
  2196. "default %d, current %d\n",
  2197. data_value[0], data_value[1], response);
  2198. }
  2199. if (sdvo_data.contrast) {
  2200. intel_sdvo_write_cmd(intel_output,
  2201. SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
  2202. status = intel_sdvo_read_response(intel_output,
  2203. &data_value, 4);
  2204. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2205. DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
  2206. return;
  2207. }
  2208. intel_sdvo_write_cmd(intel_output,
  2209. SDVO_CMD_GET_CONTRAST, NULL, 0);
  2210. status = intel_sdvo_read_response(intel_output,
  2211. &response, 2);
  2212. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2213. DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
  2214. return;
  2215. }
  2216. sdvo_priv->max_contrast = data_value[0];
  2217. sdvo_priv->cur_contrast = response;
  2218. sdvo_priv->contrast_property =
  2219. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2220. "contrast", 2);
  2221. sdvo_priv->contrast_property->values[0] = 0;
  2222. sdvo_priv->contrast_property->values[1] = data_value[0];
  2223. drm_connector_attach_property(connector,
  2224. sdvo_priv->contrast_property,
  2225. sdvo_priv->cur_contrast);
  2226. DRM_DEBUG_KMS("contrast: max %d, "
  2227. "default %d, current %d\n",
  2228. data_value[0], data_value[1], response);
  2229. }
  2230. if (sdvo_data.hue) {
  2231. intel_sdvo_write_cmd(intel_output,
  2232. SDVO_CMD_GET_MAX_HUE, NULL, 0);
  2233. status = intel_sdvo_read_response(intel_output,
  2234. &data_value, 4);
  2235. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2236. DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
  2237. return;
  2238. }
  2239. intel_sdvo_write_cmd(intel_output,
  2240. SDVO_CMD_GET_HUE, NULL, 0);
  2241. status = intel_sdvo_read_response(intel_output,
  2242. &response, 2);
  2243. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2244. DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
  2245. return;
  2246. }
  2247. sdvo_priv->max_hue = data_value[0];
  2248. sdvo_priv->cur_hue = response;
  2249. sdvo_priv->hue_property =
  2250. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2251. "hue", 2);
  2252. sdvo_priv->hue_property->values[0] = 0;
  2253. sdvo_priv->hue_property->values[1] =
  2254. data_value[0];
  2255. drm_connector_attach_property(connector,
  2256. sdvo_priv->hue_property,
  2257. sdvo_priv->cur_hue);
  2258. DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
  2259. data_value[0], data_value[1], response);
  2260. }
  2261. }
  2262. if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
  2263. if (sdvo_data.brightness) {
  2264. intel_sdvo_write_cmd(intel_output,
  2265. SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
  2266. status = intel_sdvo_read_response(intel_output,
  2267. &data_value, 4);
  2268. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2269. DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
  2270. return;
  2271. }
  2272. intel_sdvo_write_cmd(intel_output,
  2273. SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
  2274. status = intel_sdvo_read_response(intel_output,
  2275. &response, 2);
  2276. if (status != SDVO_CMD_STATUS_SUCCESS) {
  2277. DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
  2278. return;
  2279. }
  2280. sdvo_priv->max_brightness = data_value[0];
  2281. sdvo_priv->cur_brightness = response;
  2282. sdvo_priv->brightness_property =
  2283. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2284. "brightness", 2);
  2285. sdvo_priv->brightness_property->values[0] = 0;
  2286. sdvo_priv->brightness_property->values[1] =
  2287. data_value[0];
  2288. drm_connector_attach_property(connector,
  2289. sdvo_priv->brightness_property,
  2290. sdvo_priv->cur_brightness);
  2291. DRM_DEBUG_KMS("brightness: max %d, "
  2292. "default %d, current %d\n",
  2293. data_value[0], data_value[1], response);
  2294. }
  2295. }
  2296. return;
  2297. }
  2298. bool intel_sdvo_init(struct drm_device *dev, int output_device)
  2299. {
  2300. struct drm_connector *connector;
  2301. struct intel_output *intel_output;
  2302. struct intel_sdvo_priv *sdvo_priv;
  2303. u8 ch[0x40];
  2304. int i;
  2305. intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
  2306. if (!intel_output) {
  2307. return false;
  2308. }
  2309. sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
  2310. sdvo_priv->output_device = output_device;
  2311. intel_output->dev_priv = sdvo_priv;
  2312. intel_output->type = INTEL_OUTPUT_SDVO;
  2313. /* setup the DDC bus. */
  2314. if (output_device == SDVOB)
  2315. intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
  2316. else
  2317. intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
  2318. if (!intel_output->i2c_bus)
  2319. goto err_inteloutput;
  2320. sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
  2321. /* Save the bit-banging i2c functionality for use by the DDC wrapper */
  2322. intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
  2323. /* Read the regs to test if we can talk to the device */
  2324. for (i = 0; i < 0x40; i++) {
  2325. if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
  2326. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2327. output_device == SDVOB ? 'B' : 'C');
  2328. goto err_i2c;
  2329. }
  2330. }
  2331. /* setup the DDC bus. */
  2332. if (output_device == SDVOB) {
  2333. intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
  2334. sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
  2335. "SDVOB/VGA DDC BUS");
  2336. } else {
  2337. intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
  2338. sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
  2339. "SDVOC/VGA DDC BUS");
  2340. }
  2341. if (intel_output->ddc_bus == NULL)
  2342. goto err_i2c;
  2343. /* Wrap with our custom algo which switches to DDC mode */
  2344. intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
  2345. /* In defaut case sdvo lvds is false */
  2346. intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
  2347. if (intel_sdvo_output_setup(intel_output,
  2348. sdvo_priv->caps.output_flags) != true) {
  2349. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2350. output_device == SDVOB ? 'B' : 'C');
  2351. goto err_i2c;
  2352. }
  2353. connector = &intel_output->base;
  2354. drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
  2355. connector->connector_type);
  2356. drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
  2357. connector->interlace_allowed = 0;
  2358. connector->doublescan_allowed = 0;
  2359. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  2360. drm_encoder_init(dev, &intel_output->enc,
  2361. &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
  2362. drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
  2363. drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
  2364. if (sdvo_priv->is_tv)
  2365. intel_sdvo_tv_create_property(connector);
  2366. if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
  2367. intel_sdvo_create_enhance_property(connector);
  2368. drm_sysfs_connector_add(connector);
  2369. intel_sdvo_select_ddc_bus(sdvo_priv);
  2370. /* Set the input timing to the screen. Assume always input 0. */
  2371. intel_sdvo_set_target_input(intel_output, true, false);
  2372. intel_sdvo_get_input_pixel_clock_range(intel_output,
  2373. &sdvo_priv->pixel_clock_min,
  2374. &sdvo_priv->pixel_clock_max);
  2375. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2376. "clock range %dMHz - %dMHz, "
  2377. "input 1: %c, input 2: %c, "
  2378. "output 1: %c, output 2: %c\n",
  2379. SDVO_NAME(sdvo_priv),
  2380. sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
  2381. sdvo_priv->caps.device_rev_id,
  2382. sdvo_priv->pixel_clock_min / 1000,
  2383. sdvo_priv->pixel_clock_max / 1000,
  2384. (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2385. (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2386. /* check currently supported outputs */
  2387. sdvo_priv->caps.output_flags &
  2388. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2389. sdvo_priv->caps.output_flags &
  2390. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2391. return true;
  2392. err_i2c:
  2393. if (sdvo_priv->analog_ddc_bus != NULL)
  2394. intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
  2395. if (intel_output->ddc_bus != NULL)
  2396. intel_i2c_destroy(intel_output->ddc_bus);
  2397. if (intel_output->i2c_bus != NULL)
  2398. intel_i2c_destroy(intel_output->i2c_bus);
  2399. err_inteloutput:
  2400. kfree(intel_output);
  2401. return false;
  2402. }