intel_display.c 128 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include "drmP.h"
  31. #include "intel_drv.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include "intel_dp.h"
  35. #include "drm_crtc_helper.h"
  36. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  37. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  38. static void intel_update_watermarks(struct drm_device *dev);
  39. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  40. typedef struct {
  41. /* given values */
  42. int n;
  43. int m1, m2;
  44. int p1, p2;
  45. /* derived values */
  46. int dot;
  47. int vco;
  48. int m;
  49. int p;
  50. } intel_clock_t;
  51. typedef struct {
  52. int min, max;
  53. } intel_range_t;
  54. typedef struct {
  55. int dot_limit;
  56. int p2_slow, p2_fast;
  57. } intel_p2_t;
  58. #define INTEL_P2_NUM 2
  59. typedef struct intel_limit intel_limit_t;
  60. struct intel_limit {
  61. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  62. intel_p2_t p2;
  63. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64. int, int, intel_clock_t *);
  65. bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  66. int, int, intel_clock_t *);
  67. };
  68. #define I8XX_DOT_MIN 25000
  69. #define I8XX_DOT_MAX 350000
  70. #define I8XX_VCO_MIN 930000
  71. #define I8XX_VCO_MAX 1400000
  72. #define I8XX_N_MIN 3
  73. #define I8XX_N_MAX 16
  74. #define I8XX_M_MIN 96
  75. #define I8XX_M_MAX 140
  76. #define I8XX_M1_MIN 18
  77. #define I8XX_M1_MAX 26
  78. #define I8XX_M2_MIN 6
  79. #define I8XX_M2_MAX 16
  80. #define I8XX_P_MIN 4
  81. #define I8XX_P_MAX 128
  82. #define I8XX_P1_MIN 2
  83. #define I8XX_P1_MAX 33
  84. #define I8XX_P1_LVDS_MIN 1
  85. #define I8XX_P1_LVDS_MAX 6
  86. #define I8XX_P2_SLOW 4
  87. #define I8XX_P2_FAST 2
  88. #define I8XX_P2_LVDS_SLOW 14
  89. #define I8XX_P2_LVDS_FAST 7
  90. #define I8XX_P2_SLOW_LIMIT 165000
  91. #define I9XX_DOT_MIN 20000
  92. #define I9XX_DOT_MAX 400000
  93. #define I9XX_VCO_MIN 1400000
  94. #define I9XX_VCO_MAX 2800000
  95. #define IGD_VCO_MIN 1700000
  96. #define IGD_VCO_MAX 3500000
  97. #define I9XX_N_MIN 1
  98. #define I9XX_N_MAX 6
  99. /* IGD's Ncounter is a ring counter */
  100. #define IGD_N_MIN 3
  101. #define IGD_N_MAX 6
  102. #define I9XX_M_MIN 70
  103. #define I9XX_M_MAX 120
  104. #define IGD_M_MIN 2
  105. #define IGD_M_MAX 256
  106. #define I9XX_M1_MIN 10
  107. #define I9XX_M1_MAX 22
  108. #define I9XX_M2_MIN 5
  109. #define I9XX_M2_MAX 9
  110. /* IGD M1 is reserved, and must be 0 */
  111. #define IGD_M1_MIN 0
  112. #define IGD_M1_MAX 0
  113. #define IGD_M2_MIN 0
  114. #define IGD_M2_MAX 254
  115. #define I9XX_P_SDVO_DAC_MIN 5
  116. #define I9XX_P_SDVO_DAC_MAX 80
  117. #define I9XX_P_LVDS_MIN 7
  118. #define I9XX_P_LVDS_MAX 98
  119. #define IGD_P_LVDS_MIN 7
  120. #define IGD_P_LVDS_MAX 112
  121. #define I9XX_P1_MIN 1
  122. #define I9XX_P1_MAX 8
  123. #define I9XX_P2_SDVO_DAC_SLOW 10
  124. #define I9XX_P2_SDVO_DAC_FAST 5
  125. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  126. #define I9XX_P2_LVDS_SLOW 14
  127. #define I9XX_P2_LVDS_FAST 7
  128. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  129. /*The parameter is for SDVO on G4x platform*/
  130. #define G4X_DOT_SDVO_MIN 25000
  131. #define G4X_DOT_SDVO_MAX 270000
  132. #define G4X_VCO_MIN 1750000
  133. #define G4X_VCO_MAX 3500000
  134. #define G4X_N_SDVO_MIN 1
  135. #define G4X_N_SDVO_MAX 4
  136. #define G4X_M_SDVO_MIN 104
  137. #define G4X_M_SDVO_MAX 138
  138. #define G4X_M1_SDVO_MIN 17
  139. #define G4X_M1_SDVO_MAX 23
  140. #define G4X_M2_SDVO_MIN 5
  141. #define G4X_M2_SDVO_MAX 11
  142. #define G4X_P_SDVO_MIN 10
  143. #define G4X_P_SDVO_MAX 30
  144. #define G4X_P1_SDVO_MIN 1
  145. #define G4X_P1_SDVO_MAX 3
  146. #define G4X_P2_SDVO_SLOW 10
  147. #define G4X_P2_SDVO_FAST 10
  148. #define G4X_P2_SDVO_LIMIT 270000
  149. /*The parameter is for HDMI_DAC on G4x platform*/
  150. #define G4X_DOT_HDMI_DAC_MIN 22000
  151. #define G4X_DOT_HDMI_DAC_MAX 400000
  152. #define G4X_N_HDMI_DAC_MIN 1
  153. #define G4X_N_HDMI_DAC_MAX 4
  154. #define G4X_M_HDMI_DAC_MIN 104
  155. #define G4X_M_HDMI_DAC_MAX 138
  156. #define G4X_M1_HDMI_DAC_MIN 16
  157. #define G4X_M1_HDMI_DAC_MAX 23
  158. #define G4X_M2_HDMI_DAC_MIN 5
  159. #define G4X_M2_HDMI_DAC_MAX 11
  160. #define G4X_P_HDMI_DAC_MIN 5
  161. #define G4X_P_HDMI_DAC_MAX 80
  162. #define G4X_P1_HDMI_DAC_MIN 1
  163. #define G4X_P1_HDMI_DAC_MAX 8
  164. #define G4X_P2_HDMI_DAC_SLOW 10
  165. #define G4X_P2_HDMI_DAC_FAST 5
  166. #define G4X_P2_HDMI_DAC_LIMIT 165000
  167. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  168. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  169. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  170. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  171. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  172. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  173. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  174. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  175. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  176. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  177. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  178. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  179. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  180. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  181. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  182. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  183. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  184. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  185. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  186. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  187. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  188. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  189. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  190. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  191. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  192. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  193. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  194. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  195. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  196. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  197. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  198. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  199. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  200. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  201. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  202. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  203. /*The parameter is for DISPLAY PORT on G4x platform*/
  204. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  205. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  206. #define G4X_N_DISPLAY_PORT_MIN 1
  207. #define G4X_N_DISPLAY_PORT_MAX 2
  208. #define G4X_M_DISPLAY_PORT_MIN 97
  209. #define G4X_M_DISPLAY_PORT_MAX 108
  210. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  211. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  212. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  213. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  214. #define G4X_P_DISPLAY_PORT_MIN 10
  215. #define G4X_P_DISPLAY_PORT_MAX 20
  216. #define G4X_P1_DISPLAY_PORT_MIN 1
  217. #define G4X_P1_DISPLAY_PORT_MAX 2
  218. #define G4X_P2_DISPLAY_PORT_SLOW 10
  219. #define G4X_P2_DISPLAY_PORT_FAST 10
  220. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  221. /* IGDNG */
  222. /* as we calculate clock using (register_value + 2) for
  223. N/M1/M2, so here the range value for them is (actual_value-2).
  224. */
  225. #define IGDNG_DOT_MIN 25000
  226. #define IGDNG_DOT_MAX 350000
  227. #define IGDNG_VCO_MIN 1760000
  228. #define IGDNG_VCO_MAX 3510000
  229. #define IGDNG_N_MIN 1
  230. #define IGDNG_N_MAX 5
  231. #define IGDNG_M_MIN 79
  232. #define IGDNG_M_MAX 118
  233. #define IGDNG_M1_MIN 12
  234. #define IGDNG_M1_MAX 23
  235. #define IGDNG_M2_MIN 5
  236. #define IGDNG_M2_MAX 9
  237. #define IGDNG_P_SDVO_DAC_MIN 5
  238. #define IGDNG_P_SDVO_DAC_MAX 80
  239. #define IGDNG_P_LVDS_MIN 28
  240. #define IGDNG_P_LVDS_MAX 112
  241. #define IGDNG_P1_MIN 1
  242. #define IGDNG_P1_MAX 8
  243. #define IGDNG_P2_SDVO_DAC_SLOW 10
  244. #define IGDNG_P2_SDVO_DAC_FAST 5
  245. #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
  246. #define IGDNG_P2_LVDS_FAST 7 /* double channel */
  247. #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
  248. static bool
  249. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  250. int target, int refclk, intel_clock_t *best_clock);
  251. static bool
  252. intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  253. int target, int refclk, intel_clock_t *best_clock);
  254. static bool
  255. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  256. int target, int refclk, intel_clock_t *best_clock);
  257. static bool
  258. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  259. int target, int refclk, intel_clock_t *best_clock);
  260. static bool
  261. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  262. int target, int refclk, intel_clock_t *best_clock);
  263. static bool
  264. intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
  265. int target, int refclk, intel_clock_t *best_clock);
  266. static const intel_limit_t intel_limits_i8xx_dvo = {
  267. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  268. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  269. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  270. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  271. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  272. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  273. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  274. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  275. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  276. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  277. .find_pll = intel_find_best_PLL,
  278. .find_reduced_pll = intel_find_best_reduced_PLL,
  279. };
  280. static const intel_limit_t intel_limits_i8xx_lvds = {
  281. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  282. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  283. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  284. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  285. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  286. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  287. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  288. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  289. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  290. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  291. .find_pll = intel_find_best_PLL,
  292. .find_reduced_pll = intel_find_best_reduced_PLL,
  293. };
  294. static const intel_limit_t intel_limits_i9xx_sdvo = {
  295. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  296. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  297. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  298. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  299. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  300. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  301. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  302. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  303. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  304. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  305. .find_pll = intel_find_best_PLL,
  306. .find_reduced_pll = intel_find_best_reduced_PLL,
  307. };
  308. static const intel_limit_t intel_limits_i9xx_lvds = {
  309. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  310. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  311. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  312. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  313. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  314. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  315. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  316. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  317. /* The single-channel range is 25-112Mhz, and dual-channel
  318. * is 80-224Mhz. Prefer single channel as much as possible.
  319. */
  320. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  321. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  322. .find_pll = intel_find_best_PLL,
  323. .find_reduced_pll = intel_find_best_reduced_PLL,
  324. };
  325. /* below parameter and function is for G4X Chipset Family*/
  326. static const intel_limit_t intel_limits_g4x_sdvo = {
  327. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  328. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  329. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  330. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  331. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  332. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  333. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  334. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  335. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  336. .p2_slow = G4X_P2_SDVO_SLOW,
  337. .p2_fast = G4X_P2_SDVO_FAST
  338. },
  339. .find_pll = intel_g4x_find_best_PLL,
  340. .find_reduced_pll = intel_g4x_find_best_PLL,
  341. };
  342. static const intel_limit_t intel_limits_g4x_hdmi = {
  343. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  344. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  345. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  346. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  347. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  348. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  349. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  350. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  351. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  352. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  353. .p2_fast = G4X_P2_HDMI_DAC_FAST
  354. },
  355. .find_pll = intel_g4x_find_best_PLL,
  356. .find_reduced_pll = intel_g4x_find_best_PLL,
  357. };
  358. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  359. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  360. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  361. .vco = { .min = G4X_VCO_MIN,
  362. .max = G4X_VCO_MAX },
  363. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  364. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  365. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  366. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  367. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  368. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  369. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  370. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  371. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  372. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  373. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  374. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  375. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  376. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  377. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  378. },
  379. .find_pll = intel_g4x_find_best_PLL,
  380. .find_reduced_pll = intel_g4x_find_best_PLL,
  381. };
  382. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  383. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  384. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  385. .vco = { .min = G4X_VCO_MIN,
  386. .max = G4X_VCO_MAX },
  387. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  388. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  389. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  390. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  391. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  392. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  393. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  394. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  395. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  396. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  397. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  398. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  399. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  400. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  401. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  402. },
  403. .find_pll = intel_g4x_find_best_PLL,
  404. .find_reduced_pll = intel_g4x_find_best_PLL,
  405. };
  406. static const intel_limit_t intel_limits_g4x_display_port = {
  407. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  408. .max = G4X_DOT_DISPLAY_PORT_MAX },
  409. .vco = { .min = G4X_VCO_MIN,
  410. .max = G4X_VCO_MAX},
  411. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  412. .max = G4X_N_DISPLAY_PORT_MAX },
  413. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  414. .max = G4X_M_DISPLAY_PORT_MAX },
  415. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  416. .max = G4X_M1_DISPLAY_PORT_MAX },
  417. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  418. .max = G4X_M2_DISPLAY_PORT_MAX },
  419. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  420. .max = G4X_P_DISPLAY_PORT_MAX },
  421. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  422. .max = G4X_P1_DISPLAY_PORT_MAX},
  423. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  424. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  425. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  426. .find_pll = intel_find_pll_g4x_dp,
  427. };
  428. static const intel_limit_t intel_limits_igd_sdvo = {
  429. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  430. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  431. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  432. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  433. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  434. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  435. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  436. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  437. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  438. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  439. .find_pll = intel_find_best_PLL,
  440. .find_reduced_pll = intel_find_best_reduced_PLL,
  441. };
  442. static const intel_limit_t intel_limits_igd_lvds = {
  443. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  444. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  445. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  446. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  447. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  448. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  449. .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
  450. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  451. /* IGD only supports single-channel mode. */
  452. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  453. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  454. .find_pll = intel_find_best_PLL,
  455. .find_reduced_pll = intel_find_best_reduced_PLL,
  456. };
  457. static const intel_limit_t intel_limits_igdng_sdvo = {
  458. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  459. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  460. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  461. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  462. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  463. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  464. .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
  465. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  466. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  467. .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
  468. .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
  469. .find_pll = intel_igdng_find_best_PLL,
  470. };
  471. static const intel_limit_t intel_limits_igdng_lvds = {
  472. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  473. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  474. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  475. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  476. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  477. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  478. .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
  479. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  480. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  481. .p2_slow = IGDNG_P2_LVDS_SLOW,
  482. .p2_fast = IGDNG_P2_LVDS_FAST },
  483. .find_pll = intel_igdng_find_best_PLL,
  484. };
  485. static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
  486. {
  487. const intel_limit_t *limit;
  488. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  489. limit = &intel_limits_igdng_lvds;
  490. else
  491. limit = &intel_limits_igdng_sdvo;
  492. return limit;
  493. }
  494. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  495. {
  496. struct drm_device *dev = crtc->dev;
  497. struct drm_i915_private *dev_priv = dev->dev_private;
  498. const intel_limit_t *limit;
  499. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  500. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  501. LVDS_CLKB_POWER_UP)
  502. /* LVDS with dual channel */
  503. limit = &intel_limits_g4x_dual_channel_lvds;
  504. else
  505. /* LVDS with dual channel */
  506. limit = &intel_limits_g4x_single_channel_lvds;
  507. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  508. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  509. limit = &intel_limits_g4x_hdmi;
  510. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  511. limit = &intel_limits_g4x_sdvo;
  512. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  513. limit = &intel_limits_g4x_display_port;
  514. } else /* The option is for other outputs */
  515. limit = &intel_limits_i9xx_sdvo;
  516. return limit;
  517. }
  518. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  519. {
  520. struct drm_device *dev = crtc->dev;
  521. const intel_limit_t *limit;
  522. if (IS_IGDNG(dev))
  523. limit = intel_igdng_limit(crtc);
  524. else if (IS_G4X(dev)) {
  525. limit = intel_g4x_limit(crtc);
  526. } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
  527. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  528. limit = &intel_limits_i9xx_lvds;
  529. else
  530. limit = &intel_limits_i9xx_sdvo;
  531. } else if (IS_IGD(dev)) {
  532. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  533. limit = &intel_limits_igd_lvds;
  534. else
  535. limit = &intel_limits_igd_sdvo;
  536. } else {
  537. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  538. limit = &intel_limits_i8xx_lvds;
  539. else
  540. limit = &intel_limits_i8xx_dvo;
  541. }
  542. return limit;
  543. }
  544. /* m1 is reserved as 0 in IGD, n is a ring counter */
  545. static void igd_clock(int refclk, intel_clock_t *clock)
  546. {
  547. clock->m = clock->m2 + 2;
  548. clock->p = clock->p1 * clock->p2;
  549. clock->vco = refclk * clock->m / clock->n;
  550. clock->dot = clock->vco / clock->p;
  551. }
  552. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  553. {
  554. if (IS_IGD(dev)) {
  555. igd_clock(refclk, clock);
  556. return;
  557. }
  558. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  559. clock->p = clock->p1 * clock->p2;
  560. clock->vco = refclk * clock->m / (clock->n + 2);
  561. clock->dot = clock->vco / clock->p;
  562. }
  563. /**
  564. * Returns whether any output on the specified pipe is of the specified type
  565. */
  566. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  567. {
  568. struct drm_device *dev = crtc->dev;
  569. struct drm_mode_config *mode_config = &dev->mode_config;
  570. struct drm_connector *l_entry;
  571. list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  572. if (l_entry->encoder &&
  573. l_entry->encoder->crtc == crtc) {
  574. struct intel_output *intel_output = to_intel_output(l_entry);
  575. if (intel_output->type == type)
  576. return true;
  577. }
  578. }
  579. return false;
  580. }
  581. struct drm_connector *
  582. intel_pipe_get_output (struct drm_crtc *crtc)
  583. {
  584. struct drm_device *dev = crtc->dev;
  585. struct drm_mode_config *mode_config = &dev->mode_config;
  586. struct drm_connector *l_entry, *ret = NULL;
  587. list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  588. if (l_entry->encoder &&
  589. l_entry->encoder->crtc == crtc) {
  590. ret = l_entry;
  591. break;
  592. }
  593. }
  594. return ret;
  595. }
  596. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  597. /**
  598. * Returns whether the given set of divisors are valid for a given refclk with
  599. * the given connectors.
  600. */
  601. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  602. {
  603. const intel_limit_t *limit = intel_limit (crtc);
  604. struct drm_device *dev = crtc->dev;
  605. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  606. INTELPllInvalid ("p1 out of range\n");
  607. if (clock->p < limit->p.min || limit->p.max < clock->p)
  608. INTELPllInvalid ("p out of range\n");
  609. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  610. INTELPllInvalid ("m2 out of range\n");
  611. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  612. INTELPllInvalid ("m1 out of range\n");
  613. if (clock->m1 <= clock->m2 && !IS_IGD(dev))
  614. INTELPllInvalid ("m1 <= m2\n");
  615. if (clock->m < limit->m.min || limit->m.max < clock->m)
  616. INTELPllInvalid ("m out of range\n");
  617. if (clock->n < limit->n.min || limit->n.max < clock->n)
  618. INTELPllInvalid ("n out of range\n");
  619. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  620. INTELPllInvalid ("vco out of range\n");
  621. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  622. * connector, etc., rather than just a single range.
  623. */
  624. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  625. INTELPllInvalid ("dot out of range\n");
  626. return true;
  627. }
  628. static bool
  629. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  630. int target, int refclk, intel_clock_t *best_clock)
  631. {
  632. struct drm_device *dev = crtc->dev;
  633. struct drm_i915_private *dev_priv = dev->dev_private;
  634. intel_clock_t clock;
  635. int err = target;
  636. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  637. (I915_READ(LVDS)) != 0) {
  638. /*
  639. * For LVDS, if the panel is on, just rely on its current
  640. * settings for dual-channel. We haven't figured out how to
  641. * reliably set up different single/dual channel state, if we
  642. * even can.
  643. */
  644. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  645. LVDS_CLKB_POWER_UP)
  646. clock.p2 = limit->p2.p2_fast;
  647. else
  648. clock.p2 = limit->p2.p2_slow;
  649. } else {
  650. if (target < limit->p2.dot_limit)
  651. clock.p2 = limit->p2.p2_slow;
  652. else
  653. clock.p2 = limit->p2.p2_fast;
  654. }
  655. memset (best_clock, 0, sizeof (*best_clock));
  656. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  657. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  658. clock.m1++) {
  659. for (clock.m2 = limit->m2.min;
  660. clock.m2 <= limit->m2.max; clock.m2++) {
  661. /* m1 is always 0 in IGD */
  662. if (clock.m2 >= clock.m1 && !IS_IGD(dev))
  663. break;
  664. for (clock.n = limit->n.min;
  665. clock.n <= limit->n.max; clock.n++) {
  666. int this_err;
  667. intel_clock(dev, refclk, &clock);
  668. if (!intel_PLL_is_valid(crtc, &clock))
  669. continue;
  670. this_err = abs(clock.dot - target);
  671. if (this_err < err) {
  672. *best_clock = clock;
  673. err = this_err;
  674. }
  675. }
  676. }
  677. }
  678. }
  679. return (err != target);
  680. }
  681. static bool
  682. intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  683. int target, int refclk, intel_clock_t *best_clock)
  684. {
  685. struct drm_device *dev = crtc->dev;
  686. intel_clock_t clock;
  687. int err = target;
  688. bool found = false;
  689. memcpy(&clock, best_clock, sizeof(intel_clock_t));
  690. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  691. for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
  692. /* m1 is always 0 in IGD */
  693. if (clock.m2 >= clock.m1 && !IS_IGD(dev))
  694. break;
  695. for (clock.n = limit->n.min; clock.n <= limit->n.max;
  696. clock.n++) {
  697. int this_err;
  698. intel_clock(dev, refclk, &clock);
  699. if (!intel_PLL_is_valid(crtc, &clock))
  700. continue;
  701. this_err = abs(clock.dot - target);
  702. if (this_err < err) {
  703. *best_clock = clock;
  704. err = this_err;
  705. found = true;
  706. }
  707. }
  708. }
  709. }
  710. return found;
  711. }
  712. static bool
  713. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  714. int target, int refclk, intel_clock_t *best_clock)
  715. {
  716. struct drm_device *dev = crtc->dev;
  717. struct drm_i915_private *dev_priv = dev->dev_private;
  718. intel_clock_t clock;
  719. int max_n;
  720. bool found;
  721. /* approximately equals target * 0.00488 */
  722. int err_most = (target >> 8) + (target >> 10);
  723. found = false;
  724. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  725. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  726. LVDS_CLKB_POWER_UP)
  727. clock.p2 = limit->p2.p2_fast;
  728. else
  729. clock.p2 = limit->p2.p2_slow;
  730. } else {
  731. if (target < limit->p2.dot_limit)
  732. clock.p2 = limit->p2.p2_slow;
  733. else
  734. clock.p2 = limit->p2.p2_fast;
  735. }
  736. memset(best_clock, 0, sizeof(*best_clock));
  737. max_n = limit->n.max;
  738. /* based on hardware requriment prefer smaller n to precision */
  739. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  740. /* based on hardware requirment prefere larger m1,m2 */
  741. for (clock.m1 = limit->m1.max;
  742. clock.m1 >= limit->m1.min; clock.m1--) {
  743. for (clock.m2 = limit->m2.max;
  744. clock.m2 >= limit->m2.min; clock.m2--) {
  745. for (clock.p1 = limit->p1.max;
  746. clock.p1 >= limit->p1.min; clock.p1--) {
  747. int this_err;
  748. intel_clock(dev, refclk, &clock);
  749. if (!intel_PLL_is_valid(crtc, &clock))
  750. continue;
  751. this_err = abs(clock.dot - target) ;
  752. if (this_err < err_most) {
  753. *best_clock = clock;
  754. err_most = this_err;
  755. max_n = clock.n;
  756. found = true;
  757. }
  758. }
  759. }
  760. }
  761. }
  762. return found;
  763. }
  764. static bool
  765. intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  766. int target, int refclk, intel_clock_t *best_clock)
  767. {
  768. struct drm_device *dev = crtc->dev;
  769. intel_clock_t clock;
  770. if (target < 200000) {
  771. clock.n = 1;
  772. clock.p1 = 2;
  773. clock.p2 = 10;
  774. clock.m1 = 12;
  775. clock.m2 = 9;
  776. } else {
  777. clock.n = 2;
  778. clock.p1 = 1;
  779. clock.p2 = 10;
  780. clock.m1 = 14;
  781. clock.m2 = 8;
  782. }
  783. intel_clock(dev, refclk, &clock);
  784. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  785. return true;
  786. }
  787. static bool
  788. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  789. int target, int refclk, intel_clock_t *best_clock)
  790. {
  791. struct drm_device *dev = crtc->dev;
  792. struct drm_i915_private *dev_priv = dev->dev_private;
  793. intel_clock_t clock;
  794. int max_n;
  795. bool found;
  796. int err_most = 47;
  797. found = false;
  798. /* eDP has only 2 clock choice, no n/m/p setting */
  799. if (HAS_eDP)
  800. return true;
  801. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  802. return intel_find_pll_igdng_dp(limit, crtc, target,
  803. refclk, best_clock);
  804. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  805. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  806. LVDS_CLKB_POWER_UP)
  807. clock.p2 = limit->p2.p2_fast;
  808. else
  809. clock.p2 = limit->p2.p2_slow;
  810. } else {
  811. if (target < limit->p2.dot_limit)
  812. clock.p2 = limit->p2.p2_slow;
  813. else
  814. clock.p2 = limit->p2.p2_fast;
  815. }
  816. memset(best_clock, 0, sizeof(*best_clock));
  817. max_n = limit->n.max;
  818. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  819. /* based on hardware requriment prefer smaller n to precision */
  820. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  821. /* based on hardware requirment prefere larger m1,m2 */
  822. for (clock.m1 = limit->m1.max;
  823. clock.m1 >= limit->m1.min; clock.m1--) {
  824. for (clock.m2 = limit->m2.max;
  825. clock.m2 >= limit->m2.min; clock.m2--) {
  826. int this_err;
  827. intel_clock(dev, refclk, &clock);
  828. if (!intel_PLL_is_valid(crtc, &clock))
  829. continue;
  830. this_err = abs((10000 - (target*10000/clock.dot)));
  831. if (this_err < err_most) {
  832. *best_clock = clock;
  833. err_most = this_err;
  834. max_n = clock.n;
  835. found = true;
  836. /* found on first matching */
  837. goto out;
  838. }
  839. }
  840. }
  841. }
  842. }
  843. out:
  844. return found;
  845. }
  846. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  847. static bool
  848. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  849. int target, int refclk, intel_clock_t *best_clock)
  850. {
  851. intel_clock_t clock;
  852. if (target < 200000) {
  853. clock.p1 = 2;
  854. clock.p2 = 10;
  855. clock.n = 2;
  856. clock.m1 = 23;
  857. clock.m2 = 8;
  858. } else {
  859. clock.p1 = 1;
  860. clock.p2 = 10;
  861. clock.n = 1;
  862. clock.m1 = 14;
  863. clock.m2 = 2;
  864. }
  865. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  866. clock.p = (clock.p1 * clock.p2);
  867. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  868. clock.vco = 0;
  869. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  870. return true;
  871. }
  872. void
  873. intel_wait_for_vblank(struct drm_device *dev)
  874. {
  875. /* Wait for 20ms, i.e. one cycle at 50hz. */
  876. mdelay(20);
  877. }
  878. /* Parameters have changed, update FBC info */
  879. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  880. {
  881. struct drm_device *dev = crtc->dev;
  882. struct drm_i915_private *dev_priv = dev->dev_private;
  883. struct drm_framebuffer *fb = crtc->fb;
  884. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  885. struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
  886. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  887. int plane, i;
  888. u32 fbc_ctl, fbc_ctl2;
  889. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  890. if (fb->pitch < dev_priv->cfb_pitch)
  891. dev_priv->cfb_pitch = fb->pitch;
  892. /* FBC_CTL wants 64B units */
  893. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  894. dev_priv->cfb_fence = obj_priv->fence_reg;
  895. dev_priv->cfb_plane = intel_crtc->plane;
  896. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  897. /* Clear old tags */
  898. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  899. I915_WRITE(FBC_TAG + (i * 4), 0);
  900. /* Set it up... */
  901. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  902. if (obj_priv->tiling_mode != I915_TILING_NONE)
  903. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  904. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  905. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  906. /* enable it... */
  907. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  908. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  909. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  910. if (obj_priv->tiling_mode != I915_TILING_NONE)
  911. fbc_ctl |= dev_priv->cfb_fence;
  912. I915_WRITE(FBC_CONTROL, fbc_ctl);
  913. DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  914. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  915. }
  916. void i8xx_disable_fbc(struct drm_device *dev)
  917. {
  918. struct drm_i915_private *dev_priv = dev->dev_private;
  919. u32 fbc_ctl;
  920. if (!I915_HAS_FBC(dev))
  921. return;
  922. /* Disable compression */
  923. fbc_ctl = I915_READ(FBC_CONTROL);
  924. fbc_ctl &= ~FBC_CTL_EN;
  925. I915_WRITE(FBC_CONTROL, fbc_ctl);
  926. /* Wait for compressing bit to clear */
  927. while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
  928. ; /* nothing */
  929. intel_wait_for_vblank(dev);
  930. DRM_DEBUG("disabled FBC\n");
  931. }
  932. static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
  933. {
  934. struct drm_device *dev = crtc->dev;
  935. struct drm_i915_private *dev_priv = dev->dev_private;
  936. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  937. }
  938. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  939. {
  940. struct drm_device *dev = crtc->dev;
  941. struct drm_i915_private *dev_priv = dev->dev_private;
  942. struct drm_framebuffer *fb = crtc->fb;
  943. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  944. struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
  945. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  946. int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
  947. DPFC_CTL_PLANEB);
  948. unsigned long stall_watermark = 200;
  949. u32 dpfc_ctl;
  950. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  951. dev_priv->cfb_fence = obj_priv->fence_reg;
  952. dev_priv->cfb_plane = intel_crtc->plane;
  953. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  954. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  955. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  956. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  957. } else {
  958. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  959. }
  960. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  961. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  962. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  963. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  964. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  965. /* enable it... */
  966. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  967. DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
  968. }
  969. void g4x_disable_fbc(struct drm_device *dev)
  970. {
  971. struct drm_i915_private *dev_priv = dev->dev_private;
  972. u32 dpfc_ctl;
  973. /* Disable compression */
  974. dpfc_ctl = I915_READ(DPFC_CONTROL);
  975. dpfc_ctl &= ~DPFC_CTL_EN;
  976. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  977. intel_wait_for_vblank(dev);
  978. DRM_DEBUG("disabled FBC\n");
  979. }
  980. static bool g4x_fbc_enabled(struct drm_crtc *crtc)
  981. {
  982. struct drm_device *dev = crtc->dev;
  983. struct drm_i915_private *dev_priv = dev->dev_private;
  984. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  985. }
  986. /**
  987. * intel_update_fbc - enable/disable FBC as needed
  988. * @crtc: CRTC to point the compressor at
  989. * @mode: mode in use
  990. *
  991. * Set up the framebuffer compression hardware at mode set time. We
  992. * enable it if possible:
  993. * - plane A only (on pre-965)
  994. * - no pixel mulitply/line duplication
  995. * - no alpha buffer discard
  996. * - no dual wide
  997. * - framebuffer <= 2048 in width, 1536 in height
  998. *
  999. * We can't assume that any compression will take place (worst case),
  1000. * so the compressed buffer has to be the same size as the uncompressed
  1001. * one. It also must reside (along with the line length buffer) in
  1002. * stolen memory.
  1003. *
  1004. * We need to enable/disable FBC on a global basis.
  1005. */
  1006. static void intel_update_fbc(struct drm_crtc *crtc,
  1007. struct drm_display_mode *mode)
  1008. {
  1009. struct drm_device *dev = crtc->dev;
  1010. struct drm_i915_private *dev_priv = dev->dev_private;
  1011. struct drm_framebuffer *fb = crtc->fb;
  1012. struct intel_framebuffer *intel_fb;
  1013. struct drm_i915_gem_object *obj_priv;
  1014. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1015. int plane = intel_crtc->plane;
  1016. if (!i915_powersave)
  1017. return;
  1018. if (!dev_priv->display.fbc_enabled ||
  1019. !dev_priv->display.enable_fbc ||
  1020. !dev_priv->display.disable_fbc)
  1021. return;
  1022. if (!crtc->fb)
  1023. return;
  1024. intel_fb = to_intel_framebuffer(fb);
  1025. obj_priv = intel_fb->obj->driver_private;
  1026. /*
  1027. * If FBC is already on, we just have to verify that we can
  1028. * keep it that way...
  1029. * Need to disable if:
  1030. * - changing FBC params (stride, fence, mode)
  1031. * - new fb is too large to fit in compressed buffer
  1032. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1033. */
  1034. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1035. DRM_DEBUG("framebuffer too large, disabling compression\n");
  1036. goto out_disable;
  1037. }
  1038. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  1039. (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
  1040. DRM_DEBUG("mode incompatible with compression, disabling\n");
  1041. goto out_disable;
  1042. }
  1043. if ((mode->hdisplay > 2048) ||
  1044. (mode->vdisplay > 1536)) {
  1045. DRM_DEBUG("mode too large for compression, disabling\n");
  1046. goto out_disable;
  1047. }
  1048. if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
  1049. DRM_DEBUG("plane not 0, disabling compression\n");
  1050. goto out_disable;
  1051. }
  1052. if (obj_priv->tiling_mode != I915_TILING_X) {
  1053. DRM_DEBUG("framebuffer not tiled, disabling compression\n");
  1054. goto out_disable;
  1055. }
  1056. if (dev_priv->display.fbc_enabled(crtc)) {
  1057. /* We can re-enable it in this case, but need to update pitch */
  1058. if (fb->pitch > dev_priv->cfb_pitch)
  1059. dev_priv->display.disable_fbc(dev);
  1060. if (obj_priv->fence_reg != dev_priv->cfb_fence)
  1061. dev_priv->display.disable_fbc(dev);
  1062. if (plane != dev_priv->cfb_plane)
  1063. dev_priv->display.disable_fbc(dev);
  1064. }
  1065. if (!dev_priv->display.fbc_enabled(crtc)) {
  1066. /* Now try to turn it back on if possible */
  1067. dev_priv->display.enable_fbc(crtc, 500);
  1068. }
  1069. return;
  1070. out_disable:
  1071. DRM_DEBUG("unsupported config, disabling FBC\n");
  1072. /* Multiple disables should be harmless */
  1073. if (dev_priv->display.fbc_enabled(crtc))
  1074. dev_priv->display.disable_fbc(dev);
  1075. }
  1076. static int
  1077. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1078. struct drm_framebuffer *old_fb)
  1079. {
  1080. struct drm_device *dev = crtc->dev;
  1081. struct drm_i915_private *dev_priv = dev->dev_private;
  1082. struct drm_i915_master_private *master_priv;
  1083. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1084. struct intel_framebuffer *intel_fb;
  1085. struct drm_i915_gem_object *obj_priv;
  1086. struct drm_gem_object *obj;
  1087. int pipe = intel_crtc->pipe;
  1088. int plane = intel_crtc->plane;
  1089. unsigned long Start, Offset;
  1090. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1091. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1092. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1093. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1094. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1095. u32 dspcntr, alignment;
  1096. int ret;
  1097. /* no fb bound */
  1098. if (!crtc->fb) {
  1099. DRM_DEBUG("No FB bound\n");
  1100. return 0;
  1101. }
  1102. switch (plane) {
  1103. case 0:
  1104. case 1:
  1105. break;
  1106. default:
  1107. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1108. return -EINVAL;
  1109. }
  1110. intel_fb = to_intel_framebuffer(crtc->fb);
  1111. obj = intel_fb->obj;
  1112. obj_priv = obj->driver_private;
  1113. switch (obj_priv->tiling_mode) {
  1114. case I915_TILING_NONE:
  1115. alignment = 64 * 1024;
  1116. break;
  1117. case I915_TILING_X:
  1118. /* pin() will align the object as required by fence */
  1119. alignment = 0;
  1120. break;
  1121. case I915_TILING_Y:
  1122. /* FIXME: Is this true? */
  1123. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1124. return -EINVAL;
  1125. default:
  1126. BUG();
  1127. }
  1128. mutex_lock(&dev->struct_mutex);
  1129. ret = i915_gem_object_pin(obj, alignment);
  1130. if (ret != 0) {
  1131. mutex_unlock(&dev->struct_mutex);
  1132. return ret;
  1133. }
  1134. ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  1135. if (ret != 0) {
  1136. i915_gem_object_unpin(obj);
  1137. mutex_unlock(&dev->struct_mutex);
  1138. return ret;
  1139. }
  1140. /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
  1141. * whereas 965+ only requires a fence if using framebuffer compression.
  1142. * For simplicity, we always install a fence as the cost is not that onerous.
  1143. */
  1144. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1145. obj_priv->tiling_mode != I915_TILING_NONE) {
  1146. ret = i915_gem_object_get_fence_reg(obj);
  1147. if (ret != 0) {
  1148. i915_gem_object_unpin(obj);
  1149. mutex_unlock(&dev->struct_mutex);
  1150. return ret;
  1151. }
  1152. }
  1153. dspcntr = I915_READ(dspcntr_reg);
  1154. /* Mask out pixel format bits in case we change it */
  1155. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1156. switch (crtc->fb->bits_per_pixel) {
  1157. case 8:
  1158. dspcntr |= DISPPLANE_8BPP;
  1159. break;
  1160. case 16:
  1161. if (crtc->fb->depth == 15)
  1162. dspcntr |= DISPPLANE_15_16BPP;
  1163. else
  1164. dspcntr |= DISPPLANE_16BPP;
  1165. break;
  1166. case 24:
  1167. case 32:
  1168. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1169. break;
  1170. default:
  1171. DRM_ERROR("Unknown color depth\n");
  1172. i915_gem_object_unpin(obj);
  1173. mutex_unlock(&dev->struct_mutex);
  1174. return -EINVAL;
  1175. }
  1176. if (IS_I965G(dev)) {
  1177. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1178. dspcntr |= DISPPLANE_TILED;
  1179. else
  1180. dspcntr &= ~DISPPLANE_TILED;
  1181. }
  1182. if (IS_IGDNG(dev))
  1183. /* must disable */
  1184. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1185. I915_WRITE(dspcntr_reg, dspcntr);
  1186. Start = obj_priv->gtt_offset;
  1187. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  1188. DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
  1189. I915_WRITE(dspstride, crtc->fb->pitch);
  1190. if (IS_I965G(dev)) {
  1191. I915_WRITE(dspbase, Offset);
  1192. I915_READ(dspbase);
  1193. I915_WRITE(dspsurf, Start);
  1194. I915_READ(dspsurf);
  1195. I915_WRITE(dsptileoff, (y << 16) | x);
  1196. } else {
  1197. I915_WRITE(dspbase, Start + Offset);
  1198. I915_READ(dspbase);
  1199. }
  1200. if ((IS_I965G(dev) || plane == 0))
  1201. intel_update_fbc(crtc, &crtc->mode);
  1202. intel_wait_for_vblank(dev);
  1203. if (old_fb) {
  1204. intel_fb = to_intel_framebuffer(old_fb);
  1205. obj_priv = intel_fb->obj->driver_private;
  1206. i915_gem_object_unpin(intel_fb->obj);
  1207. }
  1208. intel_increase_pllclock(crtc, true);
  1209. mutex_unlock(&dev->struct_mutex);
  1210. if (!dev->primary->master)
  1211. return 0;
  1212. master_priv = dev->primary->master->driver_priv;
  1213. if (!master_priv->sarea_priv)
  1214. return 0;
  1215. if (pipe) {
  1216. master_priv->sarea_priv->pipeB_x = x;
  1217. master_priv->sarea_priv->pipeB_y = y;
  1218. } else {
  1219. master_priv->sarea_priv->pipeA_x = x;
  1220. master_priv->sarea_priv->pipeA_y = y;
  1221. }
  1222. return 0;
  1223. }
  1224. /* Disable the VGA plane that we never use */
  1225. static void i915_disable_vga (struct drm_device *dev)
  1226. {
  1227. struct drm_i915_private *dev_priv = dev->dev_private;
  1228. u8 sr1;
  1229. u32 vga_reg;
  1230. if (IS_IGDNG(dev))
  1231. vga_reg = CPU_VGACNTRL;
  1232. else
  1233. vga_reg = VGACNTRL;
  1234. if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
  1235. return;
  1236. I915_WRITE8(VGA_SR_INDEX, 1);
  1237. sr1 = I915_READ8(VGA_SR_DATA);
  1238. I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
  1239. udelay(100);
  1240. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  1241. }
  1242. static void igdng_disable_pll_edp (struct drm_crtc *crtc)
  1243. {
  1244. struct drm_device *dev = crtc->dev;
  1245. struct drm_i915_private *dev_priv = dev->dev_private;
  1246. u32 dpa_ctl;
  1247. DRM_DEBUG("\n");
  1248. dpa_ctl = I915_READ(DP_A);
  1249. dpa_ctl &= ~DP_PLL_ENABLE;
  1250. I915_WRITE(DP_A, dpa_ctl);
  1251. }
  1252. static void igdng_enable_pll_edp (struct drm_crtc *crtc)
  1253. {
  1254. struct drm_device *dev = crtc->dev;
  1255. struct drm_i915_private *dev_priv = dev->dev_private;
  1256. u32 dpa_ctl;
  1257. dpa_ctl = I915_READ(DP_A);
  1258. dpa_ctl |= DP_PLL_ENABLE;
  1259. I915_WRITE(DP_A, dpa_ctl);
  1260. udelay(200);
  1261. }
  1262. static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
  1263. {
  1264. struct drm_device *dev = crtc->dev;
  1265. struct drm_i915_private *dev_priv = dev->dev_private;
  1266. u32 dpa_ctl;
  1267. DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
  1268. dpa_ctl = I915_READ(DP_A);
  1269. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1270. if (clock < 200000) {
  1271. u32 temp;
  1272. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1273. /* workaround for 160Mhz:
  1274. 1) program 0x4600c bits 15:0 = 0x8124
  1275. 2) program 0x46010 bit 0 = 1
  1276. 3) program 0x46034 bit 24 = 1
  1277. 4) program 0x64000 bit 14 = 1
  1278. */
  1279. temp = I915_READ(0x4600c);
  1280. temp &= 0xffff0000;
  1281. I915_WRITE(0x4600c, temp | 0x8124);
  1282. temp = I915_READ(0x46010);
  1283. I915_WRITE(0x46010, temp | 1);
  1284. temp = I915_READ(0x46034);
  1285. I915_WRITE(0x46034, temp | (1 << 24));
  1286. } else {
  1287. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1288. }
  1289. I915_WRITE(DP_A, dpa_ctl);
  1290. udelay(500);
  1291. }
  1292. static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
  1293. {
  1294. struct drm_device *dev = crtc->dev;
  1295. struct drm_i915_private *dev_priv = dev->dev_private;
  1296. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1297. int pipe = intel_crtc->pipe;
  1298. int plane = intel_crtc->plane;
  1299. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1300. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1301. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1302. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1303. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1304. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1305. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1306. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1307. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1308. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  1309. int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
  1310. int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
  1311. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1312. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1313. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1314. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1315. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1316. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1317. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  1318. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  1319. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  1320. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  1321. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  1322. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  1323. u32 temp;
  1324. int tries = 5, j, n;
  1325. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1326. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1327. */
  1328. switch (mode) {
  1329. case DRM_MODE_DPMS_ON:
  1330. case DRM_MODE_DPMS_STANDBY:
  1331. case DRM_MODE_DPMS_SUSPEND:
  1332. DRM_DEBUG("crtc %d dpms on\n", pipe);
  1333. if (HAS_eDP) {
  1334. /* enable eDP PLL */
  1335. igdng_enable_pll_edp(crtc);
  1336. } else {
  1337. /* enable PCH DPLL */
  1338. temp = I915_READ(pch_dpll_reg);
  1339. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1340. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  1341. I915_READ(pch_dpll_reg);
  1342. }
  1343. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1344. temp = I915_READ(fdi_rx_reg);
  1345. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
  1346. FDI_SEL_PCDCLK |
  1347. FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
  1348. I915_READ(fdi_rx_reg);
  1349. udelay(200);
  1350. /* Enable CPU FDI TX PLL, always on for IGDNG */
  1351. temp = I915_READ(fdi_tx_reg);
  1352. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1353. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  1354. I915_READ(fdi_tx_reg);
  1355. udelay(100);
  1356. }
  1357. }
  1358. /* Enable panel fitting for LVDS */
  1359. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1360. temp = I915_READ(pf_ctl_reg);
  1361. I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
  1362. /* currently full aspect */
  1363. I915_WRITE(pf_win_pos, 0);
  1364. I915_WRITE(pf_win_size,
  1365. (dev_priv->panel_fixed_mode->hdisplay << 16) |
  1366. (dev_priv->panel_fixed_mode->vdisplay));
  1367. }
  1368. /* Enable CPU pipe */
  1369. temp = I915_READ(pipeconf_reg);
  1370. if ((temp & PIPEACONF_ENABLE) == 0) {
  1371. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1372. I915_READ(pipeconf_reg);
  1373. udelay(100);
  1374. }
  1375. /* configure and enable CPU plane */
  1376. temp = I915_READ(dspcntr_reg);
  1377. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1378. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1379. /* Flush the plane changes */
  1380. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1381. }
  1382. if (!HAS_eDP) {
  1383. /* enable CPU FDI TX and PCH FDI RX */
  1384. temp = I915_READ(fdi_tx_reg);
  1385. temp |= FDI_TX_ENABLE;
  1386. temp |= FDI_DP_PORT_WIDTH_X4; /* default */
  1387. temp &= ~FDI_LINK_TRAIN_NONE;
  1388. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1389. I915_WRITE(fdi_tx_reg, temp);
  1390. I915_READ(fdi_tx_reg);
  1391. temp = I915_READ(fdi_rx_reg);
  1392. temp &= ~FDI_LINK_TRAIN_NONE;
  1393. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1394. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1395. I915_READ(fdi_rx_reg);
  1396. udelay(150);
  1397. /* Train FDI. */
  1398. /* umask FDI RX Interrupt symbol_lock and bit_lock bit
  1399. for train result */
  1400. temp = I915_READ(fdi_rx_imr_reg);
  1401. temp &= ~FDI_RX_SYMBOL_LOCK;
  1402. temp &= ~FDI_RX_BIT_LOCK;
  1403. I915_WRITE(fdi_rx_imr_reg, temp);
  1404. I915_READ(fdi_rx_imr_reg);
  1405. udelay(150);
  1406. temp = I915_READ(fdi_rx_iir_reg);
  1407. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1408. if ((temp & FDI_RX_BIT_LOCK) == 0) {
  1409. for (j = 0; j < tries; j++) {
  1410. temp = I915_READ(fdi_rx_iir_reg);
  1411. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1412. if (temp & FDI_RX_BIT_LOCK)
  1413. break;
  1414. udelay(200);
  1415. }
  1416. if (j != tries)
  1417. I915_WRITE(fdi_rx_iir_reg,
  1418. temp | FDI_RX_BIT_LOCK);
  1419. else
  1420. DRM_DEBUG("train 1 fail\n");
  1421. } else {
  1422. I915_WRITE(fdi_rx_iir_reg,
  1423. temp | FDI_RX_BIT_LOCK);
  1424. DRM_DEBUG("train 1 ok 2!\n");
  1425. }
  1426. temp = I915_READ(fdi_tx_reg);
  1427. temp &= ~FDI_LINK_TRAIN_NONE;
  1428. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1429. I915_WRITE(fdi_tx_reg, temp);
  1430. temp = I915_READ(fdi_rx_reg);
  1431. temp &= ~FDI_LINK_TRAIN_NONE;
  1432. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1433. I915_WRITE(fdi_rx_reg, temp);
  1434. udelay(150);
  1435. temp = I915_READ(fdi_rx_iir_reg);
  1436. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1437. if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
  1438. for (j = 0; j < tries; j++) {
  1439. temp = I915_READ(fdi_rx_iir_reg);
  1440. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1441. if (temp & FDI_RX_SYMBOL_LOCK)
  1442. break;
  1443. udelay(200);
  1444. }
  1445. if (j != tries) {
  1446. I915_WRITE(fdi_rx_iir_reg,
  1447. temp | FDI_RX_SYMBOL_LOCK);
  1448. DRM_DEBUG("train 2 ok 1!\n");
  1449. } else
  1450. DRM_DEBUG("train 2 fail\n");
  1451. } else {
  1452. I915_WRITE(fdi_rx_iir_reg,
  1453. temp | FDI_RX_SYMBOL_LOCK);
  1454. DRM_DEBUG("train 2 ok 2!\n");
  1455. }
  1456. DRM_DEBUG("train done\n");
  1457. /* set transcoder timing */
  1458. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1459. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1460. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1461. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1462. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1463. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1464. /* enable PCH transcoder */
  1465. temp = I915_READ(transconf_reg);
  1466. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1467. I915_READ(transconf_reg);
  1468. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1469. ;
  1470. /* enable normal */
  1471. temp = I915_READ(fdi_tx_reg);
  1472. temp &= ~FDI_LINK_TRAIN_NONE;
  1473. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1474. FDI_TX_ENHANCE_FRAME_ENABLE);
  1475. I915_READ(fdi_tx_reg);
  1476. temp = I915_READ(fdi_rx_reg);
  1477. temp &= ~FDI_LINK_TRAIN_NONE;
  1478. I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
  1479. FDI_RX_ENHANCE_FRAME_ENABLE);
  1480. I915_READ(fdi_rx_reg);
  1481. /* wait one idle pattern time */
  1482. udelay(100);
  1483. }
  1484. intel_crtc_load_lut(crtc);
  1485. break;
  1486. case DRM_MODE_DPMS_OFF:
  1487. DRM_DEBUG("crtc %d dpms off\n", pipe);
  1488. i915_disable_vga(dev);
  1489. /* Disable display plane */
  1490. temp = I915_READ(dspcntr_reg);
  1491. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1492. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1493. /* Flush the plane changes */
  1494. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1495. I915_READ(dspbase_reg);
  1496. }
  1497. /* disable cpu pipe, disable after all planes disabled */
  1498. temp = I915_READ(pipeconf_reg);
  1499. if ((temp & PIPEACONF_ENABLE) != 0) {
  1500. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1501. I915_READ(pipeconf_reg);
  1502. n = 0;
  1503. /* wait for cpu pipe off, pipe state */
  1504. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
  1505. n++;
  1506. if (n < 60) {
  1507. udelay(500);
  1508. continue;
  1509. } else {
  1510. DRM_DEBUG("pipe %d off delay\n", pipe);
  1511. break;
  1512. }
  1513. }
  1514. } else
  1515. DRM_DEBUG("crtc %d is disabled\n", pipe);
  1516. if (HAS_eDP) {
  1517. igdng_disable_pll_edp(crtc);
  1518. }
  1519. /* disable CPU FDI tx and PCH FDI rx */
  1520. temp = I915_READ(fdi_tx_reg);
  1521. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1522. I915_READ(fdi_tx_reg);
  1523. temp = I915_READ(fdi_rx_reg);
  1524. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1525. I915_READ(fdi_rx_reg);
  1526. udelay(100);
  1527. /* still set train pattern 1 */
  1528. temp = I915_READ(fdi_tx_reg);
  1529. temp &= ~FDI_LINK_TRAIN_NONE;
  1530. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1531. I915_WRITE(fdi_tx_reg, temp);
  1532. temp = I915_READ(fdi_rx_reg);
  1533. temp &= ~FDI_LINK_TRAIN_NONE;
  1534. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1535. I915_WRITE(fdi_rx_reg, temp);
  1536. udelay(100);
  1537. /* disable PCH transcoder */
  1538. temp = I915_READ(transconf_reg);
  1539. if ((temp & TRANS_ENABLE) != 0) {
  1540. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1541. I915_READ(transconf_reg);
  1542. n = 0;
  1543. /* wait for PCH transcoder off, transcoder state */
  1544. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
  1545. n++;
  1546. if (n < 60) {
  1547. udelay(500);
  1548. continue;
  1549. } else {
  1550. DRM_DEBUG("transcoder %d off delay\n", pipe);
  1551. break;
  1552. }
  1553. }
  1554. }
  1555. /* disable PCH DPLL */
  1556. temp = I915_READ(pch_dpll_reg);
  1557. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1558. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1559. I915_READ(pch_dpll_reg);
  1560. }
  1561. temp = I915_READ(fdi_rx_reg);
  1562. if ((temp & FDI_RX_PLL_ENABLE) != 0) {
  1563. temp &= ~FDI_SEL_PCDCLK;
  1564. temp &= ~FDI_RX_PLL_ENABLE;
  1565. I915_WRITE(fdi_rx_reg, temp);
  1566. I915_READ(fdi_rx_reg);
  1567. }
  1568. /* Disable CPU FDI TX PLL */
  1569. temp = I915_READ(fdi_tx_reg);
  1570. if ((temp & FDI_TX_PLL_ENABLE) != 0) {
  1571. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
  1572. I915_READ(fdi_tx_reg);
  1573. udelay(100);
  1574. }
  1575. /* Disable PF */
  1576. temp = I915_READ(pf_ctl_reg);
  1577. if ((temp & PF_ENABLE) != 0) {
  1578. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1579. I915_READ(pf_ctl_reg);
  1580. }
  1581. I915_WRITE(pf_win_size, 0);
  1582. /* Wait for the clocks to turn off. */
  1583. udelay(150);
  1584. break;
  1585. }
  1586. }
  1587. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  1588. {
  1589. struct drm_device *dev = crtc->dev;
  1590. struct drm_i915_private *dev_priv = dev->dev_private;
  1591. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1592. int pipe = intel_crtc->pipe;
  1593. int plane = intel_crtc->plane;
  1594. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1595. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1596. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1597. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1598. u32 temp;
  1599. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1600. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1601. */
  1602. switch (mode) {
  1603. case DRM_MODE_DPMS_ON:
  1604. case DRM_MODE_DPMS_STANDBY:
  1605. case DRM_MODE_DPMS_SUSPEND:
  1606. intel_update_watermarks(dev);
  1607. /* Enable the DPLL */
  1608. temp = I915_READ(dpll_reg);
  1609. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1610. I915_WRITE(dpll_reg, temp);
  1611. I915_READ(dpll_reg);
  1612. /* Wait for the clocks to stabilize. */
  1613. udelay(150);
  1614. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1615. I915_READ(dpll_reg);
  1616. /* Wait for the clocks to stabilize. */
  1617. udelay(150);
  1618. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1619. I915_READ(dpll_reg);
  1620. /* Wait for the clocks to stabilize. */
  1621. udelay(150);
  1622. }
  1623. /* Enable the pipe */
  1624. temp = I915_READ(pipeconf_reg);
  1625. if ((temp & PIPEACONF_ENABLE) == 0)
  1626. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1627. /* Enable the plane */
  1628. temp = I915_READ(dspcntr_reg);
  1629. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1630. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1631. /* Flush the plane changes */
  1632. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1633. }
  1634. intel_crtc_load_lut(crtc);
  1635. if ((IS_I965G(dev) || plane == 0))
  1636. intel_update_fbc(crtc, &crtc->mode);
  1637. /* Give the overlay scaler a chance to enable if it's on this pipe */
  1638. //intel_crtc_dpms_video(crtc, true); TODO
  1639. break;
  1640. case DRM_MODE_DPMS_OFF:
  1641. intel_update_watermarks(dev);
  1642. /* Give the overlay scaler a chance to disable if it's on this pipe */
  1643. //intel_crtc_dpms_video(crtc, FALSE); TODO
  1644. if (dev_priv->cfb_plane == plane &&
  1645. dev_priv->display.disable_fbc)
  1646. dev_priv->display.disable_fbc(dev);
  1647. /* Disable the VGA plane that we never use */
  1648. i915_disable_vga(dev);
  1649. /* Disable display plane */
  1650. temp = I915_READ(dspcntr_reg);
  1651. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1652. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1653. /* Flush the plane changes */
  1654. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1655. I915_READ(dspbase_reg);
  1656. }
  1657. if (!IS_I9XX(dev)) {
  1658. /* Wait for vblank for the disable to take effect */
  1659. intel_wait_for_vblank(dev);
  1660. }
  1661. /* Next, disable display pipes */
  1662. temp = I915_READ(pipeconf_reg);
  1663. if ((temp & PIPEACONF_ENABLE) != 0) {
  1664. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1665. I915_READ(pipeconf_reg);
  1666. }
  1667. /* Wait for vblank for the disable to take effect. */
  1668. intel_wait_for_vblank(dev);
  1669. temp = I915_READ(dpll_reg);
  1670. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1671. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1672. I915_READ(dpll_reg);
  1673. }
  1674. /* Wait for the clocks to turn off. */
  1675. udelay(150);
  1676. break;
  1677. }
  1678. }
  1679. /**
  1680. * Sets the power management mode of the pipe and plane.
  1681. *
  1682. * This code should probably grow support for turning the cursor off and back
  1683. * on appropriately at the same time as we're turning the pipe off/on.
  1684. */
  1685. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  1686. {
  1687. struct drm_device *dev = crtc->dev;
  1688. struct drm_i915_private *dev_priv = dev->dev_private;
  1689. struct drm_i915_master_private *master_priv;
  1690. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1691. int pipe = intel_crtc->pipe;
  1692. bool enabled;
  1693. dev_priv->display.dpms(crtc, mode);
  1694. intel_crtc->dpms_mode = mode;
  1695. if (!dev->primary->master)
  1696. return;
  1697. master_priv = dev->primary->master->driver_priv;
  1698. if (!master_priv->sarea_priv)
  1699. return;
  1700. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  1701. switch (pipe) {
  1702. case 0:
  1703. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  1704. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  1705. break;
  1706. case 1:
  1707. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  1708. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  1709. break;
  1710. default:
  1711. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  1712. break;
  1713. }
  1714. }
  1715. static void intel_crtc_prepare (struct drm_crtc *crtc)
  1716. {
  1717. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1718. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  1719. }
  1720. static void intel_crtc_commit (struct drm_crtc *crtc)
  1721. {
  1722. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1723. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1724. }
  1725. void intel_encoder_prepare (struct drm_encoder *encoder)
  1726. {
  1727. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1728. /* lvds has its own version of prepare see intel_lvds_prepare */
  1729. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  1730. }
  1731. void intel_encoder_commit (struct drm_encoder *encoder)
  1732. {
  1733. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1734. /* lvds has its own version of commit see intel_lvds_commit */
  1735. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  1736. }
  1737. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  1738. struct drm_display_mode *mode,
  1739. struct drm_display_mode *adjusted_mode)
  1740. {
  1741. struct drm_device *dev = crtc->dev;
  1742. if (IS_IGDNG(dev)) {
  1743. /* FDI link clock is fixed at 2.7G */
  1744. if (mode->clock * 3 > 27000 * 4)
  1745. return MODE_CLOCK_HIGH;
  1746. }
  1747. return true;
  1748. }
  1749. static int i945_get_display_clock_speed(struct drm_device *dev)
  1750. {
  1751. return 400000;
  1752. }
  1753. static int i915_get_display_clock_speed(struct drm_device *dev)
  1754. {
  1755. return 333000;
  1756. }
  1757. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  1758. {
  1759. return 200000;
  1760. }
  1761. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  1762. {
  1763. u16 gcfgc = 0;
  1764. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  1765. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  1766. return 133000;
  1767. else {
  1768. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  1769. case GC_DISPLAY_CLOCK_333_MHZ:
  1770. return 333000;
  1771. default:
  1772. case GC_DISPLAY_CLOCK_190_200_MHZ:
  1773. return 190000;
  1774. }
  1775. }
  1776. }
  1777. static int i865_get_display_clock_speed(struct drm_device *dev)
  1778. {
  1779. return 266000;
  1780. }
  1781. static int i855_get_display_clock_speed(struct drm_device *dev)
  1782. {
  1783. u16 hpllcc = 0;
  1784. /* Assume that the hardware is in the high speed state. This
  1785. * should be the default.
  1786. */
  1787. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  1788. case GC_CLOCK_133_200:
  1789. case GC_CLOCK_100_200:
  1790. return 200000;
  1791. case GC_CLOCK_166_250:
  1792. return 250000;
  1793. case GC_CLOCK_100_133:
  1794. return 133000;
  1795. }
  1796. /* Shouldn't happen */
  1797. return 0;
  1798. }
  1799. static int i830_get_display_clock_speed(struct drm_device *dev)
  1800. {
  1801. return 133000;
  1802. }
  1803. /**
  1804. * Return the pipe currently connected to the panel fitter,
  1805. * or -1 if the panel fitter is not present or not in use
  1806. */
  1807. static int intel_panel_fitter_pipe (struct drm_device *dev)
  1808. {
  1809. struct drm_i915_private *dev_priv = dev->dev_private;
  1810. u32 pfit_control;
  1811. /* i830 doesn't have a panel fitter */
  1812. if (IS_I830(dev))
  1813. return -1;
  1814. pfit_control = I915_READ(PFIT_CONTROL);
  1815. /* See if the panel fitter is in use */
  1816. if ((pfit_control & PFIT_ENABLE) == 0)
  1817. return -1;
  1818. /* 965 can place panel fitter on either pipe */
  1819. if (IS_I965G(dev))
  1820. return (pfit_control >> 29) & 0x3;
  1821. /* older chips can only use pipe 1 */
  1822. return 1;
  1823. }
  1824. struct fdi_m_n {
  1825. u32 tu;
  1826. u32 gmch_m;
  1827. u32 gmch_n;
  1828. u32 link_m;
  1829. u32 link_n;
  1830. };
  1831. static void
  1832. fdi_reduce_ratio(u32 *num, u32 *den)
  1833. {
  1834. while (*num > 0xffffff || *den > 0xffffff) {
  1835. *num >>= 1;
  1836. *den >>= 1;
  1837. }
  1838. }
  1839. #define DATA_N 0x800000
  1840. #define LINK_N 0x80000
  1841. static void
  1842. igdng_compute_m_n(int bits_per_pixel, int nlanes,
  1843. int pixel_clock, int link_clock,
  1844. struct fdi_m_n *m_n)
  1845. {
  1846. u64 temp;
  1847. m_n->tu = 64; /* default size */
  1848. temp = (u64) DATA_N * pixel_clock;
  1849. temp = div_u64(temp, link_clock);
  1850. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  1851. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  1852. m_n->gmch_n = DATA_N;
  1853. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  1854. temp = (u64) LINK_N * pixel_clock;
  1855. m_n->link_m = div_u64(temp, link_clock);
  1856. m_n->link_n = LINK_N;
  1857. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  1858. }
  1859. struct intel_watermark_params {
  1860. unsigned long fifo_size;
  1861. unsigned long max_wm;
  1862. unsigned long default_wm;
  1863. unsigned long guard_size;
  1864. unsigned long cacheline_size;
  1865. };
  1866. /* IGD has different values for various configs */
  1867. static struct intel_watermark_params igd_display_wm = {
  1868. IGD_DISPLAY_FIFO,
  1869. IGD_MAX_WM,
  1870. IGD_DFT_WM,
  1871. IGD_GUARD_WM,
  1872. IGD_FIFO_LINE_SIZE
  1873. };
  1874. static struct intel_watermark_params igd_display_hplloff_wm = {
  1875. IGD_DISPLAY_FIFO,
  1876. IGD_MAX_WM,
  1877. IGD_DFT_HPLLOFF_WM,
  1878. IGD_GUARD_WM,
  1879. IGD_FIFO_LINE_SIZE
  1880. };
  1881. static struct intel_watermark_params igd_cursor_wm = {
  1882. IGD_CURSOR_FIFO,
  1883. IGD_CURSOR_MAX_WM,
  1884. IGD_CURSOR_DFT_WM,
  1885. IGD_CURSOR_GUARD_WM,
  1886. IGD_FIFO_LINE_SIZE,
  1887. };
  1888. static struct intel_watermark_params igd_cursor_hplloff_wm = {
  1889. IGD_CURSOR_FIFO,
  1890. IGD_CURSOR_MAX_WM,
  1891. IGD_CURSOR_DFT_WM,
  1892. IGD_CURSOR_GUARD_WM,
  1893. IGD_FIFO_LINE_SIZE
  1894. };
  1895. static struct intel_watermark_params g4x_wm_info = {
  1896. G4X_FIFO_SIZE,
  1897. G4X_MAX_WM,
  1898. G4X_MAX_WM,
  1899. 2,
  1900. G4X_FIFO_LINE_SIZE,
  1901. };
  1902. static struct intel_watermark_params i945_wm_info = {
  1903. I945_FIFO_SIZE,
  1904. I915_MAX_WM,
  1905. 1,
  1906. 2,
  1907. I915_FIFO_LINE_SIZE
  1908. };
  1909. static struct intel_watermark_params i915_wm_info = {
  1910. I915_FIFO_SIZE,
  1911. I915_MAX_WM,
  1912. 1,
  1913. 2,
  1914. I915_FIFO_LINE_SIZE
  1915. };
  1916. static struct intel_watermark_params i855_wm_info = {
  1917. I855GM_FIFO_SIZE,
  1918. I915_MAX_WM,
  1919. 1,
  1920. 2,
  1921. I830_FIFO_LINE_SIZE
  1922. };
  1923. static struct intel_watermark_params i830_wm_info = {
  1924. I830_FIFO_SIZE,
  1925. I915_MAX_WM,
  1926. 1,
  1927. 2,
  1928. I830_FIFO_LINE_SIZE
  1929. };
  1930. /**
  1931. * intel_calculate_wm - calculate watermark level
  1932. * @clock_in_khz: pixel clock
  1933. * @wm: chip FIFO params
  1934. * @pixel_size: display pixel size
  1935. * @latency_ns: memory latency for the platform
  1936. *
  1937. * Calculate the watermark level (the level at which the display plane will
  1938. * start fetching from memory again). Each chip has a different display
  1939. * FIFO size and allocation, so the caller needs to figure that out and pass
  1940. * in the correct intel_watermark_params structure.
  1941. *
  1942. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  1943. * on the pixel size. When it reaches the watermark level, it'll start
  1944. * fetching FIFO line sized based chunks from memory until the FIFO fills
  1945. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  1946. * will occur, and a display engine hang could result.
  1947. */
  1948. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  1949. struct intel_watermark_params *wm,
  1950. int pixel_size,
  1951. unsigned long latency_ns)
  1952. {
  1953. long entries_required, wm_size;
  1954. /*
  1955. * Note: we need to make sure we don't overflow for various clock &
  1956. * latency values.
  1957. * clocks go from a few thousand to several hundred thousand.
  1958. * latency is usually a few thousand
  1959. */
  1960. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  1961. 1000;
  1962. entries_required /= wm->cacheline_size;
  1963. DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
  1964. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  1965. DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
  1966. /* Don't promote wm_size to unsigned... */
  1967. if (wm_size > (long)wm->max_wm)
  1968. wm_size = wm->max_wm;
  1969. if (wm_size <= 0)
  1970. wm_size = wm->default_wm;
  1971. return wm_size;
  1972. }
  1973. struct cxsr_latency {
  1974. int is_desktop;
  1975. unsigned long fsb_freq;
  1976. unsigned long mem_freq;
  1977. unsigned long display_sr;
  1978. unsigned long display_hpll_disable;
  1979. unsigned long cursor_sr;
  1980. unsigned long cursor_hpll_disable;
  1981. };
  1982. static struct cxsr_latency cxsr_latency_table[] = {
  1983. {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  1984. {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  1985. {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  1986. {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  1987. {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  1988. {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  1989. {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  1990. {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  1991. {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  1992. {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  1993. {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  1994. {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  1995. {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  1996. {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  1997. {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  1998. {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  1999. {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2000. {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2001. };
  2002. static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
  2003. int mem)
  2004. {
  2005. int i;
  2006. struct cxsr_latency *latency;
  2007. if (fsb == 0 || mem == 0)
  2008. return NULL;
  2009. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2010. latency = &cxsr_latency_table[i];
  2011. if (is_desktop == latency->is_desktop &&
  2012. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2013. return latency;
  2014. }
  2015. DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
  2016. return NULL;
  2017. }
  2018. static void igd_disable_cxsr(struct drm_device *dev)
  2019. {
  2020. struct drm_i915_private *dev_priv = dev->dev_private;
  2021. u32 reg;
  2022. /* deactivate cxsr */
  2023. reg = I915_READ(DSPFW3);
  2024. reg &= ~(IGD_SELF_REFRESH_EN);
  2025. I915_WRITE(DSPFW3, reg);
  2026. DRM_INFO("Big FIFO is disabled\n");
  2027. }
  2028. static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
  2029. int pixel_size)
  2030. {
  2031. struct drm_i915_private *dev_priv = dev->dev_private;
  2032. u32 reg;
  2033. unsigned long wm;
  2034. struct cxsr_latency *latency;
  2035. latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
  2036. dev_priv->mem_freq);
  2037. if (!latency) {
  2038. DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
  2039. igd_disable_cxsr(dev);
  2040. return;
  2041. }
  2042. /* Display SR */
  2043. wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
  2044. latency->display_sr);
  2045. reg = I915_READ(DSPFW1);
  2046. reg &= 0x7fffff;
  2047. reg |= wm << 23;
  2048. I915_WRITE(DSPFW1, reg);
  2049. DRM_DEBUG("DSPFW1 register is %x\n", reg);
  2050. /* cursor SR */
  2051. wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
  2052. latency->cursor_sr);
  2053. reg = I915_READ(DSPFW3);
  2054. reg &= ~(0x3f << 24);
  2055. reg |= (wm & 0x3f) << 24;
  2056. I915_WRITE(DSPFW3, reg);
  2057. /* Display HPLL off SR */
  2058. wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
  2059. latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
  2060. reg = I915_READ(DSPFW3);
  2061. reg &= 0xfffffe00;
  2062. reg |= wm & 0x1ff;
  2063. I915_WRITE(DSPFW3, reg);
  2064. /* cursor HPLL off SR */
  2065. wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
  2066. latency->cursor_hpll_disable);
  2067. reg = I915_READ(DSPFW3);
  2068. reg &= ~(0x3f << 16);
  2069. reg |= (wm & 0x3f) << 16;
  2070. I915_WRITE(DSPFW3, reg);
  2071. DRM_DEBUG("DSPFW3 register is %x\n", reg);
  2072. /* activate cxsr */
  2073. reg = I915_READ(DSPFW3);
  2074. reg |= IGD_SELF_REFRESH_EN;
  2075. I915_WRITE(DSPFW3, reg);
  2076. DRM_INFO("Big FIFO is enabled\n");
  2077. return;
  2078. }
  2079. /*
  2080. * Latency for FIFO fetches is dependent on several factors:
  2081. * - memory configuration (speed, channels)
  2082. * - chipset
  2083. * - current MCH state
  2084. * It can be fairly high in some situations, so here we assume a fairly
  2085. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2086. * set this value too high, the FIFO will fetch frequently to stay full)
  2087. * and power consumption (set it too low to save power and we might see
  2088. * FIFO underruns and display "flicker").
  2089. *
  2090. * A value of 5us seems to be a good balance; safe for very low end
  2091. * platforms but not overly aggressive on lower latency configs.
  2092. */
  2093. const static int latency_ns = 5000;
  2094. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2095. {
  2096. struct drm_i915_private *dev_priv = dev->dev_private;
  2097. uint32_t dsparb = I915_READ(DSPARB);
  2098. int size;
  2099. if (plane == 0)
  2100. size = dsparb & 0x7f;
  2101. else
  2102. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
  2103. (dsparb & 0x7f);
  2104. DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
  2105. size);
  2106. return size;
  2107. }
  2108. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2109. {
  2110. struct drm_i915_private *dev_priv = dev->dev_private;
  2111. uint32_t dsparb = I915_READ(DSPARB);
  2112. int size;
  2113. if (plane == 0)
  2114. size = dsparb & 0x1ff;
  2115. else
  2116. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
  2117. (dsparb & 0x1ff);
  2118. size >>= 1; /* Convert to cachelines */
  2119. DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
  2120. size);
  2121. return size;
  2122. }
  2123. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2124. {
  2125. struct drm_i915_private *dev_priv = dev->dev_private;
  2126. uint32_t dsparb = I915_READ(DSPARB);
  2127. int size;
  2128. size = dsparb & 0x7f;
  2129. size >>= 2; /* Convert to cachelines */
  2130. DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
  2131. size);
  2132. return size;
  2133. }
  2134. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2135. {
  2136. struct drm_i915_private *dev_priv = dev->dev_private;
  2137. uint32_t dsparb = I915_READ(DSPARB);
  2138. int size;
  2139. size = dsparb & 0x7f;
  2140. size >>= 1; /* Convert to cachelines */
  2141. DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
  2142. size);
  2143. return size;
  2144. }
  2145. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2146. int planeb_clock, int sr_hdisplay, int pixel_size)
  2147. {
  2148. struct drm_i915_private *dev_priv = dev->dev_private;
  2149. int total_size, cacheline_size;
  2150. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2151. struct intel_watermark_params planea_params, planeb_params;
  2152. unsigned long line_time_us;
  2153. int sr_clock, sr_entries = 0, entries_required;
  2154. /* Create copies of the base settings for each pipe */
  2155. planea_params = planeb_params = g4x_wm_info;
  2156. /* Grab a couple of global values before we overwrite them */
  2157. total_size = planea_params.fifo_size;
  2158. cacheline_size = planea_params.cacheline_size;
  2159. /*
  2160. * Note: we need to make sure we don't overflow for various clock &
  2161. * latency values.
  2162. * clocks go from a few thousand to several hundred thousand.
  2163. * latency is usually a few thousand
  2164. */
  2165. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2166. 1000;
  2167. entries_required /= G4X_FIFO_LINE_SIZE;
  2168. planea_wm = entries_required + planea_params.guard_size;
  2169. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2170. 1000;
  2171. entries_required /= G4X_FIFO_LINE_SIZE;
  2172. planeb_wm = entries_required + planeb_params.guard_size;
  2173. cursora_wm = cursorb_wm = 16;
  2174. cursor_sr = 32;
  2175. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2176. /* Calc sr entries for one plane configs */
  2177. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2178. /* self-refresh has much higher latency */
  2179. const static int sr_latency_ns = 12000;
  2180. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2181. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2182. /* Use ns/us then divide to preserve precision */
  2183. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2184. pixel_size * sr_hdisplay) / 1000;
  2185. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2186. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2187. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2188. }
  2189. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2190. planea_wm, planeb_wm, sr_entries);
  2191. planea_wm &= 0x3f;
  2192. planeb_wm &= 0x3f;
  2193. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2194. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2195. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2196. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2197. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2198. /* HPLL off in SR has some issues on G4x... disable it */
  2199. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2200. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2201. }
  2202. static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
  2203. int unused3, int unused4)
  2204. {
  2205. struct drm_i915_private *dev_priv = dev->dev_private;
  2206. DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
  2207. /* 965 has limitations... */
  2208. I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
  2209. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2210. }
  2211. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2212. int planeb_clock, int sr_hdisplay, int pixel_size)
  2213. {
  2214. struct drm_i915_private *dev_priv = dev->dev_private;
  2215. uint32_t fwater_lo;
  2216. uint32_t fwater_hi;
  2217. int total_size, cacheline_size, cwm, srwm = 1;
  2218. int planea_wm, planeb_wm;
  2219. struct intel_watermark_params planea_params, planeb_params;
  2220. unsigned long line_time_us;
  2221. int sr_clock, sr_entries = 0;
  2222. /* Create copies of the base settings for each pipe */
  2223. if (IS_I965GM(dev) || IS_I945GM(dev))
  2224. planea_params = planeb_params = i945_wm_info;
  2225. else if (IS_I9XX(dev))
  2226. planea_params = planeb_params = i915_wm_info;
  2227. else
  2228. planea_params = planeb_params = i855_wm_info;
  2229. /* Grab a couple of global values before we overwrite them */
  2230. total_size = planea_params.fifo_size;
  2231. cacheline_size = planea_params.cacheline_size;
  2232. /* Update per-plane FIFO sizes */
  2233. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2234. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2235. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2236. pixel_size, latency_ns);
  2237. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2238. pixel_size, latency_ns);
  2239. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2240. /*
  2241. * Overlay gets an aggressive default since video jitter is bad.
  2242. */
  2243. cwm = 2;
  2244. /* Calc sr entries for one plane configs */
  2245. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2246. (!planea_clock || !planeb_clock)) {
  2247. /* self-refresh has much higher latency */
  2248. const static int sr_latency_ns = 6000;
  2249. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2250. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2251. /* Use ns/us then divide to preserve precision */
  2252. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2253. pixel_size * sr_hdisplay) / 1000;
  2254. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2255. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2256. srwm = total_size - sr_entries;
  2257. if (srwm < 0)
  2258. srwm = 1;
  2259. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
  2260. }
  2261. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2262. planea_wm, planeb_wm, cwm, srwm);
  2263. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2264. fwater_hi = (cwm & 0x1f);
  2265. /* Set request length to 8 cachelines per fetch */
  2266. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2267. fwater_hi = fwater_hi | (1 << 8);
  2268. I915_WRITE(FW_BLC, fwater_lo);
  2269. I915_WRITE(FW_BLC2, fwater_hi);
  2270. }
  2271. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2272. int unused2, int pixel_size)
  2273. {
  2274. struct drm_i915_private *dev_priv = dev->dev_private;
  2275. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2276. int planea_wm;
  2277. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2278. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2279. pixel_size, latency_ns);
  2280. fwater_lo |= (3<<8) | planea_wm;
  2281. DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
  2282. I915_WRITE(FW_BLC, fwater_lo);
  2283. }
  2284. /**
  2285. * intel_update_watermarks - update FIFO watermark values based on current modes
  2286. *
  2287. * Calculate watermark values for the various WM regs based on current mode
  2288. * and plane configuration.
  2289. *
  2290. * There are several cases to deal with here:
  2291. * - normal (i.e. non-self-refresh)
  2292. * - self-refresh (SR) mode
  2293. * - lines are large relative to FIFO size (buffer can hold up to 2)
  2294. * - lines are small relative to FIFO size (buffer can hold more than 2
  2295. * lines), so need to account for TLB latency
  2296. *
  2297. * The normal calculation is:
  2298. * watermark = dotclock * bytes per pixel * latency
  2299. * where latency is platform & configuration dependent (we assume pessimal
  2300. * values here).
  2301. *
  2302. * The SR calculation is:
  2303. * watermark = (trunc(latency/line time)+1) * surface width *
  2304. * bytes per pixel
  2305. * where
  2306. * line time = htotal / dotclock
  2307. * and latency is assumed to be high, as above.
  2308. *
  2309. * The final value programmed to the register should always be rounded up,
  2310. * and include an extra 2 entries to account for clock crossings.
  2311. *
  2312. * We don't use the sprite, so we can ignore that. And on Crestline we have
  2313. * to set the non-SR watermarks to 8.
  2314. */
  2315. static void intel_update_watermarks(struct drm_device *dev)
  2316. {
  2317. struct drm_i915_private *dev_priv = dev->dev_private;
  2318. struct drm_crtc *crtc;
  2319. struct intel_crtc *intel_crtc;
  2320. int sr_hdisplay = 0;
  2321. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  2322. int enabled = 0, pixel_size = 0;
  2323. if (!dev_priv->display.update_wm)
  2324. return;
  2325. /* Get the clock config from both planes */
  2326. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2327. intel_crtc = to_intel_crtc(crtc);
  2328. if (crtc->enabled) {
  2329. enabled++;
  2330. if (intel_crtc->plane == 0) {
  2331. DRM_DEBUG("plane A (pipe %d) clock: %d\n",
  2332. intel_crtc->pipe, crtc->mode.clock);
  2333. planea_clock = crtc->mode.clock;
  2334. } else {
  2335. DRM_DEBUG("plane B (pipe %d) clock: %d\n",
  2336. intel_crtc->pipe, crtc->mode.clock);
  2337. planeb_clock = crtc->mode.clock;
  2338. }
  2339. sr_hdisplay = crtc->mode.hdisplay;
  2340. sr_clock = crtc->mode.clock;
  2341. if (crtc->fb)
  2342. pixel_size = crtc->fb->bits_per_pixel / 8;
  2343. else
  2344. pixel_size = 4; /* by default */
  2345. }
  2346. }
  2347. if (enabled <= 0)
  2348. return;
  2349. /* Single plane configs can enable self refresh */
  2350. if (enabled == 1 && IS_IGD(dev))
  2351. igd_enable_cxsr(dev, sr_clock, pixel_size);
  2352. else if (IS_IGD(dev))
  2353. igd_disable_cxsr(dev);
  2354. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  2355. sr_hdisplay, pixel_size);
  2356. }
  2357. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  2358. struct drm_display_mode *mode,
  2359. struct drm_display_mode *adjusted_mode,
  2360. int x, int y,
  2361. struct drm_framebuffer *old_fb)
  2362. {
  2363. struct drm_device *dev = crtc->dev;
  2364. struct drm_i915_private *dev_priv = dev->dev_private;
  2365. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2366. int pipe = intel_crtc->pipe;
  2367. int plane = intel_crtc->plane;
  2368. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  2369. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2370. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  2371. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2372. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2373. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  2374. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  2375. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  2376. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  2377. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  2378. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  2379. int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
  2380. int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
  2381. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  2382. int refclk, num_outputs = 0;
  2383. intel_clock_t clock, reduced_clock;
  2384. u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
  2385. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  2386. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  2387. bool is_edp = false;
  2388. struct drm_mode_config *mode_config = &dev->mode_config;
  2389. struct drm_connector *connector;
  2390. const intel_limit_t *limit;
  2391. int ret;
  2392. struct fdi_m_n m_n = {0};
  2393. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  2394. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  2395. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  2396. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  2397. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  2398. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  2399. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  2400. int lvds_reg = LVDS;
  2401. u32 temp;
  2402. int sdvo_pixel_multiply;
  2403. int target_clock;
  2404. drm_vblank_pre_modeset(dev, pipe);
  2405. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2406. struct intel_output *intel_output = to_intel_output(connector);
  2407. if (!connector->encoder || connector->encoder->crtc != crtc)
  2408. continue;
  2409. switch (intel_output->type) {
  2410. case INTEL_OUTPUT_LVDS:
  2411. is_lvds = true;
  2412. break;
  2413. case INTEL_OUTPUT_SDVO:
  2414. case INTEL_OUTPUT_HDMI:
  2415. is_sdvo = true;
  2416. if (intel_output->needs_tv_clock)
  2417. is_tv = true;
  2418. break;
  2419. case INTEL_OUTPUT_DVO:
  2420. is_dvo = true;
  2421. break;
  2422. case INTEL_OUTPUT_TVOUT:
  2423. is_tv = true;
  2424. break;
  2425. case INTEL_OUTPUT_ANALOG:
  2426. is_crt = true;
  2427. break;
  2428. case INTEL_OUTPUT_DISPLAYPORT:
  2429. is_dp = true;
  2430. break;
  2431. case INTEL_OUTPUT_EDP:
  2432. is_edp = true;
  2433. break;
  2434. }
  2435. num_outputs++;
  2436. }
  2437. if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
  2438. refclk = dev_priv->lvds_ssc_freq * 1000;
  2439. DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
  2440. } else if (IS_I9XX(dev)) {
  2441. refclk = 96000;
  2442. if (IS_IGDNG(dev))
  2443. refclk = 120000; /* 120Mhz refclk */
  2444. } else {
  2445. refclk = 48000;
  2446. }
  2447. /*
  2448. * Returns a set of divisors for the desired target clock with the given
  2449. * refclk, or FALSE. The returned values represent the clock equation:
  2450. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  2451. */
  2452. limit = intel_limit(crtc);
  2453. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  2454. if (!ok) {
  2455. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  2456. drm_vblank_post_modeset(dev, pipe);
  2457. return -EINVAL;
  2458. }
  2459. if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
  2460. memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
  2461. has_reduced_clock = limit->find_reduced_pll(limit, crtc,
  2462. (adjusted_mode->clock*3/4),
  2463. refclk,
  2464. &reduced_clock);
  2465. }
  2466. /* SDVO TV has fixed PLL values depend on its clock range,
  2467. this mirrors vbios setting. */
  2468. if (is_sdvo && is_tv) {
  2469. if (adjusted_mode->clock >= 100000
  2470. && adjusted_mode->clock < 140500) {
  2471. clock.p1 = 2;
  2472. clock.p2 = 10;
  2473. clock.n = 3;
  2474. clock.m1 = 16;
  2475. clock.m2 = 8;
  2476. } else if (adjusted_mode->clock >= 140500
  2477. && adjusted_mode->clock <= 200000) {
  2478. clock.p1 = 1;
  2479. clock.p2 = 10;
  2480. clock.n = 6;
  2481. clock.m1 = 12;
  2482. clock.m2 = 8;
  2483. }
  2484. }
  2485. /* FDI link */
  2486. if (IS_IGDNG(dev)) {
  2487. int lane, link_bw, bpp;
  2488. /* eDP doesn't require FDI link, so just set DP M/N
  2489. according to current link config */
  2490. if (is_edp) {
  2491. struct drm_connector *edp;
  2492. target_clock = mode->clock;
  2493. edp = intel_pipe_get_output(crtc);
  2494. intel_edp_link_config(to_intel_output(edp),
  2495. &lane, &link_bw);
  2496. } else {
  2497. /* DP over FDI requires target mode clock
  2498. instead of link clock */
  2499. if (is_dp)
  2500. target_clock = mode->clock;
  2501. else
  2502. target_clock = adjusted_mode->clock;
  2503. lane = 4;
  2504. link_bw = 270000;
  2505. }
  2506. /* determine panel color depth */
  2507. temp = I915_READ(pipeconf_reg);
  2508. switch (temp & PIPE_BPC_MASK) {
  2509. case PIPE_8BPC:
  2510. bpp = 24;
  2511. break;
  2512. case PIPE_10BPC:
  2513. bpp = 30;
  2514. break;
  2515. case PIPE_6BPC:
  2516. bpp = 18;
  2517. break;
  2518. case PIPE_12BPC:
  2519. bpp = 36;
  2520. break;
  2521. default:
  2522. DRM_ERROR("unknown pipe bpc value\n");
  2523. bpp = 24;
  2524. }
  2525. igdng_compute_m_n(bpp, lane, target_clock,
  2526. link_bw, &m_n);
  2527. }
  2528. /* Ironlake: try to setup display ref clock before DPLL
  2529. * enabling. This is only under driver's control after
  2530. * PCH B stepping, previous chipset stepping should be
  2531. * ignoring this setting.
  2532. */
  2533. if (IS_IGDNG(dev)) {
  2534. temp = I915_READ(PCH_DREF_CONTROL);
  2535. /* Always enable nonspread source */
  2536. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  2537. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  2538. I915_WRITE(PCH_DREF_CONTROL, temp);
  2539. POSTING_READ(PCH_DREF_CONTROL);
  2540. temp &= ~DREF_SSC_SOURCE_MASK;
  2541. temp |= DREF_SSC_SOURCE_ENABLE;
  2542. I915_WRITE(PCH_DREF_CONTROL, temp);
  2543. POSTING_READ(PCH_DREF_CONTROL);
  2544. udelay(200);
  2545. if (is_edp) {
  2546. if (dev_priv->lvds_use_ssc) {
  2547. temp |= DREF_SSC1_ENABLE;
  2548. I915_WRITE(PCH_DREF_CONTROL, temp);
  2549. POSTING_READ(PCH_DREF_CONTROL);
  2550. udelay(200);
  2551. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  2552. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  2553. I915_WRITE(PCH_DREF_CONTROL, temp);
  2554. POSTING_READ(PCH_DREF_CONTROL);
  2555. } else {
  2556. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  2557. I915_WRITE(PCH_DREF_CONTROL, temp);
  2558. POSTING_READ(PCH_DREF_CONTROL);
  2559. }
  2560. }
  2561. }
  2562. if (IS_IGD(dev)) {
  2563. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  2564. if (has_reduced_clock)
  2565. fp2 = (1 << reduced_clock.n) << 16 |
  2566. reduced_clock.m1 << 8 | reduced_clock.m2;
  2567. } else {
  2568. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  2569. if (has_reduced_clock)
  2570. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  2571. reduced_clock.m2;
  2572. }
  2573. if (!IS_IGDNG(dev))
  2574. dpll = DPLL_VGA_MODE_DIS;
  2575. if (IS_I9XX(dev)) {
  2576. if (is_lvds)
  2577. dpll |= DPLLB_MODE_LVDS;
  2578. else
  2579. dpll |= DPLLB_MODE_DAC_SERIAL;
  2580. if (is_sdvo) {
  2581. dpll |= DPLL_DVO_HIGH_SPEED;
  2582. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  2583. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  2584. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  2585. else if (IS_IGDNG(dev))
  2586. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  2587. }
  2588. if (is_dp)
  2589. dpll |= DPLL_DVO_HIGH_SPEED;
  2590. /* compute bitmask from p1 value */
  2591. if (IS_IGD(dev))
  2592. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
  2593. else {
  2594. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  2595. /* also FPA1 */
  2596. if (IS_IGDNG(dev))
  2597. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  2598. if (IS_G4X(dev) && has_reduced_clock)
  2599. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  2600. }
  2601. switch (clock.p2) {
  2602. case 5:
  2603. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  2604. break;
  2605. case 7:
  2606. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  2607. break;
  2608. case 10:
  2609. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  2610. break;
  2611. case 14:
  2612. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  2613. break;
  2614. }
  2615. if (IS_I965G(dev) && !IS_IGDNG(dev))
  2616. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  2617. } else {
  2618. if (is_lvds) {
  2619. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  2620. } else {
  2621. if (clock.p1 == 2)
  2622. dpll |= PLL_P1_DIVIDE_BY_TWO;
  2623. else
  2624. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  2625. if (clock.p2 == 4)
  2626. dpll |= PLL_P2_DIVIDE_BY_4;
  2627. }
  2628. }
  2629. if (is_sdvo && is_tv)
  2630. dpll |= PLL_REF_INPUT_TVCLKINBC;
  2631. else if (is_tv)
  2632. /* XXX: just matching BIOS for now */
  2633. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  2634. dpll |= 3;
  2635. else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
  2636. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  2637. else
  2638. dpll |= PLL_REF_INPUT_DREFCLK;
  2639. /* setup pipeconf */
  2640. pipeconf = I915_READ(pipeconf_reg);
  2641. /* Set up the display plane register */
  2642. dspcntr = DISPPLANE_GAMMA_ENABLE;
  2643. /* IGDNG's plane is forced to pipe, bit 24 is to
  2644. enable color space conversion */
  2645. if (!IS_IGDNG(dev)) {
  2646. if (pipe == 0)
  2647. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  2648. else
  2649. dspcntr |= DISPPLANE_SEL_PIPE_B;
  2650. }
  2651. if (pipe == 0 && !IS_I965G(dev)) {
  2652. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  2653. * core speed.
  2654. *
  2655. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  2656. * pipe == 0 check?
  2657. */
  2658. if (mode->clock >
  2659. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  2660. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  2661. else
  2662. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  2663. }
  2664. dspcntr |= DISPLAY_PLANE_ENABLE;
  2665. pipeconf |= PIPEACONF_ENABLE;
  2666. dpll |= DPLL_VCO_ENABLE;
  2667. /* Disable the panel fitter if it was on our pipe */
  2668. if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
  2669. I915_WRITE(PFIT_CONTROL, 0);
  2670. DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  2671. drm_mode_debug_printmodeline(mode);
  2672. /* assign to IGDNG registers */
  2673. if (IS_IGDNG(dev)) {
  2674. fp_reg = pch_fp_reg;
  2675. dpll_reg = pch_dpll_reg;
  2676. }
  2677. if (is_edp) {
  2678. igdng_disable_pll_edp(crtc);
  2679. } else if ((dpll & DPLL_VCO_ENABLE)) {
  2680. I915_WRITE(fp_reg, fp);
  2681. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  2682. I915_READ(dpll_reg);
  2683. udelay(150);
  2684. }
  2685. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  2686. * This is an exception to the general rule that mode_set doesn't turn
  2687. * things on.
  2688. */
  2689. if (is_lvds) {
  2690. u32 lvds;
  2691. if (IS_IGDNG(dev))
  2692. lvds_reg = PCH_LVDS;
  2693. lvds = I915_READ(lvds_reg);
  2694. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
  2695. /* set the corresponsding LVDS_BORDER bit */
  2696. lvds |= dev_priv->lvds_border_bits;
  2697. /* Set the B0-B3 data pairs corresponding to whether we're going to
  2698. * set the DPLLs for dual-channel mode or not.
  2699. */
  2700. if (clock.p2 == 7)
  2701. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  2702. else
  2703. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  2704. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  2705. * appropriately here, but we need to look more thoroughly into how
  2706. * panels behave in the two modes.
  2707. */
  2708. I915_WRITE(lvds_reg, lvds);
  2709. I915_READ(lvds_reg);
  2710. }
  2711. if (is_dp)
  2712. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  2713. if (!is_edp) {
  2714. I915_WRITE(fp_reg, fp);
  2715. I915_WRITE(dpll_reg, dpll);
  2716. I915_READ(dpll_reg);
  2717. /* Wait for the clocks to stabilize. */
  2718. udelay(150);
  2719. if (IS_I965G(dev) && !IS_IGDNG(dev)) {
  2720. if (is_sdvo) {
  2721. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  2722. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  2723. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  2724. } else
  2725. I915_WRITE(dpll_md_reg, 0);
  2726. } else {
  2727. /* write it again -- the BIOS does, after all */
  2728. I915_WRITE(dpll_reg, dpll);
  2729. }
  2730. I915_READ(dpll_reg);
  2731. /* Wait for the clocks to stabilize. */
  2732. udelay(150);
  2733. }
  2734. if (is_lvds && has_reduced_clock && i915_powersave) {
  2735. I915_WRITE(fp_reg + 4, fp2);
  2736. intel_crtc->lowfreq_avail = true;
  2737. if (HAS_PIPE_CXSR(dev)) {
  2738. DRM_DEBUG("enabling CxSR downclocking\n");
  2739. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  2740. }
  2741. } else {
  2742. I915_WRITE(fp_reg + 4, fp);
  2743. intel_crtc->lowfreq_avail = false;
  2744. if (HAS_PIPE_CXSR(dev)) {
  2745. DRM_DEBUG("disabling CxSR downclocking\n");
  2746. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  2747. }
  2748. }
  2749. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  2750. ((adjusted_mode->crtc_htotal - 1) << 16));
  2751. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  2752. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  2753. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  2754. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  2755. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  2756. ((adjusted_mode->crtc_vtotal - 1) << 16));
  2757. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  2758. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  2759. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  2760. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  2761. /* pipesrc and dspsize control the size that is scaled from, which should
  2762. * always be the user's requested size.
  2763. */
  2764. if (!IS_IGDNG(dev)) {
  2765. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  2766. (mode->hdisplay - 1));
  2767. I915_WRITE(dsppos_reg, 0);
  2768. }
  2769. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  2770. if (IS_IGDNG(dev)) {
  2771. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  2772. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  2773. I915_WRITE(link_m1_reg, m_n.link_m);
  2774. I915_WRITE(link_n1_reg, m_n.link_n);
  2775. if (is_edp) {
  2776. igdng_set_pll_edp(crtc, adjusted_mode->clock);
  2777. } else {
  2778. /* enable FDI RX PLL too */
  2779. temp = I915_READ(fdi_rx_reg);
  2780. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  2781. udelay(200);
  2782. }
  2783. }
  2784. I915_WRITE(pipeconf_reg, pipeconf);
  2785. I915_READ(pipeconf_reg);
  2786. intel_wait_for_vblank(dev);
  2787. if (IS_IGDNG(dev)) {
  2788. /* enable address swizzle for tiling buffer */
  2789. temp = I915_READ(DISP_ARB_CTL);
  2790. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  2791. }
  2792. I915_WRITE(dspcntr_reg, dspcntr);
  2793. /* Flush the plane changes */
  2794. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  2795. if ((IS_I965G(dev) || plane == 0))
  2796. intel_update_fbc(crtc, &crtc->mode);
  2797. intel_update_watermarks(dev);
  2798. drm_vblank_post_modeset(dev, pipe);
  2799. return ret;
  2800. }
  2801. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  2802. void intel_crtc_load_lut(struct drm_crtc *crtc)
  2803. {
  2804. struct drm_device *dev = crtc->dev;
  2805. struct drm_i915_private *dev_priv = dev->dev_private;
  2806. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2807. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  2808. int i;
  2809. /* The clocks have to be on to load the palette. */
  2810. if (!crtc->enabled)
  2811. return;
  2812. /* use legacy palette for IGDNG */
  2813. if (IS_IGDNG(dev))
  2814. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  2815. LGC_PALETTE_B;
  2816. for (i = 0; i < 256; i++) {
  2817. I915_WRITE(palreg + 4 * i,
  2818. (intel_crtc->lut_r[i] << 16) |
  2819. (intel_crtc->lut_g[i] << 8) |
  2820. intel_crtc->lut_b[i]);
  2821. }
  2822. }
  2823. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  2824. struct drm_file *file_priv,
  2825. uint32_t handle,
  2826. uint32_t width, uint32_t height)
  2827. {
  2828. struct drm_device *dev = crtc->dev;
  2829. struct drm_i915_private *dev_priv = dev->dev_private;
  2830. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2831. struct drm_gem_object *bo;
  2832. struct drm_i915_gem_object *obj_priv;
  2833. int pipe = intel_crtc->pipe;
  2834. uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
  2835. uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
  2836. uint32_t temp = I915_READ(control);
  2837. size_t addr;
  2838. int ret;
  2839. DRM_DEBUG("\n");
  2840. /* if we want to turn off the cursor ignore width and height */
  2841. if (!handle) {
  2842. DRM_DEBUG("cursor off\n");
  2843. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  2844. temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  2845. temp |= CURSOR_MODE_DISABLE;
  2846. } else {
  2847. temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  2848. }
  2849. addr = 0;
  2850. bo = NULL;
  2851. mutex_lock(&dev->struct_mutex);
  2852. goto finish;
  2853. }
  2854. /* Currently we only support 64x64 cursors */
  2855. if (width != 64 || height != 64) {
  2856. DRM_ERROR("we currently only support 64x64 cursors\n");
  2857. return -EINVAL;
  2858. }
  2859. bo = drm_gem_object_lookup(dev, file_priv, handle);
  2860. if (!bo)
  2861. return -ENOENT;
  2862. obj_priv = bo->driver_private;
  2863. if (bo->size < width * height * 4) {
  2864. DRM_ERROR("buffer is to small\n");
  2865. ret = -ENOMEM;
  2866. goto fail;
  2867. }
  2868. /* we only need to pin inside GTT if cursor is non-phy */
  2869. mutex_lock(&dev->struct_mutex);
  2870. if (!dev_priv->cursor_needs_physical) {
  2871. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  2872. if (ret) {
  2873. DRM_ERROR("failed to pin cursor bo\n");
  2874. goto fail_locked;
  2875. }
  2876. addr = obj_priv->gtt_offset;
  2877. } else {
  2878. ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  2879. if (ret) {
  2880. DRM_ERROR("failed to attach phys object\n");
  2881. goto fail_locked;
  2882. }
  2883. addr = obj_priv->phys_obj->handle->busaddr;
  2884. }
  2885. if (!IS_I9XX(dev))
  2886. I915_WRITE(CURSIZE, (height << 12) | width);
  2887. /* Hooray for CUR*CNTR differences */
  2888. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  2889. temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  2890. temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  2891. temp |= (pipe << 28); /* Connect to correct pipe */
  2892. } else {
  2893. temp &= ~(CURSOR_FORMAT_MASK);
  2894. temp |= CURSOR_ENABLE;
  2895. temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  2896. }
  2897. finish:
  2898. I915_WRITE(control, temp);
  2899. I915_WRITE(base, addr);
  2900. if (intel_crtc->cursor_bo) {
  2901. if (dev_priv->cursor_needs_physical) {
  2902. if (intel_crtc->cursor_bo != bo)
  2903. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  2904. } else
  2905. i915_gem_object_unpin(intel_crtc->cursor_bo);
  2906. drm_gem_object_unreference(intel_crtc->cursor_bo);
  2907. }
  2908. mutex_unlock(&dev->struct_mutex);
  2909. intel_crtc->cursor_addr = addr;
  2910. intel_crtc->cursor_bo = bo;
  2911. return 0;
  2912. fail:
  2913. mutex_lock(&dev->struct_mutex);
  2914. fail_locked:
  2915. drm_gem_object_unreference(bo);
  2916. mutex_unlock(&dev->struct_mutex);
  2917. return ret;
  2918. }
  2919. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  2920. {
  2921. struct drm_device *dev = crtc->dev;
  2922. struct drm_i915_private *dev_priv = dev->dev_private;
  2923. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2924. struct intel_framebuffer *intel_fb;
  2925. int pipe = intel_crtc->pipe;
  2926. uint32_t temp = 0;
  2927. uint32_t adder;
  2928. if (crtc->fb) {
  2929. intel_fb = to_intel_framebuffer(crtc->fb);
  2930. intel_mark_busy(dev, intel_fb->obj);
  2931. }
  2932. if (x < 0) {
  2933. temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  2934. x = -x;
  2935. }
  2936. if (y < 0) {
  2937. temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  2938. y = -y;
  2939. }
  2940. temp |= x << CURSOR_X_SHIFT;
  2941. temp |= y << CURSOR_Y_SHIFT;
  2942. adder = intel_crtc->cursor_addr;
  2943. I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
  2944. I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
  2945. return 0;
  2946. }
  2947. /** Sets the color ramps on behalf of RandR */
  2948. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  2949. u16 blue, int regno)
  2950. {
  2951. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2952. intel_crtc->lut_r[regno] = red >> 8;
  2953. intel_crtc->lut_g[regno] = green >> 8;
  2954. intel_crtc->lut_b[regno] = blue >> 8;
  2955. }
  2956. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  2957. u16 *blue, int regno)
  2958. {
  2959. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2960. *red = intel_crtc->lut_r[regno] << 8;
  2961. *green = intel_crtc->lut_g[regno] << 8;
  2962. *blue = intel_crtc->lut_b[regno] << 8;
  2963. }
  2964. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  2965. u16 *blue, uint32_t size)
  2966. {
  2967. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2968. int i;
  2969. if (size != 256)
  2970. return;
  2971. for (i = 0; i < 256; i++) {
  2972. intel_crtc->lut_r[i] = red[i] >> 8;
  2973. intel_crtc->lut_g[i] = green[i] >> 8;
  2974. intel_crtc->lut_b[i] = blue[i] >> 8;
  2975. }
  2976. intel_crtc_load_lut(crtc);
  2977. }
  2978. /**
  2979. * Get a pipe with a simple mode set on it for doing load-based monitor
  2980. * detection.
  2981. *
  2982. * It will be up to the load-detect code to adjust the pipe as appropriate for
  2983. * its requirements. The pipe will be connected to no other outputs.
  2984. *
  2985. * Currently this code will only succeed if there is a pipe with no outputs
  2986. * configured for it. In the future, it could choose to temporarily disable
  2987. * some outputs to free up a pipe for its use.
  2988. *
  2989. * \return crtc, or NULL if no pipes are available.
  2990. */
  2991. /* VESA 640x480x72Hz mode to set on the pipe */
  2992. static struct drm_display_mode load_detect_mode = {
  2993. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  2994. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  2995. };
  2996. struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
  2997. struct drm_display_mode *mode,
  2998. int *dpms_mode)
  2999. {
  3000. struct intel_crtc *intel_crtc;
  3001. struct drm_crtc *possible_crtc;
  3002. struct drm_crtc *supported_crtc =NULL;
  3003. struct drm_encoder *encoder = &intel_output->enc;
  3004. struct drm_crtc *crtc = NULL;
  3005. struct drm_device *dev = encoder->dev;
  3006. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3007. struct drm_crtc_helper_funcs *crtc_funcs;
  3008. int i = -1;
  3009. /*
  3010. * Algorithm gets a little messy:
  3011. * - if the connector already has an assigned crtc, use it (but make
  3012. * sure it's on first)
  3013. * - try to find the first unused crtc that can drive this connector,
  3014. * and use that if we find one
  3015. * - if there are no unused crtcs available, try to use the first
  3016. * one we found that supports the connector
  3017. */
  3018. /* See if we already have a CRTC for this connector */
  3019. if (encoder->crtc) {
  3020. crtc = encoder->crtc;
  3021. /* Make sure the crtc and connector are running */
  3022. intel_crtc = to_intel_crtc(crtc);
  3023. *dpms_mode = intel_crtc->dpms_mode;
  3024. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3025. crtc_funcs = crtc->helper_private;
  3026. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3027. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3028. }
  3029. return crtc;
  3030. }
  3031. /* Find an unused one (if possible) */
  3032. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3033. i++;
  3034. if (!(encoder->possible_crtcs & (1 << i)))
  3035. continue;
  3036. if (!possible_crtc->enabled) {
  3037. crtc = possible_crtc;
  3038. break;
  3039. }
  3040. if (!supported_crtc)
  3041. supported_crtc = possible_crtc;
  3042. }
  3043. /*
  3044. * If we didn't find an unused CRTC, don't use any.
  3045. */
  3046. if (!crtc) {
  3047. return NULL;
  3048. }
  3049. encoder->crtc = crtc;
  3050. intel_output->base.encoder = encoder;
  3051. intel_output->load_detect_temp = true;
  3052. intel_crtc = to_intel_crtc(crtc);
  3053. *dpms_mode = intel_crtc->dpms_mode;
  3054. if (!crtc->enabled) {
  3055. if (!mode)
  3056. mode = &load_detect_mode;
  3057. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  3058. } else {
  3059. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3060. crtc_funcs = crtc->helper_private;
  3061. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3062. }
  3063. /* Add this connector to the crtc */
  3064. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  3065. encoder_funcs->commit(encoder);
  3066. }
  3067. /* let the connector get through one full cycle before testing */
  3068. intel_wait_for_vblank(dev);
  3069. return crtc;
  3070. }
  3071. void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
  3072. {
  3073. struct drm_encoder *encoder = &intel_output->enc;
  3074. struct drm_device *dev = encoder->dev;
  3075. struct drm_crtc *crtc = encoder->crtc;
  3076. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3077. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  3078. if (intel_output->load_detect_temp) {
  3079. encoder->crtc = NULL;
  3080. intel_output->base.encoder = NULL;
  3081. intel_output->load_detect_temp = false;
  3082. crtc->enabled = drm_helper_crtc_in_use(crtc);
  3083. drm_helper_disable_unused_functions(dev);
  3084. }
  3085. /* Switch crtc and output back off if necessary */
  3086. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  3087. if (encoder->crtc == crtc)
  3088. encoder_funcs->dpms(encoder, dpms_mode);
  3089. crtc_funcs->dpms(crtc, dpms_mode);
  3090. }
  3091. }
  3092. /* Returns the clock of the currently programmed mode of the given pipe. */
  3093. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  3094. {
  3095. struct drm_i915_private *dev_priv = dev->dev_private;
  3096. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3097. int pipe = intel_crtc->pipe;
  3098. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  3099. u32 fp;
  3100. intel_clock_t clock;
  3101. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  3102. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  3103. else
  3104. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  3105. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  3106. if (IS_IGD(dev)) {
  3107. clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  3108. clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3109. } else {
  3110. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  3111. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3112. }
  3113. if (IS_I9XX(dev)) {
  3114. if (IS_IGD(dev))
  3115. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
  3116. DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
  3117. else
  3118. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  3119. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3120. switch (dpll & DPLL_MODE_MASK) {
  3121. case DPLLB_MODE_DAC_SERIAL:
  3122. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  3123. 5 : 10;
  3124. break;
  3125. case DPLLB_MODE_LVDS:
  3126. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  3127. 7 : 14;
  3128. break;
  3129. default:
  3130. DRM_DEBUG("Unknown DPLL mode %08x in programmed "
  3131. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  3132. return 0;
  3133. }
  3134. /* XXX: Handle the 100Mhz refclk */
  3135. intel_clock(dev, 96000, &clock);
  3136. } else {
  3137. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  3138. if (is_lvds) {
  3139. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  3140. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3141. clock.p2 = 14;
  3142. if ((dpll & PLL_REF_INPUT_MASK) ==
  3143. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  3144. /* XXX: might not be 66MHz */
  3145. intel_clock(dev, 66000, &clock);
  3146. } else
  3147. intel_clock(dev, 48000, &clock);
  3148. } else {
  3149. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  3150. clock.p1 = 2;
  3151. else {
  3152. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  3153. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  3154. }
  3155. if (dpll & PLL_P2_DIVIDE_BY_4)
  3156. clock.p2 = 4;
  3157. else
  3158. clock.p2 = 2;
  3159. intel_clock(dev, 48000, &clock);
  3160. }
  3161. }
  3162. /* XXX: It would be nice to validate the clocks, but we can't reuse
  3163. * i830PllIsValid() because it relies on the xf86_config connector
  3164. * configuration being accurate, which it isn't necessarily.
  3165. */
  3166. return clock.dot;
  3167. }
  3168. /** Returns the currently programmed mode of the given pipe. */
  3169. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  3170. struct drm_crtc *crtc)
  3171. {
  3172. struct drm_i915_private *dev_priv = dev->dev_private;
  3173. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3174. int pipe = intel_crtc->pipe;
  3175. struct drm_display_mode *mode;
  3176. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  3177. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  3178. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  3179. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  3180. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  3181. if (!mode)
  3182. return NULL;
  3183. mode->clock = intel_crtc_clock_get(dev, crtc);
  3184. mode->hdisplay = (htot & 0xffff) + 1;
  3185. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  3186. mode->hsync_start = (hsync & 0xffff) + 1;
  3187. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  3188. mode->vdisplay = (vtot & 0xffff) + 1;
  3189. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  3190. mode->vsync_start = (vsync & 0xffff) + 1;
  3191. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  3192. drm_mode_set_name(mode);
  3193. drm_mode_set_crtcinfo(mode, 0);
  3194. return mode;
  3195. }
  3196. #define GPU_IDLE_TIMEOUT 500 /* ms */
  3197. /* When this timer fires, we've been idle for awhile */
  3198. static void intel_gpu_idle_timer(unsigned long arg)
  3199. {
  3200. struct drm_device *dev = (struct drm_device *)arg;
  3201. drm_i915_private_t *dev_priv = dev->dev_private;
  3202. DRM_DEBUG("idle timer fired, downclocking\n");
  3203. dev_priv->busy = false;
  3204. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3205. }
  3206. void intel_increase_renderclock(struct drm_device *dev, bool schedule)
  3207. {
  3208. drm_i915_private_t *dev_priv = dev->dev_private;
  3209. if (IS_IGDNG(dev))
  3210. return;
  3211. if (!dev_priv->render_reclock_avail) {
  3212. DRM_DEBUG("not reclocking render clock\n");
  3213. return;
  3214. }
  3215. /* Restore render clock frequency to original value */
  3216. if (IS_G4X(dev) || IS_I9XX(dev))
  3217. pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
  3218. else if (IS_I85X(dev))
  3219. pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
  3220. DRM_DEBUG("increasing render clock frequency\n");
  3221. /* Schedule downclock */
  3222. if (schedule)
  3223. mod_timer(&dev_priv->idle_timer, jiffies +
  3224. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  3225. }
  3226. void intel_decrease_renderclock(struct drm_device *dev)
  3227. {
  3228. drm_i915_private_t *dev_priv = dev->dev_private;
  3229. if (IS_IGDNG(dev))
  3230. return;
  3231. if (!dev_priv->render_reclock_avail) {
  3232. DRM_DEBUG("not reclocking render clock\n");
  3233. return;
  3234. }
  3235. if (IS_G4X(dev)) {
  3236. u16 gcfgc;
  3237. /* Adjust render clock... */
  3238. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3239. /* Down to minimum... */
  3240. gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
  3241. gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
  3242. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3243. } else if (IS_I965G(dev)) {
  3244. u16 gcfgc;
  3245. /* Adjust render clock... */
  3246. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3247. /* Down to minimum... */
  3248. gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
  3249. gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
  3250. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3251. } else if (IS_I945G(dev) || IS_I945GM(dev)) {
  3252. u16 gcfgc;
  3253. /* Adjust render clock... */
  3254. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3255. /* Down to minimum... */
  3256. gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
  3257. gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
  3258. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3259. } else if (IS_I915G(dev)) {
  3260. u16 gcfgc;
  3261. /* Adjust render clock... */
  3262. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3263. /* Down to minimum... */
  3264. gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
  3265. gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
  3266. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3267. } else if (IS_I85X(dev)) {
  3268. u16 hpllcc;
  3269. /* Adjust render clock... */
  3270. pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
  3271. /* Up to maximum... */
  3272. hpllcc &= ~GC_CLOCK_CONTROL_MASK;
  3273. hpllcc |= GC_CLOCK_133_200;
  3274. pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
  3275. }
  3276. DRM_DEBUG("decreasing render clock frequency\n");
  3277. }
  3278. /* Note that no increase function is needed for this - increase_renderclock()
  3279. * will also rewrite these bits
  3280. */
  3281. void intel_decrease_displayclock(struct drm_device *dev)
  3282. {
  3283. if (IS_IGDNG(dev))
  3284. return;
  3285. if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
  3286. IS_I915GM(dev)) {
  3287. u16 gcfgc;
  3288. /* Adjust render clock... */
  3289. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3290. /* Down to minimum... */
  3291. gcfgc &= ~0xf0;
  3292. gcfgc |= 0x80;
  3293. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3294. }
  3295. }
  3296. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  3297. static void intel_crtc_idle_timer(unsigned long arg)
  3298. {
  3299. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  3300. struct drm_crtc *crtc = &intel_crtc->base;
  3301. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  3302. DRM_DEBUG("idle timer fired, downclocking\n");
  3303. intel_crtc->busy = false;
  3304. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3305. }
  3306. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
  3307. {
  3308. struct drm_device *dev = crtc->dev;
  3309. drm_i915_private_t *dev_priv = dev->dev_private;
  3310. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3311. int pipe = intel_crtc->pipe;
  3312. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3313. int dpll = I915_READ(dpll_reg);
  3314. if (IS_IGDNG(dev))
  3315. return;
  3316. if (!dev_priv->lvds_downclock_avail)
  3317. return;
  3318. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  3319. DRM_DEBUG("upclocking LVDS\n");
  3320. /* Unlock panel regs */
  3321. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3322. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  3323. I915_WRITE(dpll_reg, dpll);
  3324. dpll = I915_READ(dpll_reg);
  3325. intel_wait_for_vblank(dev);
  3326. dpll = I915_READ(dpll_reg);
  3327. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  3328. DRM_DEBUG("failed to upclock LVDS!\n");
  3329. /* ...and lock them again */
  3330. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3331. }
  3332. /* Schedule downclock */
  3333. if (schedule)
  3334. mod_timer(&intel_crtc->idle_timer, jiffies +
  3335. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3336. }
  3337. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  3338. {
  3339. struct drm_device *dev = crtc->dev;
  3340. drm_i915_private_t *dev_priv = dev->dev_private;
  3341. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3342. int pipe = intel_crtc->pipe;
  3343. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3344. int dpll = I915_READ(dpll_reg);
  3345. if (IS_IGDNG(dev))
  3346. return;
  3347. if (!dev_priv->lvds_downclock_avail)
  3348. return;
  3349. /*
  3350. * Since this is called by a timer, we should never get here in
  3351. * the manual case.
  3352. */
  3353. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  3354. DRM_DEBUG("downclocking LVDS\n");
  3355. /* Unlock panel regs */
  3356. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3357. dpll |= DISPLAY_RATE_SELECT_FPA1;
  3358. I915_WRITE(dpll_reg, dpll);
  3359. dpll = I915_READ(dpll_reg);
  3360. intel_wait_for_vblank(dev);
  3361. dpll = I915_READ(dpll_reg);
  3362. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  3363. DRM_DEBUG("failed to downclock LVDS!\n");
  3364. /* ...and lock them again */
  3365. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3366. }
  3367. }
  3368. /**
  3369. * intel_idle_update - adjust clocks for idleness
  3370. * @work: work struct
  3371. *
  3372. * Either the GPU or display (or both) went idle. Check the busy status
  3373. * here and adjust the CRTC and GPU clocks as necessary.
  3374. */
  3375. static void intel_idle_update(struct work_struct *work)
  3376. {
  3377. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  3378. idle_work);
  3379. struct drm_device *dev = dev_priv->dev;
  3380. struct drm_crtc *crtc;
  3381. struct intel_crtc *intel_crtc;
  3382. if (!i915_powersave)
  3383. return;
  3384. mutex_lock(&dev->struct_mutex);
  3385. /* GPU isn't processing, downclock it. */
  3386. if (!dev_priv->busy) {
  3387. intel_decrease_renderclock(dev);
  3388. intel_decrease_displayclock(dev);
  3389. }
  3390. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3391. /* Skip inactive CRTCs */
  3392. if (!crtc->fb)
  3393. continue;
  3394. intel_crtc = to_intel_crtc(crtc);
  3395. if (!intel_crtc->busy)
  3396. intel_decrease_pllclock(crtc);
  3397. }
  3398. mutex_unlock(&dev->struct_mutex);
  3399. }
  3400. /**
  3401. * intel_mark_busy - mark the GPU and possibly the display busy
  3402. * @dev: drm device
  3403. * @obj: object we're operating on
  3404. *
  3405. * Callers can use this function to indicate that the GPU is busy processing
  3406. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  3407. * buffer), we'll also mark the display as busy, so we know to increase its
  3408. * clock frequency.
  3409. */
  3410. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  3411. {
  3412. drm_i915_private_t *dev_priv = dev->dev_private;
  3413. struct drm_crtc *crtc = NULL;
  3414. struct intel_framebuffer *intel_fb;
  3415. struct intel_crtc *intel_crtc;
  3416. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  3417. return;
  3418. dev_priv->busy = true;
  3419. intel_increase_renderclock(dev, true);
  3420. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3421. if (!crtc->fb)
  3422. continue;
  3423. intel_crtc = to_intel_crtc(crtc);
  3424. intel_fb = to_intel_framebuffer(crtc->fb);
  3425. if (intel_fb->obj == obj) {
  3426. if (!intel_crtc->busy) {
  3427. /* Non-busy -> busy, upclock */
  3428. intel_increase_pllclock(crtc, true);
  3429. intel_crtc->busy = true;
  3430. } else {
  3431. /* Busy -> busy, put off timer */
  3432. mod_timer(&intel_crtc->idle_timer, jiffies +
  3433. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3434. }
  3435. }
  3436. }
  3437. }
  3438. static void intel_crtc_destroy(struct drm_crtc *crtc)
  3439. {
  3440. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3441. drm_crtc_cleanup(crtc);
  3442. kfree(intel_crtc);
  3443. }
  3444. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  3445. .dpms = intel_crtc_dpms,
  3446. .mode_fixup = intel_crtc_mode_fixup,
  3447. .mode_set = intel_crtc_mode_set,
  3448. .mode_set_base = intel_pipe_set_base,
  3449. .prepare = intel_crtc_prepare,
  3450. .commit = intel_crtc_commit,
  3451. .load_lut = intel_crtc_load_lut,
  3452. };
  3453. static const struct drm_crtc_funcs intel_crtc_funcs = {
  3454. .cursor_set = intel_crtc_cursor_set,
  3455. .cursor_move = intel_crtc_cursor_move,
  3456. .gamma_set = intel_crtc_gamma_set,
  3457. .set_config = drm_crtc_helper_set_config,
  3458. .destroy = intel_crtc_destroy,
  3459. };
  3460. static void intel_crtc_init(struct drm_device *dev, int pipe)
  3461. {
  3462. struct intel_crtc *intel_crtc;
  3463. int i;
  3464. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  3465. if (intel_crtc == NULL)
  3466. return;
  3467. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  3468. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  3469. intel_crtc->pipe = pipe;
  3470. intel_crtc->plane = pipe;
  3471. for (i = 0; i < 256; i++) {
  3472. intel_crtc->lut_r[i] = i;
  3473. intel_crtc->lut_g[i] = i;
  3474. intel_crtc->lut_b[i] = i;
  3475. }
  3476. /* Swap pipes & planes for FBC on pre-965 */
  3477. intel_crtc->pipe = pipe;
  3478. intel_crtc->plane = pipe;
  3479. if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
  3480. DRM_DEBUG("swapping pipes & planes for FBC\n");
  3481. intel_crtc->plane = ((pipe == 0) ? 1 : 0);
  3482. }
  3483. intel_crtc->cursor_addr = 0;
  3484. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  3485. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  3486. intel_crtc->busy = false;
  3487. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  3488. (unsigned long)intel_crtc);
  3489. }
  3490. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  3491. struct drm_file *file_priv)
  3492. {
  3493. drm_i915_private_t *dev_priv = dev->dev_private;
  3494. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  3495. struct drm_mode_object *drmmode_obj;
  3496. struct intel_crtc *crtc;
  3497. if (!dev_priv) {
  3498. DRM_ERROR("called with no initialization\n");
  3499. return -EINVAL;
  3500. }
  3501. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  3502. DRM_MODE_OBJECT_CRTC);
  3503. if (!drmmode_obj) {
  3504. DRM_ERROR("no such CRTC id\n");
  3505. return -EINVAL;
  3506. }
  3507. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  3508. pipe_from_crtc_id->pipe = crtc->pipe;
  3509. return 0;
  3510. }
  3511. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  3512. {
  3513. struct drm_crtc *crtc = NULL;
  3514. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3515. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3516. if (intel_crtc->pipe == pipe)
  3517. break;
  3518. }
  3519. return crtc;
  3520. }
  3521. static int intel_connector_clones(struct drm_device *dev, int type_mask)
  3522. {
  3523. int index_mask = 0;
  3524. struct drm_connector *connector;
  3525. int entry = 0;
  3526. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3527. struct intel_output *intel_output = to_intel_output(connector);
  3528. if (type_mask & intel_output->clone_mask)
  3529. index_mask |= (1 << entry);
  3530. entry++;
  3531. }
  3532. return index_mask;
  3533. }
  3534. static void intel_setup_outputs(struct drm_device *dev)
  3535. {
  3536. struct drm_i915_private *dev_priv = dev->dev_private;
  3537. struct drm_connector *connector;
  3538. intel_crt_init(dev);
  3539. /* Set up integrated LVDS */
  3540. if (IS_MOBILE(dev) && !IS_I830(dev))
  3541. intel_lvds_init(dev);
  3542. if (IS_IGDNG(dev)) {
  3543. int found;
  3544. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  3545. intel_dp_init(dev, DP_A);
  3546. if (I915_READ(HDMIB) & PORT_DETECTED) {
  3547. /* check SDVOB */
  3548. /* found = intel_sdvo_init(dev, HDMIB); */
  3549. found = 0;
  3550. if (!found)
  3551. intel_hdmi_init(dev, HDMIB);
  3552. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  3553. intel_dp_init(dev, PCH_DP_B);
  3554. }
  3555. if (I915_READ(HDMIC) & PORT_DETECTED)
  3556. intel_hdmi_init(dev, HDMIC);
  3557. if (I915_READ(HDMID) & PORT_DETECTED)
  3558. intel_hdmi_init(dev, HDMID);
  3559. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  3560. intel_dp_init(dev, PCH_DP_C);
  3561. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  3562. intel_dp_init(dev, PCH_DP_D);
  3563. } else if (IS_I9XX(dev)) {
  3564. bool found = false;
  3565. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  3566. found = intel_sdvo_init(dev, SDVOB);
  3567. if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
  3568. intel_hdmi_init(dev, SDVOB);
  3569. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  3570. intel_dp_init(dev, DP_B);
  3571. }
  3572. /* Before G4X SDVOC doesn't have its own detect register */
  3573. if (I915_READ(SDVOB) & SDVO_DETECTED)
  3574. found = intel_sdvo_init(dev, SDVOC);
  3575. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  3576. if (SUPPORTS_INTEGRATED_HDMI(dev))
  3577. intel_hdmi_init(dev, SDVOC);
  3578. if (SUPPORTS_INTEGRATED_DP(dev))
  3579. intel_dp_init(dev, DP_C);
  3580. }
  3581. if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
  3582. intel_dp_init(dev, DP_D);
  3583. } else
  3584. intel_dvo_init(dev);
  3585. if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
  3586. intel_tv_init(dev);
  3587. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3588. struct intel_output *intel_output = to_intel_output(connector);
  3589. struct drm_encoder *encoder = &intel_output->enc;
  3590. encoder->possible_crtcs = intel_output->crtc_mask;
  3591. encoder->possible_clones = intel_connector_clones(dev,
  3592. intel_output->clone_mask);
  3593. }
  3594. }
  3595. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  3596. {
  3597. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  3598. struct drm_device *dev = fb->dev;
  3599. if (fb->fbdev)
  3600. intelfb_remove(dev, fb);
  3601. drm_framebuffer_cleanup(fb);
  3602. mutex_lock(&dev->struct_mutex);
  3603. drm_gem_object_unreference(intel_fb->obj);
  3604. mutex_unlock(&dev->struct_mutex);
  3605. kfree(intel_fb);
  3606. }
  3607. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  3608. struct drm_file *file_priv,
  3609. unsigned int *handle)
  3610. {
  3611. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  3612. struct drm_gem_object *object = intel_fb->obj;
  3613. return drm_gem_handle_create(file_priv, object, handle);
  3614. }
  3615. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  3616. .destroy = intel_user_framebuffer_destroy,
  3617. .create_handle = intel_user_framebuffer_create_handle,
  3618. };
  3619. int intel_framebuffer_create(struct drm_device *dev,
  3620. struct drm_mode_fb_cmd *mode_cmd,
  3621. struct drm_framebuffer **fb,
  3622. struct drm_gem_object *obj)
  3623. {
  3624. struct intel_framebuffer *intel_fb;
  3625. int ret;
  3626. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  3627. if (!intel_fb)
  3628. return -ENOMEM;
  3629. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  3630. if (ret) {
  3631. DRM_ERROR("framebuffer init failed %d\n", ret);
  3632. return ret;
  3633. }
  3634. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  3635. intel_fb->obj = obj;
  3636. *fb = &intel_fb->base;
  3637. return 0;
  3638. }
  3639. static struct drm_framebuffer *
  3640. intel_user_framebuffer_create(struct drm_device *dev,
  3641. struct drm_file *filp,
  3642. struct drm_mode_fb_cmd *mode_cmd)
  3643. {
  3644. struct drm_gem_object *obj;
  3645. struct drm_framebuffer *fb;
  3646. int ret;
  3647. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  3648. if (!obj)
  3649. return NULL;
  3650. ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
  3651. if (ret) {
  3652. mutex_lock(&dev->struct_mutex);
  3653. drm_gem_object_unreference(obj);
  3654. mutex_unlock(&dev->struct_mutex);
  3655. return NULL;
  3656. }
  3657. return fb;
  3658. }
  3659. static const struct drm_mode_config_funcs intel_mode_funcs = {
  3660. .fb_create = intel_user_framebuffer_create,
  3661. .fb_changed = intelfb_probe,
  3662. };
  3663. void intel_init_clock_gating(struct drm_device *dev)
  3664. {
  3665. struct drm_i915_private *dev_priv = dev->dev_private;
  3666. /*
  3667. * Disable clock gating reported to work incorrectly according to the
  3668. * specs, but enable as much else as we can.
  3669. */
  3670. if (IS_IGDNG(dev)) {
  3671. return;
  3672. } else if (IS_G4X(dev)) {
  3673. uint32_t dspclk_gate;
  3674. I915_WRITE(RENCLK_GATE_D1, 0);
  3675. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  3676. GS_UNIT_CLOCK_GATE_DISABLE |
  3677. CL_UNIT_CLOCK_GATE_DISABLE);
  3678. I915_WRITE(RAMCLK_GATE_D, 0);
  3679. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  3680. OVRUNIT_CLOCK_GATE_DISABLE |
  3681. OVCUNIT_CLOCK_GATE_DISABLE;
  3682. if (IS_GM45(dev))
  3683. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  3684. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  3685. } else if (IS_I965GM(dev)) {
  3686. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  3687. I915_WRITE(RENCLK_GATE_D2, 0);
  3688. I915_WRITE(DSPCLK_GATE_D, 0);
  3689. I915_WRITE(RAMCLK_GATE_D, 0);
  3690. I915_WRITE16(DEUC, 0);
  3691. } else if (IS_I965G(dev)) {
  3692. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  3693. I965_RCC_CLOCK_GATE_DISABLE |
  3694. I965_RCPB_CLOCK_GATE_DISABLE |
  3695. I965_ISC_CLOCK_GATE_DISABLE |
  3696. I965_FBC_CLOCK_GATE_DISABLE);
  3697. I915_WRITE(RENCLK_GATE_D2, 0);
  3698. } else if (IS_I9XX(dev)) {
  3699. u32 dstate = I915_READ(D_STATE);
  3700. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  3701. DSTATE_DOT_CLOCK_GATING;
  3702. I915_WRITE(D_STATE, dstate);
  3703. } else if (IS_I855(dev) || IS_I865G(dev)) {
  3704. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  3705. } else if (IS_I830(dev)) {
  3706. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  3707. }
  3708. }
  3709. /* Set up chip specific display functions */
  3710. static void intel_init_display(struct drm_device *dev)
  3711. {
  3712. struct drm_i915_private *dev_priv = dev->dev_private;
  3713. /* We always want a DPMS function */
  3714. if (IS_IGDNG(dev))
  3715. dev_priv->display.dpms = igdng_crtc_dpms;
  3716. else
  3717. dev_priv->display.dpms = i9xx_crtc_dpms;
  3718. /* Only mobile has FBC, leave pointers NULL for other chips */
  3719. if (IS_MOBILE(dev)) {
  3720. if (IS_GM45(dev)) {
  3721. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  3722. dev_priv->display.enable_fbc = g4x_enable_fbc;
  3723. dev_priv->display.disable_fbc = g4x_disable_fbc;
  3724. } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
  3725. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  3726. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  3727. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  3728. }
  3729. /* 855GM needs testing */
  3730. }
  3731. /* Returns the core display clock speed */
  3732. if (IS_I945G(dev))
  3733. dev_priv->display.get_display_clock_speed =
  3734. i945_get_display_clock_speed;
  3735. else if (IS_I915G(dev))
  3736. dev_priv->display.get_display_clock_speed =
  3737. i915_get_display_clock_speed;
  3738. else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
  3739. dev_priv->display.get_display_clock_speed =
  3740. i9xx_misc_get_display_clock_speed;
  3741. else if (IS_I915GM(dev))
  3742. dev_priv->display.get_display_clock_speed =
  3743. i915gm_get_display_clock_speed;
  3744. else if (IS_I865G(dev))
  3745. dev_priv->display.get_display_clock_speed =
  3746. i865_get_display_clock_speed;
  3747. else if (IS_I855(dev))
  3748. dev_priv->display.get_display_clock_speed =
  3749. i855_get_display_clock_speed;
  3750. else /* 852, 830 */
  3751. dev_priv->display.get_display_clock_speed =
  3752. i830_get_display_clock_speed;
  3753. /* For FIFO watermark updates */
  3754. if (IS_IGDNG(dev))
  3755. dev_priv->display.update_wm = NULL;
  3756. else if (IS_G4X(dev))
  3757. dev_priv->display.update_wm = g4x_update_wm;
  3758. else if (IS_I965G(dev))
  3759. dev_priv->display.update_wm = i965_update_wm;
  3760. else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
  3761. dev_priv->display.update_wm = i9xx_update_wm;
  3762. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  3763. } else {
  3764. if (IS_I85X(dev))
  3765. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  3766. else if (IS_845G(dev))
  3767. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  3768. else
  3769. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3770. dev_priv->display.update_wm = i830_update_wm;
  3771. }
  3772. }
  3773. void intel_modeset_init(struct drm_device *dev)
  3774. {
  3775. struct drm_i915_private *dev_priv = dev->dev_private;
  3776. int num_pipe;
  3777. int i;
  3778. drm_mode_config_init(dev);
  3779. dev->mode_config.min_width = 0;
  3780. dev->mode_config.min_height = 0;
  3781. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  3782. intel_init_display(dev);
  3783. if (IS_I965G(dev)) {
  3784. dev->mode_config.max_width = 8192;
  3785. dev->mode_config.max_height = 8192;
  3786. } else if (IS_I9XX(dev)) {
  3787. dev->mode_config.max_width = 4096;
  3788. dev->mode_config.max_height = 4096;
  3789. } else {
  3790. dev->mode_config.max_width = 2048;
  3791. dev->mode_config.max_height = 2048;
  3792. }
  3793. /* set memory base */
  3794. if (IS_I9XX(dev))
  3795. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  3796. else
  3797. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  3798. if (IS_MOBILE(dev) || IS_I9XX(dev))
  3799. num_pipe = 2;
  3800. else
  3801. num_pipe = 1;
  3802. DRM_DEBUG("%d display pipe%s available.\n",
  3803. num_pipe, num_pipe > 1 ? "s" : "");
  3804. if (IS_I85X(dev))
  3805. pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
  3806. else if (IS_I9XX(dev) || IS_G4X(dev))
  3807. pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
  3808. for (i = 0; i < num_pipe; i++) {
  3809. intel_crtc_init(dev, i);
  3810. }
  3811. intel_setup_outputs(dev);
  3812. intel_init_clock_gating(dev);
  3813. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  3814. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  3815. (unsigned long)dev);
  3816. }
  3817. void intel_modeset_cleanup(struct drm_device *dev)
  3818. {
  3819. struct drm_i915_private *dev_priv = dev->dev_private;
  3820. struct drm_crtc *crtc;
  3821. struct intel_crtc *intel_crtc;
  3822. mutex_lock(&dev->struct_mutex);
  3823. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3824. /* Skip inactive CRTCs */
  3825. if (!crtc->fb)
  3826. continue;
  3827. intel_crtc = to_intel_crtc(crtc);
  3828. intel_increase_pllclock(crtc, false);
  3829. del_timer_sync(&intel_crtc->idle_timer);
  3830. }
  3831. intel_increase_renderclock(dev, false);
  3832. del_timer_sync(&dev_priv->idle_timer);
  3833. mutex_unlock(&dev->struct_mutex);
  3834. if (dev_priv->display.disable_fbc)
  3835. dev_priv->display.disable_fbc(dev);
  3836. drm_mode_config_cleanup(dev);
  3837. }
  3838. /* current intel driver doesn't take advantage of encoders
  3839. always give back the encoder for the connector
  3840. */
  3841. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  3842. {
  3843. struct intel_output *intel_output = to_intel_output(connector);
  3844. return &intel_output->enc;
  3845. }
  3846. /*
  3847. * set vga decode state - true == enable VGA decode
  3848. */
  3849. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  3850. {
  3851. struct drm_i915_private *dev_priv = dev->dev_private;
  3852. u16 gmch_ctrl;
  3853. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  3854. if (state)
  3855. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  3856. else
  3857. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  3858. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  3859. return 0;
  3860. }