swim3.c 29 KB

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  1. /*
  2. * Driver for the SWIM3 (Super Woz Integrated Machine 3)
  3. * floppy controller found on Power Macintoshes.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. /*
  13. * TODO:
  14. * handle 2 drives
  15. * handle GCR disks
  16. */
  17. #include <linux/stddef.h>
  18. #include <linux/kernel.h>
  19. #include <linux/sched.h>
  20. #include <linux/timer.h>
  21. #include <linux/delay.h>
  22. #include <linux/fd.h>
  23. #include <linux/ioctl.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/spinlock.h>
  28. #include <asm/io.h>
  29. #include <asm/dbdma.h>
  30. #include <asm/prom.h>
  31. #include <asm/uaccess.h>
  32. #include <asm/mediabay.h>
  33. #include <asm/machdep.h>
  34. #include <asm/pmac_feature.h>
  35. static struct request_queue *swim3_queue;
  36. static struct gendisk *disks[2];
  37. static struct request *fd_req;
  38. #define MAX_FLOPPIES 2
  39. enum swim_state {
  40. idle,
  41. locating,
  42. seeking,
  43. settling,
  44. do_transfer,
  45. jogging,
  46. available,
  47. revalidating,
  48. ejecting
  49. };
  50. #define REG(x) unsigned char x; char x ## _pad[15];
  51. /*
  52. * The names for these registers mostly represent speculation on my part.
  53. * It will be interesting to see how close they are to the names Apple uses.
  54. */
  55. struct swim3 {
  56. REG(data);
  57. REG(timer); /* counts down at 1MHz */
  58. REG(error);
  59. REG(mode);
  60. REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
  61. REG(setup);
  62. REG(control); /* writing bits clears them */
  63. REG(status); /* writing bits sets them in control */
  64. REG(intr);
  65. REG(nseek); /* # tracks to seek */
  66. REG(ctrack); /* current track number */
  67. REG(csect); /* current sector number */
  68. REG(gap3); /* size of gap 3 in track format */
  69. REG(sector); /* sector # to read or write */
  70. REG(nsect); /* # sectors to read or write */
  71. REG(intr_enable);
  72. };
  73. #define control_bic control
  74. #define control_bis status
  75. /* Bits in select register */
  76. #define CA_MASK 7
  77. #define LSTRB 8
  78. /* Bits in control register */
  79. #define DO_SEEK 0x80
  80. #define FORMAT 0x40
  81. #define SELECT 0x20
  82. #define WRITE_SECTORS 0x10
  83. #define DO_ACTION 0x08
  84. #define DRIVE2_ENABLE 0x04
  85. #define DRIVE_ENABLE 0x02
  86. #define INTR_ENABLE 0x01
  87. /* Bits in status register */
  88. #define FIFO_1BYTE 0x80
  89. #define FIFO_2BYTE 0x40
  90. #define ERROR 0x20
  91. #define DATA 0x08
  92. #define RDDATA 0x04
  93. #define INTR_PENDING 0x02
  94. #define MARK_BYTE 0x01
  95. /* Bits in intr and intr_enable registers */
  96. #define ERROR_INTR 0x20
  97. #define DATA_CHANGED 0x10
  98. #define TRANSFER_DONE 0x08
  99. #define SEEN_SECTOR 0x04
  100. #define SEEK_DONE 0x02
  101. #define TIMER_DONE 0x01
  102. /* Bits in error register */
  103. #define ERR_DATA_CRC 0x80
  104. #define ERR_ADDR_CRC 0x40
  105. #define ERR_OVERRUN 0x04
  106. #define ERR_UNDERRUN 0x01
  107. /* Bits in setup register */
  108. #define S_SW_RESET 0x80
  109. #define S_GCR_WRITE 0x40
  110. #define S_IBM_DRIVE 0x20
  111. #define S_TEST_MODE 0x10
  112. #define S_FCLK_DIV2 0x08
  113. #define S_GCR 0x04
  114. #define S_COPY_PROT 0x02
  115. #define S_INV_WDATA 0x01
  116. /* Select values for swim3_action */
  117. #define SEEK_POSITIVE 0
  118. #define SEEK_NEGATIVE 4
  119. #define STEP 1
  120. #define MOTOR_ON 2
  121. #define MOTOR_OFF 6
  122. #define INDEX 3
  123. #define EJECT 7
  124. #define SETMFM 9
  125. #define SETGCR 13
  126. /* Select values for swim3_select and swim3_readbit */
  127. #define STEP_DIR 0
  128. #define STEPPING 1
  129. #define MOTOR_ON 2
  130. #define RELAX 3 /* also eject in progress */
  131. #define READ_DATA_0 4
  132. #define TWOMEG_DRIVE 5
  133. #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */
  134. #define DRIVE_PRESENT 7
  135. #define DISK_IN 8
  136. #define WRITE_PROT 9
  137. #define TRACK_ZERO 10
  138. #define TACHO 11
  139. #define READ_DATA_1 12
  140. #define MFM_MODE 13
  141. #define SEEK_COMPLETE 14
  142. #define ONEMEG_MEDIA 15
  143. /* Definitions of values used in writing and formatting */
  144. #define DATA_ESCAPE 0x99
  145. #define GCR_SYNC_EXC 0x3f
  146. #define GCR_SYNC_CONV 0x80
  147. #define GCR_FIRST_MARK 0xd5
  148. #define GCR_SECOND_MARK 0xaa
  149. #define GCR_ADDR_MARK "\xd5\xaa\x00"
  150. #define GCR_DATA_MARK "\xd5\xaa\x0b"
  151. #define GCR_SLIP_BYTE "\x27\xaa"
  152. #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f"
  153. #define DATA_99 "\x99\x99"
  154. #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
  155. #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
  156. #define MFM_GAP_LEN 12
  157. struct floppy_state {
  158. enum swim_state state;
  159. spinlock_t lock;
  160. struct swim3 __iomem *swim3; /* hardware registers */
  161. struct dbdma_regs __iomem *dma; /* DMA controller registers */
  162. int swim3_intr; /* interrupt number for SWIM3 */
  163. int dma_intr; /* interrupt number for DMA channel */
  164. int cur_cyl; /* cylinder head is on, or -1 */
  165. int cur_sector; /* last sector we saw go past */
  166. int req_cyl; /* the cylinder for the current r/w request */
  167. int head; /* head number ditto */
  168. int req_sector; /* sector number ditto */
  169. int scount; /* # sectors we're transferring at present */
  170. int retries;
  171. int settle_time;
  172. int secpercyl; /* disk geometry information */
  173. int secpertrack;
  174. int total_secs;
  175. int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
  176. struct dbdma_cmd *dma_cmd;
  177. int ref_count;
  178. int expect_cyl;
  179. struct timer_list timeout;
  180. int timeout_pending;
  181. int ejected;
  182. wait_queue_head_t wait;
  183. int wanted;
  184. struct device_node* media_bay; /* NULL when not in bay */
  185. char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
  186. };
  187. static struct floppy_state floppy_states[MAX_FLOPPIES];
  188. static int floppy_count = 0;
  189. static DEFINE_SPINLOCK(swim3_lock);
  190. static unsigned short write_preamble[] = {
  191. 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
  192. 0, 0, 0, 0, 0, 0, /* sync field */
  193. 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */
  194. 0x990f /* no escape for 512 bytes */
  195. };
  196. static unsigned short write_postamble[] = {
  197. 0x9904, /* insert CRC */
  198. 0x4e4e, 0x4e4e,
  199. 0x9908, /* stop writing */
  200. 0, 0, 0, 0, 0, 0
  201. };
  202. static void swim3_select(struct floppy_state *fs, int sel);
  203. static void swim3_action(struct floppy_state *fs, int action);
  204. static int swim3_readbit(struct floppy_state *fs, int bit);
  205. static void do_fd_request(struct request_queue * q);
  206. static void start_request(struct floppy_state *fs);
  207. static void set_timeout(struct floppy_state *fs, int nticks,
  208. void (*proc)(unsigned long));
  209. static void scan_track(struct floppy_state *fs);
  210. static void seek_track(struct floppy_state *fs, int n);
  211. static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count);
  212. static void setup_transfer(struct floppy_state *fs);
  213. static void act(struct floppy_state *fs);
  214. static void scan_timeout(unsigned long data);
  215. static void seek_timeout(unsigned long data);
  216. static void settle_timeout(unsigned long data);
  217. static void xfer_timeout(unsigned long data);
  218. static irqreturn_t swim3_interrupt(int irq, void *dev_id);
  219. /*static void fd_dma_interrupt(int irq, void *dev_id);*/
  220. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  221. int interruptible);
  222. static void release_drive(struct floppy_state *fs);
  223. static int fd_eject(struct floppy_state *fs);
  224. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  225. unsigned int cmd, unsigned long param);
  226. static int floppy_open(struct block_device *bdev, fmode_t mode);
  227. static int floppy_release(struct gendisk *disk, fmode_t mode);
  228. static int floppy_check_change(struct gendisk *disk);
  229. static int floppy_revalidate(struct gendisk *disk);
  230. static bool swim3_end_request(int err, unsigned int nr_bytes)
  231. {
  232. if (__blk_end_request(fd_req, err, nr_bytes))
  233. return true;
  234. fd_req = NULL;
  235. return false;
  236. }
  237. static bool swim3_end_request_cur(int err)
  238. {
  239. return swim3_end_request(err, blk_rq_cur_bytes(fd_req));
  240. }
  241. static void swim3_select(struct floppy_state *fs, int sel)
  242. {
  243. struct swim3 __iomem *sw = fs->swim3;
  244. out_8(&sw->select, RELAX);
  245. if (sel & 8)
  246. out_8(&sw->control_bis, SELECT);
  247. else
  248. out_8(&sw->control_bic, SELECT);
  249. out_8(&sw->select, sel & CA_MASK);
  250. }
  251. static void swim3_action(struct floppy_state *fs, int action)
  252. {
  253. struct swim3 __iomem *sw = fs->swim3;
  254. swim3_select(fs, action);
  255. udelay(1);
  256. out_8(&sw->select, sw->select | LSTRB);
  257. udelay(2);
  258. out_8(&sw->select, sw->select & ~LSTRB);
  259. udelay(1);
  260. }
  261. static int swim3_readbit(struct floppy_state *fs, int bit)
  262. {
  263. struct swim3 __iomem *sw = fs->swim3;
  264. int stat;
  265. swim3_select(fs, bit);
  266. udelay(1);
  267. stat = in_8(&sw->status);
  268. return (stat & DATA) == 0;
  269. }
  270. static void do_fd_request(struct request_queue * q)
  271. {
  272. int i;
  273. for(i=0;i<floppy_count;i++)
  274. {
  275. #ifdef CONFIG_PMAC_MEDIABAY
  276. if (floppy_states[i].media_bay &&
  277. check_media_bay(floppy_states[i].media_bay, MB_FD))
  278. continue;
  279. #endif /* CONFIG_PMAC_MEDIABAY */
  280. start_request(&floppy_states[i]);
  281. }
  282. }
  283. static void start_request(struct floppy_state *fs)
  284. {
  285. struct request *req;
  286. unsigned long x;
  287. if (fs->state == idle && fs->wanted) {
  288. fs->state = available;
  289. wake_up(&fs->wait);
  290. return;
  291. }
  292. while (fs->state == idle) {
  293. if (!fd_req) {
  294. fd_req = blk_fetch_request(swim3_queue);
  295. if (!fd_req)
  296. break;
  297. }
  298. req = fd_req;
  299. #if 0
  300. printk("do_fd_req: dev=%s cmd=%d sec=%ld nr_sec=%u buf=%p\n",
  301. req->rq_disk->disk_name, req->cmd,
  302. (long)blk_rq_pos(req), blk_rq_sectors(req), req->buffer);
  303. printk(" errors=%d current_nr_sectors=%u\n",
  304. req->errors, blk_rq_cur_sectors(req));
  305. #endif
  306. if (blk_rq_pos(req) >= fs->total_secs) {
  307. swim3_end_request_cur(-EIO);
  308. continue;
  309. }
  310. if (fs->ejected) {
  311. swim3_end_request_cur(-EIO);
  312. continue;
  313. }
  314. if (rq_data_dir(req) == WRITE) {
  315. if (fs->write_prot < 0)
  316. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  317. if (fs->write_prot) {
  318. swim3_end_request_cur(-EIO);
  319. continue;
  320. }
  321. }
  322. /* Do not remove the cast. blk_rq_pos(req) is now a
  323. * sector_t and can be 64 bits, but it will never go
  324. * past 32 bits for this driver anyway, so we can
  325. * safely cast it down and not have to do a 64/32
  326. * division
  327. */
  328. fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
  329. x = ((long)blk_rq_pos(req)) % fs->secpercyl;
  330. fs->head = x / fs->secpertrack;
  331. fs->req_sector = x % fs->secpertrack + 1;
  332. fd_req = req;
  333. fs->state = do_transfer;
  334. fs->retries = 0;
  335. act(fs);
  336. }
  337. }
  338. static void set_timeout(struct floppy_state *fs, int nticks,
  339. void (*proc)(unsigned long))
  340. {
  341. unsigned long flags;
  342. spin_lock_irqsave(&fs->lock, flags);
  343. if (fs->timeout_pending)
  344. del_timer(&fs->timeout);
  345. fs->timeout.expires = jiffies + nticks;
  346. fs->timeout.function = proc;
  347. fs->timeout.data = (unsigned long) fs;
  348. add_timer(&fs->timeout);
  349. fs->timeout_pending = 1;
  350. spin_unlock_irqrestore(&fs->lock, flags);
  351. }
  352. static inline void scan_track(struct floppy_state *fs)
  353. {
  354. struct swim3 __iomem *sw = fs->swim3;
  355. swim3_select(fs, READ_DATA_0);
  356. in_8(&sw->intr); /* clear SEEN_SECTOR bit */
  357. in_8(&sw->error);
  358. out_8(&sw->intr_enable, SEEN_SECTOR);
  359. out_8(&sw->control_bis, DO_ACTION);
  360. /* enable intr when track found */
  361. set_timeout(fs, HZ, scan_timeout); /* enable timeout */
  362. }
  363. static inline void seek_track(struct floppy_state *fs, int n)
  364. {
  365. struct swim3 __iomem *sw = fs->swim3;
  366. if (n >= 0) {
  367. swim3_action(fs, SEEK_POSITIVE);
  368. sw->nseek = n;
  369. } else {
  370. swim3_action(fs, SEEK_NEGATIVE);
  371. sw->nseek = -n;
  372. }
  373. fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
  374. swim3_select(fs, STEP);
  375. in_8(&sw->error);
  376. /* enable intr when seek finished */
  377. out_8(&sw->intr_enable, SEEK_DONE);
  378. out_8(&sw->control_bis, DO_SEEK);
  379. set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */
  380. fs->settle_time = 0;
  381. }
  382. static inline void init_dma(struct dbdma_cmd *cp, int cmd,
  383. void *buf, int count)
  384. {
  385. st_le16(&cp->req_count, count);
  386. st_le16(&cp->command, cmd);
  387. st_le32(&cp->phy_addr, virt_to_bus(buf));
  388. cp->xfer_status = 0;
  389. }
  390. static inline void setup_transfer(struct floppy_state *fs)
  391. {
  392. int n;
  393. struct swim3 __iomem *sw = fs->swim3;
  394. struct dbdma_cmd *cp = fs->dma_cmd;
  395. struct dbdma_regs __iomem *dr = fs->dma;
  396. if (blk_rq_cur_sectors(fd_req) <= 0) {
  397. printk(KERN_ERR "swim3: transfer 0 sectors?\n");
  398. return;
  399. }
  400. if (rq_data_dir(fd_req) == WRITE)
  401. n = 1;
  402. else {
  403. n = fs->secpertrack - fs->req_sector + 1;
  404. if (n > blk_rq_cur_sectors(fd_req))
  405. n = blk_rq_cur_sectors(fd_req);
  406. }
  407. fs->scount = n;
  408. swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
  409. out_8(&sw->sector, fs->req_sector);
  410. out_8(&sw->nsect, n);
  411. out_8(&sw->gap3, 0);
  412. out_le32(&dr->cmdptr, virt_to_bus(cp));
  413. if (rq_data_dir(fd_req) == WRITE) {
  414. /* Set up 3 dma commands: write preamble, data, postamble */
  415. init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
  416. ++cp;
  417. init_dma(cp, OUTPUT_MORE, fd_req->buffer, 512);
  418. ++cp;
  419. init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
  420. } else {
  421. init_dma(cp, INPUT_LAST, fd_req->buffer, n * 512);
  422. }
  423. ++cp;
  424. out_le16(&cp->command, DBDMA_STOP);
  425. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  426. in_8(&sw->error);
  427. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  428. if (rq_data_dir(fd_req) == WRITE)
  429. out_8(&sw->control_bis, WRITE_SECTORS);
  430. in_8(&sw->intr);
  431. out_le32(&dr->control, (RUN << 16) | RUN);
  432. /* enable intr when transfer complete */
  433. out_8(&sw->intr_enable, TRANSFER_DONE);
  434. out_8(&sw->control_bis, DO_ACTION);
  435. set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
  436. }
  437. static void act(struct floppy_state *fs)
  438. {
  439. for (;;) {
  440. switch (fs->state) {
  441. case idle:
  442. return; /* XXX shouldn't get here */
  443. case locating:
  444. if (swim3_readbit(fs, TRACK_ZERO)) {
  445. fs->cur_cyl = 0;
  446. if (fs->req_cyl == 0)
  447. fs->state = do_transfer;
  448. else
  449. fs->state = seeking;
  450. break;
  451. }
  452. scan_track(fs);
  453. return;
  454. case seeking:
  455. if (fs->cur_cyl < 0) {
  456. fs->expect_cyl = -1;
  457. fs->state = locating;
  458. break;
  459. }
  460. if (fs->req_cyl == fs->cur_cyl) {
  461. printk("whoops, seeking 0\n");
  462. fs->state = do_transfer;
  463. break;
  464. }
  465. seek_track(fs, fs->req_cyl - fs->cur_cyl);
  466. return;
  467. case settling:
  468. /* check for SEEK_COMPLETE after 30ms */
  469. fs->settle_time = (HZ + 32) / 33;
  470. set_timeout(fs, fs->settle_time, settle_timeout);
  471. return;
  472. case do_transfer:
  473. if (fs->cur_cyl != fs->req_cyl) {
  474. if (fs->retries > 5) {
  475. swim3_end_request_cur(-EIO);
  476. fs->state = idle;
  477. return;
  478. }
  479. fs->state = seeking;
  480. break;
  481. }
  482. setup_transfer(fs);
  483. return;
  484. case jogging:
  485. seek_track(fs, -5);
  486. return;
  487. default:
  488. printk(KERN_ERR"swim3: unknown state %d\n", fs->state);
  489. return;
  490. }
  491. }
  492. }
  493. static void scan_timeout(unsigned long data)
  494. {
  495. struct floppy_state *fs = (struct floppy_state *) data;
  496. struct swim3 __iomem *sw = fs->swim3;
  497. fs->timeout_pending = 0;
  498. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  499. out_8(&sw->select, RELAX);
  500. out_8(&sw->intr_enable, 0);
  501. fs->cur_cyl = -1;
  502. if (fs->retries > 5) {
  503. swim3_end_request_cur(-EIO);
  504. fs->state = idle;
  505. start_request(fs);
  506. } else {
  507. fs->state = jogging;
  508. act(fs);
  509. }
  510. }
  511. static void seek_timeout(unsigned long data)
  512. {
  513. struct floppy_state *fs = (struct floppy_state *) data;
  514. struct swim3 __iomem *sw = fs->swim3;
  515. fs->timeout_pending = 0;
  516. out_8(&sw->control_bic, DO_SEEK);
  517. out_8(&sw->select, RELAX);
  518. out_8(&sw->intr_enable, 0);
  519. printk(KERN_ERR "swim3: seek timeout\n");
  520. swim3_end_request_cur(-EIO);
  521. fs->state = idle;
  522. start_request(fs);
  523. }
  524. static void settle_timeout(unsigned long data)
  525. {
  526. struct floppy_state *fs = (struct floppy_state *) data;
  527. struct swim3 __iomem *sw = fs->swim3;
  528. fs->timeout_pending = 0;
  529. if (swim3_readbit(fs, SEEK_COMPLETE)) {
  530. out_8(&sw->select, RELAX);
  531. fs->state = locating;
  532. act(fs);
  533. return;
  534. }
  535. out_8(&sw->select, RELAX);
  536. if (fs->settle_time < 2*HZ) {
  537. ++fs->settle_time;
  538. set_timeout(fs, 1, settle_timeout);
  539. return;
  540. }
  541. printk(KERN_ERR "swim3: seek settle timeout\n");
  542. swim3_end_request_cur(-EIO);
  543. fs->state = idle;
  544. start_request(fs);
  545. }
  546. static void xfer_timeout(unsigned long data)
  547. {
  548. struct floppy_state *fs = (struct floppy_state *) data;
  549. struct swim3 __iomem *sw = fs->swim3;
  550. struct dbdma_regs __iomem *dr = fs->dma;
  551. int n;
  552. fs->timeout_pending = 0;
  553. out_le32(&dr->control, RUN << 16);
  554. /* We must wait a bit for dbdma to stop */
  555. for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
  556. udelay(1);
  557. out_8(&sw->intr_enable, 0);
  558. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  559. out_8(&sw->select, RELAX);
  560. printk(KERN_ERR "swim3: timeout %sing sector %ld\n",
  561. (rq_data_dir(fd_req)==WRITE? "writ": "read"),
  562. (long)blk_rq_pos(fd_req));
  563. swim3_end_request_cur(-EIO);
  564. fs->state = idle;
  565. start_request(fs);
  566. }
  567. static irqreturn_t swim3_interrupt(int irq, void *dev_id)
  568. {
  569. struct floppy_state *fs = (struct floppy_state *) dev_id;
  570. struct swim3 __iomem *sw = fs->swim3;
  571. int intr, err, n;
  572. int stat, resid;
  573. struct dbdma_regs __iomem *dr;
  574. struct dbdma_cmd *cp;
  575. intr = in_8(&sw->intr);
  576. err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
  577. if ((intr & ERROR_INTR) && fs->state != do_transfer)
  578. printk(KERN_ERR "swim3_interrupt, state=%d, dir=%x, intr=%x, err=%x\n",
  579. fs->state, rq_data_dir(fd_req), intr, err);
  580. switch (fs->state) {
  581. case locating:
  582. if (intr & SEEN_SECTOR) {
  583. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  584. out_8(&sw->select, RELAX);
  585. out_8(&sw->intr_enable, 0);
  586. del_timer(&fs->timeout);
  587. fs->timeout_pending = 0;
  588. if (sw->ctrack == 0xff) {
  589. printk(KERN_ERR "swim3: seen sector but cyl=ff?\n");
  590. fs->cur_cyl = -1;
  591. if (fs->retries > 5) {
  592. swim3_end_request_cur(-EIO);
  593. fs->state = idle;
  594. start_request(fs);
  595. } else {
  596. fs->state = jogging;
  597. act(fs);
  598. }
  599. break;
  600. }
  601. fs->cur_cyl = sw->ctrack;
  602. fs->cur_sector = sw->csect;
  603. if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
  604. printk(KERN_ERR "swim3: expected cyl %d, got %d\n",
  605. fs->expect_cyl, fs->cur_cyl);
  606. fs->state = do_transfer;
  607. act(fs);
  608. }
  609. break;
  610. case seeking:
  611. case jogging:
  612. if (sw->nseek == 0) {
  613. out_8(&sw->control_bic, DO_SEEK);
  614. out_8(&sw->select, RELAX);
  615. out_8(&sw->intr_enable, 0);
  616. del_timer(&fs->timeout);
  617. fs->timeout_pending = 0;
  618. if (fs->state == seeking)
  619. ++fs->retries;
  620. fs->state = settling;
  621. act(fs);
  622. }
  623. break;
  624. case settling:
  625. out_8(&sw->intr_enable, 0);
  626. del_timer(&fs->timeout);
  627. fs->timeout_pending = 0;
  628. act(fs);
  629. break;
  630. case do_transfer:
  631. if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
  632. break;
  633. out_8(&sw->intr_enable, 0);
  634. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  635. out_8(&sw->select, RELAX);
  636. del_timer(&fs->timeout);
  637. fs->timeout_pending = 0;
  638. dr = fs->dma;
  639. cp = fs->dma_cmd;
  640. if (rq_data_dir(fd_req) == WRITE)
  641. ++cp;
  642. /*
  643. * Check that the main data transfer has finished.
  644. * On writing, the swim3 sometimes doesn't use
  645. * up all the bytes of the postamble, so we can still
  646. * see DMA active here. That doesn't matter as long
  647. * as all the sector data has been transferred.
  648. */
  649. if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
  650. /* wait a little while for DMA to complete */
  651. for (n = 0; n < 100; ++n) {
  652. if (cp->xfer_status != 0)
  653. break;
  654. udelay(1);
  655. barrier();
  656. }
  657. }
  658. /* turn off DMA */
  659. out_le32(&dr->control, (RUN | PAUSE) << 16);
  660. stat = ld_le16(&cp->xfer_status);
  661. resid = ld_le16(&cp->res_count);
  662. if (intr & ERROR_INTR) {
  663. n = fs->scount - 1 - resid / 512;
  664. if (n > 0) {
  665. blk_update_request(fd_req, 0, n << 9);
  666. fs->req_sector += n;
  667. }
  668. if (fs->retries < 5) {
  669. ++fs->retries;
  670. act(fs);
  671. } else {
  672. printk("swim3: error %sing block %ld (err=%x)\n",
  673. rq_data_dir(fd_req) == WRITE? "writ": "read",
  674. (long)blk_rq_pos(fd_req), err);
  675. swim3_end_request_cur(-EIO);
  676. fs->state = idle;
  677. }
  678. } else {
  679. if ((stat & ACTIVE) == 0 || resid != 0) {
  680. /* musta been an error */
  681. printk(KERN_ERR "swim3: fd dma: stat=%x resid=%d\n", stat, resid);
  682. printk(KERN_ERR " state=%d, dir=%x, intr=%x, err=%x\n",
  683. fs->state, rq_data_dir(fd_req), intr, err);
  684. swim3_end_request_cur(-EIO);
  685. fs->state = idle;
  686. start_request(fs);
  687. break;
  688. }
  689. if (swim3_end_request(0, fs->scount << 9)) {
  690. fs->req_sector += fs->scount;
  691. if (fs->req_sector > fs->secpertrack) {
  692. fs->req_sector -= fs->secpertrack;
  693. if (++fs->head > 1) {
  694. fs->head = 0;
  695. ++fs->req_cyl;
  696. }
  697. }
  698. act(fs);
  699. } else
  700. fs->state = idle;
  701. }
  702. if (fs->state == idle)
  703. start_request(fs);
  704. break;
  705. default:
  706. printk(KERN_ERR "swim3: don't know what to do in state %d\n", fs->state);
  707. }
  708. return IRQ_HANDLED;
  709. }
  710. /*
  711. static void fd_dma_interrupt(int irq, void *dev_id)
  712. {
  713. }
  714. */
  715. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  716. int interruptible)
  717. {
  718. unsigned long flags;
  719. spin_lock_irqsave(&fs->lock, flags);
  720. if (fs->state != idle) {
  721. ++fs->wanted;
  722. while (fs->state != available) {
  723. if (interruptible && signal_pending(current)) {
  724. --fs->wanted;
  725. spin_unlock_irqrestore(&fs->lock, flags);
  726. return -EINTR;
  727. }
  728. interruptible_sleep_on(&fs->wait);
  729. }
  730. --fs->wanted;
  731. }
  732. fs->state = state;
  733. spin_unlock_irqrestore(&fs->lock, flags);
  734. return 0;
  735. }
  736. static void release_drive(struct floppy_state *fs)
  737. {
  738. unsigned long flags;
  739. spin_lock_irqsave(&fs->lock, flags);
  740. fs->state = idle;
  741. start_request(fs);
  742. spin_unlock_irqrestore(&fs->lock, flags);
  743. }
  744. static int fd_eject(struct floppy_state *fs)
  745. {
  746. int err, n;
  747. err = grab_drive(fs, ejecting, 1);
  748. if (err)
  749. return err;
  750. swim3_action(fs, EJECT);
  751. for (n = 20; n > 0; --n) {
  752. if (signal_pending(current)) {
  753. err = -EINTR;
  754. break;
  755. }
  756. swim3_select(fs, RELAX);
  757. schedule_timeout_interruptible(1);
  758. if (swim3_readbit(fs, DISK_IN) == 0)
  759. break;
  760. }
  761. swim3_select(fs, RELAX);
  762. udelay(150);
  763. fs->ejected = 1;
  764. release_drive(fs);
  765. return err;
  766. }
  767. static struct floppy_struct floppy_type =
  768. { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */
  769. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  770. unsigned int cmd, unsigned long param)
  771. {
  772. struct floppy_state *fs = bdev->bd_disk->private_data;
  773. int err;
  774. if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
  775. return -EPERM;
  776. #ifdef CONFIG_PMAC_MEDIABAY
  777. if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
  778. return -ENXIO;
  779. #endif
  780. switch (cmd) {
  781. case FDEJECT:
  782. if (fs->ref_count != 1)
  783. return -EBUSY;
  784. err = fd_eject(fs);
  785. return err;
  786. case FDGETPRM:
  787. if (copy_to_user((void __user *) param, &floppy_type,
  788. sizeof(struct floppy_struct)))
  789. return -EFAULT;
  790. return 0;
  791. }
  792. return -ENOTTY;
  793. }
  794. static int floppy_open(struct block_device *bdev, fmode_t mode)
  795. {
  796. struct floppy_state *fs = bdev->bd_disk->private_data;
  797. struct swim3 __iomem *sw = fs->swim3;
  798. int n, err = 0;
  799. if (fs->ref_count == 0) {
  800. #ifdef CONFIG_PMAC_MEDIABAY
  801. if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
  802. return -ENXIO;
  803. #endif
  804. out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
  805. out_8(&sw->control_bic, 0xff);
  806. out_8(&sw->mode, 0x95);
  807. udelay(10);
  808. out_8(&sw->intr_enable, 0);
  809. out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
  810. swim3_action(fs, MOTOR_ON);
  811. fs->write_prot = -1;
  812. fs->cur_cyl = -1;
  813. for (n = 0; n < 2 * HZ; ++n) {
  814. if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
  815. break;
  816. if (signal_pending(current)) {
  817. err = -EINTR;
  818. break;
  819. }
  820. swim3_select(fs, RELAX);
  821. schedule_timeout_interruptible(1);
  822. }
  823. if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
  824. || swim3_readbit(fs, DISK_IN) == 0))
  825. err = -ENXIO;
  826. swim3_action(fs, SETMFM);
  827. swim3_select(fs, RELAX);
  828. } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
  829. return -EBUSY;
  830. if (err == 0 && (mode & FMODE_NDELAY) == 0
  831. && (mode & (FMODE_READ|FMODE_WRITE))) {
  832. check_disk_change(bdev);
  833. if (fs->ejected)
  834. err = -ENXIO;
  835. }
  836. if (err == 0 && (mode & FMODE_WRITE)) {
  837. if (fs->write_prot < 0)
  838. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  839. if (fs->write_prot)
  840. err = -EROFS;
  841. }
  842. if (err) {
  843. if (fs->ref_count == 0) {
  844. swim3_action(fs, MOTOR_OFF);
  845. out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
  846. swim3_select(fs, RELAX);
  847. }
  848. return err;
  849. }
  850. if (mode & FMODE_EXCL)
  851. fs->ref_count = -1;
  852. else
  853. ++fs->ref_count;
  854. return 0;
  855. }
  856. static int floppy_release(struct gendisk *disk, fmode_t mode)
  857. {
  858. struct floppy_state *fs = disk->private_data;
  859. struct swim3 __iomem *sw = fs->swim3;
  860. if (fs->ref_count > 0 && --fs->ref_count == 0) {
  861. swim3_action(fs, MOTOR_OFF);
  862. out_8(&sw->control_bic, 0xff);
  863. swim3_select(fs, RELAX);
  864. }
  865. return 0;
  866. }
  867. static int floppy_check_change(struct gendisk *disk)
  868. {
  869. struct floppy_state *fs = disk->private_data;
  870. return fs->ejected;
  871. }
  872. static int floppy_revalidate(struct gendisk *disk)
  873. {
  874. struct floppy_state *fs = disk->private_data;
  875. struct swim3 __iomem *sw;
  876. int ret, n;
  877. #ifdef CONFIG_PMAC_MEDIABAY
  878. if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
  879. return -ENXIO;
  880. #endif
  881. sw = fs->swim3;
  882. grab_drive(fs, revalidating, 0);
  883. out_8(&sw->intr_enable, 0);
  884. out_8(&sw->control_bis, DRIVE_ENABLE);
  885. swim3_action(fs, MOTOR_ON); /* necessary? */
  886. fs->write_prot = -1;
  887. fs->cur_cyl = -1;
  888. mdelay(1);
  889. for (n = HZ; n > 0; --n) {
  890. if (swim3_readbit(fs, SEEK_COMPLETE))
  891. break;
  892. if (signal_pending(current))
  893. break;
  894. swim3_select(fs, RELAX);
  895. schedule_timeout_interruptible(1);
  896. }
  897. ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
  898. || swim3_readbit(fs, DISK_IN) == 0;
  899. if (ret)
  900. swim3_action(fs, MOTOR_OFF);
  901. else {
  902. fs->ejected = 0;
  903. swim3_action(fs, SETMFM);
  904. }
  905. swim3_select(fs, RELAX);
  906. release_drive(fs);
  907. return ret;
  908. }
  909. static const struct block_device_operations floppy_fops = {
  910. .open = floppy_open,
  911. .release = floppy_release,
  912. .locked_ioctl = floppy_ioctl,
  913. .media_changed = floppy_check_change,
  914. .revalidate_disk= floppy_revalidate,
  915. };
  916. static int swim3_add_device(struct macio_dev *mdev, int index)
  917. {
  918. struct device_node *swim = mdev->ofdev.node;
  919. struct device_node *mediabay;
  920. struct floppy_state *fs = &floppy_states[index];
  921. int rc = -EBUSY;
  922. /* Check & Request resources */
  923. if (macio_resource_count(mdev) < 2) {
  924. printk(KERN_WARNING "ifd%d: no address for %s\n",
  925. index, swim->full_name);
  926. return -ENXIO;
  927. }
  928. if (macio_irq_count(mdev) < 2) {
  929. printk(KERN_WARNING "fd%d: no intrs for device %s\n",
  930. index, swim->full_name);
  931. }
  932. if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
  933. printk(KERN_ERR "fd%d: can't request mmio resource for %s\n",
  934. index, swim->full_name);
  935. return -EBUSY;
  936. }
  937. if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
  938. printk(KERN_ERR "fd%d: can't request dma resource for %s\n",
  939. index, swim->full_name);
  940. macio_release_resource(mdev, 0);
  941. return -EBUSY;
  942. }
  943. dev_set_drvdata(&mdev->ofdev.dev, fs);
  944. mediabay = (strcasecmp(swim->parent->type, "media-bay") == 0) ?
  945. swim->parent : NULL;
  946. if (mediabay == NULL)
  947. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
  948. memset(fs, 0, sizeof(*fs));
  949. spin_lock_init(&fs->lock);
  950. fs->state = idle;
  951. fs->swim3 = (struct swim3 __iomem *)
  952. ioremap(macio_resource_start(mdev, 0), 0x200);
  953. if (fs->swim3 == NULL) {
  954. printk("fd%d: couldn't map registers for %s\n",
  955. index, swim->full_name);
  956. rc = -ENOMEM;
  957. goto out_release;
  958. }
  959. fs->dma = (struct dbdma_regs __iomem *)
  960. ioremap(macio_resource_start(mdev, 1), 0x200);
  961. if (fs->dma == NULL) {
  962. printk("fd%d: couldn't map DMA for %s\n",
  963. index, swim->full_name);
  964. iounmap(fs->swim3);
  965. rc = -ENOMEM;
  966. goto out_release;
  967. }
  968. fs->swim3_intr = macio_irq(mdev, 0);
  969. fs->dma_intr = macio_irq(mdev, 1);
  970. fs->cur_cyl = -1;
  971. fs->cur_sector = -1;
  972. fs->secpercyl = 36;
  973. fs->secpertrack = 18;
  974. fs->total_secs = 2880;
  975. fs->media_bay = mediabay;
  976. init_waitqueue_head(&fs->wait);
  977. fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
  978. memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
  979. st_le16(&fs->dma_cmd[1].command, DBDMA_STOP);
  980. if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
  981. printk(KERN_ERR "fd%d: couldn't request irq %d for %s\n",
  982. index, fs->swim3_intr, swim->full_name);
  983. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
  984. goto out_unmap;
  985. return -EBUSY;
  986. }
  987. /*
  988. if (request_irq(fs->dma_intr, fd_dma_interrupt, 0, "SWIM3-dma", fs)) {
  989. printk(KERN_ERR "Couldn't get irq %d for SWIM3 DMA",
  990. fs->dma_intr);
  991. return -EBUSY;
  992. }
  993. */
  994. init_timer(&fs->timeout);
  995. printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count,
  996. mediabay ? "in media bay" : "");
  997. return 0;
  998. out_unmap:
  999. iounmap(fs->dma);
  1000. iounmap(fs->swim3);
  1001. out_release:
  1002. macio_release_resource(mdev, 0);
  1003. macio_release_resource(mdev, 1);
  1004. return rc;
  1005. }
  1006. static int __devinit swim3_attach(struct macio_dev *mdev, const struct of_device_id *match)
  1007. {
  1008. int i, rc;
  1009. struct gendisk *disk;
  1010. /* Add the drive */
  1011. rc = swim3_add_device(mdev, floppy_count);
  1012. if (rc)
  1013. return rc;
  1014. /* Now create the queue if not there yet */
  1015. if (swim3_queue == NULL) {
  1016. /* If we failed, there isn't much we can do as the driver is still
  1017. * too dumb to remove the device, just bail out
  1018. */
  1019. if (register_blkdev(FLOPPY_MAJOR, "fd"))
  1020. return 0;
  1021. swim3_queue = blk_init_queue(do_fd_request, &swim3_lock);
  1022. if (swim3_queue == NULL) {
  1023. unregister_blkdev(FLOPPY_MAJOR, "fd");
  1024. return 0;
  1025. }
  1026. }
  1027. /* Now register that disk. Same comment about failure handling */
  1028. i = floppy_count++;
  1029. disk = disks[i] = alloc_disk(1);
  1030. if (disk == NULL)
  1031. return 0;
  1032. disk->major = FLOPPY_MAJOR;
  1033. disk->first_minor = i;
  1034. disk->fops = &floppy_fops;
  1035. disk->private_data = &floppy_states[i];
  1036. disk->queue = swim3_queue;
  1037. disk->flags |= GENHD_FL_REMOVABLE;
  1038. sprintf(disk->disk_name, "fd%d", i);
  1039. set_capacity(disk, 2880);
  1040. add_disk(disk);
  1041. return 0;
  1042. }
  1043. static struct of_device_id swim3_match[] =
  1044. {
  1045. {
  1046. .name = "swim3",
  1047. },
  1048. {
  1049. .compatible = "ohare-swim3"
  1050. },
  1051. {
  1052. .compatible = "swim3"
  1053. },
  1054. };
  1055. static struct macio_driver swim3_driver =
  1056. {
  1057. .name = "swim3",
  1058. .match_table = swim3_match,
  1059. .probe = swim3_attach,
  1060. #if 0
  1061. .suspend = swim3_suspend,
  1062. .resume = swim3_resume,
  1063. #endif
  1064. };
  1065. int swim3_init(void)
  1066. {
  1067. macio_register_driver(&swim3_driver);
  1068. return 0;
  1069. }
  1070. module_init(swim3_init)
  1071. MODULE_LICENSE("GPL");
  1072. MODULE_AUTHOR("Paul Mackerras");
  1073. MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);